JPH01109445A - Register filing device - Google Patents

Abstract

PURPOSE:To improve throughput in a whole data processor by independently reading the data of a storing part and a mask bit. CONSTITUTION:A storing part 101 stores writing data 14 to a storing element to be instructed by a writing instructing signal 3 and outputs the data, which are stored in the instructed storing element, to a reading means 103 as reading data 11 by a reading instructing signal 3. A mask register 102 stores writing data 17 by a writing instructing signal 2 and outputs the data to the reading means 103 as mask data 12. The reading means 103 outputs the reading instructing signal 3 to the storing part 101 and obtains the reading data 11 and the mask data 12 as inputs. Then, reading data 13 are outputted and one mask bit is selected out of the mask data 12. Then, this is outputted as a mask bit 19. Thus, the data of the storing part and the mask data can be respectively independently read.

Description

[Detailed description of the invention] Technical field The present invention relates to a register file integrated circuit device.

J1 register file is widely used in high-speed calculation parts of information processing equipment as a high-speed memory that can read and write to any two storage elements at the same time, and it can be integrated like general memory. It is circuitized.

An example of a conventional register file integrated circuit is shown in FIG. Referring to FIG. 7, the register file in this example includes two storage units 10 and 11, a read data switching circuit 12, a read address register 13, a mask register read designation circuit 14, a mask register 15, and a write data switching circuit 12. including data switching circuit 16 and five AND circuits 20, 21.2
2.23 and 24 and two OR circuits 30 and 31
and four gate circuits 40, 41, 42 and 43.

Storage units 10 and 11 each have a storage capacity of 32 words x 9 bits/word, and read address 100 and write address 101 each consist of 6 bits. Storage part 1
0 is selected when the least significant bit of each of the read address 10G and the write address 101 is “0”, and the storage unit 11 is selected when the least significant bit of each of the read address 100 and the write address 101 is “1”. It is designed to be selected correspondingly when °.

The read operation of the storage units 10 and 11 is performed by setting the mask register read designation signal 105 to "0" and setting the read address 10G from the external address register 13. At this time, read data is cut off! @path 12 receives a read signal from storage unit 10 or 11. Since only the top five pits of the read address are input to the storage units 10 and 11, read signals from both storage units are simultaneously read out to the read data switching circuit 12. 22 and 23, only one of the two successive signals is read data 104 according to the lowest pit of read address 1.00.
is output externally as .

The one-word write operation of the storage units 10 and 11 is performed using the mask register write designation signal 107 and the 2WI write designation signal 109 as #O#, and the write address 101. This is done by supplying write enable signals 102a, 102b and write data 103 from outside. At this time, the write data switching circuit 16 determines that the 2I write designation signal 109 is “0”.
'', the write data 103 is accepted, so the write address 1 is stored in the storage units 10 and 11.
The top five pits of 01 and write data 103 are input at the same time.

However, due to the gate n path 40, the OR circuits 30 and 31, and the AND circuits 20 and 21, the address 1
The lowest pit of 01 controls only one of the write enable signals 102a and 102b to be input to the corresponding storage section.

Another mode for the 1111 write operation of the storage units 10 and 11 is to externally supply only the upper six bits as the write address 101, and switch the write enable signals 102a and 102b externally in correspondence with the storage unit to be written. This can be achieved by supplying By doing this, the one-word write mentioned above will be performed at the write address 10.
The write enable signal 10 and 11 are alternately performed in response to changes in the lowest pit of 11 and 11, respectively.
By changing the switching synchronization between 2a and 102b, it becomes possible to perform continuous writing to a plurality of addresses in the storage units 10 and 11.

In the 211■ write operation of the storage units 10 and 11, the mask register write designation signal 107 is set to "o", the 2!1-write designation signal 109 is set to "1", the write address is 1°1, and the write enable signal 102a is set. , 102b and write data 103a, 103b from the outside. At this time, the write data switching circuit 16
Since the 1-include designation signal 109 is “1”, the write data 103b is accepted, so the storage unit 10
The write data 103a is input to the storage unit 11, and the write data 103b is input to the storage unit 11, respectively. Also, the mask register write designation signal 107 is “0” and 2!
Since the ill-included designation signal 109 is "1'', the write enable signals 102a and 102b are simultaneously supplied to the storage units 1o and 11, respectively, by the OR circuits 30 and 31 and the AND circuits 20 and 21, and 21
1 write operation will be performed.

Incidentally, a 6411.times.72 pit/word register file can be constructed using only eight register file integrated circuits shown in FIG. 72 bits of data per 1i11 are supplied to the arithmetic unit, of which 64 pits excluding the parity pit correspond to each of the aforementioned data bits.

Reading of the mask register 15 is performed by setting the mask register read designation signal @105 to "1" and set it in the mask register read designation circuit 14. At this time, “1” passed through the gate path 41 indicates that the read data is off! Il
The line 12 operates to accept the output of the mask register 15, and the contents held in the mask register 15 can be taken out as read data 104. Mask register 1
When reading 5, 1 to memory 'PIA10 or 11
Word write operation or 21i! to storage units 10 and 11! I
I-in operation is possible at the same time.

Writing to the mask register 15 is performed by setting the mask register write designation signal 107 to “1” and turning on the write enable signal 10.
2a and write data 103a are supplied from outside. At this time, the mask register write designation signal 107 and the -write enable signal 102a that have passed through the gate circuit 43 satisfy the AND condition in the AND circuit 24, so that the write enable signal 102a is input to the mask register 15. When writing to the mask register 15, reading from the storage section 10 or 11 is possible at the same time.

Note that the read address register hold signal 106 is supplied from the outside when it is desired to fix the contents held in the read address register 13, such as during failure diagnosis. Also,
The read address register through signal 108 is used when the read address 10G is to pass through the read address register 13 and be input to the storage units 10 and 11 due to the timing of the circuit or device in which the register file collection M circuit is used. is supplied from outside.

In the example shown in FIG. 7, the write address 101 is input directly to the storage units 10 and 11, but a write address register that can be set to a through state like the read address register 13 may be provided. You may also do so.

The register file integrated circuit shown in FIG. 7 is an example of the most advanced circuit in terms of versatility and high speed among conventional register file integrated circuits.

However, since reading and writing of the mask register 15 is shared with other storage units 10.11, there is a drawback that data in the storage unit and data in the mask register cannot be read or written at the same time.

Also, data office FI! In design, mask data is often treated bit by bit, but the conventional example described above has a drawback in that it cannot be read or written bit by bit.

The present invention has been made by focusing on the reading side of the above-mentioned drawbacks, and its purpose is to provide a register that allows data in a storage section and mask data to be read independently. An object of the present invention is to provide a file device. A register file device according to the present invention includes: a storage section capable of storing a plurality of data; a mask register holding a plurality of mask data to be supplied to an arithmetic section; means for reading one of the mask data in the mask register; a means for reading one of the data in the storage; and an overcontrol means for loading one write data into the storage and the mask register. It is characterized by containing.

! Shift 1 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment of the present invention, and is a block diagram showing the basic configuration of the present invention. In FIG. 1, writing means 104
When write data 18 is input, outputs write instruction signal 1 and write data 14 to storage unit 101, and/or outputs write instruction signal 2 and write data 17 to mask register 102. Output for.

When the storage section 101 receives the write instruction signal 1 and the write data 14 from the writing means 104, the storage section 101 selects the 11 elements specified by the write instruction signal 1 among the plurality of storage elements in the storage section 101. 1-include data 14 is stored in . Also, storage unit 1
01 indicates that when the read instruction signal 3 is input from the read means 103, among the plurality of memory elements in the memory unit 101,
The data stored in the memory element designated by the read instruction signal @3 is outputted to the reading means 103 as read data 11.

When the write instruction signal 2 and write data 17 are inputted from the write means 104, the mask register 102 stores the write data 17 according to the write instruction signal 2, and writes the mask data 12.
It is outputted to the reading means 103 as . This reading means 1
03 outputs read instruction signal 3 to storage unit 101;
It inputs read data 11 and mask data 12 and outputs read data 13, and also selects one mask bit of the mask data 12 and outputs this read mask bit 19.

In FIG. 1, read data 13 and read mask bit 1
9 is the output data of the register file integrated circuit,
Further, the write data 18 is input data to the register file integrated circuit.

FIG. 2 is a block diagram showing an example in which the present invention is applied to a circuit equivalent to the conventional register file integrated circuit shown in FIG. 7, and parts equivalent to those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, the writing means 104 writes two pieces of data 1.
When 8a and 18b are input, write address 4.1 write enable 5a, 11 write enable 5b, and write enable 2 are output as write instruction signals, and three pieces of write data 14a, 14b, and 17 are output. Output. The write address 4 and the two write enables 5a and 5b are the storage unit 10.
1 and is used as a write instruction signal for two pieces of write data 14a and 14b. Further, write enable 2 is input to mask register 102 and used as a 1 write instruction signal for write data 17.

The storage unit 101 has 4 write addresses, 2 write enables 5a, 5b, and 2 female write data 14a.

14b is input, the write address 4 specifies each storage element of the two storage units 211 and 212 in the storage unit 101, and when the write enable 5a is “1”, the write data 14a is specified. The write data 14b is stored in the specified memory element in the memory unit 211, and when the write enable 5b is 1'', the write data 14b is stored in the specified memory element in the memory unit 212. When either write enable 5a or write enable 5b is "1", one piece of write data is stored, and when both write enables 5a, 5b are "1", two pieces of write data are stored. They will be stored at the same time.

The write means 104 includes a write data selection circuit 243 that determines the write data 14b, and selects the two write data 18a, 18 by the selection signal 6 from the write control means 241.
b is selected and output as write data 14b.

The write control means 241 also outputs two write enables 5a and 5b in addition to the aforementioned selection signal 6 for the write data 14b. For example, if the write data 18a- is vector data consisting of a plurality of consecutive (for example, 64) elements, the write data 18a is selected by the selection signal 6 and outputted from the write address storage means. write address 4
If the same address is assigned to two consecutive pieces of write data 18a and the write enable bits 5a and 5b of 291 are outputted as "1'' alternately, then one of the vector data of write data 18a , the number of elements (e.g. 6
Half of them (for example, 3211) are stored in the storage unit 211, and the other half are stored in the storage unit 212 continuously. Also, among similar vector data (consisting of, for example, 64 elements), the first even-numbered element is set as 8-write data 18a, the odd-numbered element is set as write data 18b, and half (for example, 32 pieces) of vector data is generated. When inputting , write data 18b is selected by selection signal 6, write address 4 is assigned continuously, and both write enable 5a and write enable 5b are output as "1". Equivalent contents can be stored in the storage unit 211 and the storage unit 212 in half the time as in the case described above (when the !I write data 28a is selected).
is stored in

When the write enable 2 and write data 17 are inputted from the write means 104, the mask register 102 stores the write data 17 by the write enable 2, and sends it to the successive output means 103 as mask data 12. Output. This reading means 103 uses the read address 3 as a read instruction signal.
is output to the storage unit 101, and the two read data 11
a, 11b, and mask data 12 as well, and outputs read data 13 and read mask bits 1-9.

When the storage unit 101 receives the read address 3 as a read instruction signal, the two storage units 211 in the storage unit 101,
, 212, and outputs the data stored in the storage elements as read data 11a, 11b.

The readout means 103 includes a readout data selection circuit 233 that determines the readout data 13, and the readout i11 control means 231
Two successive data 11a, 1 are selected by the selection signal 9 from
1b and mask data 12 is selected and outputted as read data 13.

Further, the successive output means 103 includes a mask bit selection circuit 234 that determines the read mask bit 19, and selects one of the plurality of bits (for example, 64 bits) in the mask data 12 according to the read address 7 by the read address storage means 235.
The bit designated by read address 7 is selected and outputted as read mask bit 19.

In FIG. 2, read data 13 and read mask bit 1
9 is output data of this register file integrated circuit, and two pieces of write data 18a and 18b are input data of the register file integrated circuit.

FIG. 3 shows, as means for reading one mask bit, a read address that specifies one mask bit in mask data 12, similar to read address 3 that specifies one piece of stored data in storage unit 101. FIG. In FIG. 3, when the mask bit selection circuit 234 receives the read address A(7), the decoder 301 generates the selection signal S, and the selection circuit 30 generates the selection signal S.
2 input. The selection circuit 302 is the mask register 10
When the mask data M (12) from 2 is input, any bit in the mask data M is selected by the selection signal S and a read mask bit RM (19) is output.

FIG. 4(A) shows the mask bit selection circuit 2 shown in FIG.
This is a specific example of a circuit equivalent to No. 34, in which the input read address A=(a, a4.a5) is 3-bit data, and the input mask data M-(m, m,
This is an example in which the data (m2, . . . 1m 71mp) is 9-bit data including the validity bit mp.

Successive addresses A=(a, a, s, a5) inputted to the mask bit selection circuit 234 become input to the decoder 301, and the decoder 30 shown in FIG. 4(B)
The input/output relationship of 1 is true! A selection signal 3-(s, ss O1·2° . . . , S7) is generated by a logical configuration according to the Il value table and is input to the selection circuit 302. The selection circuit 302 receives mask data M-(mo.

m, m, ·; ·, mI, m,) and selection signal S=
When (So, S4.2..., S7) is input, logical formula: RM-8, ·m, +51-m, +52-m2
+・+s7-mI RMP-m.

It outputs a mask bit RM and a parity bit RMP expressed by . Here, RMP-mp is bit data for a parity check implemented in a general data processing device, and although it is not directly related to the present invention, when implementing the present invention, RMP-mp is bit data for a parity check performed in a general data processing device. It is shown in the block diagram because it may be used in applications such as

FIG. 5 is an example of a mask bit selection circuit in which the mask bit selection circuit 234 of FIG. 4(A) is developed to double the pit length of input mask data. In this Figure 5,
Read address A input to mask bit selection circuit 234 = (a2, a3, a4).

a ] lower 3 bits - a , a4 , a
5) becomes the input of the decoder 301a, and the upper 1 bit = (a2) becomes the input of the decoder 301b.The decoder 301a is equivalent to the decoder 301 shown in FIG. 4(A), and the selection circuit 302a and the selection circuit 302b is equivalent to the selection circuit 302 shown in FIG. 4(A), and the mask data M - (m, m, , -, mI, m,
o.

When "8-m9l"'-m15"mI)1' is input, mask bits RMtJ and RML expressed by the logical formula: %formula% are output.

The decoder 301b inputs bit [a2] of the read address, generates a selection signal 5=aS-a 21 L2, and inputs this to each of the selection circuits 302C and 302d. The selection circuit 302C selects mask bits RMLJ, RM
When L and selection signals S, , S, etc. are combined, the logical formula: R
M-8, -RMU+8. - Output mask bits RM denoted by RML. The selection circuit 302d receives parity bit data MPu-mDo.

When MPL-mpl and selection signals qsU,s, are input tL, parity φ bit data RMP expressed by the logical formula: RMP-80-MPLJ+SL-MPL is output.

FIG. 6 is a block diagram showing an example of a mask bit reading means in a device having a 64-bit mask register using four register file integrated circuits of the present invention each having a 16-pit register as a mask register. , is an application example of the present invention. In FIG. 6, a 7-bit successive address A-(a
, al.

a 2 , a , a 4. a5-ap), the lower 4-bit address AI-(a2, a
3, a4.

aS) has four register file integrated circuits 601, 6
02.603,604. The read mask bits RMO and RM1 of the mask data input to and stored in the 16-bit mask register provided inside each
．． RM2. Used to select RM3.

Address of top 2 pits AO = (a, al)
becomes the input of the decoder 60G, and the logical formula "Suu"ao"al-Sut"ao-T
1=SLU-ao-al, 5LL-100-al.

Selection signals SUu, Su4 . S, U, SL,
is generated, and this is input to the selection 0 path 607.

The selection circuit 607 selects these four read mask pits RMO.
, RMI, RM2, RM3 and selection signals SUU, S
11. S1u, S1. When input, the logical formula: RM
-8-RMO+Su, .RMI +u S -RM2+S11.RM3 [Output the mask bit RM represented by U. Here, mask bit RM is 1-bit data specified by read address A out of 64-bit mask data.

As described above, according to the present invention, by employing a configuration that allows data in the storage section and mask bits to be read independently, data processing for data in the storage section and mask data can be performed in addition to the functions of the conventional technology. Since the bit-by-bit processing can be executed in parallel, the processing capacity of the entire data processing device can be improved. This integrated circuit can take full advantage of its features when used as a vector register in a vector data processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention;
2 is a diagram showing a specific example of the block in FIG. 1, FIG. 3 is a diagram showing a block of the mask bit selection circuit, and FIG. 4 (A
) is a diagram showing a specific example of the mask bit selection circuit of the third rjA, FIG. 4(B) is a diagram showing a truth table of the input/output relationship of the decoder, and FIG. FIG. 6 is a block diagram showing an example of application of the present invention, and FIG. 7 is a block diagram of an example of a conventional register file integrated circuit. Explanation of symbols of main parts 101...Storage section 102...Mask register 103...Reading means 104-...Writing means

Claims (1)

[Claims] a storage section capable of storing a plurality of data; a mask register holding a plurality of mask data to be supplied to an arithmetic section; means for reading out one of the mask data in the mask register; 1. A register file device comprising: means for reading one; and write control means for writing write data into the storage section and the mask register.