JPH01109427A - Binary number multiplying system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to binary number arithmetic, and particularly to a binary number multiplication method suitable for vibe line processing.

(Prior art) Regarding the multiplication method for unsigned binary numbers that combines a conventional addition circuit and AND circuit, see "High-speed calculation method for computers" (translated by Yaya Horikoshi, published by Kindai Kagakusha), pages 163 to 167. being discussed.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, a logical product is performed between the multiplicand and 1 bit of the multiplier, and after weight processing, the sum of these results is calculated to obtain the 1-multiplication result. Therefore, the number of stages equal to the bit length of the multiplier is A circuit and a one-stage AND circuit are required. Therefore, the bit length of the multiplier is m; the calculation time of the adder circuit is ta.

If the delay time of the logical product is tn, the multiplication time tc needs to be tc=taXm+t4, and there is a problem that the multiplication time increases as the bit length of the multiplier increases.

An object of the present invention is to make the multiplication time independent of the bit length m of the multiplier, that is, to add the calculation time ta of the adder circuit and the delay time t4 of the AND circuit.

The objective is to improve the temperature to tc=taXt4. In addition, the purpose is to simplify the circuit configuration and facilitate LSI implementation.

[Means for solving problems]

The above purpose is to add a group of registers to store the output of the adder circuit that calculates the multiplicand for each bit of the multiplier to the conventional unsigned binary multiplication method consisting of an adder circuit and an AND circuit. This can be achieved by using a pipeline configuration in which the outputs of the adder circuits in the stages are stored sequentially using clock inputs, and processing proceeds for each clock input.

[Effect]

Multiplying unsigned binary numbers performs an AND operation between the multiplicand and one bit of the multiplier, giving 2" equal to the weight for each bit.
This can be achieved by multiplying and then calculating the sum of the multiplicand calculation results for each bit. At this time, the output of the adder circuit that calculates the multiplicand for each bit of the 1st multiplier is
Using the clock input, the results are sequentially stored in a group of result storage registers and used as input to the primary stage. Furthermore, separate delay register groups are used for the multiplicand and the multiplier, so that each clock input is delayed to match the timing with the operation results up to the previous stage. By doing so, since the result of the operation at the previous stage is stored in the result storage register, the adder circuit and the AND circuit at the stage before each result storage register can perform an operation on another input. In this way, by creating a pipeline configuration in which the calculation proceeds using the clock input and outputs the multiplication result for each clock input, the time required for one multiplication can be improved to a time equal to the period of the clock input. . In order to perform reliable multiplication, the period of the clock input must be less than or equal to the sum of the calculation time of the adder circuit and the delay time of the AND circuit.

〔Example〕

An embodiment of an unsigned binary multiplication circuit according to the present invention will be described below with reference to FIGS. 1 and 2. Also,
FIG. 3 shows a signed binary number multiplication circuit using the unsigned binary number multiplication circuit shown in FIG.

The unsigned binary multiplication circuit includes a group of multiplicand delay registers 11 that delay the multiplicand, a multiplier delay register that delays the multiplier, a group of AND gates 3 and an adder group 4 that perform an operation on the multiplicand for one bit of the multiplier. It consists of a group of result storage registers 5 that sequentially store the outputs of , respectively, and is operated in synchronization with a clock input, and outputs a multiplication result for each clock input.

First, the first-stage AND gate 3-1 calculates the multiplicand K
O""'

A constant "0" is added, and the result, excluding the least significant bit, is stored in the first stage result storage register 5-1 at clock timing. At this time, the multiplicand x.

~Xn-1 is latched into the first stage multiplicand delay register,
The contents of the first stage multiplicand delay register 1-1 are as follows.

It is moved to the next stage multiplicand delay register 1-2. Furthermore, the lowest bits of the multipliers y1 to 7m''l and the output of the first-stage adder 4-1 are latched in the multiplier delay register 2-1, and except for the second lowest bit (y*), It is moved to the next stage multiplier delay register 2-2.

Next, the second-stage AND gate 3-2 outputs the contents of the first-stage multiplicand delay register 1-1 indicating the previous multiplicand and the output of the first-stage multiplier delay register 2-1 indicating the previous multiplicand. A logical AND operation is performed with the second bit (yl) from the lowest, and the result is added to the contents of the first stage result storage register 5-1 using the second stage adder 4-2. Adder 4-2
The output of the least significant bit of is the second stage multiplier delay register 2-
2, and the other bits are stored in the second stage result storage register 5-2.

Although not shown in FIG. 1, similar processing is performed on all bits of the multiplier, and finally the output of the adder 4-m at the final stage is output, and the least significant bit is output from the multiplier delay register 2-m at the final stage. The mth bit of m is latched, and the other bits are stored in the final stage result storage register 5-m.

In this way, the result storage register 5-m and multiplier delay register 2-m at the final stage contain the multiplication result z for the multiplicand xo to X5-1 and the multiplier 70 7 wa-1.

~2. ◆The feature of the configuration of the six circuits that yields -1 is that multiplication of unsigned binary numbers is realized using five types of components: each register group 1, 2.5, AND gate group 3, and adder group 4. It is possible.

Further, the calculation progresses for each clock input, as shown in the timing chart of FIG. In this case, it is assumed that the multiplicand x(i) and the multiplier y(t) change in synchronization with the clock. Therefore, the inputs x(s), y(1)
The multiplication result Z(,) for is also output for each clock input. 1st input x(o).

The output for y (o) is z (0), and the output for the input x (z) t y (z) delayed by one clock is z
(1), and the final multiplication result Z(,) is the input x
(1).

For y(,), if the clock period is T, then m
Output is delayed by XT. At this time, the sum of the delay time of the AND gate group 3 and the operation time of the adder group 4 must be smaller than the period of the clock input. Conversely, if this condition is satisfied, the multiplication time This means that the period has been improved to the period of the clock input. Here, we have shown the timing when the multiplicand and multiplier are already synchronized with the clock input, but if they are not synchronized, the purpose is to synchronize with the previous stage of the input (multiplicand 9 multiplier) in Figure 1. All you have to do is add a register.

FIG. 3 shows a group of code registers 7 for storing and delaying the output of the exclusive OR gate 6 and the non-alternative OR gate 6 for processing codes in the unsigned binary multiplication circuit shown in FIG. Complement calculation circuit for calculating the two's complement of the multiplicand 8. A multiplicand register 10 stores the output, a complement arithmetic circuit 9 calculates the two's complement of the multiplier, and a multiplier register 112 stores the result.
Complement calculation circuit 13 that calculates the two's complement of the multiplication result. It is a signed binary multiplier circuit with an additional output register to store the final result.

Here, the multiplicand 1 multiplier and the multiplication result are expressed as two's complement numbers, and the sign bits Xs g ys gzs are “
Complement calculation circuits 8 and 9, which indicate a negative value when the value is 1'' and a positive value when the value is '0'', calculate the feed values of the multiplicand and the multiplier, and the respective results are stored in the multiplicand register 10 and the multiplier register 11. , and then input to the unsigned binary multiplier circuit 12. The unsigned binary multiplication circuit 12 performs absolute value multiplication, and the sign is processed by exclusive OR 6. If the output of the exclusive OR gate 6 is “0”, the multiplication result will be a positive value, so the unsigned 2
If the result of the hexadecimal multiplication circuit 12 is output as is and the output of the exclusive OR gate 6 is "1", the multiplication result will be a negative value, so the complement arithmetic circuit 13 calculates the two's complement and outputs it. The purpose of the code register group 7 is to match the timing of the code and the output of the unsigned binary number multiplication circuit 12 (supply value multiplication result). The final signed multiplication result is stored in output register 14. At this time.

The multiplication time is determined by the calculation time of each complement calculation circuit or the multiplication time of the unsigned binary multiplication circuit 12.

〔Effect of the invention〕

According to the present invention, in the unsigned binary multiplication method, the multiplication time can be improved to the sum of the calculation time of the adder circuit and the delay time of the AND circuit. Further, since the multiplication circuit can be realized by a combination of two types of register groups having different bit lengths, an adder circuit group, and an AND gate group, the architecture can be simplified and the structure is suitable for LSI implementation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an unsigned binary multiplication circuit which is an embodiment of the present invention, Fig. 2 is a timing chart of the unsigned binary multiplication circuit shown in Fig. 1, and Fig. 3 is an unsigned binary multiplication circuit. FIG. 2 is a configuration diagram of a signed binary number multiplication circuit to which the calculation is applied. 1... Multiplicand delay register group, 2... Multiplier delay register group, 3... AND gate group, 4... Adder group,
5...Result storage register group, 6...Exclusive OR gate. 7... Sign register group, 8... Multiplicand complement arithmetic circuit, 9... Multiplicand complement arithmetic circuit, 10... Multiplicand register, 11... Multiplier register, 12... Unsigned binary number Multiplier circuit, 13... Output complement arithmetic circuit, 14
...Output register. Figure 3

Claims (1)

[Scope of Claims] 1. In an unsigned binary multiplier circuit composed of an adder circuit and an AND circuit, a register group is provided to sequentially store the calculation results of the multiplicand for each bit of the multiplier, and the multiplication results are stored for each clock input. A binary number multiplication system characterized in that it has a pipeline configuration for outputting, and circuits that perform operations on each bit of a multiplier have the same configuration.