JPH01108806A - Digital filter - Google Patents

Abstract

PURPOSE:To prevent adverse effect onto other circuit by adding an offset value to an input digital signal so as to apply filter operation thereby reducing bit number inverted synchronously and power consumption. CONSTITUTION:An offset value adder section 1 adds a specific offset to an input digital signal V1 depending on an addition offset signal VOA and outputs the sum. A filter arithmetic section 2 is provided with registers 21, 22, a multiplier 23 and an adder 24 to express the internal digital signal including an output digital signal VFI from the offset adder section 1 in a form of 2's complement and applies prescribed filter operation and gives the output. An offset subtraction section 3 subtracts a value corresponding to an offset from the digital signal VFO outputted from the filter arithmetic section 2 based on a subtraction offset signal VOD and gives an output. Thus, the inverted bit number is reduced to reduce the power consumption and the adverse effect on other circuit is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter, and particularly to a digital filter used in an analog/digital mixed communication LSI.

[Conventional technology]

Traditionally, this type of digital filter is an adder.

It generally includes a multiplier, a register, etc., and expresses the internal digital signal including the input digital signal τ signal in one's complement representation format, and performs a predetermined filter operation.

As an example of a conventional digital filter, the transfer function H1
(z) is Ht(z) = 1 + 2z 1z However, Z-' = 6-J''r, f: Signal frequency a
.

T: sampling period A circuit represented by is shown in FIG.

A signal V is input to the manually input digital input with a sampling period T.
x is given the delay time of register 21.22 yb z-" *2, that is, T, 2T, and
The output signal VRI of 1 is subjected to a coefficient multiplication operation (
×2) and these input digits A! , 4M issue v! , the output signal 32 of the register 22 and the output signal of the multiplier 23 are added together by the adder 24 and output.

The transfer function Ht(Z) with this configuration becomes a low-pass filter having a frequency of "/(2T)K zero points, as shown in FIG.

The reason why the two's complement representation format is used to express the value of the digital signal calculated internally is mainly due to the ease of constructing hardware such as an adder and two multipliers.

[Problem that the invention seeks to solve]

The above-mentioned conventional digital filter is configured to express and calculate the internal digital signal t-2 in the complement representation format, so when the λ digital signal v is near zero, the inverted high-order bit is The number of bits and the frequency of inversion increase, and when integrated into an LSI (particularly an 0MO8 type), there are disadvantages in that it adversely affects other circuits on the same chip, especially analog circuits, such as noise, and increases power consumption.

The state of bit inversion when the λ digital signal vx is near zero will be explained with reference to FIG.

λ digital signal V! is almost @0'', that is, when there is no signal, the values of registers 21 and 22 are all 10''.
Time fleFe every sampling period T from time 1o of
... rO at t9, 1,0°-1,0,-1,...0
” is assumed to be input. In other words, it is assumed that noise with an amplitude value of 1 (L8B1 bit phase, etc.) is randomly input even though there is no signal.

At this time, the output signal of each register 21.22 ■81°'V
The value of IL1 also changes as shown in FIG. 8, but the amplitude value itself is small. However, since the amplitude value is expressed in two's complement format, bit inversion occurs in many high-order bits when transitioning from a positive value to a negative value or from a negative value to a positive value. . From time t3 in Fig. 8 "4s*t to t"
・The transition to is equivalent to this.

The number of bits to be inverted increases as the amplitude of the noise becomes smaller and as the word length becomes longer.

Regarding the operation of the digital filter itself, this bit reversal phenomenon when there is no signal has no negative effect, but if it is realized as a CMOa type 18I that includes circuits other than the digital filter, it will become a problem, but the consumption It is electricity. This is because the gate of the 0M08mFET has the property of consuming power during bit inversion.

In addition, when analog circuits are implemented on the same chip, bit inversion, power supply circuits, and ground lines are required.

Noise generated on the board, etc. enters the analog circuit and adversely affects its characteristics. This adverse effect results in a digital filter inverting a large number of bits in synchronization, and four logic gates operating at high speed.

The objective is to provide a digital filter that can prevent this.

[Means for solving problems]

The digital quill router of the present invention includes an offset value addition section that adds a specific offset value to the value of an input digital signal and outputs the result, an adder 9 multiplier, and a register, and includes an output digital signal from the offset value addition section. A filter calculation unit that performs a predetermined filter calculation on the signal by expressing the value of an internal digital signal including this output digital signal in t-2 complement representation format, and outputs the digital signal output from the filter calculation unit. and an offset value subtraction section that subtracts a value corresponding to the offset value from the signal value.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

Offset ii, m calculation part it! , input digital signal V
! A specific offset value is added to the value by the addition offset signal ■om and output.

The filter calculation unit 2 includes registers 21, 22 . Multiplier 23
and an adder 24, and expresses the value of the internal digital signal including the output digital signal Vvx'fr from the offset value adder 1 in a t-2 complement representation format, performs a predetermined filter operation, and outputs the result. This filter calculation section 2 is the sixth
It is the same as the conventional digital filter shown in the figure.
A filter calculation of the transfer function Ht(z)=1+22+z is performed.

The three offset value subtracting sections subtract the value corresponding to the offset value from the digital signal VFOO value outputted from the filter calculation section 2 and output the subtracted offset signal VOD.

Next, the operation of this embodiment will be explained.

FIG. 2 is a diagram showing the values of various signals over time to explain the operation of this embodiment.

In this example, the offset value to be added is “4”
After setting, the DC gain of filter calculation section 2 is “4”
Therefore, the offset value to be subtracted is set to 116''.

As an input digital signal
,1. A case where "Q, -1, 0, -1, . . . O" is input will be explained.

The value of the input digital signal ■I fluctuates between positive and negative, but
Since 14" is added to the offset value addition section l,
Output digital signal of offset value adder 1 ■F! , the output signals of registers 21.22 VRI, vIL2 s
'Digital signal VF output from filter calculation unit 2
The values of O are all positive values. Taking the value of the digital signal VFO as an example, each sampling time t. of1~1. Looking at the change in bit configuration in , the inverted bits are limited to the lower five bits.

Assuming data @t-16 and t of each of the above digital signals, in the conventional example, almost all bits are inverted, but in this embodiment, it is limited to the lower 5 bits, and the number of inverted bits is V.
It can be seen that it has been reduced to about 3.

Regis fi 21 * 2201ti force signal Vat,
The number of inverted bits of VB2 and the output signal of the multiplier 23 is similarly reduced.

Mayu, the output side of offset value subtraction section 3 is positive again.

Although the output digital signal ``o'' has a negative swing, the number of bits is small compared to the total number of bits of the digital signal processed by the entire filter operation section 2, and can be ignored.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this second embodiment, the filter calculation unit 2a has a different configuration from the first embodiment, and even if the offset value to be added is the same as that in the first embodiment, the offset value to be subtracted is different. .

FIG. 4 shows the case where the offset value to be added and subtracted is 10'' in the second embodiment, that is, the filter calculation unit 2
Fig. 5 shows the state of the inverted bit in the case of a conventional digital filter with only a. The state of the inverted bit is shown when the offset value is 8''.

In the case of FIG. 4, all bits are inverted around time t6, whereas in the case of FIG. 5, the inverted bits are limited to the lower four bits.

If the data width f is 16 bits, the number of inverted bits is V4
This will reduce the amount of damage to a certain extent.

〔Effect of the invention〕

As explained above, the invention has a configuration in which filter calculation is performed by adding an offset value to the value of the input digital signal, so that positive and negative fluctuations due to minute noise in the vicinity of 10" that is manually input when there is no signal are eliminated. Since the number of unnecessary inversion bits can be reduced, power consumption can be reduced, and there is an effect that it is possible to prevent adverse effects of inversion noise on other circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention;
The figures are diagrams showing one sequence of signals of each part over time to explain the operation of the embodiment shown in Fig. 1, Fig. 3 is a block diagram showing a second embodiment of the invention, and Fig. 4. and FIG. 5 are diagrams illustrating the operation of the embodiment shown in FIG. 3 over time, and FIG.
The figure is a block diagram showing an example of a conventional digital filter, FIG. 7 is a frequency characteristic diagram of the digital filter shown in FIG. 6, and FIG. 8 is a diagram for explaining the operation of the digital filter shown in FIG. 6. FIG. 2 is a diagram showing Mt of each part of the signal over time. 1... Offset value addition section %2e2a... Filter calculation section %3e3a... Offset value subtraction section, 21°2
1a, 22... register, 23.23a... multiplier, 24.248... adder. Agent: Patent Attorney Shino Uchihara/Figure 2 Figure 5 Figure 6 Figure 8

Claims (1)

[Claims] It includes an offset value addition section that adds a specific offset value to the value of an input digital signal and outputs the result, an adder, a multiplier, and a register, and adds this output digital signal to the output digital signal from the offset value addition section. a filter calculation unit that expresses the value of the internal digital signal in a two's complement representation format, performs a predetermined filter calculation, and outputs the result;
A digital filter comprising: an offset value subtraction section that subtracts a value corresponding to the offset value from the value of the digital signal output from the filter calculation section.