JPH011072A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing device such as a linear density converting device that converts an image to a linear density or scales an image at an arbitrary magnification.

(Prior Art) Conventionally, methods for performing linear density conversion or scaling conversion of an image include (1) selecting a specific pixel from the pixels of the original image according to a predetermined algorithm, and converting the selected pixel into a Method of using the value as it is as the value of the converted pixel (2) There is a method of selecting some pixels from the original image, performing calculations on them, and determining the pixels of the converted image as a result.

Among these, a typical method (1) is the shortest distance approximation method. This is the value of the pixel on the original image that is closest to the position of the pixel after conversion in the original image, and is representative of the value of the pixel after conversion. This method is simple as an algorithm, and the amount of hardware required to develop it as a device is relatively small.

However, for example, when performing reduction conversion, the pixel density of the converted image is simply thinned out of the pixels of the original image, so even if significant characters are drawn in black on a white background, they will disappear if they are not sampled. Even if a relatively large pattern is drawn in black, if the sampled point happens to be on a white background, the converted image will be significantly deformed, resulting in significant image deterioration during the conversion process.

On the other hand, method (2) was devised to improve the shortcomings of method (1), and is a method in which the pixel density after conversion is calculated by referring to the original pixels surrounding this pixel in the original image. It is. In this method, the density value of the converted pixel is determined depending on the density distribution state of the pixel in the original image that is referred to.
Compared to method (1), the image quality deteriorates much less.

Furthermore, the method (2) can be classified into the following two types in terms of its specific implementation method. One method is to calculate the pixel density of the converted image using a logical operation on the pixel density of the original image as a reference, and the other method is to perform arithmetic operations according to a theoretical formula and perform binarization processing etc. on the result. This method determines the pixel density value of the converted image by applying

In general, the former method, which uses logical operations, is often used because of its ease of processing, and even though the latter method is logically used, there are also cases where the results are replaced with logical operation expressions for processing.

However, the range of practical conversion magnification in which the logical formula can determine the pixel density of the converted image is often at most 1/2 to 2 due to the limitation on the number of pixels of the original image that is referred to during conversion. When enlarged over a wide range, the number of combinations of original image pixels to be referenced increases explosively, making it difficult to reduce the size of the hardware. Furthermore, if the original image pixels to be referred to are restricted within a certain range, the flexibility of the linear density conversion device will be significantly impaired, and furthermore, the image quality will be significantly degraded for the same reason as method (1).

On the other hand, the method of calculating pixel density values through arithmetic operations using theoretical formulas and then binarizing them has wide generality and the processing itself is highly flexible; however, the hardware within the film is large. It has the disadvantage of becoming. This point has been improved to maintain flexibility while being compact.
Furthermore, a linear density converter capable of high-speed processing has been proposed (Japanese Patent Laid-Open No. 56-90375).

In this linear density conversion device, a theoretical formula is set as a kind of smoothing function, and a high-quality converted image can be obtained at any magnification by performing this smoothing processing and then resampling. Conversion processing by smoothing and sampling is a method that can theoretically improve the S/N ratio by appropriately selecting its parameters, and in particular, the similarity of the reduced-converted converted image to the original image is extremely good.

However, even in this linear density converter, major problems remain from a practical standpoint.

In other words, if this linear density conversion device performs normal smoothing processing, resampling, and enlarging conversion,
A problem arises in that the converted image becomes blurred or has a distorted shape. In other words, since enlargement conversion is a process of pre-M1ing information on points for which there is no information to begin with, it is difficult to achieve a satisfactory conversion process using simple smoothing processing. Particularly, the part that spoils the shape is the inclined part, especially the diagonal line consisting of a series of dots, which causes a constriction phenomenon and becomes a dumpling-like shape. Thicker diagonal lines cause the boundary to wave. In addition, smearing occurs in the cross portion of a key shape or a cross shape, resulting in a distorted shape.

As described above, the conventional linear density conversion device as an image processing device has a problem in that diagonal lines, key shapes, cross shapes, etc. cannot be enlarged and converted without deteriorating the image quality.

(Problems to be Solved by the Invention) This invention has been made in response to the above-mentioned circumstances, and an object thereof is to provide an image processing device that can perform image linear density conversion without deteriorating image quality. shall be.

[Structure of the Invention] (Means for Solving the Problems) The image processing device of the present invention determines the position in the original image corresponding to each pixel of the converted image when linear density conversion or scaling conversion is performed on the original image. A converted pixel position detection means that calculates and outputs the converted pixel position information as converted pixel position information, and an original pixel extraction means that selectively extracts referenced original pixel information from original pixels around the position determined by the converted pixel position detection means. a pattern detection means for detecting a specific pixel pattern of the referenced original pixel information extracted from the original pixel extraction means; and a pattern generation circuit for generating a pixel pattern according to the pattern detected by the pattern detection means. It consists of:

(Operation) The present invention detects a specific pixel pattern in referenced original pixel information and generates a pixel pattern according to the detected pattern.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of a linear density conversion device as an image processing device according to an embodiment of the present invention.

This linear density conversion device includes a conversion pixel position detection circuit 1 that detects the position of a rhombic pixel in an original image, an original pixel extraction circuit 2 that extracts a referenced original pixel, and a specific pattern from the extracted original pixel. a pattern detection circuit 3 that detects a pattern, a pattern generation circuit 4 that generates a higher-definition pattern according to the detected pattern, an input interface 5 that takes in image data, an output interface 6 that outputs image data, The main parts are composed of a control circuit 7 that controls output processing, conversion processing, etc., and an external image data bus 8 and an external CP through which image data is transmitted.
C exchanges control commands, execution parameters, etc. with U
They are connected by a control bus (not shown) that connects the PU bus 9 and the control circuit 7 to other circuits.

Furthermore, this original pixel extraction circuit 2 has a line buffer 2a with a maximum number of reference lines so that reference pixels can be easily selected.
and a pixel extraction circuit 2b that accesses the line buffer 2a.

Next, the specific configuration and operation of the main parts of this embodiment will be explained.

First, the converted pixel position detection circuit l will be explained.

Figures 2 and 3 show the positional relationship between original pixels and converted pixels in the original image during reduction conversion and enlargement conversion, respectively, and the positions of the conversion pixels in the figures indicate the sampling positions during conversion. It is.

When the distance between metal pixels is normalized to 1, the conversion rate is r = 1 / s, where S is the distance between converted pixels in both figures.
...... It is expressed as (1). Also, the sampling position of the j# conversion pixel is i = [s-j] (where [] is a Gauss symbol)...
......(2) From the position where the i-th original pixel satisfying It can be thought of as a position with displacement.

As a result, the converted pixel position detection circuit 1 can be composed of a counter that indicates the coordinate position of the original pixel in synchronization with the transfer of the original pixel, an arithmetic unit that updates the converted pixel position, and a comparator that compares both. It is possible.

Therefore, as shown in FIG. 4, this original pixel position detection circuit 1 has a register 11 that stores the integer part and a register 12 that stores the decimal part of the sampling interval S of the converted image, and updates the sampling position of the converted image. Adder 13.
14, the converted pixel position is stored and the clock CP-CNV
a counter 17 that stores the coordinate position of the original image and is incremented by a clock CP-ORG;
An X-coordinate circuit consisting of a comparator 18 that compares the converted image data stored in 7 and the original pixel and outputs a conversion calculation request signal RQ-CNV when both match, and a Y-coordinate circuit with the same configuration as the comparator 18. It is composed of circuits. Note that the latches 15 and 16 and the counter 17 are initially cleared.

First, in the case of reduction, both latches 15 and 16 are 0 at the initial stage.
Therefore, the conversion calculation request signal RQ-CNV is output, and the conversion calculation is performed. At this time, this conversion calculation request signal RQ
-CNV, the clock CP-CNV is input, and the next converted pixel position is stored in the latch 15.16.

The counter 17 is updated every time the original pixel is sequentially input, and when the value of the latch 15 and the value of the counter 17 match again, the conversion calculation request signal RQ-CNV is output again. Further, at this time, the minute displacement t shown in equation (3) is stored in the latch 16.

In addition, in the case of enlargement, since interpolation is performed between original pixels using multiple pixels, the conversion calculation request signal RQ-CNV is always output, but conversely, the latch 1 in which the converted pixel position is stored
5.16 exceeds the original pixel position in the process of sequential updating, that is, position detection is sequentially processed by using the carry of the adder 14 as the original pixel capture request RQ-INF. Note that the coordinate positions of the converted pixel and the original pixel are cleared each time the end of the line is reached.

Next, the original pixel extraction circuit 2 will be briefly explained.

FIG. 5 is a block diagram of the original pixel extraction circuit 2 of this embodiment. The original pixel extracting circuit 2 consists of four line buffers 21 to 24, a register 25 for storing a portion (4×4) of the reference original pixels, and a multiplexer 26 for rotating the reference original pixels.

This original pixel extraction circuit 2 sequentially stores and shifts the original pixels of each row in line buffers 21 to 24 connected in series, extracts four pixels of each row to a register 25, and outputs a conversion operation request signal RQ-CNV. When received, the 4×4 pixels tt to p44 are subjected to rotation processing by the multiplexer 26, and then the referenced original pixel data q1. ~ Output as Q44.

Furthermore, the rotation processing of this original pixel extraction circuit 2 will be explained. In this embodiment, a specific pattern is detected by referring to 4×4 original pixels. In this case, when the reference pixel is shown in FIG. 6(A), the pattern to be generated at the position of the converted pixel Q1, and when the reference pixel is shown in FIG. 6(B), the pattern to be generated at the converted pixel Q
This is the pattern that should be generated at position 2.

Therefore, in order to eliminate redundancy in pattern detection, in this embodiment, the original pixels are divided into four as shown in FIG.
The reference original pixel is rotated depending on which of these the converted pixel position belongs to, so that all the converted pixel positions are gathered in the second quadrant. Note that the converted pixel position detection circuit 1 determines which divided area this converted pixel position belongs to.
All you have to do is refer to the minute displacement that is output.

Next, an example of the configuration of the pattern detection circuit 3 is shown in FIG. In FIG. 7, pixels qlB, Q22, q23, Q2 after rotation
4. Conditions for generating a diagonal pattern from Q31, q32, q33, and q42 in gate circuit 30 a 130 b s
30 c s 30 d s 31 a 531b,
32.33a, 33b, 33c, 33d.

34a and 34b. A diagonal line is generated when any of the following conditions (Yama to Dogo) are satisfied.

(1) q 22・/q23・/q32・/q33 (
However, φ: and +2 or q22: q22 is black, /: negative) (2)/ q 22 ・q23 ・q32 ・Q33 (
3) / q 22 ・ q 23 ・ q
32 ・ /q 33 ・(q13+q24) ・
(q31+q42) (4) q 22 ・/q23
・/q32 ・q33 ・(/q13+/q24
) ・ (/q31+/q42)q22, Q 23,
FIG. 8 shows the patterns generated in the four-division area near q22 for each combination of q32 and Q33.

The circuit of FIG.
This can be realized using extremely small-scale hardware called an LD (programmable logic device).

Adding additional conditions to the judgment conditions (1) to (4) above,
More accurate diagonal line determination is possible. For example, above (
When diagonal line determination is performed under the determination conditions 1) to (4), as shown in FIGS. 9(a) and 9(b), there is a white diagonal line/black diagonal line determination error near the intersection of diagonal lines in a series of - dots, and Misjudgment occurs,
The image is distorted. A diagonal line pattern detection circuit improved in this respect is shown in FIG. 13, determination conditions (5) to (12) are shown, and images are shown in FIGS. 9(c) and (d).

(5) Same as (1) (6) Same as (2) (7) q 22 ・/q 23 ・/q 32
・q33 ・/(q13 − q24) ・ /
(Q31 ・q42) ・/(Q13 ・q
31) ・/(q 24 ・ q42) (8)/q2
2 ・ q2B ・ q32 ・/q 33 ・
/(/q13 ・/q 24) ・/(/q31
・/q 42 ) ・/(/q13 ・/q3
1) ・/(/q24 ・/Q42) (9) q 22 ・/q23 ・/q32 ・ q
3B ・/q 12 φ/q21 ・/q34 ・/
q43(/Q13 ・/q 24 ・q31 ・
q42+q 1 3・Q 24 ・/q 3
1 ・/q42) (1,0)/q22 ・q23
・q 32 ・/q33 ・q12 ・Q2
1 ・ q34 ・ q43 (Q13 ・q24
・/q 31 ・/ q42 + / q 1
3 ・/q 24 ・ Q31 ・ q42) (1
1) Q22 ・/q 23 ・/q 32 ・
q33 ・(/q13 ・q24 ・/q 3
1 ・ Q42 ・ qll ten q13・/q24・Q
31・/q42・q44) (12)/q22・q
2B ・QB2 ・/q 33 ・(q 13
・/q 24 ・ q31 ・/q42 ・/qll
+/q13 ・q24 ・/q 31 ・/q4
2 ・/q44) In the circuit of FIG. 13, 14 points excluding Q14 and Q41 of the 4×4 reference pixels after rotation are manually input, and then the conditions for generating a diagonal line pattern are determined by gate circuits 40a and 4ob.
, 40C% 40ds 41a, ~41h, 42a,
42b, 43a, 43b, 44.45 a, 45 b
, 46 a, 46 b, 47.48.49a, 4
9b, 50.51a, 51b, 52a-52h, 53a
~53d, 54a, 54b.

It is determined based on 55. When any of the above conditions (5) to (12) is satisfied, a diagonal line detection signal is generated. If this circuit is constructed using general-purpose logic elements, the number of elements will increase compared to the circuit shown in FIG. 7, but if a PLD is used, it can still be realized with one element.

As examples of the configuration of a pattern detection circuit, we have shown examples of -intra-membrane judgment conditions and more rigorous examples. You can choose as appropriate.

For example, when the target of linear density conversion is limited to document images, the configuration shown in FIG. 7 is sufficient because patterns in which - dot series diagonal lines intersect as shown in FIGS. 9(a) and (b) almost never occur. be.

On the other hand, in the case of an image created using a graphics function or the like, the configuration shown in FIG. 13 may be used.

Next, the pattern generation circuit 4 having this configuration will be explained. As shown in FIG. 10, the pattern generation circuit 4 manually generates a boundary line of a diagonal line pattern by slightly displacing the converted pixel position, and an adder 61 generates a boundary line and a boundary line for the nearest pixel q22. EX to invert the white/black in the area beyond the line
- OR circuit 62, depending on the diagonal line detection signal from pattern detection circuit 3, outputs the value of q22 as it is, or outputs the value of q22 as it is, or
1. The selector 63 selects whether to output the diagonal line pattern generated by the EX-OR circuit 62, and the slight displacement of the converted pixel position is inverted and "1" is added to the adder 61 to generate it in a shifted manner. The circuit is connected to an inverter circuit 60 which supplies signals for the operation.

If it is not determined that it is a diagonal line, q22 becomes the value of the i-converted pixel as it is, so the four-division area near q22 becomes a solid white or solid black pattern.

Here, as shown in FIGS. 11(a) and (b), Q 22
If the same boundary line is used to generate diagonal lines when the area is white and black, the diagonal line patterns in adjacent areas will be discontinuous, so when the diagonal lines are enlarged as shown in Figure 11(C), A rippling phenomenon occurs.

In order to prevent this, in the embodiment, a signal that becomes "1#" when q22 is white, that is, Q2 is input to the least significant bit of the adder 61.
By inputting the inverted signal of 2, the result shown in FIG.
As shown in b), the diagonal line boundary when q22 is white is moved closer to Q22 by one unit of minute displacement. This process solves the problem of discontinuity and faithfully reproduces the diagonal lines, as shown in FIG. 12(c). A similar effect can be obtained by shifting the diagonal line pattern when q22 is black.

As another embodiment of the pattern generation circuit, an example in which the EX-OR circuit 62 controls no inversion in place of the selector 63, that is, an AND circuit 71 is provided between the adder 61 and the EX-OR circuit 62. An example is shown in FIG. 14, where q22 generates a white diagonal line and q23 generates a black diagonal line in separate adders 81 and 82, and the diagonal line pattern generated in adder 81 or the diagonal line pattern generated in adder 82 is Inverter circuit 8
The 15th example shows an example in which the selector 83 selects the item inverted in step 4.
As shown in the figure. Also, instead of an adder, an equivalent PLD
Alternatively, a ROM or a combinational circuit may be used.

In the above embodiment, since the minute displacement amount is 3 bits each for X and Y, the resolution of the generated diagonal line is 1/16 of the reference pixel interval, as shown in FIG. Therefore, if the image is enlarged up to 16 times, no jagged edges will appear in the shaded area, and a good image can be obtained.

Next, the operation of this linear density converter will be explained.

First, the original image data to be subjected to the linear density conversion device is externally taken in by the input interface 6 via the image data bus 9. This original image data may be stored in a temporary buffer memory or may be received by a communication means. If this input image data is parallel data, parallel-to-serial conversion is performed at the input interface 6, and the line buffer 2
One pixel at a time is transferred to a.

In synchronization with the transfer of each pixel of the input image data, the conversion pixel position detection circuit 1 executes conversion pixel position detection processing.

When the corresponding position of the converted pixel is detected, the pixel extraction circuit 2b
The reference original pixel data that has been subjected to rotation processing is input from the line buffer 2a to the pattern detection circuit 3 via the line buffer 2a.

On the other hand, 1. Pattern generation circuit 4 is q2
2 is a white diagonal pattern, q22 is a black diagonal pattern, white solid, or black solid, and select the white/solid pattern of the converted pixel.
Decide on black.

Then, this result is sent from the output interface 6 via the image data bus 8 in synchronization with the external device.

[Effects of the Invention] As explained above, according to the present invention, a specific pattern in the referenced original pixel is detected and a pixel pattern is generated accordingly. It is possible to provide an image processing device that can be configured with hardware.

[Brief explanation of the drawing]

1 to 12 show an embodiment of the present invention, in which FIG. 1 is a block diagram showing the overall configuration, FIGS. 2 and 3 are diagrams explaining conversion operations, and FIG. 5 is a block diagram of the converted pixel position detection circuit, FIG. 5 is a block diagram of the original pixel extraction circuit, and FIG. 6 is a diagram explaining rotation processing.
FIG. 7 is a block diagram of the pattern detection circuit, FIG. 8 is a diagram showing the generated pattern, FIG. 9 is a diagram showing the generated pattern in a specific original pixel arrangement, and FIG. 10 is the configuration of the pattern generating circuit in the above embodiment. 11 and 12 are diagrams for explaining output examples of the pattern generation circuit.
Figure 3 is a configuration diagram of a pattern detection circuit in another embodiment,
FIGS. 14 and 15 are configuration diagrams of pattern generation circuits in other embodiments. DESCRIPTION OF SYMBOLS 1... Converted pixel position detection circuit, 2... Original pixel extraction circuit, 2a... Line buffer, 2b... Pixel extraction circuit, 3... Pattern detection circuit, 4... Pattern generation circuit, 5... Input interface, 6... Output interface, 7... Control circuit, 8... External image data bus, 9... CPU bus, q... Pixel. Applicant's agent Patent attorney Takehiko Suzue Figure 1 O000 X X X o 000 Figure 2 Q ○ 0 0 XXXXX XXXXX Figure 3 11 12 13 1
(A) 0 @ 00 (B) Figure 6 Figure 7 r! ! , IiI series Shanabatan Q32
'ni 33 Upper front nosuwoto-22 and circle suitable Figure 8 (a) (b) Figure 10 Figure 14

Claims (5)

[Claims] (1) Converted pixel position detection means that calculates the position in the original image corresponding to each pixel of the converted image when linear density conversion or scaling conversion is performed on the original image and outputs this as converted pixel position information, and this conversion Original pixel extraction means for selectively extracting referenced original pixel information from original pixels around the position determined by the pixel position detection means; and a specific pixel of referenced original pixel information extracted from the original pixel extraction means. An image processing apparatus comprising: a pattern detection means for detecting a pattern; and a pattern generation circuit for generating a pixel pattern according to the pattern detected by the pattern detection means. (2) The image processing apparatus according to claim 1, wherein the pattern detection means detects a diagonal line component in the referenced original pixel information. (3) The image processing apparatus according to claim 1, wherein the pattern generating means generates a diagonal line having an inclination of 45 degrees. (4) The pattern generation means generates a diagonal line by inputting minute displacement amounts in the main scanning direction and sub-scanning direction with respect to the nearest original pixel of the converted pixel position information to an adder, and using the output as a boundary line. An image processing device according to claim 3, characterized in that: (5) Claim 3, characterized in that the pattern generation means generates different boundaries of the diagonal pattern when the nearest original pixel of the converted pixel position information is black and when it is white. The image processing device described.