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JPH01106675A - Mos type solid-stage image pickup element - Google Patents

Mos type solid-stage image pickup element

Info

Publication number
JPH01106675A
JPH01106675A JP62264302A JP26430287A JPH01106675A JP H01106675 A JPH01106675 A JP H01106675A JP 62264302 A JP62264302 A JP 62264302A JP 26430287 A JP26430287 A JP 26430287A JP H01106675 A JPH01106675 A JP H01106675A
Authority
JP
Japan
Prior art keywords
scanning
sub
picture cells
cells
scanning direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62264302A
Other languages
Japanese (ja)
Inventor
Takashi Shinozaki
俊 篠崎
Hiroyuki Miyahara
弘之 宮原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP62264302A priority Critical patent/JPH01106675A/en
Publication of JPH01106675A publication Critical patent/JPH01106675A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To obtain an n-fold magnifying image pickup by composing an imager part in arranging, in a horizontal scanning direction, plural picture cells composed of an LED and an MOSFET arranged in a subscanning direction and supplying subscanning pulses to the picture cells for 1/n stages. CONSTITUTION:In an imager part 4, picture cells 3 four times as many as a valid scanning line for 1 field are arranged in a vertical scanning direction corresponding to a horizontal scanning line and the cell strings are arranged in the horizontal scanning direction. The cell 3 is composed of an LED 1 and an MOSFET 2 and the photoelectric converting output of the LED 1 is removed from the MOSFET 2 by a vertical scanning pulse PV supplied from a vertical driving circuit 5. In such a constitution, the pulse PV is supplied to the cells 3 in a prescribed stage by a magnification designating signal S from a terminal 9. Namely, at the time of a twofold magnification, the pulse PV is supplied to the cells 3 of the adjoining two stages in a vertical direction and a charge obtained at the cells 3 of the two stages is made into the portion of 1 scanning line and swept in a batch. In such a way, the magnifying image can be obtained without lowering a vertical resolution.

Description

【発明の詳細な説明】[Detailed description of the invention]

(産業上の利用分野) 本発明はMOS型固体撮@素子に関し、特に素子自体に
ズーム機能を備えたものである。 (従来の技術) 最近のビデオカメラは、居ながらにして被写体像の大き
さを可変し得るズーム機能を備えている。 そして、従来からこのようなズーム機能は、ビデオカメ
ラにおける光学系のズームレンズを光軸方向に移動させ
たり、あるいはビデオカメラに内蔵されたフレームメモ
リからの映像信号の読み出しを制御することにより実現
されている。 (発明が解決すぺぎ問題点) ところで、上述の従来例の如く、ズームレンズを光軸方
向に移動させてズーミングを行うものでは、ズームレン
ズ及びズームレンズを駆動させる機構が必要となるため
軽量化、小型化及び低コスト化を阻害する要因となる。 一方、フレームメモリを用いてズーミングを行うものに
おいてはこのフレームメモリの消費電力が大きいために
ボータプルタイプのビデオカメラには不向きであり、ま
たA/D(アナ[1グーデジタル)変換器等が必要とな
るため高価なものになってしまう。 (問題点を解決するための手段) 本発明は上述の如き実情に鑑みてt
(Industrial Field of Application) The present invention relates to a MOS type solid-state sensor, and particularly to one in which the device itself has a zoom function. (Prior Art) Recent video cameras are equipped with a zoom function that allows the size of a subject image to be varied while the camera is in the room. Traditionally, such zoom functions have been realized by moving the zoom lens of the optical system of the video camera in the optical axis direction, or by controlling the reading of video signals from the frame memory built into the video camera. ing. (Problems to be solved by the invention) By the way, in the conventional example described above, in which zooming is performed by moving the zoom lens in the optical axis direction, a zoom lens and a mechanism for driving the zoom lens are required, so it is lightweight. This becomes a factor that hinders miniaturization, miniaturization, and cost reduction. On the other hand, cameras that use frame memory for zooming are unsuitable for vertical type video cameras because the power consumption of this frame memory is large, and A/D (analog digital) converters, etc. Because it is necessary, it becomes expensive. (Means for solving the problems) The present invention has been developed in view of the above-mentioned circumstances.

【されたしのであり
、素子自体にズーム機能を備えたMOS型固体搬像素子
を提供することを目的とする。 そして、本発明はこの目的を達成でるために、走査線(
LINE)に対応して副走査方向(一般に垂直走査方向
)に配列された複数のフォトダイオード1とMOSトラ
ンジスタ2とから成るピクチャセル3の列を主走査方向
く一般に水平走査方向)に順次配列して成るイメージヤ
部4と、1電妃MOSトランジスタ2を駆動するための
副走査パルスPvを出力する副走査駆動回路5と、lf
H像倍率に応じて上記副走査パルスPvを副走査方向の
所定の段のビクヂレセル3に供給するデ」−ダ6と、こ
の所定の段のピクチャセル3から取り出された電荷を1
主走査期聞毎に順次出力する掃出し用トランジスタ7と
、この掃出し用トランジスタ7を駆動するだめの主走査
パルスPHを出力する主走査駆動回路8とを備え、被写
体からのR像光を各フォトダイオード1にて光電変換し
て得られた電荷を上記デコーダ6を介して供給される副
走査パルスPvにて駆動される所定段のMOS トラン
ジスタ2及び上記主走査パルスPHに(駆動される掃出
し用トランジスタ7を介して取り出すMOS型固体搬像
素子であって、 副走査方向に配列されるピクチャセル数を走査線の2n
倍(nは2以上の整数)とするとともに、これらピクチ
ャヒル3を各走査線に対して2n個づつ対応させ、 通常撮像時には、上記副走査パルスpvを各走査線に対
応して副走査方向に隣り合う2n段のピクチャセル毎に
供給し、これら2n段のビクチ1νセル3から得られる
各電荷を各走査線分の゛電荷としてまとめて掃き出させ
、 n倍拡大搬像時には、上記副走査パルスpvを01走査
方向に配列されたピクチャセル3のうちの連続した1、
/n段のビクチt?セル毎に供給することによって、こ
れら1/n段のピクチャセル3から得られる各電荷を副
走査方向に隣り合う2段のピクチャセル3のbの毎にま
とめて各走査線分の電荷としてそのまま掃き出させるよ
うにしたことを特徴とするMOS型固体躍像素子を提供
するものである。 (作 用) 上述の如き構成の固体撮像素子によれば、各ピクチャセ
ル3のフォトダイオード1に’Ct17られた電荷の掃
き出しを制御することにより、垂直解像度を落1ことな
く画像の大きさを可変づることかできる。 さらに、MOS型固体@像素子であるため、COD等に
比して電荷の転送時間を極めで短くすることができる。 (実施例) 以下本発明に係るMOS型固体撮像素子の好適な一実施
例を第1図ないし第6図を用いて詳細に説明する。 本実施例に係るMOS型固体撮像素子は、第1図に示す
如くイメージヤ部4ど垂直駆動回路(副走査方向駆動回
路)5とデコーダ6及び水平駆動回路(主走査方向駆動
回路)8とを備えて構成されている。 上記イメージヤ部4には第1図に示す如く、各ホヤ走査
線に対応して垂直走査方向に1フイ一ルド分の有効走査
線の4倍(984個)のピクチャセル3が配列されてお
り、これら垂直走査方向(副走査方向)に連なるピクチ
ャビル列が水平走査方向(主走査方向)に順次配列され
ている。 そして、これらピクチャセル3は第2図に示す如くフt
 t−ダイオード1とHO3トランジスタ2から構成さ
れており、−回の露光により上記各フォトダイオード1
にて光電変換されて得られた電荷は、上記デコーダ6を
介して上記垂直駆動回路5から供給される垂直走査パル
ス(n1走査パルス)pvによって上記HO3トランジ
スタ2から取り出されるようになっている。 また、上記各ピクチャセル3には、第3図に示す如くホ
ワイト(W)、シアン(Cy)。 グリーン(G)、イ]ニロー(Ye)の各色フィルりが
設けられており、奇数段のピクチャセル3にはホワイト
とシアンの各色フィルタが水平走査方向に交互に設けら
れ、同様に偶数段のピクチャセル3にはグリーンとイエ
ロの各色フィルタが水平走査方向に交互に設けられてい
る。 そして、これら色フィルタに対応するピクチャセル3の
フォトダイオード1から得られる電荷に基づいて、 R= ((W−G)−(Cy −Ye ))/2B= 
((W−G)、+ (Cy −Ye )) /2なる式
にて示す如く各走査線毎に赤(R)信号及び青(B)信
号を得ることができるようになっている。 一方、上記デコーダ6は、上記垂直駆動回路5から供給
される垂直走査パルスPvを、入力端子9′を介して供
給される倍率指定信号Sに基づく撮像倍率に応じて所定
の段のピクチャセル3に分配供給するようになっている
。 すなわち、通常撮像時には、上記垂直走査パルスPvを
垂直方向に隣り合う4段のピクチャセル毎に供給し、こ
れら4段のピクチャセル3にて得られる電荷を1走査線
分の電荷としてまとめて掃き出させる。 これにより、通常撮像時には、上記各ピクチャセル3は
第3図(A)に示す如く各走査線(LINE)に対して
垂直方向に連なる4段が対応し、各走査線の電荷は第4
図に示す如く4段のピクチャセル3の内の奇数段目の和
と偶数段目の和とを加えることによって得ることができ
る。 例えば、F2式におけるn+2番目の走査線のW成分は
W (n+2)−1とW(n+2)−2との和として得
ることができ、Cy酸成分Cy (n+2)−1とCV
 (n+2)−2として得ることができる。 これに対して、2倍拡大撮像時には、上記垂直走査パル
スpvを垂直方向にて隣り合う2段のピクチャセル3毎
に供給し、これら2段のピクチャセル3にて得られた電
荷を1走査線分の電荷としてまとめて棉き出させる。 これにより、2倍拡大撮像時には、上記各ピクチャセル
3は第3図(B)に承す如く各走査線に対して垂直走査
方向に連なる2段が対応し、各走査線の電荷は第5図に
示す如く上下にで隣り合うものを加えることによって得
ることができる。 そして、このように得られた各走査線の電荷は、前記掃
出し用トランジスタ7を水平走査パルスPHにて順次駆
動することにより出力端子10から1水平走査線分づつ
取り出される。 なお、上記水平走査パルスPHは、水平方向に配置され
た掃出し用トランジスタ7を1水平走査期間(63,5
μsec )以内に1ぺて駆り】させるものである。 上述の如き構成のMOS型固体撮像素子によって通常の
撮影を行う場合、すなわち拡大倍率が1倍の撮影を行う
場合には、第6図に示す如く、イメージヤ部2の有効画
素領域A1の全面から得られる電荷を用いて各走査線毎
の信@電荷(W+Cy 、G+Ye )を得る。 そして、この場合には第3図(A)に示す如く、各走査
線に4段のピクチャセル3を各々対応さけ1それらピク
チャセル3から掃き出される電荷を、第4図に示す如く
同色の色フィルタが設けられたものどうし、すなわち奇
数段どうしあるいは偶数段どうし加尊し、この加算され
た電荷(例えば(Wn−1+Wn−2) 、  (Cy
n−1+Cyn−2) )をざらに加算して上記掃出し
用トランジスタ7から出力させる。 これにより、各走査線に4段のピクチャセル3を対応さ
せたにもかかわらず、1フイ一ルド分の映像信号に必要
な走査線数の信号電荷(W+CV。 G+YO)を得ることができる。 これに対して、2倍拡大撮像時には第6図に示す如く、
イメージ1/部2の有効画素領域A2における水平走査
方向及び垂直走査方向の各半分の領域△2から得られる
電荷を用いて各走査線毎の信号電荷(W十Cy 、G十
Ye )を得る。 そして、この場合には第3図(B)に示す如く、各走査
線に2段のピクチャセル3を各々対応させ、(れらピク
チャセル3から掃き出される電荷を上記掃出し用トラン
ジスタ7から出力させる。 また、この場合において、第6図中Vt+及びvt3の
期間については、この期間に対応−4る各ピクチャはル
3から掃き出される電荷を図示しないオーバフロードレ
インを介して垂直帰線期間中に捨てる。 一方、図中vt2の期間中については、11t1及び[
1t3の期間に対応するピクチャセル3からJ+iぎ出
される電荷を同様に捨て去り、Ht2の期間に対応する
光電変換素子から局ぎ出される電荷を[記N出し用トラ
ンジスタ7から出力する。 上述の如く、本実施例に係るMOS型固体固体CQ素子
は、1列あたり走査線数の4倍のピクプI7レル3を備
え、通常撮像時には各走査線に対して4段のピクチャヒ
ル3を対応さけて必要とげる各走査線毎に信号電荷を得
るとともに、2倍拡大服像時には各走査線に対して2段
のピッチ12セル3を対応さ往て必要とする各走査線毎
に信Σ〕電荷をi、r、7るようにしたため、いずれの
比像時においても必要とするり−ベての走査線の信号電
荷を1;することができる。 また、2倍拡大搬像時においても各走査線に対して2段
の光電変換素子が対応しているため、垂直解像度が劣化
することはない。 なお、上述の実施例においては拡大倍率として2倍の場
合について説明したが、それ以上の拡大倍率であっても
上述のような効果を得ることができることは当然であり
、例えば4 (n=4)倍の拡大倍率にする場合には4
倍拡大撮像時に各走査線に対しで8(2x4・)段のピ
クチャセルを対応さぼればよい。 (発明の効果) 上述の説明から明らかなように、本発明によれば垂n解
像度を劣化さぼることなく通常撮像とnイ8拡大撮像を
実現することができる。 そして、本発明によればMOS型固体囮像素子の電荷の
痒き出しを制御するだけで上述の如き画像の拡大(ズー
ミング)を行なうことができズームレンズやフレームメ
モリ等が不要となるためビデオカメラ等の装置の小型化
、l1ffi化、低消費電力化を図ることができるとと
もに、ズーミングに要する時間を大幅に短かくすること
ができる。 また、本発明に係る固体搬像系子をズームレンズを備え
たビデオカメラに適用すれば、より大きな拡大倍率を実
現1”ることができる。
[The object of the present invention is to provide a MOS type solid-state image carrier having a zoom function in the element itself. In order to achieve this object, the present invention provides scanning lines (
A row of picture cells 3 each consisting of a plurality of photodiodes 1 and MOS transistors 2 arranged in the sub-scanning direction (generally the vertical scanning direction) corresponding to the LINE (line) is sequentially arranged in the main scanning direction (generally the horizontal scanning direction). a sub-scanning drive circuit 5 that outputs a sub-scanning pulse Pv for driving the MOS transistor 2;
A decoder 6 supplies the sub-scanning pulse Pv to the picture cell 3 at a predetermined stage in the sub-scanning direction in accordance with the H image magnification, and converts the charge taken out from the picture cell 3 at the predetermined stage to 1
It is equipped with a sweeping transistor 7 that sequentially outputs an output in each main scanning period, and a main scanning drive circuit 8 that outputs a main scanning pulse PH to drive this sweeping transistor 7, and converts the R image light from the subject into each photo. The charge obtained by photoelectric conversion in the diode 1 is applied to a predetermined stage of MOS transistor 2 driven by the sub-scanning pulse Pv supplied via the decoder 6 and the main scanning pulse PH (for sweeping It is a MOS type solid-state image carrier that is taken out via a transistor 7, and the number of picture cells arranged in the sub-scanning direction is 2n of the scanning line.
(n is an integer of 2 or more), and 2n of these picture hills 3 are made to correspond to each scanning line. During normal imaging, the sub-scanning pulse pv is applied in the sub-scanning direction corresponding to each scanning line. The charges obtained from the 2n-stage picture cells 3 are collectively swept out as charges for each scanning line. The scanning pulse pv is applied to consecutive 1 of the picture cells 3 arranged in the 01 scanning direction,
/N stage bikuchi t? By supplying each cell, each charge obtained from these 1/n-stage picture cells 3 is collected for each b of two stages of picture cells 3 adjacent in the sub-scanning direction, and is directly converted into a charge for each scanning line. The object of the present invention is to provide a MOS type solid-state dynamic image element characterized in that it is made to sweep out. (Function) According to the solid-state image pickup device having the above-described configuration, the size of the image can be increased without reducing the vertical resolution by controlling the discharge of the charge applied to the photodiode 1 of each picture cell 3. It is possible to make a variable string. Furthermore, since it is a MOS type solid state image element, the charge transfer time can be extremely shortened compared to COD and the like. (Embodiment) A preferred embodiment of the MOS solid-state image sensor according to the present invention will be described in detail below with reference to FIGS. 1 to 6. As shown in FIG. 1, the MOS solid-state image sensor according to this embodiment includes an imager section 4, a vertical drive circuit (sub-scanning direction drive circuit) 5, a decoder 6, and a horizontal drive circuit (main-scanning direction drive circuit) 8. It is configured with. As shown in FIG. 1, in the imager section 4, four times as many (984) picture cells 3 as the effective scanning lines for one field are arranged in the vertical scanning direction corresponding to each Hoya scanning line. These picture building rows that are continuous in the vertical scanning direction (sub-scanning direction) are sequentially arranged in the horizontal scanning direction (main-scanning direction). Then, these picture cells 3 have a bottom as shown in FIG.
It is composed of a T-diode 1 and an HO3 transistor 2, and each photodiode 1 is
The charges obtained by photoelectric conversion are extracted from the HO3 transistor 2 by a vertical scanning pulse (n1 scanning pulse) pv supplied from the vertical drive circuit 5 via the decoder 6. Further, each picture cell 3 has white (W) and cyan (Cy) as shown in FIG. Green (G), yellow (Ye) color filters are provided, and white and cyan color filters are provided alternately in the horizontal scanning direction in the odd-numbered picture cells 3, and similarly, in the even-numbered picture cells 3, white and cyan color filters are provided alternately in the horizontal scanning direction. In the picture cell 3, green and yellow color filters are provided alternately in the horizontal scanning direction. Then, based on the charges obtained from the photodiodes 1 of the picture cells 3 corresponding to these color filters, R= ((W-G)-(Cy-Ye))/2B=
As shown by the formula ((W-G), + (Cy-Ye))/2, a red (R) signal and a blue (B) signal can be obtained for each scanning line. On the other hand, the decoder 6 applies the vertical scanning pulse Pv supplied from the vertical drive circuit 5 to the picture cells 3 of a predetermined stage according to the imaging magnification based on the magnification designation signal S supplied via the input terminal 9'. It is distributed and supplied to That is, during normal imaging, the vertical scanning pulse Pv is supplied to each of four vertically adjacent picture cells, and the charges obtained in the four picture cells 3 are collectively swept as charges for one scanning line. Let it come out. As a result, during normal imaging, each picture cell 3 corresponds to four stages that are vertically connected to each scanning line (LINE), as shown in FIG.
As shown in the figure, it can be obtained by adding the sum of the odd-numbered rows and the sum of the even-numbered rows of the four rows of picture cells 3. For example, the W component of the n+2-th scanning line in the F2 formula can be obtained as the sum of W (n+2)-1 and W (n+2)-2, and the Cy acid component Cy (n+2)-1 and CV
It can be obtained as (n+2)-2. On the other hand, during double enlarged imaging, the vertical scanning pulse pv is supplied to every two vertically adjacent picture cells 3, and the charges obtained in these two stages of picture cells 3 are used for one scan. The electric charge of the line segment is removed all at once. As a result, during double-enlargement imaging, each picture cell 3 corresponds to two stages that are continuous in the vertical scanning direction with respect to each scanning line, as shown in FIG. It can be obtained by adding the adjacent ones above and below as shown in the figure. The charges of each scanning line thus obtained are taken out from the output terminal 10 one horizontal scanning line at a time by sequentially driving the sweeping transistor 7 with a horizontal scanning pulse PH. Note that the horizontal scanning pulse PH causes the sweeping transistor 7 arranged in the horizontal direction to move during one horizontal scanning period (63, 5
1 peso drive] within 1 μsec). When performing normal photography using the MOS type solid-state image sensor configured as described above, that is, when performing photography at a magnification of 1x, the entire effective pixel area A1 of the imager section 2 is captured as shown in FIG. The signals @charges (W+Cy, G+Ye) for each scanning line are obtained using the charges obtained from . In this case, as shown in FIG. 3(A), four rows of picture cells 3 are associated with each scanning line, and the charges swept out from the picture cells 3 are divided into the same color as shown in FIG. Those provided with color filters, that is, odd-numbered stages or even-numbered stages, are added together, and the added charges (for example, (Wn-1+Wn-2), (Cy
n-1+Cyn-2)) is roughly added and output from the sweep transistor 7. As a result, even though each scanning line is associated with four stages of picture cells 3, the number of signal charges (W+CV, G+YO) required for one field of video signals can be obtained. On the other hand, as shown in FIG.
Signal charges (W0Cy, G0Ye) for each scanning line are obtained using charges obtained from each half area Δ2 in the horizontal scanning direction and vertical scanning direction in the effective pixel area A2 of image 1/part 2. . In this case, as shown in FIG. 3(B), two stages of picture cells 3 are made to correspond to each scanning line (charges swept out from these picture cells 3 are outputted from the above-mentioned sweeping transistor 7). In addition, in this case, for the periods Vt+ and vt3 in FIG. On the other hand, during the period vt2 in the figure, 11t1 and [
The charges J+i discharged from the picture cell 3 corresponding to the period 1t3 are similarly discarded, and the charges discharged from the photoelectric conversion element corresponding to the period Ht2 are outputted from the transistor 7 for outputting N. As mentioned above, the MOS type solid state CQ element according to this embodiment has four picture hills 3 per column as many as the number of scanning lines, and four stages of picture hills 3 for each scanning line during normal imaging. In addition to obtaining a signal charge for each scanning line that is required to avoid correspondence, in the case of a double magnification image, two stages of pitch 12 cells 3 are provided for each scanning line. ] Since the charges are made to be i, r, and 7, the signal charges of all the necessary scanning lines can be reduced to 1 in any ratio image. Further, even during double magnification image transport, since two stages of photoelectric conversion elements correspond to each scanning line, the vertical resolution does not deteriorate. In the above embodiment, the case where the magnification is 2 times has been explained, but it is natural that the above-mentioned effect can be obtained even if the magnification is higher than that, for example, 4 (n=4 ) to increase the magnification by 4
At the time of double-enlarged imaging, it is sufficient to correspond to eight (2×4·) rows of picture cells for each scanning line. (Effects of the Invention) As is clear from the above description, according to the present invention, normal imaging and enlarged imaging can be realized without deteriorating the vertical resolution. According to the present invention, the image can be enlarged (zoomed) as described above simply by controlling the generation of electric charges in the MOS type solid-state decoy image element, and a zoom lens, frame memory, etc. are not required. Devices such as cameras can be downsized, integrated, and consume less power, and the time required for zooming can be significantly shortened. Furthermore, if the solid-state image carrier according to the present invention is applied to a video camera equipped with a zoom lens, a larger magnification of 1'' can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るMOS型固体搬像素子の一実施例
を模式的に示す図、第2図は同じ<MOS型固体11υ
像素子のピクチャセルの構成を示す図、第3図はMOS
型固体撮像素子のカラーフィルタの配置を模式的に示1
図であり、第3図(A)は通常撮像時、第3図(B)は
2倍拡大撮像時を各々示す図、第4図は通常1fi1m
時の出力を模式的に示す図、第5図は同じく2倍拡大撮
像時の出力を模式的に示す図、第6図はイメージヤ部の
通常搬像時と2倍拡大撮像時の使用分部を模式的に示す
図である。 1・・・フォトダイオード、2・・・HO3トランジス
タ、3・・・ピクチャセル、4・・・イメージヤ部、5
・・・副走査駆動回路(垂直駆動回路)、6・・・デコ
ーダ、7・・・掃出し用トランジスタ、8・・・主走査
方向駆動回路(水平駆動回路)。 、  第3図(F3)
FIG. 1 is a diagram schematically showing an embodiment of a MOS type solid image carrier according to the present invention, and FIG.
A diagram showing the configuration of a picture cell of an image element, FIG. 3 is a MOS
1 schematically shows the arrangement of color filters in a type solid-state image sensor.
3(A) is a diagram showing normal imaging, FIG. 3(B) is a diagram showing 2 times enlarged imaging, and FIG. 4 is a diagram showing normal imaging.
Figure 5 is a diagram schematically showing the output during 2x magnification imaging, and Figure 6 is the imager section used during normal image transport and 2x magnification imaging. FIG. DESCRIPTION OF SYMBOLS 1... Photodiode, 2... HO3 transistor, 3... Picture cell, 4... Imager part, 5
... Sub-scanning drive circuit (vertical drive circuit), 6... Decoder, 7... Sweeping transistor, 8... Main-scanning direction drive circuit (horizontal drive circuit). , Figure 3 (F3)

Claims (1)

【特許請求の範囲】  走査線に対応して副走査方向に配列された複数のフォ
トダイオードとMOSトランジスタとから成るピクチャ
セルの列を主走査方向に順次配列して成るイメージャ部
と、上記MOSトランジスタを駆動するための副走査パ
ルスを出力する副走査駆動回路と、撮像倍率に応じて上
記副走査パルスを副走査方向の所定の段のピクチャセル
に供給するデコーダと、この所定の段のピクチャセルか
ら取り出された電荷を1主走査期間毎に順次出力する掃
出し用トランジスタと、この掃出し用トランジスタを駆
動するための主走査パルスを出力する主走査駆動回路と
を備え、被写体からの撮像光を各フォトダイオードにて
光電変換して得られた電荷を上記デコーダを介して供給
される副走査パルスにて駆動される所定段のMOSトラ
ンジスタ及び上記主走査パルスにて駆動される掃出し用
トランジスタを介して取り出すMOS型固体撮像素子で
あって、 副走査方向に配列されるピクチャセル数を走査線の2n
倍(nは2以上の整数)とするとともに、これらピクチ
ャセルを各走査線に対して2n個づつ対応させ、 通常撮像時には、上記副走査パルスを各走査線に対応し
て副走査方向に隣り合う2n段のピクチャセル毎に供給
し、これら2n段のピクチャセルから得られる各電荷を
各走査線分の電荷としてまとめて掃き出させ、 n倍拡大撮像時には、上記面走査パルスを副走査方向に
配列されたピクチャセルのうちの連続した1/n段のピ
クチャセル毎に供給することによって、これら1/n段
のピクチャセルから得られる各電荷を副走査方向に隣り
合う2段のピクチャセルのもの毎にまとめて各走査線分
の電荷としてそのまま掃き出させるようにしたことを特
徴とするMOS型固体撮像素子。
[Scope of Claims] An imager section comprising a row of picture cells each consisting of a plurality of photodiodes and MOS transistors arranged in the sub-scanning direction corresponding to a scanning line and arranged in sequence in the main-scanning direction; and the MOS transistors. a sub-scanning drive circuit that outputs sub-scanning pulses for driving the sub-scanning pulses; a decoder that supplies the sub-scanning pulses to picture cells in a predetermined stage in the sub-scanning direction according to the imaging magnification; and picture cells in the predetermined stage. It is equipped with a sweeping transistor that sequentially outputs the charge taken out from the camera every main scanning period, and a main scanning drive circuit that outputs a main scanning pulse to drive the sweeping transistor, and a main scanning drive circuit that outputs a main scanning pulse to drive the sweeping transistor. The charges obtained by photoelectric conversion by the photodiode are transferred through a predetermined stage of MOS transistors driven by the sub-scanning pulses supplied via the decoder and a sweeping transistor driven by the main-scanning pulses. The number of picture cells arranged in the sub-scanning direction of the MOS solid-state image sensor to be taken out is 2n of the scanning line.
(n is an integer of 2 or more), and 2n of these picture cells are made to correspond to each scanning line. During normal imaging, the above-mentioned sub-scanning pulses are applied to each scanning line adjacent to each other in the sub-scanning direction. The charges obtained from the 2n picture cells are collectively swept out as charges for each scanning line, and when imaging is enlarged by n times, the surface scanning pulse is applied in the sub-scanning direction. By supplying each charge to each successive 1/n stage of picture cells among the picture cells arranged in the 1/n stage, each charge obtained from these 1/n stage picture cells is applied to two adjacent stage picture cells in the sub-scanning direction. 1. A MOS type solid-state imaging device characterized in that the charges are collected for each scanning line and are swept out as they are.
JP62264302A 1987-10-20 1987-10-20 Mos type solid-stage image pickup element Pending JPH01106675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62264302A JPH01106675A (en) 1987-10-20 1987-10-20 Mos type solid-stage image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62264302A JPH01106675A (en) 1987-10-20 1987-10-20 Mos type solid-stage image pickup element

Publications (1)

Publication Number Publication Date
JPH01106675A true JPH01106675A (en) 1989-04-24

Family

ID=17401287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62264302A Pending JPH01106675A (en) 1987-10-20 1987-10-20 Mos type solid-stage image pickup element

Country Status (1)

Country Link
JP (1) JPH01106675A (en)

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