JPH01106463A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01106463A JPH01106463A JP62262673A JP26267387A JPH01106463A JP H01106463 A JPH01106463 A JP H01106463A JP 62262673 A JP62262673 A JP 62262673A JP 26267387 A JP26267387 A JP 26267387A JP H01106463 A JPH01106463 A JP H01106463A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film resistor
- substrate
- interlayer insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
し産業上の利用分野］
この発明は半導体装置に関し、特に薄膜抵抗が形成され
る半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a thin film resistor is formed.
［従来の技術］
第３図は従来の装置を示す断面図、第４図はその平面図
である。これらの図において１は基板、２は層間絶縁膜
、３は薄膜抵抗、４は配線物質、５は層間絶縁膜である
。[Prior Art] FIG. 3 is a sectional view showing a conventional device, and FIG. 4 is a plan view thereof. In these figures, 1 is a substrate, 2 is an interlayer insulating film, 3 is a thin film resistor, 4 is a wiring material, and 5 is an interlayer insulating film.
図に示すような薄膜抵抗の製造方法等については従来よ
く知られているので一般的な説明は省略する。Since the method of manufacturing a thin film resistor as shown in the figure is well known, a general explanation will be omitted.
［発明が解決しようとする問題点］
第３図、第４図に示す従来の装置では、外部から薄膜抵
抗３の位置まで水が侵入することがあり、その場合、薄
膜抵抗３に与えられているバイアス電位のため電解現象
が起こり、薄膜抵抗３を構成する一部の物質がイオン化
して水の中に流れだし、その結果、薄膜抵抗３の抵抗値
が変化するという問題があった。この発明は従来のもの
における上述の問題点を解決するためになされたもので
、薄膜抵抗３を構成する一部の物質のイオン化を防止す
ることが出来る半導体装置を提供することを目的とする
。[Problems to be Solved by the Invention] In the conventional device shown in FIGS. 3 and 4, water may enter from the outside to the position of the thin film resistor 3, and in that case, the water applied to the thin film resistor 3 is There was a problem in that an electrolytic phenomenon occurred due to the bias potential, and some substances constituting the thin film resistor 3 were ionized and flowed into the water, resulting in a change in the resistance value of the thin film resistor 3. The present invention was made to solve the above-mentioned problems in the conventional device, and an object of the present invention is to provide a semiconductor device that can prevent ionization of a part of the material constituting the thin film resistor 3.
［問題点を解決するための手段］
この発明では、基板の平面に垂直な方向に溝を堀り、こ
の渭に薄膜抵抗を形成し、薄膜抵抗の端子となる配線物
質以外の部分は層間絶縁膜によって薄膜抵抗を保護した
。[Means for solving the problem] In this invention, a groove is dug in a direction perpendicular to the plane of the substrate, a thin film resistor is formed on this edge, and the portion other than the wiring material that becomes the terminal of the thin film resistor is provided with interlayer insulation. The membrane protected the thin film resistor.
［作用］
薄膜抵抗が基板の表面から遠い位置にあり、層間絶縁膜
で保護されているので、水の侵入の影響を受けることが
少なくなり、また層間絶縁膜の適当な場所に低い電位を
与えてイオン化を避けることが出来る。[Function] Since the thin film resistor is located far from the surface of the substrate and is protected by the interlayer insulating film, it is less affected by water intrusion, and a low potential can be applied to appropriate locations on the interlayer insulating film. ionization can be avoided.
［実施例］
以下、この発明の実施例を図面を用いて説明する。第１
図はこの発明の一実施例を示す断面図、第２図は第１図
の平面図であり、これらの図において、第３図と同一符
号は同−又は相当部分を示し、２０は第３図の２に対応
する層間絶縁膜、３０は第３図の３に対応する薄膜抵抗
、４０は第３図の４に対応する配線物質、５０は第３図
の５に対応する層間絶縁膜、４１は層間絶縁膜５０の上
に形成される配線物質である。[Examples] Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing one embodiment of the present invention, and FIG. 2 is a plan view of FIG. 1. In these figures, the same reference numerals as in FIG. 30 is a thin film resistor corresponding to 3 in FIG. 3; 40 is a wiring material corresponding to 4 in FIG. 3; 50 is an interlayer insulating film corresponding to 5 in FIG. 3; 41 is a wiring material formed on the interlayer insulating film 50.
基板１がシリコン基板である場合は基板１に溝を堀り、
溝の表面を含めて基板１の表面を酸化して層間絶縁膜２
０を形成し、層間絶縁膜２０が形成された溝の中へ薄膜
抵抗３０を形成する。薄膜抵抗３０の表面が大部分基板
１に埋没しているため水の侵入に対し影響を受は難くな
る。If the substrate 1 is a silicon substrate, dig a groove in the substrate 1,
The surface of the substrate 1 including the surface of the groove is oxidized to form an interlayer insulating film 2.
0 is formed, and a thin film resistor 30 is formed in the groove in which the interlayer insulating film 20 is formed. Since most of the surface of the thin film resistor 30 is buried in the substrate 1, it is less susceptible to water intrusion.
また、配線物質４１を低い電位に接続することによって
、薄膜抵抗３０の表面でイオン化現象が起こりにくくな
る。Furthermore, by connecting the wiring material 41 to a low potential, ionization phenomenon is less likely to occur on the surface of the thin film resistor 30.
［発明の効果］
以上のようにこの発明によれば、侵入した水の作用によ
る薄膜抵抗の経年変化を防止することができる。[Effects of the Invention] As described above, according to the present invention, it is possible to prevent the thin film resistor from deteriorating over time due to the action of infiltrated water.
第１図はこの発明の一実施例を示す断面図、第２図は第
１図の装置の平面図、第３図は従来の装置の断面図、第
４図は第３図の平面図。
１・・・基板、２０・・・層間絶縁膜、３０・・・薄膜
抵抗、 ４０．４１・・・それぞれ配線物質、５０・・
・層間絶縁膜。
なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view of the device shown in FIG. 1, FIG. 3 is a sectional view of a conventional device, and FIG. 4 is a plan view of FIG. 3. DESCRIPTION OF SYMBOLS 1... Substrate, 20... Interlayer insulating film, 30... Thin film resistor, 40.41... Wiring material, respectively, 50...
・Interlayer insulation film. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (2)
抵抗、この薄膜抵抗と上記基板との間に形成された層間
絶縁膜、上記溝状に形成された薄膜抵抗の溝の両端近傍
にそれぞれ形成された配線物質、この配線物質の存在場
所を除き上記基板の表面を覆うように形成された層間絶
縁膜を備えた半導体装置。(1) A thin film resistor formed in a groove shape in a direction perpendicular to the plane of the substrate, an interlayer insulating film formed between this thin film resistor and the substrate, and both ends of the groove of the thin film resistor formed in the groove shape. A semiconductor device comprising wiring materials formed in the vicinity thereof, and an interlayer insulating film formed to cover the surface of the substrate except where the wiring materials are present.
に形成された層間絶縁膜は、当該層間絶縁膜の表面に形
成され、薄膜抵抗より低い電位に接続される配線物質を
備えたことを特徴とする特許請求の範囲第１項記載の半
導体装置。(2) The interlayer insulating film formed to cover the surface of the substrate except where the wiring material is present has a wiring material formed on the surface of the interlayer insulating film and connected to a potential lower than the thin film resistance. A semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62262673A JPH01106463A (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62262673A JPH01106463A (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01106463A true JPH01106463A (en) | 1989-04-24 |
Family
ID=17379009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62262673A Pending JPH01106463A (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01106463A (en) |
-
1987
- 1987-10-20 JP JP62262673A patent/JPH01106463A/en active Pending
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