JP7791405B2 - Signal Detection Circuit - Google Patents

Description

The present invention relates to a circuit for detecting a signal.

In communication networks, devices that are not communicating are put into a sleep state to reduce power consumption. By sending a wake-up signal to a device in a sleep state, the device can use the received wake-up signal as a wake-up trigger.

In order to accurately detect a wake-up signal, it is necessary to accurately detect the signal level of the received wake-up signal. Patent Document 1 below discloses a waveform shaping circuit. This waveform shaping circuit compares the signal level of the detected waveform signal with a threshold value.

Japanese Patent Application Publication No. 6-237154

The method disclosed in Patent Document 1 may not be able to stably detect the signal level because the signal level of the waveform signal fluctuates due to DC components. Furthermore, the method in Patent Document 1 includes a diode in one of the circuits for the signal input to the comparator. Therefore, variations in the forward voltage (VF) of the diode may prevent accurate detection of the signal level of the waveform signal.

The object of the present invention is to provide a circuit that can accurately detect signal levels.

A signal detection circuit according to one aspect of the present invention detects the input of an AC signal and includes a signal input circuit, a bias circuit connected to the signal input circuit, a reference voltage generation circuit, and a comparison circuit connected to the signal input circuit and the reference voltage generation circuit. The bias circuit includes a first constant current source connected to a first power supply and a first diode arranged between the first constant current source and a reference potential. The signal input circuit includes a capacitor and a second diode, and the first diode is diode-matched to the second diode. The reference voltage generation circuit includes a second constant current source connected to a second power supply. The comparison circuit detects the AC signal from the magnitude of the signal level generated by the signal input circuit and the reference level generated by the reference voltage generation circuit.

A signal detection circuit according to another aspect of the present invention is a signal detection circuit that detects the input of an AC signal, and includes a signal input circuit, a bias circuit connected to the signal input circuit, and a comparison circuit connected to the signal input circuit and the bias circuit. The bias circuit has a first constant current source connected to a first power supply and a first diode arranged between the first constant current source and a reference potential. The signal input circuit has a capacitor and a second diode, and the first diode is diode-matched to the second diode. The comparison circuit detects the AC signal from the magnitude of the signal level generated by the signal input circuit and a reference level generated based on the bias circuit.

The present invention provides a circuit that can accurately detect signal levels.

FIG. 2 is a block diagram of a signal detection circuit and its periphery according to the embodiment. FIG. 1 is a circuit diagram of a signal detection circuit according to a first embodiment. 1A and 1B are diagrams illustrating a diode according to an embodiment. FIG. 10 is a diagram illustrating the operation of a circuit around a second diode. FIG. 10 is a diagram showing the Ic-Vbe characteristics of a second diode. FIG. 10 is a diagram showing the relationship between the collector-emitter voltage of the second diode and the current flowing through the second diode. FIG. 10 is a circuit diagram of a signal detection circuit according to a second embodiment. 10A and 10B are diagrams illustrating simulation results using the signal detection circuit according to the first embodiment. FIG. 10 is a diagram illustrating a simulation result using the signal detection circuit according to the second embodiment. 1 is a diagram comparing the Ic-Vbe characteristics of a bipolar transistor with the Id-Vgs characteristics of a MOS transistor. FIG. 10 is a circuit diagram of a signal detection circuit according to a third embodiment. FIG. 11 is a sequence diagram illustrating an operation of the signal detection circuit according to the third embodiment. FIG. 2 is a circuit diagram showing a pulse generating circuit. FIG. 4 is a sequence diagram showing the operation of the pulse generating circuit. FIG. 10 is a circuit diagram of a signal detection circuit according to a modified example.

Next, a signal detection circuit SD according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of peripheral circuits including the signal detection circuit SD. The signal detection circuit SD is connected to a communications network. The signal detection circuit SD receives AC signals INP and INN (INN is the opposite-phase waveform of INP) from a remote terminal connected to the communications network. The AC signals INP and INN are differential signals used to wake up circuits connected downstream of the signal detection circuit SD from a sleep state. As shown in FIG. 1, an amplifier is provided upstream of the signal detection circuit SD, which removes the common-mode components of the AC signals INP and INN, and the signal detection circuit SD receives only the differential components of the AC signals INP and INN. Common-mode noise immunity is the immunity required for reliability tests such as noise immunity tests.

In this embodiment, the signal detection circuit SD is described as being installed in a vehicle such as an automobile. The communication network is described as being Ethernet (registered trademark) installed in the vehicle. The signal detection circuit SD receives a wake-up signal from another terminal installed in the vehicle.

(1) First Embodiment Next, a signal detection circuit SD1 (SD) according to a first embodiment will be described. Fig. 2 is a circuit diagram showing the signal detection circuit SD1 according to the first embodiment. As shown in Fig. 2, the signal detection circuit SD1 includes a signal input circuit SG, a bias circuit BA, a reference voltage generation circuit BL, and a comparison circuit CP.

A first power supply P1 is connected to one end of the bias circuit BA. A first constant current source G1 is connected to the first power supply P1, supplying a predetermined current I1 to the bias circuit BA. The bias circuit BA is provided with a first resistor R1 and a first diode D1 located downstream of the first resistor R1. The other end of the bias circuit BA is connected to a reference potential downstream of the first diode D1.

The signal input circuit SG receives AC signals INP and INN. AC couplings (capacitors) C1A and C1B are connected to the signal input circuit SG. The signal input circuit SG also includes a second diode D2A downstream of the AC coupling C1A and a second diode D2B downstream of the AC coupling C1B. The other end of the signal input circuit SG is connected to a reference potential via a constant current source. A predetermined current I2 flows toward the reference potential at the other end of the signal input circuit SG.

Second resistors R2A and R2B are connected to connection node F1 of bias circuit BA. Connection node F1 is connected to connection node F2, which is upstream of first resistor R1. Current I2 flows from connection node F2 to connection node F1. Second resistors R2A and R2B have the same resistance value. Therefore, current I2/2 flows through second resistors R2A and R2B, respectively. Second resistor R2A is connected to the connection node between AC coupling C1A and second diode D2A. Second resistor R2B is connected to the connection node between AC coupling C1B and second diode D2B.

One end of the reference voltage generation circuit BL is connected to a second power supply P2. The reference voltage generation circuit BL is provided with a third resistor R3. A second constant current source G2 is connected to the second power supply P2, and a predetermined current I3 is supplied to the third resistor R3. The downstream end of the third resistor R3 is connected to a reference potential.

The comparison circuit CP includes a comparator COMP. The input voltage to the positive terminal of the comparator COMP is the detection signal voltage VFDC, and the input voltage to the negative terminal of the comparator COMP is the reference signal voltage VREF. The positive terminal of the comparator COMP is connected to the signal input circuit SG downstream of the second diodes D2A and D2B. A capacitor C2 is also connected to the positive terminal of the comparator COMP. The other end of the capacitor C2 is connected to the reference potential.

The negative terminal of comparator COMP is connected to the reference signal voltage VREF upstream of the third resistor R3. The negative terminal of comparator COMP is also connected to capacitor C3. The other end of capacitor C3 is connected to the reference potential.

In the signal detection circuit SD1, the first diode D1 and the second diodes D2A and D2B are diode-matched. That is, the first diode D1 and the second diodes D2A and D2B are configured to have the same diode size and current ratio. That is, the forward voltage VF1 of the first diode D1 and the forward voltages VF2A and VF2B of the second diodes D2A and D2B are adjusted so that VF1 = VF2A = VF2B = VF. In this embodiment, NPN transistors shown in Figure 3 are used as diodes D1, D2A, and D2B. As shown in Figure 3, diodes D1, D2A, and D2B operate as diodes by connecting the base connectors of the NPN transistors. Figure 4 shows the circuit surrounding the second diode D2A. When a forward voltage (VF2A = VF) is applied between the collector and emitter of the second diode D2A, a current IVF flows through the second diode D2A. The current is converted from AC to DC in the second diode D2A. The second diode D2B performs a similar operation.

The operation of the signal detection circuit SD1 configured as described above will be described. The DC components of the AC signals INP and INN input by the signal input circuit SG are removed by AC couplings C1A and C1B, respectively. A bias voltage is applied to the AC signals INP and INN from which the DC components have been removed by the bias circuit BA. The AC signals INP and INN to which the bias voltage has been applied are converted into a DC current IVF by the second diodes D2A and D2B, as shown in Figure 4.

Figure 5 shows the Ic-Vbe characteristics (Ic: collector current, Vbe: base-emitter voltage) of the second diodes D2A and D2B. Figure 6 shows the relationship between the collector-emitter voltage of the second diodes D2A and D2B and the current IVF flowing through the second diodes D2A and D2B. The AC signal in Figure 6 is an AC signal converted by a bias voltage, and the difference between the AC signal and the detection signal voltage VFDC is the collector-emitter voltage. As shown in Figure 5, current flows through the second diodes D2A and D2B when a voltage greater than the threshold voltage, forward voltage VF (= VF1 = VF2A = VF2B), is applied. As shown in Figure 6, the collector-emitter voltage of the second diodes D2A and D2B is initially VF + α. Because the collector-emitter voltage is greater than the forward voltage VF, current IVF flows through the second diodes D2A and D2B. When current IVF flows through second diodes D2A and D2B, charge accumulates in capacitor C2. As shown in Figure 6, as charge accumulates in capacitor C2, the detection signal voltage VFDC at the positive terminal of comparator COMP increases. As the detection signal voltage VFDC increases, the collector-emitter voltage of second diodes D2A and D2B eventually falls below forward voltage VF, and current stops flowing through second diodes D2A and D2B.

Meanwhile, current I3 flowing from the second power supply P2 accumulates charge in capacitor C3. As charge accumulates in capacitor C3, the reference signal voltage VREF at the negative terminal of comparator COMP increases.

Comparator COMP compares the detection signal voltage VFDC and the reference signal voltage VREF. When comparator COMP detects that the detection signal voltage VFDC is greater than the reference signal voltage VREF, it outputs a HIGH signal as its output OUT. This means that the signal detection circuit SD1 has detected an input signal for waking up the downstream circuit.

Here, consider the input differential voltage CompDiff, which is the difference signal between the detection signal voltage VFDC and the reference signal voltage VREF when the influence of the AC signals INP and INN is eliminated. When the influence of the AC signals INP and INN is eliminated, the circuit configuration of FIG.
VFDC=VF1+(I1-I2)×R1-I2/2×R2A-VF2A
VREF=I3×R3
Therefore,
The input difference voltage CompDiff in the comparator circuit CP is expressed by the following equation.
CompDiff
=VFDC-VREF
=VF1+(I1-I2)×R1-I2/2×R2A-VF2A-I3×R3
...(Formula 1)
In Equation 1, R2A may be replaced by R3A, and VF2A may be replaced by VF2B.

Here, since VF1=VF2A=VF2B, Equation 1 can be rewritten as follows:
CompDiff
=(I1-I2)×R1-I2/2×R2A-I3×R3
...(Equation 2)

In this embodiment, since the forward voltage VF1 of the first diode D1 and the forward voltages VF2A and VF2B of the second diodes D2A and D2B are the same, the term related to the forward voltage is eliminated in the input differential voltage CompDiff, as shown in equation 2. In other words, since the bias circuit BA is provided with the first diode D1, which is diode-matched to the second diodes D2A and D2B provided in the signal input circuit SG, the term related to the forward voltage is eliminated in the input differential voltage CompDiff. Since the input differential voltage CompDiff is independent of PVT (Process, Voltage, Temperature) and exhibits small fluctuations, the comparator circuit CP can purely compare the amplitude values of the AC signals INP and INN. This improves the noise resistance of the product circuit and increases the yield of the product circuit.

In addition, the signal detection circuit SD1 in this embodiment can operate with low current consumption because it uses a DC-converted signal for comparison in the comparison circuit CP. In other words, it is possible to detect the AC signals INP and INN with a small current.

In addition, the signal input circuit SG is provided with AC couplings C1A and C1B, which cut the DC components of the AC signals INP and INN. The operating voltage of the signal detection circuit SD1 is determined by the voltage supplied by the bias circuit BA, so the operation of the comparison circuit CP is not affected by the DC components of the AC signals INP and INN.

(2) Second Embodiment Next, a signal detection circuit SD2 according to a second embodiment will be described with reference to FIG. 7. In the signal detection circuit SD2 of the second embodiment, the same components as those in the signal detection circuit SD1 will not be described, and only the different components will be described. In the signal detection circuit SD2, the signal input circuit SG and the comparator circuit CP have the same configurations as those in the signal detection circuit SD1. Furthermore, the signal detection circuit SD2 does not include a reference voltage generation circuit BL.

As shown in FIG. 7, in the bias circuit BA, a first diode D1 is provided upstream of the first resistor R1. The connection node F2 upstream of the first diode D1 is connected to the connection node F1. The downstream of the first resistor R1 is connected to the reference potential. The negative terminal of the comparator COMP is connected to the bias circuit BA upstream of the first resistor R1 and downstream of the first diode D1.

Here, consider the input differential voltage CompDiff, which is the difference signal between the detection signal voltage VFDC and the reference signal voltage VREF when the influence of the AC signals INP and INN is eliminated. When the influence of the AC signals INP and INN is eliminated, the circuit configuration of FIG.
VFDC=(I1-I2)×R1+VF1-I2/2×R2A-VF2A
VREF=(I1-I2)×R1
Therefore,
The input difference voltage CompDiff in the comparator circuit CP is expressed by the following equation.
CompDiff=VFDC-VREF
=(I1-I2)×R1+VF1-I2/2×R2A-VF2A-(I1-I2)×R1
...(Equation 3)
In Equation 3, R2A may be replaced by R3A, and VF2A may be replaced by VF2B.

Here, since VF1=VF2A=VF2B, equation 3 can be rewritten as follows:
CompDiff
= -I2/2 x R2A
...(Equation 4)

As described above, in the second embodiment, the bias circuit BA is provided with the first diode D1, which is diode-matched to the second diodes D2A and D2B provided in the signal input circuit SG. This eliminates the term related to the forward voltage in the input differential voltage CompDiff. Furthermore, unlike the first embodiment, the detection signal voltage VFDC and the reference signal voltage VREF are determined by the power supplied from the same first power supply P1, so the potential difference across the first resistor R1 in Equation 3 is also canceled. As a result, the only term remaining as the input differential voltage CompDiff is -I2/2 x R2A, allowing the input differential voltage CompDiff to have an extremely small variance. This further effectively reduces fluctuations in the input differential voltage CompDiff, allowing the comparison circuit CP to purely compare the amplitude values of the AC signals INP and INN.

In this embodiment, it is possible to detect the AC signals INP and INN with a small current, for example, on the order of a few μA. Furthermore, because the comparator COMP is operated using a DC-converted signal, the operating speed can be slow, allowing for a circuit design with low current consumption.

(3) Simulation Results and Effects of the Embodiments FIG. 8 shows simulation results illustrating the variance of the input differential voltage CompDiff in the signal detection circuit SD1 of the first embodiment. These simulation results reveal that the variation in the input differential voltage CompDiff in the signal detection circuit SD1 is extremely small. FIG. 9 shows simulation results illustrating the variance of the input differential voltage CompDiff in the signal detection circuit SD2 of the second embodiment. These simulation results reveal that the variance of the input differential voltage CompDiff in the signal detection circuit SD2 is approximately one-fifth of the simulation results for the first embodiment, further reducing the variation in the input differential voltage CompDiff. As shown in FIG. 2, the bias circuit BA and the comparator circuit CP share a constant current source, which effectively reduces the input differential voltage CompDiff.

In the second embodiment, the term −I2/2×R2A (R2B) remains as the input difference voltage CompDiff, where the sense signal voltage VFDC and the reference signal voltage VREF are generated from a common bias voltage V_BS.
VFDC=V_BS-I2/2×R2A-VF2A
VREF=V_BS-VF1
As a result, even when I2 fluctuates relative to I1 due to factors such as mismatch between the first diode D1 and the second diodes D2A and D2B, the input differential voltage CompDiff is corrected so that the fluctuations do not become large. In other words, when I2 increases, I1-I2 decreases, which reduces the reference signal voltage VREF, but the forward voltage VF2A increases, which also reduces the sense signal voltage VFDC. Conversely, when I2 decreases, I1-I2 increases, which increases the reference signal voltage VREF, but the forward voltage VF2A decreases, which also increases the sense signal voltage VFDC. In this way, the variance of the input differential voltage CompDiff can be reduced even with fluctuations in I2.

Furthermore, because the fluctuation in the base-emitter voltage (Vbe voltage) of a bipolar transistor when current I2 fluctuates is smaller than the fluctuation in the source-gate voltage (Vgs voltage) of a CMOS, fluctuations in the input differential voltage CompDiff can be further reduced. Figure 10 compares the Ic-Vbe characteristics (Ic: collector current) of a bipolar transistor with the Id-Vgs characteristics (Id: drain current) of a MOS transistor. As shown in Figure 10, bipolar transistors have smaller voltage fluctuations in response to current fluctuations than MOS transistors. Therefore, bipolar transistors may have an advantage in terms of the range of fluctuations in the input differential voltage CompDiff caused by current variations.

(4) Third Embodiment Next, a signal detection circuit SD3 according to a third embodiment will be described with reference to FIG. 11. In the signal detection circuit SD3 of the third embodiment, the description of the same configuration as the signal detection circuit SD2 will be omitted, and only the different configuration will be described. In the signal detection circuit SD3, the configurations of the signal input circuit SG and the comparison circuit CP are the same as those in the signal detection circuit SD2.

As shown in FIG. 11, the bias circuit BA of the signal detection circuit SD3 includes a fourth resistor R4 upstream of the first resistor R1 and downstream of the first diode D1. A hysteresis voltage selection circuit EA is provided at the negative terminal of the comparator COMP.

The output terminal of the comparator circuit CP of the signal detection circuit SD3 is connected to the hysteresis voltage selection circuit EA and the pulse generation circuit PG. The output terminal of the comparator circuit CP is connected to the first switch element SW1 of the switch circuit SW via connection node F3. An inverter circuit RV is provided between the connection node F3 and the first switch element SW1. The output terminal of the comparator circuit CP is connected to the second switch element SW2 of the switch circuit SW via connection node F4. A first reference level potential VREF_REF is applied to the first switch element SW1 by the bias circuit BA. A second reference level potential VHYS_REF is applied to the second switch element SW2 by the bias circuit BA. A third switch element SW3 is connected to the negative terminal of the comparator COMP. The output signal of the pulse generation circuit PG is applied to the third switch element SW3.

The signal detection circuit SD3 according to the third embodiment has the above configuration, which prevents chattering in the judgment results of the comparison circuit CP. Figure 12 is a timing chart showing the operation of the signal detection circuit SD3. INP-INN indicates a differential signal. In Figure 12, the horizontal axis represents time. First, at time t1, the signal detection circuit SD3 begins receiving the AC signals INP and INN. From the moment the AC signals INP and INN are received, charge begins to accumulate in capacitor C2, and the detection signal voltage VFDC begins to rise.

Before starting to receive the AC signals INP and INN, the comparison circuit CP outputs a LOW signal as the output OUT. The output LOW signal is converted to a HIGH signal by the inverter circuit RV, turning the first switch element SW1 ON. The output LOW signal also turns the second switch element SW2 OFF. As a result, the reference signal voltage VREF becomes the first reference level potential VREF_REF. In other words, the reference signal voltage VREF becomes the first reference level potential VREF_REF, which is determined by the first resistor R1 and the fourth resistor R4.

As shown in Figure 12, the detection signal voltage VFDC rises and, at time t2, reaches the reference signal voltage VREF (VREF_REF). When the detection signal voltage VFDC exceeds the reference signal voltage VREF, the comparison circuit CP outputs a HIGH signal as its output OUT. This provides a HIGH signal to the pulse generation circuit PG.

Figure 13 is a circuit diagram of the pulse generation circuit PG. Figure 14 is a timing chart showing the operation of the pulse generation circuit PG. The pulse generation circuit PG includes an odd number of inverters (IVs) and an AND circuit A1. The signal (HIGH or LOW) provided by the comparison circuit CP is provided to the inverters IV and the AND circuit A1. The signal provided to the inverters IV is inverted because the inverters IV are configured with an odd number of inverters. Until time t2 in Figure 12, the comparison circuit CP outputs a LOW signal, so both a LOW signal and a HIGH signal are provided to the AND circuit A1. Therefore, the AND circuit A1 outputs a LOW signal. After time t2, the comparison circuit CP outputs a HIGH signal. However, because the inverters IV function as a multi-stage delay circuit, during the delay time, the inverters IV outputs a HIGH signal, just as they did before time t2. The output of the inverter circuit IV is shown as td in Figure 14. Therefore, two HIGH signals are given to the AND circuit A1 within the delay time. As a result, the AND circuit A1 outputs a HIGH signal. In Figure 12, the delay time is between times t2 and t3, during which the pulse generation circuit PG outputs a pulse. After the delay time has elapsed, the inverter circuit IV outputs a LOW signal, so a HIGH signal and a LOW signal are given to the AND circuit A1. As a result, the AND circuit A1 outputs a LOW signal.

While a pulse is being output within the delay time of the inverter circuit IV, the pulse generator circuit PG outputs a HIGH signal. As shown in FIG. 11, the signal output from the pulse generator circuit PG is provided to the third switch element SW3. The third switch element SW3 passes current while a HIGH signal is being provided from the pulse generator circuit PG. In other words, the third switch element SW3 passes current through the hysteresis voltage selection circuit EA while a pulse is being output from the pulse generator circuit PG. This releases the charge accumulated in capacitor C3, and as shown in FIG. 12, the reference signal voltage VREF momentarily drops to 0 V.

On the other hand, when the detection signal voltage VFDC exceeds the reference signal voltage VREF, the comparison circuit CP outputs a HIGH signal. The output HIGH signal is converted to a LOW signal by the inverter circuit RV, turning the first switch element SW1 OFF. The output HIGH signal also turns the second switch element SW2 ON. As a result, the reference signal voltage VREF becomes the second reference level potential VHYS_REF. In other words, the reference signal voltage VREF becomes the second reference level potential VHYS_REF (hysteresis voltage) determined by the first resistor R1. As shown in Figure 12, the reference signal voltage VREF, which dropped to 0 V between times t2 and t3, rises to VHYS_REF.

In this way, after the detection signal voltage VFDC exceeds the reference signal voltage VREF, the reference signal voltage VREF drops from VREF_REF to VHYS_REF. This prevents chattering in the determination result of the comparison circuit CP. Furthermore, the moment the detection signal voltage VFDC exceeds the reference signal voltage VREF, the reference signal voltage VREF drops to 0 V. This more effectively prevents chattering in the determination result of the comparison circuit CP. In the above example, the pulse generation circuit PG is configured to include three inverter circuits IV, but the number of inverter circuits IV stages may be any odd number and can be changed as appropriate depending on the pulse width.
(5) Modified Example

Next, a modified signal detection circuit SD4 will be described with reference to Figure 15. The modified signal detection circuit SD4 has a configuration in which the power supply side and the reference potential side are reversed compared to the signal detection circuit SD2 of the second embodiment. As shown in Figure 15, in the signal detection circuit SD4, all terminals connected to the reference potential in the signal detection circuit SD2 are connected to a power supply. That is, power supplies P1A, P2, and P3 are connected to the first resistor R1 and capacitors C2 and C3, and a power supply P4 is connected to one end of the signal input circuit SG. Furthermore, the terminal to which the first power supply P1 is connected in the signal detection circuit SD2 is connected to the reference potential.

Furthermore, while the signal detection circuit SD2 of the second embodiment uses NPN-type transistors as the diodes D1, D2A, and D2B, the signal detection circuit SD4 uses PNP-type transistors as the diodes D1, D2A, and D2B, as shown in the figure. In the signal detection circuit SD2, the diodes D2A and D2B detect the HIGH-side signals of the AC signals INP and INN, while the signal detection circuit SD4 detects the LOW-side signals of the AC signals INP and INN. In other words, by detecting the LOW-side signals of the AC signals INP and INN and causing current to flow through the diodes D2A and D2B, the charge in the capacitor C2 is released. Therefore, in the signal detection circuit SD4 of the modified example, the detection signal voltage VFDC decreases by detecting the LOW-side signals of the AC signals INP and INN. Then, the comparison circuit CP determines that the detection signal voltage VFDC is lower than the reference signal voltage VREF, thereby detecting the wake-up signal.

In this modified example, the power supply side and reference potential side of the signal detection circuit SD2 in the second embodiment are reversed, but the power supply side and reference potential side of the signal detection circuits SD1 and SD3 in the first and third embodiments may also be reversed.

(6) Other Embodiments In the above embodiment, bipolar transistors are used as the diodes D1, D2A, and D2B. In another embodiment, CMOS diodes may be used as the diodes D1, D2A, and D2B.

In the above embodiment, a differential signal is used as the wake-up signal. In another embodiment, a single AC signal can be used as the wake-up signal. In this case, the second signal input circuit SGB can be omitted.

(7) Aspects of the Present Invention <1> As described above, a signal detection circuit according to one aspect of the present invention is a signal detection circuit that detects the input of an AC signal, and includes a signal input circuit, a bias circuit connected to the signal input circuit, a reference voltage generation circuit, and a comparison circuit connected to the signal input circuit and the reference voltage generation circuit, wherein the bias circuit has a first constant current source connected to a first power supply and a first diode arranged between the first constant current source and a reference potential, the signal input circuit has a capacitor and a second diode, and the first diode is diode-matched to the second diode, the reference voltage generation circuit has a second constant current source connected to a second power supply, and the comparison circuit detects the AC signal from the magnitude of the signal level generated by the signal input circuit and the reference level generated by the reference voltage generation circuit.

<2> Another aspect of the present invention provides a signal detection circuit that detects the input of an AC signal, and includes a signal input circuit, a bias circuit connected to the signal input circuit, and a comparison circuit connected to the signal input circuit and the bias circuit. The bias circuit has a first constant current source connected to a first power supply and a first diode arranged between the first constant current source and a reference potential. The signal input circuit has a capacitor and a second diode, and the first diode is diode-matched to the second diode. The comparison circuit detects the AC signal from the magnitude of the signal level generated by the signal input circuit and a reference level generated based on the bias circuit.

<3>
The signal detection circuit according to <2> may further include a first switch element and a second switch element that switch the potential of the reference level depending on the output level of the comparison circuit.

＜4＞
The signal detection circuit described in <3> may further include a pulse generation circuit that generates a pulse signal from the output of the comparison circuit, and a third switch element that switches on and off based on the output of the pulse generation circuit, and the third switch element may be disposed between the first switch element and the second switch element and a reference potential.

<5>
In the signal detection circuit according to <1> or <2>, the AC signal may be a differential signal, the signal input circuit may have a first signal input circuit and a second signal input circuit, the capacitor may be provided in each of the first signal input circuit and the second signal input circuit, the second diode may be provided in each of the first signal input circuit and the second signal input circuit, and the first signal input circuit and the second signal input circuit may join downstream of the second diode provided in each of the first signal input circuit and the second signal input circuit.

<6>
In the signal detection circuit according to any one of <1> to <5>, the first diode and the second diode may be configured by diode-connecting NPN transistors.

<7> Another aspect of the present invention provides a signal detection circuit that detects the input of an AC signal, and includes a signal input circuit, a bias circuit connected to the signal input circuit, and a comparison circuit connected to the signal input circuit and the bias circuit. The bias circuit has a first constant current source connected to a first power supply and a first diode arranged between the first power supply and the first constant current source. The signal input circuit has a capacitor and a second diode, and the first diode is diode-matched with the second diode. The comparison circuit detects the AC signal from the magnitude of the signal level created by the signal input circuit and a reference level created based on the bias circuit.

＜8＞
In the signal detection circuit according to <7>, the first diode and the second diode may be configured by diode-connecting PNP transistors.

SD (SD1-SD4)...signal detection circuit, SG...signal input circuit, BA...bias circuit, BL...reference voltage generation circuit, EA...hysteresis voltage selection circuit, D1...first diode, D2A, D2B...second diode, C1A, C1B...AC coupling (capacitor), CP...comparison circuit, C2, C3...capacitor, P1...first power supply, P2...second power supply, R1...first resistor, R2A, R2B...second resistor, R3...third resistor, R4...fourth resistor, SW...switch circuit, PG...pulse generation circuit, INP, INN...AC signal

Claims (8)

A signal detection circuit for detecting an input of an AC signal,
a signal input circuit;
a bias circuit connected to the signal input circuit;
a reference voltage generating circuit;
a comparison circuit connected to the signal input circuit and the reference voltage generation circuit;
Equipped with
The bias circuit
a first constant current source connected to a first power supply;
a first diode disposed between the first constant current source and a reference potential;
and
The signal input circuit
an AC coupling capacitor for removing a DC component from the AC signal;
a second diode for rectifying the AC signal from which the DC component has been removed ;
and
the forward voltage of the first diode is equal to the forward voltage of the second diode;
the reference voltage generating circuit has a second constant current source connected to a second power supply;
a signal level input to the comparison circuit is generated by rectifying the AC signal by the signal input circuit and smoothing it by a smoothing capacitor, and is determined based on a circuit including a voltage rise across the first diode and a voltage drop across the second diode with respect to the reference potential;
The comparator circuit detects an AC signal based on the magnitude of the signal level input to the comparator circuit and the reference level generated by the reference voltage generator circuit. A signal detection circuit for detecting an input of an AC signal,
a signal input circuit;
a bias circuit connected to the signal input circuit;
a comparison circuit connected to the signal input circuit and the bias circuit;
Equipped with
The bias circuit
a first constant current source connected to a first power supply;
a first diode disposed between the first constant current source and a reference potential;
and
The signal input circuit
an AC coupling capacitor for removing a DC component from the AC signal;
a second diode for rectifying the AC signal from which the DC component has been removed ;
and
the forward voltage of the first diode is equal to the forward voltage of the second diode;
a signal level input to the comparison circuit is generated by rectifying the AC signal by the signal input circuit and smoothing it by a smoothing capacitor, and is determined based on a circuit including a voltage rise across the first diode and a voltage drop across the second diode with respect to the reference potential;
the comparison circuit detects an AC signal based on the magnitude of a signal level input to the comparison circuit and a reference level generated based on the bias circuit;
A signal detection circuit comprising a first switch element and a second switch element that switch the potential of the reference level depending on the output level of the comparison circuit. a pulse generating circuit that generates a pulse signal from the output of the comparison circuit;
a third switch element that switches on and off based on an output of the pulse generating circuit;
Equipped with
3. The signal detection circuit according to claim 2, wherein the third switch element is disposed between the first switch element and the second switch element and a reference potential. the AC signal is a differential signal;
The AC coupling capacitor is
a first capacitor and a second capacitor to which the AC signal, which is a differential signal, is input ;
Including,
The second diode is
two diodes respectively provided downstream of the first capacitor and the second capacitor;
Including,
3. The signal detection circuit according to claim 1, wherein the signal input circuit is connected to the comparison circuit downstream of the two diodes. The signal detection circuit described in any one of claims 1 to 4, wherein the first diode and the second diode are configured by diode-connecting NPN transistors. A signal detection circuit for detecting an input of an AC signal,
a signal input circuit;
a bias circuit connected to the signal input circuit;
a comparison circuit connected to the signal input circuit and the bias circuit;
Equipped with
The bias circuit
a first constant current source connected to a first power supply;
a first diode disposed between the first power supply and the first constant current source;
and
The signal input circuit
an AC coupling capacitor for removing a DC component from the AC signal;
a second diode for rectifying the AC signal from which the DC component has been removed ;
and
the forward voltage of the first diode is equal to the forward voltage of the second diode;
a signal level input to the comparison circuit is generated by rectifying the AC signal by the signal input circuit and smoothing it by a smoothing capacitor, and is determined based on a circuit including a voltage drop across the first diode and a voltage rise across the second diode with respect to the first power supply;
the comparison circuit detects an AC signal based on the magnitude of a signal level input to the comparison circuit and a reference level generated based on the bias circuit;
A signal detection circuit comprising a first switch element and a second switch element that switch the potential of the reference level depending on the output level of the comparison circuit. a pulse generating circuit that generates a pulse signal from the output of the comparison circuit;
a third switch element that switches on and off based on an output of the pulse generating circuit;
Equipped with
7. The signal detection circuit according to claim 6, wherein the third switch element is disposed between the first switch element and the second switch element and a reference potential. 8. The signal detection circuit according to claim 6, wherein the first diode and the second diode are configured by diode-connecting PNP transistors.