JP7786107B2 - Semiconductor Devices - Google Patents

Description

The present invention relates to a semiconductor device having a cell region and a peripheral region surrounding the cell region.

Conventionally, semiconductor devices having a cell region and a peripheral region surrounding the cell region have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor) element having a trench gate structure is formed in the cell region. The MOSFET element is formed, for example, as follows: An n ^- type drift layer is formed on an n ⁺ type drain region, and a p-type base region is formed on the drift layer. An n ⁺ type source region is formed in a surface layer portion of the base region, and a trench gate structure is formed to penetrate the source region and the base region and reach the drift layer. In this semiconductor device, the region where the trench gate structure is formed is defined as the cell region, and the region surrounding this cell region is defined as the peripheral region. Furthermore, in this semiconductor device, a p-type diffusion region is formed in the peripheral region to improve breakdown voltage.

Japanese Patent Application Laid-Open No. 2007-221024

In the semiconductor device described above, a parasitic bipolar transistor is formed by the drift layer, base region, and source region. The inventors are also studying semiconductor devices in which the trench gate structure is a double-gate structure, and are investigating ways to stabilize the avalanche breakdown voltage of such semiconductor devices. A double-gate structure is a structure in which a shield electrode maintained at a predetermined potential and a gate electrode to which a gate voltage is applied are stacked within a trench.

However, according to the inventors' investigations, in the configuration in which a diffusion region is formed in the peripheral region as described above, the shape of the peripheral region differs significantly from the shape of the cell region, and it has been confirmed that the location where avalanche breakdown occurs tends to be non-uniform, and the avalanche breakdown voltage tends to fluctuate.

In view of the above, the present invention aims to provide a semiconductor device that can stabilize avalanche breakdown voltage.

In order to achieve the above object, claims 1 and 2 provide a semiconductor device in which a semiconductor element having a trench gate structure of a double gate structure is formed, the semiconductor element having a cell region (1) in which the semiconductor element is formed, and an outer periphery region (2) surrounding the cell region, the cell region including a drift layer (12) of a first conductivity type, a base region (13) of a second conductivity type formed on the drift layer, an impurity region (14) of the first conductivity type formed in a surface layer portion of the base region and having a higher impurity concentration than the drift layer, a plurality of trenches (15) extending through the impurity region and the base region to reach the drift layer, the trenches (15) extending in one direction as a longitudinal direction and arranged in an arrangement direction intersecting the longitudinal direction, and a plurality of trench gate structures in which buried electrodes (17, 18) are arranged via an insulating film (16), and a base region (13) sandwiching the drift layer. The semiconductor device has a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the base region and having a higher impurity concentration than the drift layer, a first electrode (21) electrically connected to the impurity region and the base region, and a second electrode (22) electrically connected to the high-concentration layer, the region in which the impurity region is formed being a cell region, and a plurality of trench gate structures formed in the cell region have a shield electrode (17) as a buried electrode formed on a shield insulating film (16a) arranged on the bottom side of the trench, and a gate electrode (18) as a buried electrode formed on a gate insulating film (16b) arranged on the opening side of the trench, forming a double-gate structure, the trenches are arranged in a direction intersecting the longitudinal direction, and trenches located on both end sides of the arrangement direction are formed in the peripheral region.
In claim 1, when a predetermined gate voltage is applied to the gate electrode to pass a current between the first electrode and the second electrode, a gate voltage having an absolute value smaller than that of the gate electrode formed in the cell region is applied to the gate electrode formed in the peripheral region.
In claim 2, when a predetermined gate voltage is applied to the gate electrode to pass a current between the first electrode and the second electrode, a gate voltage having a smaller absolute value is applied to the gate electrode located on the outer peripheral region side among the gate electrodes formed in the cell region than to the gate electrode located on the inner edge side.

In this way, because a trench is formed in the part of the peripheral region facing the cell region, it is possible to prevent the configurations of the cell region and the part of the peripheral region facing the cell region from differing significantly, and it is possible to prevent the location of avalanche breakdown from becoming uneven.As a result, it is possible to prevent fluctuations in the avalanche breakdown voltage, and to stabilize the avalanche breakdown voltage.

Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described below.

1 is a plan view of a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment.

Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that in the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

(First embodiment)
A semiconductor device according to a first embodiment will be described with reference to the drawings. The semiconductor device according to the first embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

As shown in FIG. 1, the semiconductor device of this embodiment has a cell region 1 and a peripheral region 2. As will be described in more detail below, the semiconductor device of this embodiment is configured with an n-channel MOSFET element having a source region 14 formed as the semiconductor element. In this embodiment, the cell region 1 and the peripheral region 2 are distinguished by whether or not the source region 14 is formed, with the portion where the source region 14 is formed being the cell region 1. In other words, the portion that actually functions as a MOSFET element is the cell region 1, and the portion that does not function as a MOSFET element is the peripheral region 2. Note that FIG. 1 omits the interlayer insulating film 20 and upper electrode 21, which will be described later. Although FIG. 1 is not a cross-sectional view, the gate insulating film 16b and gate electrode 18, which will be described later, are hatched for ease of understanding.

2, the semiconductor device of this embodiment is formed using a semiconductor substrate 10 having a substrate 11 made of an n ⁺ type silicon substrate or the like with a high impurity concentration. An ^n- type drift layer 12 with a lower impurity concentration than the substrate 11 is formed on the surface of the substrate 11. In this embodiment, the substrate 11 functions as a drain region and corresponds to a high-concentration layer.

A p-type base region 13 with a relatively low impurity concentration is formed in the surface layer of the drift layer 12. The base region 13 is formed, for example, by ion implanting p-type impurities into the drift layer 12, and also functions as a channel layer that forms the channel region. In this embodiment, the base region 13 is formed from the cell region 1 to the peripheral region 2.

An n ⁺ type source region 14 having a higher impurity concentration than the drift layer 12 is provided in the cell region 1 in a surface layer portion of the base region 13. In other words, the cell region 1 in this embodiment is a region in which the source region 14 is formed. The source region 14 is formed between a plurality of trenches 15 described below so as to contact the side surfaces of the trenches 15. The source region 14 is also formed so as to terminate within the base region 13. In this embodiment, the source region 14 corresponds to an impurity region.

A plurality of trenches 15 are formed in the semiconductor substrate 10, penetrating the base region 13 and source region 14 to reach the drift layer 12. The trenches 15 are formed so that they are aligned in one direction, with the longitudinal direction being a direction intersecting the one direction. More specifically, the trenches 15 are aligned in parallel at equal intervals to form a striped layout.

In this embodiment, the two trenches 15 located at both ends in the arrangement direction are formed so as to be located in the peripheral region 2. In other words, these two trenches 15 are not formed so as to contact the source region 14, but are formed so as to penetrate only the base region 13. In FIG. 1, the trenches 15 extend longitudinally from left to right on the page, and are arranged vertically on the page. Furthermore, each trench 15 is formed so that both longitudinal ends protrude from the cell region 1 into the peripheral region 2.

The inner wall surface of the trench 15 is covered with an insulating film 16. In this embodiment, the insulating film 16 includes a shield insulating film 16a that covers the lower portion of the trench 15 and a gate insulating film 16b that covers the upper portion. Specifically, the shield insulating film 16a is formed to cover the side surfaces of the trench 15 from the bottom to the lower portion. The gate insulating film 16b is formed to cover the side surfaces of the upper portion of the trench 15.

A shield electrode 17 and a gate electrode 18 made of doped polysilicon are stacked and arranged within the trench 15, with an insulating film 16 interposed between them. In other words, a double-gate structure is arranged within the trench 15. Specifically, the shield electrode 17 is arranged on the shield insulating film 16a, and the gate electrode 18 is arranged on the gate insulating film 16b. In this embodiment, the shield electrode 17 and the gate electrode 18 correspond to buried electrodes.

In this embodiment, the shield electrode 17 is connected to the upper electrode 21 and is fixed to the source potential. This reduces the gate-drain capacitance in the semiconductor device of this embodiment, improving the electrical characteristics of the MOSFET. The gate electrode 18 performs the switching operation of the MOSFET, and when a gate voltage is applied, a channel region is formed in the base region 13 that contacts the side of the trench 15.

An intermediate insulating film 19 is formed between the shield electrode 17 and the gate electrode 18, thereby insulating the shield electrode 17 from the gate electrode 18. The trench 15, insulating film 16, shield electrode 17, gate electrode 18, and intermediate insulating film 19 form a trench gate structure.

Although not specifically shown, at the longitudinal end of the trench 15, the shield electrode 17 extends further out than the gate electrode 18. The extended portion is then pulled out onto one surface 10a of the semiconductor substrate 10 as a shield liner, and the shield electrode 17 is connected to the upper electrode 21 via the shield liner.

An interlayer insulating film 20 made of an oxide film or the like is formed on one surface 10a of the semiconductor substrate 10 to cover the gate electrode 18. Contact holes 20a are formed in the interlayer insulating film 20 to expose the source region 14 and base region 13. In this embodiment, the contact holes 20a are formed to protrude beyond the source region 14 in the longitudinal direction of the trench 15. In other words, the contact holes 20a are formed to also expose the base region 13 located in the peripheral region 2. However, the contact holes 20a are formed to terminate closer to the cell region 1 than the longitudinal ends of the trench 15. In Figure 1, the contact holes 20a are indicated by dotted lines.

An upper electrode 21, which corresponds to a source electrode, is formed on the interlayer insulating film 20. Specifically, the upper electrode 21 is formed in the cell region 1 so as to be connected to the source region 14 and the base region 13 through the contact hole 20a. The upper electrode 21 is also formed in the peripheral region 2 so as to be connected to the base region 13 through the contact hole 20a. In this embodiment, the upper electrode 21 corresponds to the first electrode.

A lower electrode 22, which corresponds to the drain electrode, is formed on the surface of the substrate 11 opposite the drift layer 12. In other words, the lower electrode 22 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 22 corresponds to the second electrode. With this configuration, the vertical MOSFET of this embodiment is formed.

The above is the configuration of the semiconductor device in this embodiment. In this embodiment, ^n- type, n- type, and n ⁺ type correspond to the first conductivity type, and p- type and p ⁺ type correspond to the second conductivity type. In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, drift layer 12, base region 13, source region 14, etc.

Next, the operation and effects of the semiconductor device described above will be explained. First, in the semiconductor device described above, when a voltage equal to or greater than the threshold voltage of the insulated gate structure is applied to the gate electrode 18, a channel region is formed in the portion of the base region 13 that contacts the trench 15, and current flows between the source and drain, turning the device into an ON state. Furthermore, when the voltage applied to the gate electrode 18 falls below the threshold voltage, the channel region formed in the base region 13 disappears, and the current is cut off, turning the device into an OFF state.

In the semiconductor device described above, a parasitic bipolar transistor is formed by the drift layer 12, base region 13, and source region 14. Therefore, in the semiconductor device described above, when switching from the on state to the off state, avalanche breakdown may occur, causing excessive current to flow between the source and drain.

In this case, in the semiconductor device of this embodiment, a trench gate structure is formed in the peripheral region 2 located in the arrangement direction of the trenches 15, but the source region 14 is not formed. In other words, the peripheral region 2 located in the arrangement direction of the trenches 15 does not function as a MOSFET element, but is configured to have a trench gate structure similar to that of the cell region 1. This prevents the configurations of the cell region 1 and the portion of the peripheral region 2 on the cell region 1 side from differing significantly, and prevents the location of avalanche breakdown from becoming uneven. Specifically, avalanche breakdown is more likely to occur in the cell region 1. This prevents fluctuations in the avalanche breakdown voltage, stabilizing the avalanche breakdown voltage.

In addition, in this embodiment, the contact hole 20a extends to the peripheral region 2. In the peripheral region 2, the base region 13 is electrically connected to the upper electrode 21. Therefore, when the semiconductor device performs avalanche operation, if avalanche breakdown occurs in the peripheral region 2, holes are more likely to be extracted from the upper electrode 21 through the base region 13 in the peripheral region 2. This makes it possible to suppress the operation of a parasitic bipolar transistor and improve the avalanche breakdown voltage.

When the semiconductor device is turned on, the absolute value of the voltage applied to the gate electrode 18 in the periphery region 2 may be set to be smaller than the absolute value of the voltage applied to the gate electrode 18 in the cell region 1. In this way, when the semiconductor device is turned off, the gate electrode 18 in the periphery region 2 falls below the threshold voltage earlier than the gate electrode 18 in the cell region 1, thereby preventing unpredictable operation in the periphery region 2. However, the gate electrode 18 located in the periphery region 2 here refers to the gate electrode 18 located in the trench 15 located at the end of the trench 15 in the arrangement direction.

Furthermore, when the semiconductor device is turned on, the absolute value of the voltage applied to the gate electrode 18 in the cell region 1 may be set so that the absolute value of the voltage applied to the gate electrode 18 located on the outer periphery region 2 side is smaller than the absolute value of the voltage applied to the gate electrode 18 located on the inner edge side. In this way, when the semiconductor device is turned off, the portion of the cell region 1 located on the outer periphery region 2 side is turned off first. This prevents carriers flowing through the cell region 1 in the on state from flowing into the outer periphery region 2, and further prevents avalanche breakdown from occurring at non-uniform locations. Note that the gate electrode 18 located on the outer periphery region 2 side here refers to the gate electrode 18 located in the trench 15 located on the outer periphery region 2 side in the arrangement direction of the trenches 15, among the trenches 15 formed in the cell region 1. The gate electrode 18 located on the inner edge side refers to the gate electrode 18 located in the trench 15 located on the opposite side of the trench 15 from the outer periphery region 2 side in the arrangement direction of the trenches 15, among the trenches 15 formed in the cell region 1.

As described above, in this embodiment, the trenches 15 on both end sides in the arrangement direction of the trenches 15 (i.e., trench gate structures) are formed in the peripheral region 2. This prevents the configurations of the cell region 1 and the portion of the peripheral region 2 on the cell region 1 side from differing significantly, and prevents the location of avalanche breakdown from becoming uneven. This prevents fluctuations in the avalanche breakdown voltage, stabilizing the avalanche breakdown voltage.

(1) In this embodiment, two trenches 15 are located at each end of the trench 15 arrangement direction in the peripheral region 2. This further stabilizes the avalanche breakdown voltage. The inventors have actually conducted studies and confirmed that by arranging two trenches 15 at each end of the trench 15 arrangement direction in the peripheral region 2, the avalanche breakdown voltage can be sufficiently stabilized.

(2) In this embodiment, when the semiconductor device is turned on, the absolute value of the voltage applied to the gate electrode 18 in the peripheral region 2 may be smaller than the absolute value of the voltage applied to the gate electrode 18 in the cell region 1. In this way, when the semiconductor device is turned off, the gate electrode 18 in the peripheral region 2 falls below the threshold voltage earlier than the gate electrode 18 in the cell region 1, thereby preventing unpredictable operation in the peripheral region 2.

(3) In this embodiment, when the semiconductor device is turned on, the absolute value of the voltage applied to the gate electrode 18 in the cell region 1 located on the outer periphery region 2 side may be smaller than the absolute value of the voltage applied to the gate electrode 18 located on the inner edge side. In this way, when the semiconductor device is turned off, the part of the cell region 1 on the outer periphery region 2 side is turned off first. This prevents carriers flowing through the cell region 1 in the on state from flowing into the outer periphery region 2, and further prevents avalanche breakdown from occurring in a non-uniform location.

Second Embodiment
A second embodiment will now be described. This embodiment is different from the first embodiment in that the configuration of the trench gate structure in the peripheral region 2 is changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

In this embodiment, as shown in FIG. 3, no shield electrode 17 is disposed in the trench 15 formed in the peripheral region 2. A gate electrode 18 is disposed in this trench 15 from the opening side to the bottom side. Furthermore, because the gate electrode 18 is disposed in this manner, the insulating film 16 is composed only of the gate insulating film 16b. In other words, in this embodiment, the trench gate structure in the peripheral region 2 is a single-gate structure.

In this embodiment, the portion of the gate insulating film 16b in the peripheral region 2 that contacts the base region 13 is formed to be thicker than the portion of the gate insulating film 16b in the cell region 1 that contacts the base region 13.

In the present embodiment described above, a trench gate structure is formed in the peripheral region 2, but the source region 14 is not formed. Therefore, the same effects as in the first embodiment can be obtained.

(1) In this embodiment, the trench 15 located in the peripheral region 2 is filled with a gate insulating film 16b and a gate electrode 18. The thickness of the portion of the gate insulating film 16b in the peripheral region 2 that contacts the base region 13 is made thicker than the thickness of the portion of the gate insulating film 16b in the cell region 1 that contacts the base region 13. This prevents the gate insulating film 16b from being destroyed in the peripheral region 2, and prevents fluctuations in the avalanche breakdown voltage.

Furthermore, by using a single-gate structure for the peripheral region 2, it is easier to adjust the thickness of the insulating film 16 compared to using a double-gate structure, and the manufacturing process for thickening the insulating film 16 can be prevented from becoming complicated.

(Other embodiments)
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

For example, in each of the above embodiments, an example was described in which two trench gate structures are arranged in the peripheral region 2, but the number of trench gate structures arranged in the peripheral region 2 may be one, or three or more.

In addition, in the above embodiments, examples have been described in which the shield electrode 17 is electrically connected to the upper electrode 21, but the shield electrode 17 may also be connected to another pad portion or the like and maintained at a predetermined potential.

In addition, in the above embodiments, an n-channel trench gate MOSFET with an n-type first conductivity type and a p-type second conductivity type has been described as an example. However, this is merely an example, and a semiconductor switching element of another structure, such as a p-channel trench gate MOSFET in which the conductivity types of each component are inverted from those of an n-channel MOSFET, may also be used. In the case of a p-channel MOSFET, the semiconductor device is turned on by applying a negative voltage less than the threshold voltage of the insulated gate structure to the gate electrode 18. Furthermore, the semiconductor device may be configured such that, in addition to a MOSFET, an IGBT with a similar structure is formed. In the case of an IGBT, the semiconductor device is similar to the vertical MOSFET described in the above embodiments, except that the n ⁺ type substrate 11 in the above embodiments is replaced with a p ⁺ type collector layer.

1 Cell region 2 Peripheral region 11 Substrate (high concentration layer)
12 Drift layer 13 Base region 14 Source region (impurity region)
15 Trench 16 Insulating film 16a Shield insulating film 16b Gate insulating film 17 Shield electrode 18 Gate electrode 21 Upper electrode (first electrode)
22 Lower electrode (second electrode)

Claims (4)

A semiconductor device in which a semiconductor element having a trench gate structure with a double gate structure is formed,
The semiconductor device has a cell region (1) in which the semiconductor element is formed and a peripheral region (2) surrounding the cell region,
The cell area is
a drift layer (12) of a first conductivity type;
a second conductivity type base region (13) formed on the drift layer;
a first conductivity type impurity region (14) formed in a surface layer portion of the base region and having a higher impurity concentration than the drift layer;
a plurality of trench gate structures in which buried electrodes (17, 18) are arranged via insulating films (16) in a plurality of trenches (15) that extend in one direction as a longitudinal direction and that extend through the impurity region and the base region to reach the drift layer, and that are arranged in an arrangement direction that intersects with the longitudinal direction;
a first conductivity type or second conductivity type high concentration layer (11) formed on the opposite side of the drift layer from the base region and having a higher impurity concentration than the drift layer;
a first electrode (21) electrically connected to the impurity region and the base region;
a second electrode (22) electrically connected to the high concentration layer,
a region where the impurity region is formed is defined as the cell region;
The plurality of trench gate structures formed in the cell region have a double gate structure in which a shield electrode (17) as the buried electrode is formed on a shield insulating film (16a) arranged on the bottom side of the trench, and a gate electrode (18) as the buried electrode is formed on a gate insulating film (16b) arranged on the opening side of the trench,
The trenches are formed in the outer periphery region such that the trenches are located on both end sides in the arrangement direction,
A semiconductor device in which, when a predetermined gate voltage is applied to the gate electrode to pass a current between the first electrode and the second electrode, a gate voltage having an absolute value smaller than that of the gate electrode formed in the cell region is applied to the gate electrode formed in the peripheral region . A semiconductor device in which a semiconductor element having a trench gate structure with a double gate structure is formed,
The semiconductor device has a cell region (1) in which the semiconductor element is formed and a peripheral region (2) surrounding the cell region,
The cell area is
a drift layer (12) of a first conductivity type;
a second conductivity type base region (13) formed on the drift layer;
a first conductivity type impurity region (14) formed in a surface layer portion of the base region and having a higher impurity concentration than the drift layer;
a plurality of trench gate structures in which buried electrodes (17, 18) are arranged via insulating films (16) in a plurality of trenches (15) that extend in one direction as a longitudinal direction and that extend through the impurity region and the base region to reach the drift layer, and that are arranged in an arrangement direction that intersects with the longitudinal direction;
a first conductivity type or second conductivity type high concentration layer (11) formed on the opposite side of the drift layer from the base region and having a higher impurity concentration than the drift layer;
a first electrode (21) electrically connected to the impurity region and the base region;
a second electrode (22) electrically connected to the high concentration layer,
a region where the impurity region is formed is defined as the cell region;
The plurality of trench gate structures formed in the cell region have a double gate structure in which a shield electrode (17) as the buried electrode is formed on a shield insulating film (16a) arranged on the bottom side of the trench, and a gate electrode (18) as the buried electrode is formed on a gate insulating film (16b) arranged on the opening side of the trench,
The trenches are formed in the outer periphery region such that the trenches are located on both end sides in the arrangement direction,
A semiconductor device in which, when a predetermined gate voltage is applied to the gate electrode to pass a current between the first electrode and the second electrode, a gate voltage having an absolute value smaller than that of a gate electrode located on the inner edge side is applied to a gate electrode located on the outer edge side of the cell region . In the trench located in the peripheral region, only the gate electrode as the buried electrode is disposed via the gate insulating film,
3. The semiconductor device according to claim 1, wherein the thickness of the gate insulating film in the peripheral region that contacts the base region is made thicker than the thickness of the gate insulating film in the cell region that contacts the base region. 4. The semiconductor device according to claim 1, wherein the number of trenches located in the peripheral region is two or more .