JP7669702B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a silicon carbide (SiC) semiconductor device having a semiconductor element made of SiC.

When forming semiconductor elements such as power devices using SiC substrates, it is necessary to form ohmic electrodes with reduced contact resistance when forming electrodes for connecting the device to electrical circuits, such as the drain electrode on the back side of the substrate in a vertical MOSFET.

Ohmic contact in SiC requires the formation of a metal silicide, which is an alloy layer of SiC and metal. For this reason, a metal film that serves as the contact base material is formed on a SiC substrate, and then high-temperature treatment is performed to form a metal silicide at the interface with the SiC substrate to form an ohmic electrode. However, since SiC contains carbon (C), a carbon layer is precipitated at the interface of the metal silicide during heat treatment. Because the adhesion between this carbon layer and metal is poor, when wiring or electrode pads are formed on an ohmic electrode containing metal silicide, they tend to peel off at the interface between the carbon layer and the metal, reducing the reliability of the device.

For this reason, Patent Document 1 proposes a method of removing the carbon layer that precipitates during the formation of metal silicide by performing plasma etching in an atmosphere containing oxygen gas or argon gas. By performing plasma etching containing oxygen gas, the carbon content is converted to CO or _CO2 and removed, and by performing plasma etching containing argon gas, the upper surface of the electrode is physically etched to remove the carbon content.

JP 2003-243323 A

However, it is difficult to accurately remove the carbon layer using plasma etching, and if it is not completely removed, there is concern that peeling may occur between the ohmic electrode and the wiring or electrode pad formed on it.

In addition, when performing plasma etching that contains argon gas, the upper surface of the electrode is physically etched to remove the carbon, which causes damage to the surface of the ohmic electrode. This raises concerns that the electrical connection between the ohmic electrode and the wiring or electrode pad may deteriorate.

In view of the above, the present invention aims to provide a method for manufacturing a SiC semiconductor device that can suppress peeling between an ohmic electrode containing metal silicide and the wiring and electrode pads formed thereon.

In order to achieve the above object, the invention described in claim 1 is a manufacturing method for a SiC semiconductor device having a SiC semiconductor substrate (101) having a main surface (101a) and a back surface (101b) which is an opposite surface thereof, and an ohmic electrode (113) which is ohmic-contacted to one surface of the SiC on at least one of the main surface side and the back surface side of the SiC semiconductor substrate, the method including: forming a silicon layer (201) on the SiC to be ohmic-contacted; forming a metal film (202) for forming an ohmic electrode on the silicon layer; performing a first heat treatment after forming the metal film to react with the metal film and form a metal silicide layer (202a) by silicidating the metal film; and performing a second heat treatment after the first heat treatment to further advance the formation of the metal silicide layer and silicidize one surface of the silicon carbide, thereby forming an ohmic electrode which becomes a silicide electrode including the metal silicide layer.

In this way, the silicon layer is formed before forming the metal film for forming the ohmic electrode. The first heat treatment reacts the metal film with the silicon layer to form a metal silicide layer, and creates a Si-rich state on the SiC substrate side of the metal silicide layer. Then, the second heat treatment is performed after this, and the SiC substrate side is silicided to form an ohmic electrode including the metal silicide layer.

This makes it possible to suppress the precipitation of a carbon layer at the interface of the metal silicide layer. This makes it possible to suppress peeling between an ohmic electrode containing a metal silicide layer and the wiring or electrode pad formed on it.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

1 is a cross-sectional view of a SiC semiconductor device described in a first embodiment of the present invention. 5A to 5C are cross-sectional views showing a process of forming an ohmic electrode. 2B is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2A. FIG. 2C is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2B. 2C; FIG. 3 is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2C; FIG. 2E is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2D. 1A to 1C are cross-sectional views showing a conventional process for forming an ohmic electrode. FIG. 3B is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 3A.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
First, a SiC semiconductor device according to the present embodiment will be described with reference to Fig. 1. Here, a SiC semiconductor device including a vertical power MOSFET with a trench gate structure as a SiC semiconductor element will be described as an example, but a SiC semiconductor device including other semiconductor elements may be used as long as it has an ohmic electrode formed of a silicide electrode.

Figure 1 shows one cell of a vertical MOSFET. A cell region is formed by arranging multiple vertical MOSFET cells shown in this figure in the left-right direction of the page, and a peripheral breakdown voltage structure (not shown) is provided to surround the cell region, forming a SiC semiconductor device.

As shown in Fig. 1, the SiC semiconductor device is formed using an n ⁺ type substrate 101 made of SiC. The n ⁺ type substrate 101 has a front surface 101a and a back surface 101b which is the opposite surface, and the back surface 101b side corresponds to a drain region connected to a drain electrode 113 which corresponds to a back surface electrode described later, in other words, a back surface high concentration region connected to the back surface electrode. An n ^- type low concentration layer 102 having a lower impurity concentration than the n ⁺ type substrate 101 is epitaxially grown on the front surface 101a of the n ⁺ type substrate 101.

The n ^- type low concentration layer 102 is a narrow JFET portion 102a at a position away from the n ⁺ type substrate 101, and a p-type deep layer 103 is formed on both sides of the JFET portion 102a. The p-type deep layer 103 is configured to have the same thickness as the JFET portion 102a. Furthermore, a p-type base region 104 is formed on the JFET portion 102a and the p-type deep layer 103, and an n ⁺ type source region 105 and a p ⁺ type contact region 106 are formed on the p-type base region 104. The n ⁺ type source region 105 is a surface high concentration region having a higher impurity concentration than the n ^- type low concentration layer 102, and is formed on a portion of the p-type base region 104 corresponding to the JFET portion 102a. The p ⁺ type contact region 106 is configured to have a higher impurity concentration than the p-type base region 104, and is formed on a portion of the p-type base region 104 corresponding to the p-type deep layer 103.

A gate trench 107 is formed, which penetrates the p-type base region 104 and the n ⁺ -type source region 105 and reaches the JFET portion 102a. The above-mentioned p-type base region 104 and n ⁺ -type source region 105 are arranged so as to contact the side surface of the gate trench 107. The gate trench 107 is formed in a line-shaped layout with the left-right direction of the paper surface of FIG. 1 as the width direction, one direction normal to the paper surface as the length direction, and the up-down direction of the paper surface as the depth direction. Although only one gate trench 107 is shown in FIG. 1, multiple gate trenches 107 are arranged at equal intervals in the left-right direction of the paper surface. As shown in FIG. 1, the gate trenches 107 are arranged so as to be sandwiched between the p-type deep layers 103, and are formed in a stripe shape.

In addition, the portion of the p-type base region 104 located on the side of the gate trench 107 is used as a channel region connecting the n ⁺ -type source region 105 and the JFET portion 102a when the vertical MOSFET is in operation. A gate insulating film 108 is formed on the inner wall surface of the gate trench 107 including this channel region. A gate electrode 109 made of doped Poly-Si is formed on the surface of the gate insulating film 108, and the inside of the gate trench 107 is filled with the gate insulating film 108 and the gate electrode 109. This forms a trench gate structure.

An interlayer insulating film 110 is formed on the surface of the n ⁺ type source region 105, the p ⁺ type contact region 106, and the trench gate structure. A source electrode 111 corresponding to a surface electrode and a gate wiring layer (not shown) are formed on the interlayer insulating film 110 as a conductor pattern. A contact hole 110a and the like are formed in the interlayer insulating film 110. The source electrode 111 is electrically connected to the n ⁺ type source region 105 and the p ⁺ type contact region 106 through the contact hole 110a. Although not shown, in a cross section different from that in FIG. 1, the gate wiring layer is electrically connected to the gate electrode 109 through another contact hole.

In addition, a drain electrode 113 corresponding to a back electrode electrically connected to the n ⁺ type substrate 101 is formed on the back surface 101b side of the n ⁺ type substrate 101, that is, on the surface opposite to the side on which the source electrode 111 is formed. The drain electrode 113 is an ohmic electrode composed of a silicide electrode, and is composed of a metal material that can be silicided, such as nickel (Ni), Mo (molybdenum), or titanium (Ti). The metal that composes the drain electrode 113 does not need to be a single type of material, and may be a material that combines two or more of the materials listed here, such as Mo/Ni. The material that composes the drain electrode 113 may also contain impurities.

The drain electrode 113 has a silicided metal silicide layer 202a (see FIG. 2E described later) at the interface with the n ⁺ type substrate 101, and is an ohmic electrode due to being a silicide electrode including the metal silicide layer 202a. Carbon precipitation at the interface of the metal silicide layer 202a included in the drain electrode 113 is suppressed.

This structure constitutes a SiC semiconductor device equipped with an n-channel type inverted trench gate structure vertical MOSFET. Since carbon precipitation is suppressed at the interface of the metal silicide layer 202a included in the drain electrode 113, peeling at the interface of the metal silicide layer 202a included in the drain electrode 113 can be suppressed. This makes it possible to suppress deterioration of the electrical connection between the drain electrode 113 and the wiring or electrode pad (not shown).

Next, a method for manufacturing a SiC semiconductor device configured as described above will be described. However, since the basic manufacturing method for the vertical power MOSFET according to this embodiment is the same as the conventional method, the method for forming the drain electrode 113, which differs from the conventional method, will be mainly described.

The vertical power MOSFET of this embodiment is manufactured through the manufacturing steps shown in Figures 2A to 2E.

First, as shown in FIG. 2A, an n ⁺ type substrate 101 is prepared. The n ⁺ type substrate 101 is manufactured, for example, by slicing an SiC ingot doped with n-type impurities and then polishing it. Then, although not shown, a device formation process is performed to form at least a part of the components of a semiconductor device on the surface 101a side of the n ⁺ type substrate 101. That is, after epitaxially growing the n ^- type low concentration layer 102, a process of forming a p-type deep layer 103 by ion implantation using a mask not shown, and a process of forming a p-type base region 104 by epitaxial growth are performed. In addition, a process of forming an n ⁺ type source region 105 by ion implantation or epitaxial growth, a process of forming a p ⁺ type contact region 106 by ion implantation, a process of forming a gate trench 107 by anisotropic etching, and a process of forming a gate insulating film 108 by thermal oxidation or the like are performed. Further, a process of forming a gate electrode 109 by depositing doped Poly-Si and etching back the same, a process of forming and patterning an interlayer insulating film 110, and a process of forming and patterning a source electrode 111 and a gate wiring layer are performed. Through these processes, the front side structure of the components of the semiconductor element is formed.

After that, although not shown, a thinning process is performed in which a part of the back surface 101b side of the n ⁺ type substrate 101 is removed by grinding and polishing to thin the n ⁺ type substrate 101. For example, the back surface 101b side of the n ⁺ type substrate 101 is turned to the front, and the opposite surface is attached to a glass substrate, and then a part of the back surface 101b side of the n ⁺ type substrate 101 is removed and flattened by performing CMP (Chemical Mechanical Polishing) or the like. Then, a process of forming a drain electrode 113 on the back surface 101b of the thinned n ⁺ type substrate 101 is performed by performing the processes shown in Figures 2B to 2E.

Specifically, as a process shown in FIG. 2B, a Poly-Si layer 201 equivalent to a silicon layer is formed on the back surface 101b of the n ⁺ type substrate 101 after thinning. Then, as a process shown in FIG. 2C, a metal film 202 for forming the drain electrode 113 is formed on the Poly-Si layer 201. The Poly-Si layer 201 may be non-doped Poly-Si that is not doped with impurities, or may be doped Poly-Si that is doped with impurities. The silicon layer is not limited to the Poly-Si layer 201, and may be formed of single crystal silicon. The metal film 202 may be made of Ni, Mo, Ti, or the like, which are metal materials that cause a silicide reaction, and Ni is used here. The thicknesses of the Poly-Si layer 201 and the metal film 202 are arbitrary, but the Poly-Si layer 201 may have a thickness that allows the entire area to be silicided with the metal film 202 in the process shown in FIG. 2D.

Specifically, when the metal film 202 is made of Ni, the thickness of the Poly-Si layer 201 is Tp and the thickness of the metal film 202 is Tm, and the relationship Tp/Tm is set to 0.5 or less. The thickness Tm of the metal film 202 is arbitrary, but can be set to, for example, 100 nm to 200 nm. If the thickness Tm is set to 100 nm, the thickness Tp of the Poly-Si layer 201 should be set to 50 nm or less.

The appropriate value for Tp/Tm depends on the metal material used to form the metal film 202, so it should be determined based on the metal material.

In the next step shown in FIG. 2D, a heating device is used to heat the sample that has been subjected to the steps shown in FIG. 2C as the first heat treatment, thereby causing a reaction between the Poly-Si layer 201 and the metal film 202. For example, heating is performed for 10 minutes or more at a heating temperature of 300 to 350°C. Any heating device may be used, but a heating device that does not affect the surface side structure of the components of the semiconductor element is used. Here, the first heat treatment is performed at a relatively low temperature, and since there is little effect on the surface side structure, the entire sample is heated at once using a heater heating device or the like, but localized heating may also be performed.

This forms a metal silicide layer 202a. When the metal film 202 is made of Ni, the metal silicide layer 202a made of nickel silicide (NiSi) is formed. The metal silicide layer 202a is preferably formed up to the rear surface 101b of the n ⁺ type substrate 101, but may be in a form in which the Poly-Si layer 201 remains between the metal silicide layer 202a and the rear surface 101b of the n ⁺ type substrate 101 at the stage of the process shown in FIG. 2D. In either form, the metal silicide layer 202a on the n ⁺ type substrate 101 side becomes a Si-rich state in which silicon elements are more abundant than carbon elements. In addition, since the metal film 202 is not entirely silicided, the remaining portion 202b of the metal material constituting the metal film 202 remains as it is on the side opposite to the n ⁺ type substrate 101 across the metal silicide layer 202a.

Then, as the step shown in Fig. 2E, a second heat treatment is performed using a heating device. The second heat treatment is performed in a state where the n ⁺ type substrate 101 side of the metal silicide layer 202a is Si-rich due to the step shown in Fig. 2D. This further advances the formation of the metal silicide layer 202a so that the back surface 101b of the n ⁺ type substrate 101 is silicided, and the drain electrode 113 can be formed as a silicide electrode including the metal silicide layer 202a.

The second heat treatment is performed at a higher temperature than the first heat treatment, for example, at a heating temperature of 950 to 1000°C for a time of 10 nsec to 0.1 sec. Any heating device may be used for the second heat treatment, but it is preferable not to affect the front side structure of the components of the semiconductor element. For this reason, it is preferable to use a device that can perform localized heating such as a laser annealing device or a device that can perform instantaneous heating such as a flash lamp annealing device. Here, a different heating device is used for the second heat treatment from the heating device used for the first heat treatment, but the same heating device may be used. In that case, not only can each heat treatment be performed using a common heating device, but transportation between devices is also unnecessary.

In this way, when the second heat treatment is performed in a state where the n ⁺ type substrate 101 side of the metal silicide layer 202a is Si-rich, it is possible to suppress the precipitation of carbon at the interface of the metal silicide layer 202a included in the drain electrode 113. Therefore, it is possible to suppress the peeling at the interface of the metal silicide layer 202a included in the drain electrode 113. This makes it possible to suppress the deterioration of the electrical connection between the drain electrode 113 and the wiring or electrode pad (not shown).

In this way, the drain electrode 113 is formed as shown in FIG. 2E. After this, the SiC semiconductor device is completed by dividing the substrate into chips by dicing (not shown).

As described above, in this embodiment, when forming the drain electrode 113 constituting the silicide electrode, the Poly-Si layer 201 is formed before forming the metal film 202 for forming the drain electrode 113. In addition, by performing a heat treatment at a relatively low temperature as the first heat treatment, the metal film 202 and the Poly-Si layer 201 are reacted to form the metal silicide layer 202a, and the n ⁺ type substrate 101 side of the metal silicide layer 202a is made to be Si-rich. Then, by performing a heat treatment at a higher temperature than the first heat treatment as the second heat treatment after this, the back surface 101b of the n ⁺ type substrate 101 is silicided to form the drain electrode 113 including the metal silicide layer 202a.

This makes it possible to suppress the precipitation of a carbon layer at the interface of the metal silicide layer 202a. This makes it possible to suppress peeling between the drain electrode 113, which constitutes a silicide electrode including the metal silicide layer 202a, and the wiring and electrode pads formed thereon.

In addition, in the case of the conventional manufacturing method, that is, in which the metal film 202 is directly formed on the n ⁺ type substrate 101 as shown in Fig. 3A and then heated at a heating temperature of 950 to 1000°C as a heat treatment, the carbon layer 300 is precipitated on the surface of the metal film 202 including the metal silicide layer 202a as shown in Fig. 3B. For this reason, a process of removing the carbon layer 300 by performing plasma etching is performed.

However, the manufacturing method of this embodiment makes it possible to suppress peeling at the interface of the metal silicide layer 202a, and therefore eliminates the need to remove the carbon layer 300 using plasma etching as in the past. This makes it possible to prevent physical damage to the drain electrode 113 caused by plasma etching, and to suppress deterioration of the electrical connection between the drain electrode 113 and the wiring and electrode pads (not shown) that would otherwise result from this.

Other Embodiments
Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

(1) For example, in the above embodiment, the manufacturing method according to the present invention has been described using an ohmic electrode on the back side of a device in which each component is formed on the front side of a SiC substrate as an example of a silicide electrode. However, the manufacturing method according to the present invention is applicable not only to the case where an ohmic electrode is formed on the back side of a device in which each component is formed on the front side of a SiC substrate. In other words, as long as an ohmic electrode is formed on either the front or back side of a SiC substrate, the method can be applied to any location where an ohmic electrode is formed, for example, to the case where an ohmic electrode is formed on the front side of a SiC substrate. Even in this case, when forming an ohmic electrode after forming each component of the device, it is possible to suppress the influence on the device by using a heating device that can perform local heat treatment, such as a laser annealing device.

(2) In addition, in the above first embodiment, a SiC semiconductor device having a vertical power MOSFET as a semiconductor element is described as an example, but this is also merely one example, and the SiC semiconductor device may have other semiconductor elements such as a diode or an IGBT. In other words, any SiC semiconductor device may be used as long as it has an ohmic electrode for a semiconductor element formed on a SiC semiconductor substrate.

101 n ⁺ type substrate 113 drain electrode 201 Poly-Si layer 202 metal film 202a metal silicide layer

Claims (7)

A method for manufacturing a silicon carbide semiconductor device comprising: a silicon carbide semiconductor substrate (101) having a main surface (101a) and a back surface (101b) opposite thereto; and an ohmic electrode (113) that is ohmic-contacted to one surface of silicon carbide on at least one of the main surface side and the back surface side of the silicon carbide semiconductor substrate, the method comprising:
forming a silicon layer (201) on the silicon carbide to be ohmic-contacted;
forming a metal film (202) for forming the ohmic electrode on the silicon layer;
After forming the metal film, a first heat treatment is performed to react the metal film with the silicon layer and form a metal silicide layer (202a) by silicidating the metal film;
performing a second heat treatment after the first heat treatment to further advance the formation of the metal silicide layer and silicide one surface of the silicon carbide, thereby forming the ohmic electrode with a silicide electrode including the metal silicide layer;
The method for manufacturing a silicon carbide semiconductor device includes: The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first heat treatment is performed to form the metal silicide layer up to a position that reaches the silicon carbide. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein the second heat treatment is performed at a temperature higher than that of the first heat treatment. The first heat treatment is carried out at a heating temperature of 300 to 350° C.,
4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the second heat treatment is performed at a heating temperature of 950 to 1000.degree. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the second heat treatment is performed by laser annealing or flash lamp annealing. In the forming of the metal film, the metal film is made of Ni;
6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein forming the silicon layer and forming the metal film are performed such that Tp/Tm≦0.5, where Tp is a thickness of the silicon layer and Tm is a thickness of the metal film. In the forming of the metal film, the metal film is made of Ni;
7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in forming said silicon layer, said silicon layer is constituted by a Poly-Si layer.

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