JP7646459B2 - Control device and control method - Google Patents

Description

Embodiments of the present invention relate to a control device and a control method.

Generally, renewable energy sources such as solar power generation and wind power generation are connected to a power conversion device that includes a converter and inverter that converts power between DC and AC, and this power conversion device is connected to an AC voltage source such as a power grid.

Power conversion devices often consist of multiple power converters to increase output. In such cases, these multiple power converters are connected in parallel to an AC voltage source such as a power grid.

Patent No. 5180457

When multiple power converters are connected in parallel to an AC voltage source such as a power grid, it is important to maintain the voltage balance of the DC voltage sections of each power converter.

In particular, when each power converter is connected to a renewable energy source such as solar or wind power, where the generated power is prone to fluctuations, the voltage amplitude and phase of the output power are likely to differ significantly between the power converters, and harmonic currents may not be offset between the power converters, resulting in a large amount of harmonics leaking into AC voltage sources such as power grids.

The problem that the present invention aims to solve is to provide a control device and control method that can maintain DC voltage balance between multiple power converters and maintain the harmonic quality of the output voltage.

The control device in an embodiment is a control device that controls a plurality of power converters connected in parallel to an AC voltage source, and includes a signal generating means that determines the level of an overall output voltage pulse that is the sum of individual output voltage pulses for driving each of the plurality of power converters, and then determines the distribution of the levels of the individual output voltage pulses for driving each of the plurality of power converters, and the signal generating means determines the distribution of the levels of the individual output voltage pulses for driving each of the plurality of power converters in accordance with the magnitude relationship of the DC voltages of the plurality of power converters.

The present invention makes it possible to maintain DC voltage balance between multiple power converters and maintain the harmonic quality of the output voltage.

1 is a diagram showing an example of the overall configuration of a system including a plurality of power converters and a microcomputer that controls the power converters according to a first embodiment; 10 is a diagram showing a procedure for generating an output signal pulse according to a conventional technique used for comparison with the first embodiment; FIG. 5A to 5C are diagrams showing a procedure for generating an output signal pulse according to the first embodiment. FIG. 2 is a diagram showing an example of the configuration of various functions realized by the computer 100 shown in FIG. 1 . 5 is a flowchart showing an example of the overall operation of a computer 100 having the various functions shown in FIG. 4 . 6 is a flowchart showing an example of an operation performed in step S2 in FIG. 5 . 6 is a flowchart showing an example of an operation performed in step S3 in FIG. 5 . 6 is a flowchart showing a more specific example of the operation performed in step S3 in FIG. 5 . FIG. 13 is a diagram showing an example of the overall configuration of a system including a plurality of power converters and a microcomputer that controls the power converters according to a second embodiment. FIG. 11 is a diagram showing a procedure for generating an output signal pulse according to a conventional technique used for comparison with the second embodiment. 10A to 10C are diagrams showing a procedure for generating an output signal pulse according to the second embodiment.

The following describes the embodiment with reference to the drawings.

First Embodiment
First, the first embodiment will be described.

Figure 1 shows an example of the overall configuration of a system including multiple power converters and a microcomputer that controls them according to the first embodiment.

As shown in FIG. 1, the system is provided with n power converters 1, 2, ..., n, and further provided with a microcomputer (control device) 100 that controls these. In this embodiment, the power converters 1, 2, ..., n are each described as a three-phase, three-level power converter.

The power converters 1, 2, ..., n are connected in parallel through n insulating transformers Tr, and connected to an AC voltage source Gr corresponding to a three-phase power system. The power converters 1, 2, ..., n are also connected to a renewable energy power source (not shown) such as solar power generation or wind power generation. Note that in FIG. 1, part of the circuit of each power converter connected to the renewable energy power source is not shown. Each power converter includes a converter and an inverter that share a DC voltage section equipped with a capacitor, and the waveform of the power flowing into each power converter is formed by switching the energization state by switching the multiple semiconductor switching elements included in each of these on/off under the control of the microcomputer 100.

In this system, the three-phase output currents _iR1 , iR2, ..., iRn, iS1, _iS2 , ..., _iSn , _iT1 , _iT2 , ..., _iTn (hereinafter abbreviated as output currents iR1 _{... n} , _iS1 ... _n , _{iT1 ... n} ) output respectively from power converters 1, ₂ , _... , n are measured by current sensors not shown, and the measured values are supplied to microcomputer 100.

In addition, in this system, DC voltages _vDC1 , _vDC2 , _... , _vDCn (hereinafter abbreviated as vDC1 _{...n) in the DC voltage sections of each of the power converters 1, 2, ..., n} are measured by voltage sensors (not shown), and the measurement values are supplied to the microcomputer 100.

Microcomputer 100 (hereinafter abbreviated as "computer 100") uses the three-phase output currents iR1 _...n , iS1 _...n , iT1 _...n and DC voltage _vDC1...n measured by each sensor to generate three-phase output voltage pulses _gR1 , gR2, ..., gRn, _gS1 , gS2, ..., _gSn , gT1, gT2, ..., _gTn (hereinafter abbreviated _{as gR1...n, gS1...n , gT1 ... n ) which correspond} to gate signals that _{drive the} gates of the individual _{semiconductor} switching elements of each power converter.

The computer 100 has a function of first determining the levels of the total output voltage pulses gR, gS _, and gT, _{which are} the sum of the output voltage pulses gR1 _{... n} , gS1 _{...n, and gT1...n for each phase, when supplying the output voltage pulses gR1...n , gS1} ...n, and _{gT1 ...n} to the power converters 1, 2, ..., n, and then determining the distribution of the levels of the output voltage pulses gR1 _{... n} , gS1 _...n , and gT1...n according to the magnitude relationship of the DC voltages _vDC1...n of the power converters 1, 2, ..., n. The total output voltage pulses _gR , _gS , and _gT can be said to represent the output voltage pulses when n power converters are collectively regarded as one power converter. The level of this total output voltage pulse is expressed in 2n+1 stages and represents any one of the values n, ..., 0, ..., and -n. The method of deriving the total output voltage pulses _gR , _gS , and _gT will be explained later.

Next, with reference to Figures 2 and 3, we will explain the difference between the procedure for generating an output signal pulse according to the conventional technology and the procedure for generating an output signal pulse according to this embodiment.

To make the explanation easier to understand, we will explain the case where there are two power converters (N=2). Also, of the three phases that make up the R, S, and T phases, only the R phase will be illustrated here, but the same applies to the S and T phases.

In the conventional technology, as shown in FIG. 2, a voltage command value (command value for AC output voltage) v _R1 ^* corresponding to power converter 1 and a voltage command value (command value for AC output voltage) v _R2 ^* corresponding to power converter 2 are used.

2, a comparison is first made between the voltage command value _vR1 ^* corresponding to the power converter 1 and the carrier modulated wave (two triangular waves) _C1 , and a comparison is also made between the voltage command value _vR2 ^* corresponding to the power converter 2 and the carrier modulated wave _C2 (the above-mentioned carrier modulated wave _C1 with its phase shifted by 180°). Then, based on the comparison result between the voltage command value _vR1 ^* and the carrier modulated wave C1, an output voltage pulse _gR1 to be provided to the power converter ₁ is generated, and based on the comparison result between the voltage command value _vR2 ^* and the carrier modulated wave _C2 , an output voltage pulse _gR2 to be provided to the power converter 2 is generated.

For example, in a time period in which the voltage command value _vR1 ^* indicates a positive value, when the voltage command value _vR1 ^* indicates a value greater than the carrier modulation wave (two triangular waves) _C1 , the level of the output voltage pulse _gR1 becomes +1, and otherwise the level of the output voltage pulse _gR1 becomes 0. Also, in a time period in which the voltage command value _vR1 ^* indicates a negative value, when the voltage command value _vR1 ^* indicates a value smaller than the value of the carrier modulation wave (two triangular waves) _C1 , the level of the output voltage pulse _gR1 becomes -1, and otherwise the level of the output voltage pulse _gR1 becomes 0.

Similarly, in a time period in which the voltage command value _vR2 ^* indicates a positive value, when the voltage command value _vR2 ^* indicates a value greater than the carrier modulation wave (two triangular waves) _C2 , the level of the output voltage pulse _gR2 becomes +1, and otherwise the level of the output voltage pulse _gR2 becomes 0. Also, in a time period in which the voltage command value _vR2 ^* indicates a negative value, when the voltage command value _vR2 ^* indicates a value smaller than the value of the carrier modulation wave (two triangular waves) _C2 , the level of the output voltage pulse _gR2 becomes -1, and otherwise the level of the output voltage pulse _gR2 becomes 0.

The output voltage pulse _gR1 of the power converter 1 and the output voltage pulse _gR2 of the power converter 2 are combined to form an output voltage pulse _gR .

2, when comparing the output voltage pulse _gR1 given to the power converter 1 and the output voltage pulse _gR2 given to the power converter 2, the total pulse width when the level is in the +1 state is the same, and the total pulse width when the level is in the -1 state is also the same, so the power flowing into each power converter is also the same. Therefore, when there is a large power difference between the output power of the power converter 1 and the power converter 2, the voltage amplitude, phase, etc. of the output power differs greatly between the power converters, and there is a possibility that a large amount of harmonics will flow into the AC voltage source without canceling out the harmonic currents between the power converters.

On the other hand, in this embodiment, as shown in FIG. 3, a total voltage command value v _R ^* obtained by combining the voltage command values corresponding to the power converters 1 and 2 is used.

First, as shown in Fig. 3, the total voltage command value _vR ^* is compared with a carrier modulated wave (two triangular waves) _C1 , and also with a carrier modulated wave _C2 (the carrier modulated wave _C1 with its phase shifted by 180°) Then, based on the comparison results ^{between the total voltage command value vR*} _and ^the carrier modulated wave _C1 and the comparison results between the total voltage command value _vR ^* and the carrier modulated wave _C2 , _a total output voltage pulse _gR is generated.

For example, in a time period when the overall voltage command value _vR ^* indicates a positive value, when the overall voltage command value _vR ^* indicates a value greater than the carrier modulation wave (two triangular waves) _C1 but does not indicate a value greater than the carrier modulation wave (two triangular waves) _C2 , or when the overall voltage command value vR* indicates a value greater than the carrier modulation wave (two triangular waves) _C2 but does not indicate a value greater than the carrier modulation wave (two triangular waves) _C1 , the level of the overall output voltage pulse _gR becomes +1, when the overall voltage command value _vR ^* indicates a value greater than both of the carrier modulation waves (two triangular waves) _C1 , _C2 , the level of the overall output voltage pulse _gR becomes +2, and otherwise the level of the overall output voltage pulse _gR is 0.

In addition, in a time period when the overall voltage command value _vR ^* indicates a negative value, when the overall voltage command value _vR ^* indicates a value smaller than the carrier modulation wave (two triangular waves) _C1 but does not indicate a value smaller than the carrier modulation wave (two triangular waves) _C2 , or when the overall voltage command value vR _* indicates a value smaller than the carrier modulation wave (two triangular waves) _C2 but does not indicate a value smaller than the carrier modulation wave (two triangular waves) _C1 , the level of the overall output voltage pulse _gR becomes -1, when the overall voltage command value vR ^* indicates a value smaller than both of the carrier modulation waves (two triangular waves) _C1 , _C2 , the level of the overall output voltage pulse _gR becomes -2, and otherwise the level of the overall output voltage pulse _gR becomes 0.

Thereafter, based on the level of the total output voltage pulse _gR , the distribution of the levels of the output voltage pulses _gR1 , _gR2 is determined in accordance with the magnitude relationship between the DC voltages _vDC1 , _vDC2 of the power converters 1, 2, respectively.

In the example of Fig. 3, when the current polarity is from the power converter to the load, and in the region where the total voltage command value _vR ^* indicates a positive value, the gate signal output to the power converter with the largest DC voltage _vDC1...n is prioritized, and the level of each output voltage pulse is determined so that the level of the output voltage pulse (either output voltage pulse _gR1 or _gR2 ) for that power converter is higher than or equal to that of the other power converters. Also, when the current polarity is from the load to the power converter, and in the region where the total voltage command value _vR ^* indicates a negative value, the gate signal output to the power converter with the smallest DC voltage _vDC1...n is prioritized, and the level of each output voltage pulse is determined so that the level of the output voltage pulse (either output voltage pulse _gR1 or _gR2 ) for that power converter is lower than or equal to that of the other power converters. However, the levels of the output voltage pulses _gR1 and _gR2 are controlled to indicate any one of values +1, 0, and -1, and not to be +2 or -2. For example, when the level of the overall output voltage pulse _gR is +2, the levels of the output voltage pulses _gR1 and _gR2 are each set to +1.

That is, when the current polarity is from the power converter to the load, the power converter with a larger DC voltage v _DC1...n is controlled so that the level of the output voltage pulse given is preferentially set to 1, and when the current polarity is from the load to the power converter, the power converter with a smaller DC voltage v _DC1...n is controlled so that the level of the output voltage pulse given is preferentially set to -1. The longer the state in which the output voltage pulse level is +1 continues (i.e., the larger the pulse width of the level +1), the more the discharge from the capacitor of the DC voltage section is promoted and the DC voltage decreases, whereas the longer the state in which the output voltage pulse level is -1 continues (i.e., the larger the pulse width of the level -1), the more the charging of the capacitor of the DC voltage section is promoted and the DC voltage increases.

In the example shown in Fig. 3, when comparing the output voltage pulse _gR1 given to the power converter 1 and the output voltage pulse _gR2 given to the power converter 2, the total amount of the pulse width when the level is in the +1 state is different, and the total amount of the pulse width when the level is in the -1 state is also different, so that the power flowing into each power converter is also different. That is, even when there is a large power difference between the output powers of the power converter 1 and the power converter 2, the power flowing into each power converter is adjusted according to the magnitude relationship between the DC voltages _vDC1 and _vDC2 , so that the DC voltage balance between the power converters is maintained. In this case, the harmonic currents are offset between the power converters, and a large amount of harmonics is prevented from flowing into the AC voltage source Gr.

Figure 4 shows an example of the configuration of various functions realized by the computer 100 shown in Figure 1.

Note that each function shown in FIG. 2 is realized by a program (software) executed by a processor, but some functions may be realized by hardware such as a circuit, if necessary.

As shown in FIG. 4, the computer 100 has, as various functions, an averaging processing unit 11, a subtraction unit 12, a PI control unit 13, averaging processing units 14 to 16, a three-phase DQ conversion unit 17, a subtraction unit 18, a PI control unit 19, a subtraction unit 20, a PI control unit 21, a three-phase DQ inverse conversion unit 22, and a gate signal generation unit (signal generation means) 23.

The averaging processor 11 generates an average value v _DC of the DC voltages (measured values) v _{DC1 . . . n} .

The subtraction section 12 generates the difference between the DC voltage command value v _DC ^* and the average value v _DC of the DC voltage (measured value).

The PI control unit 13 performs PI control using the difference generated by the subtraction unit 12, and generates an active current command value i _D ^* .

The averaging processors 14 to 16 generate average values i _R , i S , and i _T of the three-phase output currents (measured values) i _{R1 . . . n} , i _{S1 . . . n} , and i _T1 .

The three-phase DQ conversion unit 17 performs three-phase DQ conversion using the average values _iR , _iS , and _iT of the three-phase output currents (measured values) to generate an active current _iD and a reactive current _iQ .

The subtraction unit 18 generates the difference between the active current command value i _D ^* and the active current i _D .

The PI control unit 19 performs PI control using the difference generated by the subtraction unit 18, and generates an effective voltage command value v _D ^* .

The subtraction unit 20 generates the difference between the reactive current command value _iQ ^* and the reactive current _iQ .

The PI control unit 21 performs PI control using the difference generated by the subtraction unit 20, and generates a reactive voltage command value v _Q ^* .

The three-phase DQ inverse transform unit 22 performs a three-phase DQ inverse transform using the active voltage command value v _D ^* and the reactive voltage command value v _Q ^* to generate total voltage command values v _R ^* , v _S ^* , and v _T ^* .

The gate signal generating unit 23 uses the overall voltage command values _vR ^* , _vS ^* , _vT ^* as well as the average values _iR , _iS , _iT of the three-phase output currents (measured values) to generate three-phase output voltage pulses gR1 _...n , gS1 _...n , gT1 _...n which correspond to gate signals that drive the gates of the individual semiconductor switching elements of each power converter.

In the example of Fig. 4, the total voltage command values _vR ^* , _vS ^* , _vT ^* are generated based on the result of current control that brings the average values _iR , iS, iT of the output currents iR1 _...n , _{iS1 ... n} , _iT1 ...n of the power converters 1, 2, ..., n closer to the current command value _iD ^* . Also, the current command value ( _iD ^* ) used in the current control is generated based on the result of voltage control that brings the average value vDC of the _DC voltages of the power converters 1, 2, ..., n closer to the DC voltage command value _vDC ^* .

Next, an example of the overall operation of a computer 100 having the various functions shown in FIG. 4 will be described with reference to the flowchart in FIG. 5.

The computer 100 takes in the measured values of the three-phase output currents iR1 _...n , iS1 _...n , iT1 _...n of each power converter and the measured values of the DC voltages _vDC1...n (S1), uses these to generate total voltage command values _vR ^* , _vS ^* , _vT ^* (S2), and finally generates gate signals to each power converter, i.e., three-phase output voltage pulses gR1 _...n , gS1 _...n , gT1 _...n (S3). The series of processes in steps S1 to S3 are repeated.

Next, an example of the operation performed in step S2 in FIG. 5 will be described with reference to the flowchart in FIG. 6. FIG. 4 will also be referenced as appropriate.

The computer 100 generates an average value vDC of the DC voltages (measured values) _vDC1...n using the averaging processing unit 11, generates a difference between the _DC voltage command value _vDC ^* and the average value vDC of the _DC voltages (measured values) using the subtraction unit 12, and performs PI control using the difference generated by the subtraction unit 12 to generate an active current command value _iD ^* (S11).

In addition, the computer 100 generates average values _iR , iS, and iT of the three-phase output currents (measured values) _iR1...n , iS1 _...n , _iT1...n using the averaging processing units 14 to ₁₆ , and performs three-phase DQ conversion using the average values _iR , _iS , and _iT of the three-phase output currents (measured _values ) using the three-phase DQ conversion unit 17 to generate an active current _iD and a reactive current _iQ (S12).

Furthermore, the computer 100 generates the difference between the active current command value _iD ^* and the active current _iD using the subtraction unit 18, and performs PI control using the difference generated by the subtraction unit 18 using the PI control unit 19 to generate an active voltage command value _vD ^* , and generates the difference between the reactive current command value _iQ ^* and the reactive current _iQ using the subtraction unit 20, and performs PI control using the difference generated by the subtraction unit 20 using the PI control unit 21 to generate a reactive voltage command value _vQ ^* (S13).

Finally, the computer 100 performs a three-phase DQ inverse transformation using the active voltage command value _vD ^* and the reactive voltage command value _vQ ^* in the three-phase DQ inverse transformation unit 22 to generate total voltage command values _vR ^* , _vS ^* , and _vT ^* , and sends these to the gate signal generation unit 23 (S14).

Next, an example of the operation performed in step S3 in FIG. 5 will be described with reference to the flowchart in FIG. 7. Here, FIG. 3 and FIG. 4 will also be referenced as appropriate.

The computer 100 uses the overall voltage command values _vR ^* , _vS ^* , _vT ^* and the DC voltages (measured values) _vDC1...n to determine the overall output voltage pulses _gR , _gS , and _gT (S21) using the gate signal generating unit 23, and then determines the output voltage pulses gR1 _...n , gS1 _...n , gT1 _...n of each power converter (S22).

Next, a more specific example of the operation performed in step S3 in FIG. 5 will be described with reference to the flowchart in FIG. 8. Here, FIG. 3 and FIG. 4 will also be referred to as appropriate. In addition, of the R phase, S phase, and T phase that make up the three phases, only the case of the R phase will be illustrated here, but the same applies to the S phase and T phase.

The gate signal generating unit 23 compares the overall voltage command value _vR ^* with the carrier modulated waves (two triangular waves) _C1 , and also compares the overall voltage command value _vR ^{* with the carrier modulated wave C2 (the carrier modulated wave C1 with its phase shifted by 180°), and determines the level of the overall output voltage pulse gR} _{based on the} comparison results between the overall voltage command value _vR ^* and the carrier modulated wave _C1 and the comparison results between the overall voltage command value vR _* and the carrier modulated wave _C2 (S31).

Next, the gate signal generating unit 23 determines whether or not "average value i _R of the output current of each power converter ×total voltage command value v _R ^* " indicates a positive value (S32).

If "average value _iR of output current of each power converter x total voltage command value _vR ^* " indicates a positive value (YES in S32), the gate signal generating unit 23 prioritizes the gate signal output to the power converter with the largest DC voltage _vDC1...n , determines the level of each output voltage pulse so that the level of the output voltage pulse (any of output voltage pulses gR1 _...n ) for that power converter is higher than or equal to that of the other power converters, and outputs a gate signal to that power converter (S33, S35). However, if the power converter with the largest DC voltage corresponds to the power converter that has already output a gate signal with a level of +1 in the previous processing of S33 and S35, that power converter is excluded from the targets when determining the power converter with the largest DC voltage.

On the other hand, if "average value _iR of output current of each power converter × total voltage command value _vR ^* " indicates a negative value (NO in S32), the gate signal generating unit 23 prioritizes the gate signal output to the power converter with the smallest DC voltage _vDC1...n , determines the level of each output voltage pulse so that the level of the output voltage pulse (any of output voltage pulses gR1 _...n ) for that power converter is lower than or equal to that of the other power converters, and outputs a gate signal to that power converter (S34, S35). However, if the power converter with the smallest DC voltage corresponds to a power converter that has already output a gate signal with a level of -1 in the previous processing of S34 and S35, that power converter is excluded from the targets when determining the power converter with the smallest DC voltage.

According to the first embodiment, when controlling multiple three-phase, three-level power converters, even if there is a large power difference in output power between the power converters, the power flowing into each power converter is adjusted according to the magnitude relationship of the DC voltage between the power converters, so that the DC voltage balance between the power converters is maintained, harmonic currents are offset between the power converters, and a large amount of harmonics is prevented from flowing into the AC voltage source Gr.

Second Embodiment
Next, a second embodiment will be described. Note that the description of the parts common to the first embodiment will be omitted and the description will focus on the parts that are different.

Figure 9 shows an example of the overall configuration of a system including multiple power converters and a microcomputer that controls them according to the second embodiment.

In the first embodiment described above, multiple three-phase, three-level power converters were used, but in this second embodiment, multiple three-phase, two-level power converters are used instead.

Accordingly, the level of the gate signal sent from the computer 100 to the gate of each semiconductor switching element of each power converter, i.e., the three-phase output voltage pulse gR1 _...n , gS1 _...n , gT1 _...n , is expressed in two stages and takes a value of +1 or -1. Also, the level of the total output voltage pulse is expressed in three stages and takes a value of +1, 0, or -1.

Whether to adopt a three-level converter like the second embodiment or a two-level converter like the first embodiment described above can be determined taking into account the power converter capacity, DC voltage, switching frequency, elements used, and cost performance.

Next, with reference to Figures 10 and 11, we will explain the difference between the procedure for generating an output signal pulse according to the conventional technology and the procedure for generating an output signal pulse according to this embodiment.

To make the explanation easier to understand, we will explain the case where there are two power converters (N=2). Also, of the three phases that make up the R, S, and T phases, only the R phase will be illustrated here, but the same applies to the S and T phases.

In the conventional technology, as shown in FIG. 10, a voltage command value (command value for AC output voltage) v _R1 ^* corresponding to power converter 1 and a voltage command value (command value for AC output voltage) v _R2 ^* corresponding to power converter 2 are used.

10, a voltage command value _vR1 ^* corresponding to the power converter 1 is compared with a carrier modulated wave (one triangular wave) _C1 , and a voltage command value _vR2 ^* corresponding to the power converter 2 is compared with a carrier modulated wave _C2 (the above carrier modulated wave _C1 with its phase shifted by 180°). Then, based on the comparison result between the voltage command value _vR1 ^* and the carrier modulated wave C1, an output voltage pulse _gR1 to be provided to the power converter ₁ is generated, and based on the comparison result between the voltage command value _vR2 ^* and the carrier modulated wave _C2 , an output voltage pulse _gR2 to be provided to the power converter 2 is generated.

For example, in a time period in which the voltage command value _vR1 ^* indicates a positive value, when the voltage command value _vR1 ^* indicates a value greater than the carrier modulation wave (one triangular wave) _C1 , the level of the output voltage pulse _gR1 becomes +1, and otherwise the level of the output voltage pulse _gR1 becomes -1. Also, in a time period in which the voltage command value _vR1 ^* indicates a negative value, when the voltage command value _vR1 ^* indicates a value smaller than the value of the carrier modulation wave (one triangular wave) _C1 , the level of the output voltage pulse _gR1 becomes -1, and otherwise the level of the output voltage pulse _gR1 becomes +1.

Similarly, in a time period in which the voltage command value _vR2 ^* indicates a positive value, when the voltage command value _vR2 ^* indicates a value greater than the carrier modulation wave (one triangular wave) _C2 , the level of the output voltage pulse _gR2 is +1, and otherwise the level of the output voltage pulse _gR2 is -1. Also, in a time period in which the voltage command value _vR2 ^* indicates a negative value, when the voltage command value _vR2 ^* indicates a value smaller than the value of the carrier modulation wave (one triangular wave) _C2 , the level of the output voltage pulse _gR2 is -1, and otherwise the level of the output voltage pulse _gR2 is +1.

The output voltage pulse _gR1 of the power converter 1 and the output voltage pulse _gR2 of the power converter 2 are combined to form an output voltage pulse _gR .

10, when comparing the output voltage pulse _gR1 given to the power converter 1 and the output voltage pulse _gR2 given to the power converter 2, the total pulse width when the level is in the +1 state is the same, and the total pulse width when the level is in the -1 state is also the same, so the power flowing into each power converter is also the same. Therefore, when there is a large power difference between the output power of the power converter 1 and the power converter 2, the voltage amplitude, phase, etc. of the output power differs greatly between the power converters, and there is a possibility that a large amount of harmonics will flow into the AC voltage source without canceling out the harmonic currents between the power converters.

On the other hand, in this embodiment, as shown in FIG. 11, a total voltage command value v _R ^* obtained by combining the voltage command values corresponding to the power converters 1 and 2 is used.

11, the total voltage command value _vR ^* is compared with a carrier modulated wave (one triangular wave) _C1 , and also with a carrier modulated wave _C2 (the above carrier modulated wave _C1 phase-shifted by 180°). Then, based on the comparison results between the total voltage command value _vR ^* and the carrier modulated wave _C1 and the comparison results between the total voltage command value _vR ^* and ^the carrier modulated wave _C2 , _a total output voltage pulse _gR is generated.

For example, in a time period in which the overall voltage command value _vR ^* indicates a positive value, when the overall voltage command value _vR ^* indicates a value greater than either of the carrier modulation waves (one triangular wave) _C1 , _C2 , the level of the overall output voltage pulse _gR becomes +1, and otherwise the level of the overall output voltage pulse _gR becomes 0.

In addition, in a time period in which the overall voltage command value _vR ^* indicates a negative value, when the overall voltage command value _vR ^* indicates a value smaller than either of the carrier modulation waves (one triangular wave) _C1 , _C2 , the level of the overall output voltage pulse _gR becomes -1, and otherwise the level of the overall output voltage pulse _gR becomes 0.

Thereafter, based on the level of the total output voltage pulse _gR , the distribution of the levels of the output voltage pulses _gR1 , _gR2 is determined in accordance with the magnitude relationship between the DC voltages _vDC1 , _vDC2 of the power converters 1, 2, respectively.

In the example of Fig. 11, when the current polarity is from the power converter to the load and in the region where the total voltage command value _vR ^* indicates a positive value, the level of each output voltage _pulse is determined so that the level of the output voltage pulse (either output voltage pulse _gR1 or _gR2 ) for the power converter with the largest DC voltage vDC1...n is higher than or equal to that of the other power converters. Also, when the current polarity is from the load to the power converter and in the region where the total voltage command value _vR ^* indicates a negative value, the level of each output voltage pulse is determined so that the level of the output voltage pulse (either output voltage pulse _gR1 or _gR2 ) for the power converter with the smallest _DC voltage vDC1...n is lower than or equal to that of the other power converters. However, the levels of the output voltage pulses _gR1 and _gR2 are controlled to indicate either a value of +1 or -1, and not to be 0, +2, or -2.

That is, when the current polarity is from the power converter to the load, the power converter with a larger DC voltage v _DC1...n is controlled so that the level of the output voltage pulse given is preferentially set to 1, and when the current polarity is from the load to the power converter, the power converter with a smaller DC voltage v _DC1...n is controlled so that the level of the output voltage pulse given is preferentially set to -1. The longer the state in which the output voltage pulse level is +1 continues (i.e., the larger the pulse width of the level +1), the more the discharge from the capacitor of the DC voltage section is promoted and the DC voltage decreases, whereas the longer the state in which the output voltage pulse level is -1 continues (i.e., the larger the pulse width of the level -1), the more the charging of the capacitor of the DC voltage section is promoted and the DC voltage increases.

In the example shown in Fig. 11, when comparing the output voltage pulse _gR1 given to the power converter 1 and the output voltage pulse _gR2 given to the power converter 2, the total amount of the pulse width when the level is in the +1 state is different, and the total amount of the pulse width when the level is in the -1 state is also different, so that the power flowing into each power converter is also different. That is, even when there is a large power difference between the output powers of the power converter 1 and the power converter 2, the power flowing into each power converter is adjusted according to the magnitude relationship between the DC voltages _vDC1 and _vDC2 , so that the DC voltage balance between the power converters is maintained. In this case, the harmonic currents are offset between the power converters, and a large amount of harmonics is prevented from flowing into the AC voltage source Gr.

Note that the operations performed by the computer 100 according to this embodiment are similar to those described in Figures 5 to 8, and therefore will not be described here.

According to the second embodiment, the same effect as the first embodiment can be obtained even when controlling multiple three-phase two-level power converters.

As described above in detail, each embodiment makes it possible to maintain the DC voltage balance between multiple power converters and maintain the harmonic quality of the output voltage.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

1, 2, n... power converter, 11... averaging processing unit, 12... subtraction unit, 13... PI control unit, 14, 15, 16... averaging processing unit, 17... three-phase DQ conversion unit, 18... subtraction unit, 19... PI control unit, 20... subtraction unit, 21... PI control unit, 22... three-phase DQ inverse conversion unit, 23... gate signal generation unit, 100... microcomputer, Gr... AC voltage source, Tr... isolation transformer.

Claims (10)

A control device for controlling a plurality of power converters connected in parallel to an AC voltage source,
a signal generating means for determining a level of an overall output voltage pulse obtained by adding together individual output voltage pulses for driving each of the plurality of power converters, and then determining a distribution of levels of the individual output voltage pulses for driving each of the plurality of power converters;
The signal generating means
determining an allocation of levels of individual output voltage pulses for driving the plurality of power converters, respectively, in accordance with a magnitude relationship of the DC voltages of the plurality of power converters;
Control device. The signal generating means
a level of an overall voltage command value obtained by combining voltage command values for the plurality of power converters is compared with a level of each of the carrier modulated waves of the plurality of power converters, and a level of the overall output voltage pulse is determined according to the relative magnitudes of the respective values.
The control device according to claim 1 . A control device for controlling a plurality of power converters connected in parallel to an AC voltage source,
a signal generating means for determining a level of an overall output voltage pulse obtained by adding together individual output voltage pulses for driving each of the plurality of power converters, and then determining a distribution of levels of the individual output voltage pulses for driving each of the plurality of power converters;
The signal generating means
comparing a level of an overall voltage command value obtained by combining voltage command values for the plurality of power converters with levels of the carrier modulated waves of the individual power converters, and determining a level of the overall output voltage pulse according to a magnitude relationship between the respective values;
While the "average value of the output current of each power converter x the overall voltage command value" indicates a positive value, the level of each output voltage pulse is determined so that the level of the output voltage pulse for the power converter having the largest DC voltage is higher than or equal to that of the other power converters;
While the "average value of the output current of each power converter x the total voltage command value" indicates a negative value, the level of each output voltage pulse is determined so that the level of the output voltage pulse for the power converter having the smallest DC voltage is lower than or equal to that of the other power converters.
Control device. a means for generating the overall voltage command value based on a result of current control for causing an average value of output currents of the plurality of power converters to approach a current command value.
The control device according to claim 2 or 3 . a means for generating a current command value used in the current control based on a result of voltage control for bringing an average value of the DC voltages of the plurality of power converters closer to a DC voltage command value.
The control device according to claim 4 . A control method for controlling a plurality of power converters connected in parallel to an AC voltage source by a control device, comprising the steps of:
a first step of determining, by the control device, a level of an overall output voltage pulse obtained by combining individual output voltage pulses for driving each of the plurality of power converters;
a second step of determining, by the controller, after determining the level of the overall output voltage pulse, a distribution of levels of individual output voltage pulses for driving each of the plurality of power converters;
Including,
The second step includes:
determining a distribution of levels of individual output voltage pulses for driving the respective power converters in accordance with a magnitude relationship of the DC voltages of the plurality of power converters;
Control methods. The first step includes:
comparing a level of an overall voltage command value obtained by combining voltage command values for the plurality of power converters with a level of each of the carrier modulated waves of the plurality of power converters, and determining a level of the overall output voltage pulse according to a magnitude relationship between the respective levels.
The control method according to claim 6 . A control method for controlling a plurality of power converters connected in parallel to an AC voltage source by a control device, comprising the steps of:
a first step of determining, by the control device, a level of an overall output voltage pulse obtained by combining individual output voltage pulses for driving each of the plurality of power converters;
a second step of determining, by the controller, after determining the level of the overall output voltage pulse, a distribution of levels of individual output voltage pulses for driving each of the plurality of power converters;
Including,
The first step includes:
a level of an overall voltage command value obtained by combining voltage command values for the plurality of power converters is compared with a level of each of the carrier modulated waves of the plurality of power converters, and a level of the overall output voltage pulse is determined according to a magnitude relationship between the respective levels of the overall voltage command value and the plurality of power converters;
The second step includes:
While "the average value of the output current of each power converter x the total voltage command value" indicates a positive value, determining the level of each output voltage pulse so that the level of the output voltage pulse for the power converter having the highest DC voltage among the power converters that are the targets of level allocation is higher than or equal to the other power converters;
determining a level of each output voltage pulse so that, while "the average value of the output current of each power converter x the total voltage command value" indicates a negative value, the level of the output voltage pulse for the power converter having the smallest DC voltage among the power converters that are the targets of level allocation is lower than or equal to the other power converters;
Control methods. The control device further includes a step of generating the overall voltage command value based on a result of current control that causes an average value of output currents of the plurality of power converters to approach a current command value.
9. A control method according to claim 7 or 8 . The control device further includes a step of generating a current command value used in the current control based on a result of voltage control that brings an average value of DC voltages of the plurality of power converters closer to a DC voltage command value.
The control method according to claim 9 .