JP7644921B2 - METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE - Google Patents

Description

The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Nitride semiconductor devices having a vertical MOS (Metal Oxide Semiconductor) structure are known (see, for example, Patent Document 1). In addition, in nitride semiconductor devices, it is possible to control the P-type conductivity by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

In order to achieve good ohmic contact in a nitride semiconductor device, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. Ion implantation is a desirable method for selectively forming a P-type region in terms of cost, productivity, and reliability. However, when Mg is ion-implanted into a nitride semiconductor at a high concentration and heat treatment is performed at a high temperature exceeding 1300°C to activate the Mg, the Mg segregates into rod-like structures at a high density. When Mg segregates into rod-like structures at a high density, the Mg concentration decreases in regions other than the region where the segregation occurs (see, for example, Non-Patent Document 1). Furthermore, when heat treatment is performed at a high temperature exceeding 1400°C under an ultra-high pressure atmosphere, Mg diffuses deeply and the concentration decreases (see, for example, Non-Patent Document 2). For this reason, it has been difficult to form a high-concentration P-type region with small concentration variation by ion implantation.

JP 2019-096744 A JP 2014-086698 A

Kumar et. al. , J. Appl. Phys. 126 (2019) 235704. H. Sakurai et. al. , Appl. Phys. Lett. 115, 142104 (2019). G. Miceli, A. Pasquarello PRB (2016).

When Mg is activated by heat treatment to become a P-type region, the Fermi level of the P-type region approaches the valence band. When the Fermi level approaches the valence band, the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) increases, and Mg activation becomes unstable (see, for example, Non-Patent Document 3). The high-density segregation of Mg described above is thought to occur when Mg activation becomes unstable, making it easier for Mg to segregate through defects.

The present invention was developed through extensive research by the inventors based on this idea, and aims to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device that can realize a P-type region with a high concentration and small concentration variation.

In order to solve the above problem, a method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes the steps of ion-implanting an acceptor element into a nitride semiconductor, forming a protective film on the nitride semiconductor into which the acceptor element has been ion-implanted, and forming a P-type region in the nitride semiconductor by activating the acceptor element by subjecting the nitride semiconductor with the protective film to a heat treatment. The protective film is made of an N-type semiconductor.

A nitride semiconductor device according to one aspect of the present invention includes a nitride semiconductor and a P-type region provided in the nitride semiconductor. A concentration of an acceptor element in the P-type region is 1×10 ¹⁹ cm ^-3 or more and 1×10 ²¹ cm ^-3 or less. A density of the acceptor segregation in a surface layer portion of the P-type region is lower than a density of the acceptor segregation in a portion of the P-type region deeper than the surface layer portion.

The present invention provides a method for manufacturing a nitride semiconductor device that can realize a P-type region with high concentration and small concentration variation, and a nitride semiconductor device.

FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a configuration example of the vertical MOSFET according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a configuration example of the vertical MOSFET according to the first embodiment of the present invention. 4A to 4C are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. 4A to 4B are cross-sectional views showing the process steps of a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. 4A to 4C are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. 4A to 4D are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. 4A to 4E are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. 4A to 4F are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. 4A to 4G are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. FIG. 5 is a band diagram of the contact portion between GaN and a protective film (N-type semiconductor) and its vicinity, showing the valence band, conduction band, and Fermi level before and after heat treatment for activating the acceptor element. FIG. 6 is a band diagram of GaN when the protective film is an insulating film, showing the valence band, conduction band, and Fermi level before and after heat treatment for activating the acceptor element. FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a modified example of the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the second embodiment of the present invention. FIG. 10A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention in the order of steps. FIG. 10B is a cross-sectional view showing the process steps of a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. 10A to 10C are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. 10A to 10D are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. 10A to 10E are cross-sectional views showing the process steps of a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a modified example of the second embodiment of the present invention.

The following describes an embodiment of the present invention. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10 described below. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction that perpendicularly intersects with the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationships in regions, layers, films, substrates, etc., and do not limit the technical ideas of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

In the following explanation, the + or - attached to the P or N that indicates the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region that does not have a + or - attached. However, even if the same P and P (or N and N) are attached to the same semiconductor region, it does not mean that the impurity concentration of each semiconductor region is strictly the same.

<Embodiment 1>
(Configuration example)
1 is a plan view showing an example of the configuration of a gallium nitride semiconductor device 100 according to a first embodiment of the present invention (one example of the "nitride semiconductor device" of the present invention; hereinafter, referred to as a GaN semiconductor device). FIG. 1 is an XY plan view. As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 23 and a source electrode 25, respectively, which will be described later.

In a plan view from the Z-axis direction, the edge termination region 130 surrounds the active region 110. The edge termination region 130 may have one or more of a guard ring structure and a JTE (Junction Termination Extension) structure. The edge termination region 130 may have the function of preventing electric field concentration in the active region 110 by expanding the depletion layer generated in the active region 110 to the edge termination region 130.

Figure 2 is a plan view showing an example of the configuration of a vertical MOSFET 1 according to embodiment 1 of the present invention. Figure 3 is a cross-sectional view showing an example of the configuration of a vertical MOSFET 1 according to embodiment 1 of the present invention. Figure 2 shows an enlarged view of a portion of the active region 110 shown in Figure 1, and omits the gate pad 112 and source pad 114 in order to show the shapes of the gate electrode 23 and source electrode 25 in a plan view from the Z-axis direction. Figure 3 shows a cross section taken along line X-X' in the plan view of Figure 2.

The GaN semiconductor device 100 shown in Figures 2 and 3 includes a gallium nitride substrate (an example of the "nitride semiconductor" of the present invention; hereinafter, GaN substrate) 10 and a plurality of vertical MOSFETs 1 (an example of the "field effect transistor" of the present invention) provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (e.g., the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and this unit structure is arranged side by side in one direction (e.g., the X-axis direction).

As shown in Figures 2 and 3, the vertical MOSFET 1 has an N- type drift region 12, a P- type well region 14, a P+ type contact region 16 (an example of the "P type region" of the present invention), and an N+ type source region 18 provided in a GaN substrate 10, a gate insulating film 21 provided on the front surface 10a of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, a source electrode 25 (an example of the "electrode" of the present invention) provided on the front surface 10a of the GaN substrate 10 and electrically connected to the contact region 16 and the source region 18, and a drain electrode 27 provided on the back surface 10b of the GaN substrate 10 and electrically connected to the drift region 12.

The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a front surface 10a and a back surface 10b located opposite the front surface 10a. For example, the GaN substrate 10 is a low-dislocation free-standing GaN substrate having a threading dislocation density of less than 1×10 ⁷ cm ⁻² .

The donor element (N-type impurity) contained in the GaN substrate 10 may be one or more of the following elements: Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more of the following elements: Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

Since the GaN substrate 10 is a low-dislocation freestanding GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during the heat treatment included in the manufacturing process of the vertical MOSFET 1.

The GaN substrate 10 may be N-type instead of N-type. The GaN substrate 10 may also include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N type, and the GaN layer may be N type or N-type. The GaN single crystal substrate may also be a low-dislocation free-standing GaN substrate.

In the vertical MOSFET 1, the GaN substrate 10 may contain one or more elements of aluminum (Al) and indium (In). The GaN substrate 10 may be an alloy semiconductor containing trace amounts of Al and In in GaN, that is, AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

The GaN substrate 10 is provided with a drift region 12, a well region 14, a contact region 16, and a source region 18. The well region 14, the contact region 16, and the source region 18 are regions in which impurities are ion-implanted to a predetermined depth from the surface 10a of the GaN substrate 10 and the impurities are activated by heat treatment.

For example, the contact region 16 is provided on the surface side of the well region 14. The well region 14 is a P-type region, and the contact region 16 is a P+ type region. The contact region 16 has a higher P-type impurity concentration than the well region 14. The well region 14 and the contact region 16 contain at least one of Mg and Be as an acceptor element.

For example, the well region 14 and the contact region 16 contain Mg as an acceptor element. The Mg concentration in the well region 14 is not less than 1×10 ¹⁶ cm ⁻³ and not more than 3×10 ¹⁸ cm ⁻³ . The Mg concentration in the contact region 16 is not less than 1×10 ¹⁹ cm ⁻³ and not more than 1×10 ²¹ cm ⁻³ .

The drift region 12 is an N- type region, and the source region 18 is an N+ type region. The source region 18 has a higher N-type impurity concentration than the drift region 12. The drift region 12 and the source region 18 contain, for example, Si as an N-type impurity. For example, the N-type impurity concentration of the drift region 12 is the same as the N-type impurity concentration of the GaN substrate 10. In this case, the drift region 12 does not need to be ion-implanted with N-type impurities. The Si concentration in the drift region 12 is not less than 1×10 ¹⁵ cm ^-3 and not more than 1×10 ¹⁷ cm ^-3 .

The source region 18 is provided on the surface side of the well region 14. The source region 18 is formed by ion-implanting Si into the surface side of the well region 14 and activating the Si by heat treatment. The concentration of Si in the source region 18 is not less than 1×10 ¹⁹ cm ⁻³ and not more than 1×10 ²² cm ⁻³ .

The top of the source region 18 is exposed on the surface 10a of the GaN substrate 10. The source region 18 has one side in the X-axis direction and the other side located opposite the one in the X-axis direction. One side and the bottom of the source region 18 contact the well region 14, and the other side of the source region 18 contacts the contact region 16. One side of the source region 18 is located on the side of a region (hereinafter, channel region) 141 where the channel of the vertical MOSFET 1 is formed. The channel of the vertical MOSFET 1 is formed in the well region 14.

The contact region 16 is exposed on the surface 10a of the GaN substrate 10. Both sides of the contact region 16 in the X-axis direction are in contact with the source region 18, and the bottom is in contact with the well region 14. The well region 14, the contact region 16, and the source region 18 have a stripe shape extending in the Y-axis direction.

The upper part (hereinafter, the upper region) 121 of the drift region 12 is exposed on the surface 10a of the GaN substrate 10. The upper region 121 contacts the gate insulating film 21 on the surface 10a. The upper region 121 is located between a pair of well regions 14 facing each other in the Y-axis direction. The upper region 121 may be called a JFET region. The upper region 121 may be N-type instead of N-type. This makes it possible to reduce the on-resistance of the vertical MOSFET 1.

The lower part (hereinafter, lower part) 122 of the drift region 12 is in contact with the bottom of the well region 14. The lower part 122 is located between the upper part 121 and the drain electrode 27, and between the well region 14 and the drain electrode 27. The lower part 122 is provided continuously in the X-axis direction between multiple vertical MOSFETs 1 (i.e., multiple unit structures) that are repeated in the X-axis direction.

The drift region 12 functions as a current path between the drain electrode 27 and the channel region 141. The contact region 16 is a region for making contact between the well region 14 and an electrode (e.g., the source electrode 25). The contact region 16 also functions as a hole extraction path when the gate is off.

The gate insulating film 21 is, for example, a silicon oxide film ( _SiO2 film). The gate insulating film 21 is provided, for example, on the flat surface 10a.

The gate electrode 23 is provided above the channel region 141 via the gate insulating film 21. For example, the gate electrode 23 is a planar type provided on the flat gate insulating film 21. The gate electrode 23 is formed of a material different from that of the gate pad 112. The gate electrode 23 is formed of polysilicon doped with impurities, and the gate pad 112 is formed of Al or an Al-Si alloy.

The source electrode 25 is provided on the surface 10a of the GaN substrate 10. The source electrode 25 is in contact with a part of the source region 18 and the contact region 16. The source electrode 25 may also be provided on the gate electrode 23 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 23 so that the gate electrode 23 and the source electrode 25 are not electrically connected.

The source electrode 25 is made of the same material as the source pad 114. For example, the source electrode 25 made of Al or an Al-Si alloy also serves as the source pad 114. The source electrode 25 may have a barrier metal layer between the front surface 10a of the GaN substrate 10 and Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer. The drain electrode 27 is provided on the rear surface 10b side of the GaN substrate 10 and is in contact with the rear surface 10b. The drain electrode 27 is also made of the same material as the source electrode 25.

In FIG. 3, the gate terminal, source terminal, and drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or greater than the threshold voltage is applied to the gate electrode 23 via the gate terminal G, an inversion layer is formed in the channel region 141. When a predetermined high potential is applied to the drain electrode 27 and a low potential (e.g., ground potential) is applied to the source electrode 25 while the inversion layer is formed in the channel region 141, a current flows from the drain terminal D to the source terminal S. Also, when a potential lower than the threshold voltage is applied to the gate electrode 23, an inversion layer is not formed in the channel region 141 and the current is cut off. As a result, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D.

In the GaN semiconductor device 100 shown in Figures 1 to 3, the contact region 16 has a surface layer with little Mg segregation. The depth of the surface layer from the surface 10a is 1 nm or more and 30 nm or less. The density of Mg segregation in the surface layer of the contact region 16 is lower than the density of Mg segregation in a portion of the contact region 16 deeper than the surface layer (hereinafter, the deep portion).

For example, Mg segregation is classified into rod-shaped Mg segregation and non-rod-shaped Mg segregation. Rod-shaped Mg segregation is segregation with a length in one direction of 30 nm or more and a Mg concentration of 5×10 ²⁰ cm ⁻³ or more. Non-rod-shaped Mg segregation is segregation with a length in one direction of less than 30 nm and a Mg concentration of 5×10 ²⁰ cm ⁻³ or more. In the surface layer part of the contact region 16, the density of the rod-shaped acceptor segregation is 1×10 ¹⁴ cm ⁻³ or less, and the density of the non-rod-shaped acceptor segregation is less than 1×10 ¹⁵ cm ⁻³ . The density of the rod-shaped acceptor segregation and the density of the non-rod-shaped acceptor segregation in the deep part of the contact region 16 are higher than the respective densities in the surface layer part of the contact region 16.

As described below, this is achieved by covering the surface of the contact formation region 16' with a protective film (N-type semiconductor) beforehand when activating the Mg ion-implanted into the contact formation region 16' by heat treatment. By bringing the protective film (N-type semiconductor) into contact with the contact formation region 16', a depletion layer is generated in the surface portion of the contact formation region 16', and the Fermi level in the depletion layer is prevented from approaching the valence band (more preferably, the conduction band). This prevents Mg segregation in the surface portion of the contact region 16.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention will be described. Figures 4A to 4G are cross-sectional views showing the manufacturing method for the GaN semiconductor device 100 according to the first embodiment of the present invention in the order of steps. Note that Figures 4A to 4G show the manufacturing method for one vertical MOSFET 1 out of multiple vertical MOSFETs 1 repeatedly arranged in the X-axis direction in the order of steps. The GaN semiconductor device 100 is manufactured by various types of equipment, such as a film forming equipment, an exposure equipment, an etching equipment, an ion implantation equipment, and a heat treatment equipment. Hereinafter, these equipment will be collectively referred to as manufacturing equipment.

As shown in FIG. 4A, the manufacturing equipment ion-implants Mg as an acceptor element into a region (hereinafter, well formation region) 14' in the GaN substrate 10 where the well region 14 (see FIG. 3) is formed. For example, the manufacturing equipment forms a mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is a SiO ₂ film or photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the well formation region 14' and covers above other regions. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M1 is formed. After the ion implantation, the manufacturing equipment removes the mask M1 from above the GaN substrate 10.

4A, the implantation energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the implantation peak position is 200 nm to 1500 nm, for example 500 nm. Also, in this process, the dose of Mg ions is set so that the Mg concentration at the implantation peak position is 1×10 ¹⁶ cm ^-3 to 3×10 ¹⁸ cm ^-3 .

4A, the Mg implantation energy and dose may be set so that the Mg concentration is 1×10 ¹⁶ cm ^-3 or more and 3×10 ¹⁸ cm ^-3 or less not only at the implantation peak position but also throughout the well formation region 14'. The process shown in FIG. 4A may be performed by single-stage ion implantation in which the acceleration energy is one condition, or may be performed by multi-stage ion implantation in which the acceleration energy is multiple conditions.

Next, as shown in FIG. 4B, the manufacturing equipment ion-implants Mg as an acceptor element into a region 16' in which a contact region is to be formed (hereinafter, contact formation region) in the GaN substrate 10. For example, the manufacturing equipment forms a mask M2 on the GaN substrate 10. The mask M2 is a _SiO2 film or a photoresist. The mask M2 has a shape that opens above the contact formation region 16' and covers above the other regions. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M2 has been formed. After the ion implantation, the manufacturing equipment removes the mask M2 from above the GaN substrate 10.

4B, the implantation energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the implantation peak position is 1 nm to 200 nm, for example, 10 nm to 100 nm. Also, in this step, the dose of Mg ions is set so that the Mg concentration at the implantation peak position is 1× ¹⁰ cm ⁻³ to 1× ¹⁰ cm ⁻³ , for example, 1× ¹⁰ cm ⁻³ .

4B, the Mg implantation energy and dose may be set so that the Mg concentration not only at the implantation peak position but also in the entire contact formation region 16' is 1×10 ¹⁹ cm ^-3 or more and 1×10 ²¹ cm ^-3 or less, for example, 1×10 ²⁰ cm ^-3 . The process shown in FIG. 4B may be performed by single-stage ion implantation using a single acceleration energy, or may be performed by multi-stage ion implantation using different acceleration energies.

Next, as shown in FIG. 4C, the manufacturing equipment forms a protective film 30 on the surface 10a of the GaN substrate 10. As a result, at least the contact formation region 16' on the surface 10a of the GaN substrate 10 is in direct contact with the protective film 30. The surfaces of the well formation region 14' and the upper region 121 may be in direct contact with the protective film 30 or may be covered with an insulating film (not shown).

The protective film 30 is made of an N+ type semiconductor (an example of an "N-type semiconductor" of the present invention). For example, the protective film 30 is made of N+ type aluminum nitride (AlN) or N+ type silicon nitride (SiN). AlN or SiN is suitable for the protective film 30 because it has high heat resistance, good adhesion to the GaN substrate 10, does not diffuse impurities from the protective film 30 to the GaN substrate 10, and can be selectively removed from the GaN substrate 10.

The concentration of the donor element (for example, Si) contained in the protective film 30 is, for example, 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The concentration of the donor element contained in the protective film 30 may be a value equal to or greater than the concentration of the acceptor element ion-implanted into the contact formation region 16′.

The thickness of the protective film 30 when it is formed is equal to or greater than the depth from the surface of the surface layer of the contact formation region 16' (or the contact region 16 (see FIG. 3)). For example, the lower limit of the thickness of the protective film 30 is 1 nm when the depth of the surface layer of the contact formation region 16' (or the contact region 16) is 1 nm, and is 30 nm when the depth of the surface layer is 30 nm. There is no particular limit to the upper limit of the thickness of the protective film 30, but from the viewpoint of suppressing a decrease in the deposition throughput of the protective film 30 and suppressing the occurrence of warping or the like in the GaN substrate 10, the upper limit is preferably 1 μm, and more preferably 500 nm. From the above, as an example, the thickness of the protective film 30 when it is formed is 1 nm or more and 1 μm or less, and more preferably 1 nm or more and 500 nm or less.

Next, the manufacturing equipment performs a heat treatment on the GaN substrate 10 covered with the protective film 30 at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid heating process. This heat treatment activates the Mg ions implanted into the GaN substrate 10, and as shown in FIG. 4D, a P-type well region 14 and a P+-type contact region 16 are formed in the GaN substrate 10, and the drift region 12 is defined. This heat treatment also allows the GaN substrate 10 to recover to a certain degree the defects caused by the Mg ion implantation. After the heat treatment, the manufacturing equipment removes the protective film 30 from the surface 10a of the GaN substrate 10.

Next, as shown in FIG. 4E, the manufacturing equipment ion-implants Si as a donor element into a region (hereinafter, source formation region) 18' in the GaN substrate 10 where the source region 18 (see FIG. 3) is formed. For example, the manufacturing equipment forms a mask M3 on the surface 10a of the GaN substrate 10. The mask M3 is a SiO ₂ film or a photoresist. The mask M3 has a shape that opens above the source formation region 18' and covers above the other regions. The manufacturing equipment ion-implants Si into the GaN substrate 10 on which the mask M3 is formed. After the ion implantation, the manufacturing equipment removes the mask M3 from above the GaN substrate 10.

The manufacturing equipment then performs a heat treatment on the GaN substrate 10 at a maximum temperature of 1200°C or less. This heat treatment is, for example, a rapid heating process. This heat treatment activates the Si ions implanted into the GaN substrate 10, and as shown in FIG. 4F, an N+ type source region 18 is formed in the GaN substrate 10. This heat treatment also makes it possible to recover to some extent the defects that have occurred in the GaN substrate 10 due to the Si ion implantation.

Next, as shown in FIG. 4G, the manufacturing equipment forms a gate insulating film 21 on the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 23 and a source electrode 25. Next, the manufacturing equipment forms an interlayer insulating film (not shown) on the front surface 10a of the GaN substrate 10 so as to cover the gate electrode 23 and the source electrode 25. Next, the manufacturing equipment forms a gate pad 112 (see FIG. 1) electrically connected to the gate electrode 23 and a source pad 114 (see FIG. 1) electrically connected to the source electrode 25. After that, the manufacturing equipment forms a drain electrode 27 on the rear surface 10b of the GaN substrate 10. Through these steps, a GaN semiconductor device 100 including a vertical MOSFET 1 is completed.

(Fermi level of the depletion layer occurring in GaN)
5 is a band diagram of the contact portion between GaN and a protective film (N-type semiconductor) and its vicinity, showing the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after heat treatment for activating the acceptor element. Note that Mg is ion-implanted into the GaN shown in FIG. 5 as an acceptor element.

As shown in Figure 5, a depletion layer occurs at the contact area between GaN and the protective film. The depletion layer bends the band structure, and the Fermi level Ef of GaN coincides with the Fermi level Ef of the protective film (N-type semiconductor). When heat treatment is performed in this state, Mg is activated in GaN, and the Fermi level approaches the valence band, but the band structure is bent in the depletion layer. Therefore, in the region where the depletion layer occurs in GaN (i.e., the surface layer of GaN), the approach of the Fermi level Ef to the valence band is suppressed compared to the region where the depletion layer does not occur.

When the acceptor concentration in GaN is 1×10 ¹⁹ cm ^-3 or more and 1×10 ²¹ cm ^-3 or less and the donor concentration in the protective film is 1×10 ¹⁹ cm ^-3 or more and 1×10 ²¹ cm ^-3 or less, the width (depth) of the depletion layer formed in GaN due to contact with the protective film is approximately 1 nm or more and 30 nm or less. The higher the donor concentration in the protective film, the larger the width of the depletion layer formed in GaN.

Figure 6 is a band diagram of GaN when the protective film is an insulating film, showing the valence band Ev, conduction band Ec, and Fermi level Ef before and after heat treatment to activate the acceptor element. When the protective film is an insulating film, no depletion layer is formed as shown in Figure 6, and no bending of the band structure occurs in the depletion layer. When GaN covered with an insulating film is subjected to heat treatment, the Mg contained in the GaN is activated and the Fermi level of the GaN approaches the valence band.

(Suppression of Mg segregation by controlling the Fermi level)
FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. This graph is data calculated by first-principles calculation. The horizontal axis of FIG. 7 shows the Fermi level Ef (eV), and the vertical axis of FIG. 7 shows the energy (eV). The solid line (a) of FIG. 7 shows the relationship between the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) and the Fermi level Ef of GaN. The dashed line (b) of FIG. 7 shows the relationship between the energy required to insert Ga into the lattice of GaN and the Fermi level Ef of GaN.

In Figure 7, the closer the Fermi level Ef is to 0 (eV) (i.e., the closer the Fermi level Ef is to the valence band and the closer the conductivity type of GaN is to P-type), the greater the energy required to form Mg acceptors. Also, the closer the Fermi level is to 0 (eV), the smaller the energy required for Ga to enter the GaN interstitial spaces.

From the graph in Figure 7, it can be seen that the closer the Fermi level of GaN is to the valence band and the closer the conductivity type of GaN is to P-type, the more difficult it is for Mg to be activated and the more difficult it is for it to function as an acceptor. In other words, the closer the Fermi level of GaN is to the conduction band and the closer the conductivity type of GaN is to N-type, the more easily Mg is activated and the more easily it functions as an acceptor.

In an embodiment of the present invention, a depletion layer is formed in the surface portion of the contact formation region 16' due to contact with the protective film 30, which is an N-type semiconductor, and the Fermi level Ef of the depletion layer is prevented from approaching the valence band Ev. The Fermi level Ef of the surface portion of the contact formation region 16' is controlled so as not to approach the valence band. As a result, Mg is easily activated in the surface portion of the contact region 16, making it easier for it to function as an acceptor.

(Effects of the First Embodiment)
As described above, the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of ion-implanting Mg into the contact formation region 16' of the GaN substrate 10, forming the protective film 30 on the contact formation region 16' of the GaN substrate 10 into which Mg has been ion-implanted, and activating the Mg by subjecting the GaN substrate 10 on which the protective film 30 has been formed to a heat treatment, thereby forming the contact region 16 in the GaN substrate 10. The protective film 30 is made of an N+ type semiconductor.

As a result, a depletion layer is generated in the surface portion of the contact formation region 16' due to contact between the contact formation region 16' and the protective film 30, and the Fermi level of this surface portion coincides with the Fermi level of the protective film 30. Because the protective film 30 is made of an N+ type semiconductor, it is possible to prevent the Fermi level of the depletion layer generated in the surface portion from approaching the valence band.

As a result, in the surface layer of the contact formation region 16', the formation energy of the Mg acceptor can be maintained at a low level, making it easier to activate Mg, suppressing Mg segregation due to heat treatment and suppressing variations in Mg concentration due to Mg segregation. This makes it possible to realize a P+ type contact region 16 with a high concentration, small concentration variations, and little Mg segregation in the surface layer. In addition, by joining the source electrode 25 to such a P+ type contact region 16, a source contact with excellent ohmic properties can be realized.

In addition, in the above manufacturing method, the Mg ion implantation conditions may be set so that the concentration of the donor element contained in the protective film 30 is higher than the concentration of Mg ions implanted into the GaN substrate 10. This allows the width (depth) of the depletion layer formed in the GaN substrate 10 to be increased, making it easier to expand the surface layer region with less Mg segregation in the depth direction.

(Modification)
In the above embodiment 1, it has been described that the N+ type source region 18 is formed after the P+ type contact region 16 is formed. However, in the embodiment of the present invention, the source region 18 may be formed before the contact region 16 is formed. For example, the step of ion-implanting Si into the source formation region 18' shown in FIG. 4E and the step of heat treatment for activating Si shown in FIG. 4F may be performed before the step of ion-implanting Mg into the contact region 16' shown in FIG. 4B. Even with such a method, the manufacturing apparatus can manufacture the vertical MOSFET 1. Furthermore, in this method, it is not necessary to consider Mg segregation in the contact formation region 16' when performing heat treatment for activating Si. Therefore, the maximum temperature of the heat treatment for activating Si may be set to 1300° C. or higher, which makes it easy to increase the activation rate of Si in the source region 18.

In addition, in the above-described embodiment 1, the protective film 30 is removed from the surface 10a of the GaN substrate 10 after the contact region 16 is formed by heat treatment. However, in an embodiment of the present invention, at least a portion of the protective film 30 may be left on the contact region 16.

Figure 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to a modified example of embodiment 1 of the present invention. As shown in Figure 8, the GaN semiconductor device 100A includes a GaN substrate 10 and multiple vertical MOSFETs 1A provided on the GaN substrate 10 and repeatedly provided in one direction (e.g., the X-axis direction). The vertical MOSFET 1A shown in Figure 8 differs from the vertical MOSFET 1 shown in Figure 3 in that a protective film 30 remains (is interposed) between the contact region 16 and the source electrode 25, and between the source region 18 and the source electrode 25.

In the vertical MOSFET 1A, the thickness of the protective film 30 remaining between the contact region 16 and the source electrode 25 and between the source region 18 and the source electrode 25 is, for example, 1 nm to 1 μm, more preferably 1 nm to 500 nm. The protective film 30 functions as a tunnel film. The thickness of the protective film 30 may be the same as when it was formed, or may be thinned by etching. By thinning the protective film 30, the tunnel effect in the protective film 30 can be increased.

Even with this configuration, electrical connections are made between the contact region 16 and the source electrode 25, and between the source region 18 and the source electrode 25. Therefore, the vertical MOSFET 1A shown in FIG. 8 operates in the same manner as the vertical MOSFET 1 shown in FIG. 3, etc.

In addition, in the modified example shown in FIG. 8, the protective film 30 remains on the contact region 16 even after the vertical MOSFET 1A is completed. Therefore, when forming the source region 18 after forming the contact region 16, even if the maximum temperature of the heat treatment for activating Si in the source region 18 is set to 1300°C or higher, Mg segregation in the contact region 16 can be suppressed. This allows the heat treatment temperature for activating Si in the source region 18 to be increased, making it easier to increase the activation rate of Si in the source region 18.

<Embodiment 2>
(composition)
Fig. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200 according to embodiment 2 of the present invention. As shown in Fig. 9, the GaN semiconductor device 200 according to embodiment 2 includes a GaN substrate 10, a PN diode 2 (an example of a "diode" in the present invention) provided on the GaN substrate 10, and a guard ring structure 17 provided on the GaN substrate 10 and surrounding the PN diode 2.

The PN diode 2 has an N-type region 13 provided in the GaN substrate 10, a P-type region 15 provided in the GaN substrate 10, a P+-type contact region 16 provided in the GaN substrate 10, an insulating film 19 provided on the front surface 10a of the GaN substrate 10, an anode electrode 35 (one example of an "electrode" in the present invention) provided on the front surface 10a of the GaN substrate 10, provided on the contact region 16 and electrically connected to the contact region 16, and a cathode electrode 37 provided on the back surface 10b of the GaN substrate 10 and electrically connected to the N-type region 13. In the PN diode 2, the N-type region 13 is the cathode region, and the P-type region 15 is the anode region.

The P-type region 15 is formed by ion-implanting an acceptor element into the N-type GaN substrate 10 and then heat-treating it. The acceptor element is, for example, Mg.

The insulating film 19 is, for example, a silicon oxide (SiO ₂ ) film. An opening H19 having a bottom surface corresponding to the contact region 16 is provided in the insulating film 19. The anode electrode 35 is connected to the contact region 16 through the opening H19.

The anode electrode 35 and the cathode electrode 37 are made of, for example, Al or an Al-Si alloy. The anode electrode 35 and the cathode electrode 37 may have a barrier metal layer between them and the GaN substrate 10. Ti may be used as the material for the barrier metal layer.

The guard ring structure 17 has a structure in which, for example, multiple P-type regions surround the PN diode 2 in a ring shape. When a reverse bias is applied to the PN diode 2, the guard ring structure 17 can facilitate the spread of the depletion layer toward the outer periphery of the GaN substrate 10, and can suppress electric field concentration on the PN diode 2. As a result, the guard ring structure 17 can improve the breakdown voltage of the PN diode 2.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 200 according to the second embodiment of the present invention will be described. FIGS. 10A to 10E are cross-sectional views showing the process sequence of the method for manufacturing the GaN semiconductor device 200 according to the second embodiment of the present invention. As shown in FIGS. 10A and 10B, the manufacturing device ion-implants Mg as an acceptor element into a region (hereinafter, P-type formation region) 15' in which the P-type region 15 (see FIG. 9) is formed and into a contact formation region 16' in the GaN substrate 10. The ion implantation conditions are set so that the implantation depth of the acceptor element is shallower and the implantation concentration of the acceptor element is higher in the contact formation region 16' than in the P-type formation region 15'. This ion implantation may be performed by multi-stage ion implantation using the same mask.

For example, the manufacturing equipment forms a mask M11 on the surface 10a of the GaN substrate 10. The mask M11 is a SiO ₂ film or a photoresist that can be selectively removed from the GaN substrate 10. The mask M11 has a shape that opens above the P-type formation region 15' (also above the contact formation region 16' as shown in FIG. 10B) and covers the upper part of other regions. The manufacturing equipment ions-implants Mg into the GaN substrate 10 on which the mask M11 is formed, thereby introducing Mg into the P-type formation region 15'. The ion-implantation conditions at this time are, for example, the same as the ion-implantation conditions in the process shown in FIG. 4A.

Next, as shown in FIG. 10B, the manufacturing equipment ions implants Mg into the GaN substrate 10 on which the mask M11 has been formed, to introduce Mg into the contact formation region 16'. The ion implantation conditions at this time are, for example, the same as the ion implantation conditions in the process shown in FIG. 4B. After the ions are implanted into the P-type formation region 15' and the contact formation region 16', the manufacturing equipment removes the mask M11 from the GaN substrate 10.

Next, as shown in FIG. 10C, the manufacturing equipment ion-implants Mg as an acceptor element into a region (hereinafter, guard ring formation region) 17' in the GaN substrate 10 where the guard ring structure 17 (see FIG. 9) is formed. For example, the manufacturing equipment forms a mask M12 on the surface 10a of the GaN substrate 10. The mask M12 has a shape that opens above the guard ring formation region 17' and covers the upper portions of other regions. The mask M12 is a SiO ₂ film or photoresist that can be selectively removed from the GaN substrate 10. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M12 is formed, thereby introducing Mg into the guard ring formation region 17'. The ion implantation conditions at this time may be the same as or different from the ion implantation conditions in the process shown in FIG. 4A, for example. After the ion implantation into the guard ring formation region 17', the manufacturing equipment removes the mask M12 from above the GaN substrate 10.

Next, as shown in FIG. 10D, the manufacturing device forms a protective film 30 on the surface 10a of the GaN substrate 10. As a result, at least the contact formation region 16' on the surface 10a of the GaN substrate 10 is in direct contact with the protective film 30. Also, the entire surface 10a of the GaN substrate 10 may be in direct contact with the protective film 30.

Next, the manufacturing equipment performs a heat treatment on the GaN substrate 10 covered with the protective film 30 at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid heating process. This heat treatment activates the Mg introduced into the GaN substrate 10, and as shown in FIG. 10E, a P-type region 15, a P+ type contact region 16, and a P-type guard ring structure 17 are formed in the GaN substrate 10, and an N- type region 13 is defined. This heat treatment also makes it possible to recover to some extent the defects caused by the Mg ion implantation in the GaN substrate 10. After the heat treatment, the manufacturing equipment removes the protective film 30 from the surface 10a of the GaN substrate 10.

Note that FIG. 10E shows a state in which the P-type region 15 diffuses more widely in the lateral direction than the contact formation region 16, but this is merely one example. In embodiment 2 of the present invention, the P-type region 15 and the contact formation region 16 may diffuse in the lateral direction in the same manner, and the entire surface side of the P-type region 15 may be covered with the contact formation region 16.

Next, the manufacturing equipment forms an insulating film 19 (see FIG. 9) on the surface 10a of the GaN substrate 10, and forms an opening H19 (see FIG. 9) in the insulating film 19. Next, the manufacturing equipment forms an anode electrode 35 and a cathode electrode 37. Through these steps, the GaN semiconductor device 200 equipped with the PN diode 2 shown in FIG. 9 is completed.

(Effects of the Second Embodiment)
As described above, the method for manufacturing the GaN semiconductor device 200 according to the second embodiment of the present invention includes the steps of ion-implanting Mg into the contact formation region 16' of the GaN substrate 10, forming the protective film 30 on the contact formation region 16' of the GaN substrate 10 into which Mg has been ion-implanted, and activating the Mg by subjecting the GaN substrate 10 on which the protective film 30 has been formed to a heat treatment, thereby forming the contact region 16 in the GaN substrate 10. The protective film 30 is made of an N+ type semiconductor.

As a result, a P+ type contact region 16 can be realized that is highly concentrated, has small concentration variations, and has little Mg segregation in the surface layer, similar to the GaN semiconductor device 100 according to the first embodiment. In addition, by joining the anode electrode 35 to such a P+ type contact region 16, an anode contact with excellent ohmic properties can be realized.

(Modification)
As in the first embodiment, in the second embodiment, at least a part of the protective film 30 may be left on the contact region 16. Fig. 11 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200A according to a modified example of the second embodiment of the present invention. As shown in Fig. 11, the GaN semiconductor device 200A includes a GaN substrate 10 and a PN diode 2A provided on the GaN substrate 10. The PN diode 2A shown in Fig. 11 differs from the PN diode 2 shown in Fig. 9 in that the protective film 30 is left (interposed) between the contact region 16 and the anode electrode 35.

In the PN diode 2A, the thickness of the protective film 30 remaining between the contact region 16 and the anode electrode 35 is, for example, 1 nm to 1 μm, and more preferably 1 nm to 500 nm. The protective film 30 functions as a tunnel film. With this configuration, the contact region 16 and the anode electrode 35 are electrically connected, so that the PN diode 2A operates in the same manner as the PN diode 2 described above.

In the manufacturing method shown in Figures 10A to 10E, the mask M11 is used to perform multi-stage ion implantation of Mg as an acceptor element into the P-type formation region 15' and the contact formation region 16'. However, in the second embodiment of the present invention, ion implantation into the P-type formation region 15' and ion implantation into the contact formation region 16' may be performed using different masks. Even with this method, it is possible to manufacture a semiconductor device having a structure similar to that of the GaN semiconductor device 200 shown in Figure 9. Although this method increases the number of manufacturing steps, it is possible to form, for example, the shape of the contact region 16 in a plan view into a shape different from that of the P-type region 15.

In the manufacturing method shown in Figures 10A to 10E, the mask M12 is used to implant Mg as an acceptor element into the guard ring formation region 17'. However, in the second embodiment of the present invention, the ion implantation into the guard ring formation region 17' may be performed using the mask M11. Even with this method, it is possible to manufacture a semiconductor device having a structure similar to that of the GaN semiconductor device 200 shown in Figure 9. In this method, the guard ring structure 17 is formed in a structure in which the P+ type region 16 is arranged on the P type region 15.

Other Embodiments
As described above, the present invention has been described by the first and second embodiments and modifications, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

For example, the gate insulating film 21 is not limited to a _SiO2 film, and may be another insulating film. A silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon _nitride ( _Si3N4 ) film, or an aluminum oxide ( _Al2O3 ) film may also be used as the gate insulating film 21. A composite film in which several single _- layer insulating films are stacked may also be used as the gate insulating film 21. A vertical MOSFET using an insulating film other than a _SiO2 film as the gate insulating film 21 may be called a vertical MISFET. A MISFET refers to a more comprehensive insulated gate transistor including a MOSFET.

In the above embodiment 1, the contact region 16 is described as being included in a vertical MISFET. However, the embodiments of the present invention are not limited to this. The contact region 16 may be included in a lateral MISFET in which a current flows in the horizontal direction of the GaN substrate, rather than in a vertical MISFET in which a current flows in the vertical direction of the GaN substrate.

In the above embodiment 1, it has been described that the electrode in contact with the contact region 16 is the source electrode 25. In the above embodiment 2, it has been described that the electrode in contact with the contact region 16 is the anode electrode 35. However, the embodiments of the present invention are not limited to this. The contact region 16 may be in contact with an electrode other than the source electrode and the anode electrode. In addition, the P-type region exemplified as the contact region 16 may be included in an element other than a MOSFET or a PN diode, and may be included in, for example, a bipolar transistor, a capacitance element, a resistance element, etc.

As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

1,1A vertical MOSFET
2, 2A PN diode 10 GaN substrate 10a Front surface 10b Back surface 12 Drift region 13 N-type region 14 Well region 14' Well formation region 15 P-type region 15' P-type formation region 16 Contact region 16' Contact formation region 17 Guard ring structure 17' Guard ring formation region 18 Source region 18' Source formation region 19 Insulation film 21 Gate insulation film 23 Gate electrode 25 Source electrode 27 Drain electrode 30 Protective film 35 Anode electrode 37 Cathode electrode 100, 100A, 200, 200A GaN semiconductor device 110 Active region 112 Gate pad 114 Source pad 121 Upper region 122 Lower region 130 Edge termination region 141 Channel region D Drain terminal Ec Conduction band Ef Fermi level Ev Valence band G Gate terminal H19 Openings M1, M2, M3, M11, M12 Mask S Source terminal

Claims (16)

ion-implanting an acceptor element into a nitride semiconductor;
forming a protective film on the nitride semiconductor into which the acceptor element has been ion-implanted;
and a step of activating the acceptor element by subjecting the nitride semiconductor on which the protective film is formed to a heat treatment to form a P-type region in the nitride semiconductor,
The method for manufacturing a nitride semiconductor device, wherein the protective film is composed of an N-type semiconductor. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the ion implantation conditions for the acceptor element are set so that the concentration of the donor element contained in the protective film is higher than the concentration of the acceptor element ion-implanted into the nitride semiconductor. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein conditions for ion implantation of the acceptor element are set so that a concentration of the acceptor element ion-implanted into the nitride semiconductor is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 3, wherein the maximum temperature of the heat treatment is 1300°C or higher and 2000°C or lower. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 4, wherein the nitride semiconductor is gallium nitride. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 5, wherein the acceptor element includes at least one of magnesium and beryllium. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 6, wherein the protective film is aluminum nitride or silicon nitride. A nitride semiconductor;
a P-type region provided in the nitride semiconductor;
the concentration of the acceptor element in the P-type region is equal to or higher than 1×10 ¹⁹ cm ⁻³ and equal to or lower than 1×10 ²¹ cm ⁻³ ,
Acceptor segregation in the P-type region,
a rod-shaped acceptor segregation having a length in one direction of 30 nm or more and a concentration of the acceptor element of 5×10 ²⁰ cm ⁻³ or more;
and non-rod-shaped acceptor segregation having a length in one direction of less than 30 nm and a concentration of the acceptor element of 5×10 ²⁰ cm ⁻³ or more.
a density of the rod-shaped acceptor segregation and a density of the non-rod-shaped acceptor segregation in a surface layer portion of the P-type region are lower than a density of the rod-shaped acceptor segregation and a density of the non-rod-shaped acceptor segregation in a portion of the P-type region deeper than the surface layer portion, respectively . A nitride semiconductor;
a P-type region provided in the nitride semiconductor;
the concentration of the acceptor element in the P-type region is equal to or higher than 1×10 ¹⁹ cm ⁻³ and equal to or lower than 1×10 ²¹ cm ⁻³ ,
a density of the acceptor segregation in a surface layer portion of the P-type region is lower than a density of the acceptor segregation in a portion of the P-type region that is deeper than the surface layer portion;
The acceptor segregation is
a rod-shaped acceptor segregation having a length in one direction of 30 nm or more and a concentration of the acceptor element of 5×10 ²⁰ cm ⁻³ or more;
and non-rod-shaped acceptor segregation having a length in one direction of less than 30 nm and a concentration of the acceptor element of 5×10 ²⁰ cm ⁻³ or more.
In the surface layer portion, the density of the rod-shaped acceptor segregations is 1×10 ¹⁴ cm ⁻³ or less, and the density of the non -rod-shaped acceptor segregations is less than 1×10 ¹⁵ cm ⁻³ . A nitride semiconductor;
a P-type region provided in the nitride semiconductor;
the concentration of the acceptor element in the P-type region is equal to or higher than 1×10 ¹⁹ cm ⁻³ and equal to or lower than 1×10 ²¹ cm ⁻³ ,
a density of the acceptor segregation in a surface layer portion of the P-type region is lower than a density of the acceptor segregation in a portion of the P-type region that is deeper than the surface layer portion;
The depth of the surface layer from the surface is 1 nm or more and 30 nm or less. The nitride semiconductor device according to any one of claims 8 to 10, further comprising an electrode provided on the surface layer. A nitride semiconductor;
a P-type region provided in the nitride semiconductor;
the concentration of the acceptor element in the P-type region is equal to or higher than 1×10 ¹⁹ cm ⁻³ and equal to or lower than 1×10 ²¹ cm ⁻³ ,
a density of the acceptor segregation in a surface layer portion of the P-type region is lower than a density of the acceptor segregation in a portion of the P-type region that is deeper than the surface layer portion;
An electrode provided on the surface layer portion;
the nitride semiconductor device according to claim 1, further comprising: a protective film made of an N-type semiconductor and interposed between the surface layer and the electrode. The nitride semiconductor device according to claim 12, wherein the concentration of the dopant element in the protective film is higher than the concentration of the acceptor element in the surface layer. The nitride semiconductor device according to claim 12 or 13, wherein the thickness of the protective film is equal to or greater than the depth from the surface of the surface layer and is equal to or less than 1 μm. A P-type well region provided in the nitride semiconductor;
a field effect transistor provided in the nitride semiconductor, the field effect transistor having a channel formed in the well region;
15. The nitride semiconductor device according to claim 8, wherein said P-type region has a higher concentration of said acceptor element than said well region and is electrically connected to said well region. a diode provided in the nitride semiconductor;
The nitride semiconductor device according to claim 8 , wherein said P-type region is an anode region of said diode.

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