JP7636159B2 - Thin Film Devices - Google Patents

Description

This disclosure relates to thin film devices.

The use of OLED (Organic Light-Emitting Diode) elements is becoming more widespread in the field of display devices. OLED elements are current-driven light-emitting elements, which means they do not require a backlight and have the advantages of low power consumption, a wide viewing angle, and a high contrast ratio.

An active matrix type OLED display device includes a pixel circuit including a switch thin film transistor (TFT) that selects a pixel (subpixel) and a drive TFT that supplies current to the OLED element that controls the display of that pixel. In the pixel circuit, amorphous silicon TFTs, polysilicon TFTs, oxide semiconductor TFTs, etc. can be used.

Oxide semiconductor TFTs are increasingly being used in pixel circuits of display devices due to their low leakage current and relatively high electron mobility. Oxide semiconductor TFTs are also used in a variety of fields other than display devices.

US Patent Application Publication No. 2018/0175077

Different characteristics are required for the oxide semiconductor TFTs in a circuit depending on their function. For example, in a circuit that controls a current-driven light-emitting element, the switch TFT that selects the light-emitting element is required to have a sharp rise characteristic (low S value) of the drain current relative to the gate voltage. In contrast, the drive TFT is required to have a gradual rise characteristic (high S value). On the other hand, there is a demand to implement oxide semiconductor TFTs with different characteristics and to reduce the circuit area.

A thin film device according to one embodiment of the present disclosure includes a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film, a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode, a bottom gate insulating layer including the bottom gate insulating film, and a storage capacitor for holding a signal voltage to be applied to the bottom gate electrode. The first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region. The second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region. The first electrode of the storage capacitor includes a part of the bottom gate electrode. The second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer. The capacitance per unit area of the bottom gate insulating film is smaller than the capacitance per unit area of the top gate insulating film.

A thin film device according to another aspect of the present disclosure includes a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film, a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode, a bottom gate insulating layer including the bottom gate insulating film, and a storage capacitor for holding a signal voltage to be applied to the bottom gate electrode. The first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region. The second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region. The first electrode of the storage capacitor includes a part of the bottom gate electrode. The second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer. The first channel region and the second channel region each consist of a lower layer with low mobility and an upper layer with high mobility.

A thin film device according to another aspect of the present disclosure includes a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film, a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode, a bottom gate insulating layer including the bottom gate insulating film, and a storage capacitor for holding a signal voltage to be applied to the bottom gate electrode. The first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region. The second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region. The first electrode of the storage capacitor includes a part of the bottom gate electrode. The second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer. The first channel region and the second channel region are each composed of a lower layer and an upper layer whose constituent elements or composition ratios of constituent elements are different from each other.

According to one aspect of the present disclosure, the size of a circuit including oxide semiconductor TFTs with different characteristics can be reduced.

1 shows a schematic configuration example of an OLED display device. 2 shows a configuration example of a pixel circuit. 4 shows another example of the configuration of the pixel circuit. 4 shows another example of the configuration of the pixel circuit. 2 shows a schematic diagram of current-voltage characteristics of a switch TFT. 1 shows a schematic diagram of the current-voltage characteristics of a driving TFT, where the horizontal axis indicates the gate voltage (gate-source voltage) and the vertical axis indicates the drain current. 1 shows the current-voltage characteristics of an oxide semiconductor TFT having a gate insulating film with a thickness of 200 nm. The current-voltage characteristics of an oxide semiconductor TFT with a gate insulating film thickness of 350 nm are shown. The current-voltage characteristics of an IGZTO-TFT having a (relatively) high mobility (mobility μ ∼ 30 [cm ² /Vs]) are shown. The current-voltage characteristics of an IGZO-TFT with (relatively) low mobility (mobility μ~10 [cm ² /Vs]) are shown. 2A and 2B are schematic diagrams illustrating examples of cross-sectional structures of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. 2A and 2B are schematic diagrams illustrating examples of cross-sectional structures of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. 2A and 2B are schematic diagrams illustrating examples of cross-sectional structures of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. 11A and 11B are schematic diagrams illustrating other examples of the cross-sectional structures of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. 11A and 11B are schematic diagrams illustrating other examples of the cross-sectional structures of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. 11A and 11B are schematic diagrams illustrating other examples of the cross-sectional structures of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. 11A and 11B are schematic diagrams illustrating other examples of the cross-sectional structures of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate. 1 shows a process of an example of a method for manufacturing a TFT substrate.

Below, an embodiment of the present invention will be described with reference to the attached drawings. It should be noted that this embodiment is merely one example for realizing the present invention, and does not limit the technical scope of the present invention. The same reference symbols are used for common configurations in each drawing. For ease of understanding, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

[Summary]
In the following, an OLED (Organic Light-Emitting Diode) display device will be described as an example of a thin-film device. The OLED display device of the present disclosure includes oxide semiconductor thin-film transistors (TFTs) with different characteristics, for example, in a pixel circuit. A first oxide semiconductor TFT includes a top gate electrode, and another second oxide semiconductor TFT includes a bottom gate electrode. For example, the first oxide semiconductor TFT is a switch TFT, and the second oxide semiconductor TFT is a drive TFT.

The difference in gate structure between the first oxide semiconductor TFT and the second oxide semiconductor TFT allows each to have appropriate characteristics. In addition, the source/drain region of the second oxide semiconductor TFT contacts the bottom gate of the first oxide semiconductor TFT through a contact hole in the bottom gate insulating layer, thereby reducing the number of contact holes and making the circuit area smaller.

The characteristic configuration of the pixel circuit including the oxide semiconductor TFT disclosed below can be applied to other circuits within the display device and to circuits of thin-film devices in devices other than the display device.

[Display Device Configuration]
1 is a schematic diagram showing a configuration example of an OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which an OLED element is formed, a sealing substrate 20 for sealing an organic light-emitting element, and a bonding portion (glass frit seal portion) 30 for bonding the TFT substrate 10 and the sealing substrate 20. Dry nitrogen, for example, is filled between the TFT substrate 10 and the sealing substrate 20, and the TFT substrate 10 and the sealing substrate 20 are sealed by the bonding portion 30. The sealing substrate 20 and the bonding portion 30 are one of the sealing structure portions, and as another example, the sealing structure portion may have, for example, a thin film encapsulation structure (TFE: Thin Film Encapsulation).

A scanning driver 31, an emission driver 32, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation area 14 outside the display area 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via an FPC (Flexible Printed Circuit) 35. The scanning driver 31 and the emission driver 32 are peripheral circuits formed on the TFT substrate 10.

The scan driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emission period of each pixel. The driver IC 34 is implemented using, for example, an anisotropic conductive film (ACF).

The driver IC 34 provides power and timing signals (control signals) to the scan driver 31 and the emission driver 32. In addition, the driver IC 34 provides power and data signals to the demultiplexer 36.

The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 switches the data line to which the data signal from the driver IC 34 is output d times within a scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 34.

[Pixel circuit configuration]
A plurality of pixel circuits are formed on the TFT substrate 10, each of which controls a current supplied to an anode electrode of a plurality of sub-pixels (also simply called pixels). Fig. 2A shows an example of the configuration of the pixel circuits. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1 that stores a signal voltage to the gate of the drive transistor T1. The pixel circuit controls the emission of light from an OLED element E1.

The selection transistor T2 is a switch (switch transistor) that selects a subpixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate is connected to the scanning line 16. One source/drain is connected to the data line 15. The other source/drain is connected to the gate of the drive transistor T1.

The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is an n-channel oxide semiconductor TFT, and its gate is connected to the source/drain of the selection transistor T2. One source/drain of the driving transistor T1 is connected to the source/drain of the emission transistor T3. The other source/drain is connected to the OLED element E1 and the storage capacitor C1. The storage capacitor C1 is formed between the gate and source/drain (source) of the driving transistor T1.

The emission transistor T3 is a switch that controls the supply and stop of the drive current to the OLED element E1. The emission transistor T3 is an n-channel oxide semiconductor TFT, and the gate is connected to the emission control line 17. One source/drain of the emission transistor T3 is connected to the source/drain of the drive transistor T1. The other source/drain is connected to the power supply line 18. The emission transistor T3 may be disposed between the OLED element E1 and the drive transistor T1.

Next, the operation of the pixel circuit will be described. The scanning driver 31 outputs a selection pulse to the scanning line 16, turning on the selection transistor T2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the holding capacitance C1. The holding capacitance C1 holds the stored voltage throughout one frame period. The hold voltage causes the conductance of the driving transistor T1 to change in an analog manner, and the driving transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

The emission transistor T3 is located on the supply path of the drive current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on/off of the emission transistor T3. When the emission transistor T3 is in the on state, the drive current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, this supply is stopped. By controlling the on/off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled.

Figure 2B shows another example of the configuration of a pixel circuit. This pixel circuit has a reset transistor T4 instead of the emission transistor T3 in Figure 2A. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from a reset control line 19 to the gate of the reset transistor T4. The reset transistor T4 can be used for various purposes.

Figure 2C shows another example of the pixel circuit configuration. This pixel circuit includes transistors T1 to T6, which are n-channel TFTs. A Vscan2 signal is input to the gate of transistor T2, and a Vscan1 signal is input to the gates of transistors T4 and T6. A data signal (voltage) is provided to the storage capacitor C1 via transistors T2, T1, and T6, and the threshold voltage of transistor T1 is corrected. Transistor T4 provides Vref to the anode of OLED element E1. Transistors T3 and T5 are connected in series with drive transistor T1, and signals Vem1 and Vem2 are input to their gates, respectively, to control whether or not OLED element E1 emits light.

In the circuit configuration of FIG. 2C, the gate of the drive transistor T1 is connected to the source/drain of the switch transistor T6. The storage capacitor C1 is connected to the gate of the drive transistor T1 and to a node between the source/drain of the switch transistor T3 and the OLED element E1. The storage capacitor C1 holds the gate voltage (gate-source voltage) that determines the amount of drive current supplied by the drive transistor T1.

The pixel circuit described above includes a drive TFT (T1), a storage capacitor (C1) that holds a signal voltage between the source/drain and gate of the drive TFT, and a switch TFT (T2 or T6) whose source/drain is connected to the gate of the drive TFT. The circuit shown in FIG. 2C further includes a transistor T3 connected in series with the drive transistor T1. The pixel circuit structure described in this specification can provide specific characteristics to the drive TFT and switch TFT, reduce the pixel circuit area, and contribute to high definition. Note that the pixel circuits in FIGS. 2A, 2B, and 2C are examples, and the pixel circuit may have other circuit configurations.

[Characteristics of Switch TFT and Driving TFT]
Fig. 3A shows a schematic diagram of the current-voltage characteristics of the switch TFT. The horizontal axis shows the gate voltage (gate-source voltage) and the vertical axis shows the drain current. Fig. 3B shows a schematic diagram of the current-voltage characteristics of the drive TFT. The horizontal axis shows the gate voltage (gate-source voltage) and the vertical axis shows the drain current.

The switch TFT is required to have a sharp rise characteristic of the drain current with respect to the gate voltage (low S value [V/dec]) in order to turn on/off in response to the gate signal. The S value is expressed as the reciprocal of the slope in the graph shown in Figure 3A. A low S value allows the operating voltage amplitude (gate voltage amplitude) of the switch TFT to be lowered, and as a result, the voltage applied to the gate of the TFT can be reduced (the gate voltage stress applied to the TFT is reduced), reducing the variation in the threshold voltage.

On the other hand, the driving TFT that controls the amount of current to the OLED element is required to have a gradual rise characteristic (high S value). A high S value widens the usable range of the data signal (Vdata), and also reduces the effect of threshold voltage fluctuations at low gradations (low gate voltages).

There are two factors that determine the S value of a TFT. One factor is the capacitance of the gate insulating film. The S value can be increased by increasing the gate insulating film capacitance. The other factor is the density of interface defect states at the interface between the semiconductor film (channel region) and the gate insulating film. The S value can be increased by increasing the density of interface defect states.

Figures 4A and 4B show examples of measurements of the current-voltage characteristics of oxide semiconductor TFTs with different gate insulating film thicknesses. Figure 4A shows the current-voltage characteristics of an oxide semiconductor TFT with a gate insulating film thickness of 200 nm. Figure 4B shows the current-voltage characteristics of an oxide semiconductor TFT with a gate insulating film thickness of 350 nm.

The S value of the oxide semiconductor TFT with a (relatively) thin gate insulating film shown in Figure 4A is 0.2 V/dec. On the other hand, the S value of the oxide semiconductor TFT with a (relatively) thick gate insulating film shown in Figure 4B is 0.3 V/dec. Increasing the thickness of the gate insulating film increases the gate insulating film capacitance. As shown by these measurement results, the S value of the oxide semiconductor TFT can be increased by increasing the gate insulating film capacitance.

5A and 5B show examples of measurement of current-voltage characteristics of oxide semiconductor TFTs using oxide semiconductors with different mobilities. Fig. 5A shows the current-voltage characteristics of an IGZTO-TFT with (relatively) high mobility (mobility μ ∼ 30 [cm ² /Vs]). Fig. 5B shows the current-voltage characteristics of an IGZO-TFT with (relatively) low mobility (mobility μ ∼ 10 [cm ² /Vs]).

The S value of the oxide semiconductor TFT with a (relatively) low mobility shown in FIG. 5B is greater than the S value of the oxide semiconductor TFT with a (relatively) high mobility shown in FIG. 5A. A smaller mobility means that the density of interface defect states in the oxide semiconductor film is greater. Therefore, as shown by this measurement result, the S value of the oxide semiconductor TFT can be increased by decreasing the mobility of the oxide semiconductor, that is, by increasing the density of interface defect states.

[Device structure]
Based on the above findings, a structural example of a pixel circuit including a switch oxide semiconductor TFT (hereinafter also simply referred to as a switch TFT) and a drive oxide semiconductor TFT (hereinafter also simply referred to as a drive TFT) having different characteristics will be described below.

Figure 6A shows a schematic example of the cross-sectional structure of a switch oxide semiconductor TFT (first oxide semiconductor TFT) and a drive oxide semiconductor TFT (second oxide semiconductor TFT). A switch TFT 210, a drive TFT 220, and a storage capacitor 230 are formed on a flexible or inflexible insulating substrate made of resin or glass (not shown).

The switch TFT 210, the drive TFT 220, and the storage capacitor 230 correspond to the selection transistor T2, the drive transistor T1, and the storage capacitor C1 shown in FIG. 2A or 2B, respectively.

The driving TFT 220 includes a bottom gate electrode 153 and a bottom gate insulating layer (G insulating layer) 155 between the bottom gate electrode 153 and a metal oxide film (second metal oxide film). The metal oxide film includes source/drain regions (S/D regions) 111, 113 and a channel region 109 between the source/drain regions 111, 113 in the in-plane direction. The bottom gate insulating layer 155 is, for example, a silicon oxide layer or a stack of silicon oxide (upper side)/silicon nitride (lower side).

The metal oxide film is formed directly on (in contact with) the gate insulating layer 155. The metal oxide is, for example, IGZO (Indium Gallium Zinc Oxygen). The source/drain regions 111 and 113 are formed of a metal oxide with reduced resistance. The channel region 109 is formed of a metal oxide (semiconductor) that is not reduced in resistance.

The bottom gate electrode 153 (part of it) faces the channel region 109 with the bottom gate insulating layer 155 in between. The bottom gate electrode 153, the bottom gate insulating layer 155, and the channel region 109 are stacked in this order from below (from the substrate side). The gate insulating layer 155 is in contact with the channel region 109 and the bottom gate electrode 153. The part of the bottom gate insulating layer 155 that is in contact with the bottom gate electrode 153 and the channel region 109 is the bottom gate insulating film of the driving TFT 220.

A data signal (signal voltage) is applied to the bottom gate electrode 153 to control the drive current to the OLED element. A part of the bottom gate electrode 153 faces at least a part of the source/drain region 113, sandwiching a bottom gate insulating layer 155 therebetween. A storage capacitor 230 is formed between the source/drain region 113 and the bottom gate electrode 153. A part of the bottom gate electrode 153 constitutes the lower electrode (first electrode) of the storage capacitor. A part of the source/drain region 113 facing the lower electrode constitutes the upper electrode (second electrode). The storage capacitor 230 holds the signal voltage applied to the bottom gate electrode 153.

The driving TFT 220 further includes a top gate electrode 125 and a gate insulating film 117 that is present between the top gate electrode 125 and the channel region 109 in the stacking direction. The gate insulating film 117 is, for example, a silicon oxide film, a silicon nitride film, or a stacked film of these. The channel region 109, the gate insulating film 117, and the top gate electrode 125 are stacked in this order from below (from the substrate side), and the gate insulating film 117 is in contact with the channel region 109 and the top gate electrode 125.

The top gate electrode 125 is, for example, electrically floating. The top gate electrode 125 can be used as a mask for the formation of the source/drain regions 111, 113 (self-aligned). The top gate electrode 125 can also block external light from reaching the channel region 109.

The switch TFT 210 includes a metal oxide film (first metal oxide film) on the gate insulating layer 155. In the example of FIG. 6A, the metal oxide film is formed directly on the gate insulating layer 155. The metal oxide film includes source/drain regions 105, 107, and a channel region 103 between the source/drain regions 105 and 107 in the in-plane direction. The metal oxide is, for example, IGZO.

The source/drain regions 105, 107 are formed of a metal oxide with reduced resistance. The channel region 103 is formed of a metal oxide that has not been reduced in resistance (high-resistance metal oxide). The metal oxide film of the switch TFT 210 is included in the same metal oxide layer as the metal oxide film of the drive TFT 220, and is deposited at the same time.

The switch TFT 210 further includes a top gate electrode 123 and a gate insulating film 115 that is present between the top gate electrode 123 and the channel region 103 in the stacking direction. The gate insulating film 115 is, for example, a silicon oxide film, a silicon nitride film, or a stacked film of these. The channel region 103, the gate insulating film 115, and the top gate electrode 123 are stacked in this order from below (from the substrate side), and the gate insulating film 115 is in contact with the channel region 103 and the top gate electrode 123.

The gate insulating film 115 of the switch TFT 210 is included in the same insulating layer as the gate insulating film 117 of the drive TFT 220, and is deposited at the same time. The top gate electrode 123 is included in the same metal layer as the top gate electrode 125 of the drive TFT 220, and is deposited at the same time. The switch TFT 210 does not have a bottom gate electrode like the drive TFT 220, but may have a bottom gate electrode, or may be electrically connected so that the bottom gate electrode and the top gate electrode are at the same potential.

The source/drain region 105 includes a contact portion 151 in a contact hole formed in the gate insulating layer 155, and is in contact (directly connected) with the bottom gate electrode 153 at the contact portion 151.

The interlayer insulating layer 121 is formed to cover the switch TFT 210 and the drive TFT 220. The source/drain electrodes 127, 128, and 129 are in contact with the source/drain regions 111, 113, and 107, respectively, in contact holes formed in the interlayer insulating layer 121. The source/drain electrodes 127, 128, and 129 are included in the same metal layer and are deposited simultaneously.

In the configuration example shown in FIG. 6A, the characteristics of the switch TFT 210 and the drive TFT 220 can be controlled by adjusting the thickness d1 of the (top) gate insulating film 115 of the switch TFT 210 and the thickness d2 of the bottom gate insulating layer 155 of the drive TFT 220. As shown in FIG. 6A, the thickness d1 of the (top) gate insulating film 115 is thinner than the thickness d2 of the bottom gate insulating layer 155.

As a result, the capacitance per unit area of the top gate insulating film of the switch TFT 210 becomes larger than the capacitance per unit area of the bottom gate insulating film (included in the bottom gate insulating layer) of the drive TFT 220. This makes it possible to make the S value of the switch TFT 210 smaller than the S value of the drive TFT 220.

Furthermore, since the source/drain region 105 of the switch TFT 210 and the bottom gate electrode 153 are in contact with each other through contact holes in the gate insulating layer 155, the number of contact holes for connection between the switch TFT 210 and the drive TFT 220 can be reduced.

Figure 6B shows a schematic example of the cross-sectional structure of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. In the drive TFT 223 shown in Figure 6B, the top gate electrode 125 of the drive TFT 220 shown in Figure 6A is omitted. In this way, the top gate electrode of the drive TFT can be omitted. Other components of the configuration example of Figure 6B are the same as those of the configuration example shown in Figure 6A.

Figure 6C shows a schematic example of the cross-sectional structure of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. The drive TFT 226 shown in Figure 6C includes a source/drain electrode 131 that connects the top gate electrode 125 and the source/drain region 113. The source/drain electrode 131 maintains the top gate electrode 125 and the source/drain region 113 at the same potential. In this way, by maintaining the top gate electrode 125 and the source/drain region 113 at the same potential, the top channel side potential is stabilized, and more preferable saturation characteristics can be obtained for the drive TFT. The other components of the configuration example of Figure 6C are the same as those of the configuration example shown in Figure 6A.

In the configuration examples shown in Figures 6A to 6C, a part of the bottom gate electrode 153 forms the lower electrode of the storage capacitor, and a part of the source/drain region 113 facing the lower electrode forms the upper electrode. In the pixel circuit described with reference to Figure 2C, the storage capacitor is formed between the gate of the drive transistor T1 and the source/drain of the switch transistor T3 (third oxide semiconductor thin film transistor). In this configuration, the upper electrode of the storage capacitor may include at least a part of the source/drain region of the switch transistor T3. For example, a part of the source/drain region of the switch transistor T3 facing the lower electrode may form the upper electrode. This is the same in the configuration examples shown in Figures 8 and 10.

Figure 7 shows another example of the cross-sectional structure of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. The following mainly describes the differences from Figure 6A. The configuration example shown in Figure 7 includes a storage capacitor 250 having a different structure from the storage capacitor 230 in the configuration example shown in Figure 6A. Note that Figure 7 shows the shape of the contact portion 151 differently from the shape of the contact portion 151 shown in Figure 6A, but this is merely a difference in how it is depicted in the schematic diagram, and the structure is the same.

The storage capacitor 250 in the configuration example shown in FIG. 7 is formed between (a part of) the bottom gate electrode 168 and (a part of) the top gate electrode 167 of the driving TFT 240. In FIG. 7, the curve with black circles at both ends connecting the bottom gate electrode 168 and the top gate electrode 167 means that the two end portions are physically connected in-plane, that is, they are part of a continuous film.

In the configuration example shown in FIG. 7, the storage capacitor 250 is composed of a stacked film of holes formed in the gate insulating layer 155. Specifically, the bottom gate electrode 168 (part of it), the oxide semiconductor film 163, the insulating film 165, and the top gate electrode 167 (part of it) are stacked in this order from below (from the substrate side). The oxide semiconductor film 163 is in contact with the bottom gate electrode 168 and the insulating film 165. The insulating film 165 is in contact with the top gate electrode 167.

This configuration of the storage capacitor 250 allows the thickness between the electrodes to be reduced, and the area required to secure the required capacitance to be reduced. As a result, the area of the pixel circuit can be reduced.

The oxide semiconductor film 163 is included in the same layer as the metal semiconductor film of the switch TFT 210 and the metal semiconductor film of the drive TFT 240, and is deposited simultaneously. The insulating film 165 is included in the same layer as the (top) gate insulating film 115 of the switch TFT 210 and the (top) gate insulating film 117 of the drive TFT 240, and is deposited simultaneously.

In the configuration example shown in FIG. 7, the storage capacitor 250 includes an oxide semiconductor film 163 formed to cover a portion of the bottom gate electrode 168. As described below, the oxide semiconductor film 163 can prevent a portion of the bottom gate electrode 168 that constitutes a portion of the storage capacitor 250 from being etched or damaged by an etchant for the oxide semiconductor film during the manufacture of an OLED display device.

The configuration example shown in FIG. 7 further includes a source/drain electrode 161 that connects the top gate electrode 167 and the source/drain region 113 of the driving TFT 240. The source/drain electrode 161 maintains the top gate electrode 167 and the source/drain region 113 at the same potential. In this way, by maintaining the top gate electrode 167 and the source/drain region 113 at the same potential, the top channel side potential is stabilized, and more preferable saturation characteristics can be obtained for the driving TFT. The source/drain electrode 161 may be omitted. This is the same in the configuration examples shown in FIGS. 9 and 10.

Figure 8 shows another example of the cross-sectional structure of the switch oxide semiconductor TFT and the drive oxide semiconductor TFT. In the following, the differences from Figure 6A will be mainly described. In the configuration example shown in Figure 8, the switch TFT and the drive TFT include stacked metal oxide films with different characteristics. This makes it possible to realize characteristics suitable for the respective functions of the switch TFT and the drive TFT.

In the configuration example shown in FIG. 8, the driving TFT 270 includes two stacked layers of metal semiconductor films. The lower metal semiconductor film includes source/drain regions (S/D regions) 311, 313 and a channel region 309 between the source/drain regions 311, 313 in the in-plane direction.

The two stacked metal oxide semiconductor films have different composition ratios. For example, the upper layer is InGaZnO with an In:Ga:Zn composition ratio of 2:1:1, and the lower layer is InGaZnO with an In:Ga:Zn composition ratio of 1:1:1, so the composition ratios are different. In this case, InGaZnO with a high In composition ratio of 2:1:1 has a higher electron mobility than InGaZnO with a low In composition ratio of 1:1:1. Using this type of configuration makes it possible to achieve two different characteristics, as shown in Figures 3A and 3B.

Alternatively, the two stacked metal oxide semiconductor films may have different constituent elements. For example, the upper layer may be InGaZnO and the lower layer may be ZnO. In this case, InGaZnO has a higher electron mobility than ZnO. IGZTO, IGO, IZO, etc. may also be used for the upper layer. By using such a configuration, two different characteristics can be realized as shown in Figures 3A and 3B.

In these configurations, the underlying metal oxide semiconductor film is connected to the bottom gate electrode 153. The underlying metal oxide film is made of a (relatively) low mobility material (high defect density material), such as IGZO.

The upper metal semiconductor film includes source/drain regions (S/D regions) 411, 413 and a channel region 409 between the source/drain regions 411, 413 in the in-plane direction. The upper metal oxide film is made of a (relatively) high mobility material (low defect density material), such as IGZTO (Indium Gallium Zinc Tin Oxide). Metal oxides with a higher density of indium elements exhibit higher electron mobility, i.e., low defect density. Other high mobility materials include IGO (Indium Gallium Oxide) and IZO (Indium Zinc Oxide), and low mobility materials include ZnO (Zinc Oxide).

In the configuration example of FIG. 8, the lower channel region 309 and the upper channel region 409 of the driving TFT 270 have the same planar shape. The same is true for the source/drain regions. The source/drain electrodes 127 and 128 are in contact with the source/drain regions 411 and 413 of the upper metal oxide film, respectively, in contact holes formed in the interlayer insulating layer 121.

The switch TFT 260 includes two stacked metal semiconductor films. The lower metal semiconductor film includes source/drain regions (S/D regions) 305, 307 and a channel region 303 between the source/drain regions 305, 307 in the in-plane direction. The lower metal oxide film is made of a (relatively) low mobility material (high defect level density material), such as IGZO. The source/drain region 305 includes a contact portion 351 in a contact hole formed in the gate insulating layer 355, and is in contact (direct connection) with the bottom gate electrode 153 at the contact portion 351.

The upper metal semiconductor film includes source/drain regions (S/D regions) 405, 407 and a channel region 403 between the source/drain regions 405, 407 in the in-plane direction. The upper metal oxide film is made of a (relatively) high mobility material (low defect level density material), such as IGZTO.

In the configuration example of FIG. 8, the lower channel region 303 and the upper channel region 403 of the switch TFT 260 have the same planar shape. The same is true for the source/drain regions. The source/drain electrodes 129 are in contact with the source/drain regions 407 of the upper metal oxide film in contact holes formed in the interlayer insulating layer 121.

In the configuration example of FIG. 8, the metal oxide films of the lower layers of the switch TFT 260 and the drive TFT 270 are included in the same metal oxide layer and are deposited simultaneously. The metal oxide films of the upper layers of the switch TFT 260 and the drive TFT 270 are included in the same metal oxide layer and are deposited simultaneously. The upper and lower metal oxide films of the switch TFT 260 and the drive TFT 270 are etched simultaneously, so that the source/drain regions can be formed simultaneously.

In the switch TFT 260, the upper channel region 403 forms an interface with the (top) gate insulating film 115. The upper channel region 403 of the switch TFT 260 is made of a high-mobility material and exhibits a low S value. This makes it possible to obtain characteristics that are more suitable for the switch TFT 260.

On the other hand, in the driving TFT 270, the lower channel region 309 forms an interface with the bottom gate insulating layer 355. The lower channel region 309 of the driving TFT 270 is formed of a low mobility material and exhibits a high S value. This allows more favorable characteristics for the driving TFT 270 to be obtained.

By achieving a high S value for the driving TFT 270 through the characteristics of the channel region, the thickness of the bottom gate insulating layer 355 can be reduced. This allows the area of the storage capacitor 280 formed between the bottom gate electrode 153 and the source/drain region 313 to be reduced. The channels of the switch oxide semiconductor TFT and the driving oxide semiconductor TFT may be formed from different metal oxides.

Figure 9 shows a schematic diagram of another example of the cross-sectional structure of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. The following mainly describes the differences from Figure 7. In the storage capacitor 290 of the configuration example shown in Figure 9, the oxide semiconductor film 163 of the storage capacitor 250 shown in Figure 7 is removed. This makes it possible to make the capacitance insulating film of the storage capacitor 290 thinner and reduce the area of the storage capacitor 290. In addition, since the storage capacitor 290 does not include an oxide semiconductor film, it is more stable.

As described above, the oxide semiconductor film 163 has the function of preventing etching of the bottom gate electrode 168. To realize the configuration example shown in FIG. 9, in the manufacture of an OLED display device, for example, in etching the metal oxide layer, the amount of etching of the bottom gate electrode 168 by the etching solution is adjusted, or a selective etching solution is used.

Figure 10 shows another example of the cross-sectional structure of a switch oxide semiconductor TFT and a drive oxide semiconductor TFT. In the following, differences from Figure 7 will be mainly described. The configuration example shown in Figure 10 includes a switch TFT 510, a drive TFT 520, and a storage capacitor 530.

The configuration example shown in FIG. 10 includes a bottom gate insulating layer 540 made of multiple stacked insulating layers. In the configuration example of FIG. 10, the gate insulating layer 540 is made of two insulating layers, a lower insulating layer 541 and an upper insulating layer 543. The lower insulating layer 541 and the upper insulating layer 543 are present between the bottom gate electrode 168 and the channel region 109 of the driving TFT 520. Note that other insulating films may be present between the lower insulating layer 541 and the upper insulating layer 543.

The upper insulating layer 543 is formed of, for example, silicon oxide. The metal oxide films of the switch TFT 510 and the drive TFT 520 are formed on and in contact with the upper insulating layer 543. The upper insulating layer 543 formed of silicon oxide is one of the materials that can obtain better characteristics of a metal oxide film (oxide semiconductor). The lower insulating layer 541 is formed of a material having a higher dielectric constant than the upper insulating layer 543. The lower insulating layer 541 can be formed of, for example, silicon nitride or alumina.

The storage capacitor 530 is formed between a part of the bottom gate electrode 168 and a part of the source/drain region 551 of the driving TFT 520. A hole is formed in the upper insulating layer 543, and a part 553 of the source/drain region 551 is formed in contact with the lower insulating layer 541 within the hole. The storage capacitor 530 is composed of a part 553 of the source/drain region 551 (second electrode or upper electrode), a part of the lower insulating layer 541, and a part of the bottom gate electrode 168 (first electrode or lower electrode). The capacitance insulating film of the storage capacitor 530 is a layer of the lower insulating layer 541 formed of a material with a high relative dielectric constant, and the area of the storage capacitor 530 can be reduced.

In the configuration examples described with reference to Figures 6A, 6B, 6C, 8 and 10, a storage capacitor is formed between the source/drain region of the drive TFT and the bottom gate electrode. As shown in the circuit configuration example of Figure 2C, the storage capacitor can be formed between the gate of the drive TFT and the source/drain region of the switch TFT directly connected to the drive TFT. For example, in the configuration examples shown in Figures 6A, 6B, 6C, 8 or 10, a part of the bottom gate electrode faces at least a part of the source/drain region of the switch TFT with the insulating layer 155, 355, 541 sandwiched therebetween.

In the configuration examples described with reference to Figures 6A to 10, some of the components can be applied to the configuration examples of other drawings. For example, the storage capacitance structure shown in Figure 7 or 9 can be applied to the configuration example of Figure 8. An element that makes the top gate electrode and the source/drain regions have the same potential as shown in Figures 7, 9, etc. can be applied to the configuration example of Figure 8.

[Production method]
Next, a method for manufacturing the configuration example shown in Fig. 7 will be described. Fig. 11A to Fig. 11G show an example of the manufacturing method. In Fig. 11A to Fig. 11G, the ranges of the switch TFT 210, contact portion 151, storage capacitor 250, and drive TFT 240 to be created are indicated in advance by arrows for ease of understanding.

As shown in FIG. 11A, the manufacturing method involves forming a metal layer on an insulating substrate (not shown) by sputtering or the like, and then forming a bottom gate electrode 168 by photolithography and etching. Any metal material may be used, and examples of the metal that may be used include Mo, W, Nb, and Al.

11B, the manufacturing method involves forming an insulating layer (e.g., a silicon oxide layer) by CVD or the like, and forming a (bottom) gate insulating layer 155 by photolithography and etching. In the gate insulating layer 155, a hole 561 for forming the contact portion 151 and a hole 562 for forming the storage capacitor 250 are formed.

11C, the manufacturing method involves forming an oxide semiconductor layer (metal oxide layer) by sputtering or the like, and forming an oxide semiconductor pattern 565 by photolithography and etching. A part of the oxide semiconductor layer (oxide semiconductor film) is also formed in the holes 561 and 562 of the bottom gate insulating layer 155. As described above, the oxide semiconductor film 163 in the hole 562 covers the bottom gate electrode 168 so as not to be exposed to the etching solution.

Next, as shown in FIG. 11D, the manufacturing method involves forming an insulating layer (e.g., a silicon oxide layer) by CVD or the like, and then forming top gate insulating films 115, 117 and a storage capacitor insulating film 165 by photolithography and etching. Furthermore, a metal layer is formed by sputtering or the like, and then forming top gate electrodes 123, 167 by photolithography and etching. Any metal material may be used, and examples of the metal that may be used include Mo, W, Nb, and Al.

Next, as shown in FIG. 11E, the manufacturing method uses the top gate electrodes 123 and 167 as a mask to reduce the resistance of the source/drain regions of the oxide semiconductor layer. The reduction in resistance is achieved, for example, by exposing the source/drain regions of the oxide semiconductor layer to He plasma. The reduction in resistance may also be achieved by ion implantation of B, Ar, H, etc.

Next, as shown in FIG. 11F, the manufacturing method involves depositing an insulating layer (e.g., a silicon oxide layer) by a CVD method or the like, and forming an interlayer insulating layer 121 by photolithography and etching.

Next, as shown in FIG. 11G, the manufacturing method involves forming a metal layer by a sputtering method or the like, and then forming a metal layer including source/drain electrodes 161 by photolithography and etching. This metal layer includes the source/drain electrodes and data lines of the TFTs of the pixel circuit. The material and layered structure of this metal layer are arbitrary, and it is formed, for example, by depositing a conductive film such as Ti/Al/Ti and patterning it.

The manufacturing method further includes forming an insulating layer (e.g., a silicon oxide layer) by a CVD method or the like, forming a passivation layer 571 by photolithography and etching, and further forming an overcoat layer 573 made of an organic material on top of the passivation layer 571. An anode electrode 577 is formed on the overcoat layer 573, and contacts the source/drain electrodes 161 through contact holes formed in the passivation layer 571 and the overcoat layer 573.

The anode electrode 577 includes, for example, three layers: a transparent conductive film, a metal reflective film, and a transparent conductive film. The transparent conductive material is, for example, ITO, IZO, etc. The reflective metal material is, for example, Ag, Mg, Al, etc. The anode electrode 577 can be formed by sputtering and etching.

The manufacturing method further includes depositing a photosensitive organic resin film by spin coating or the like, and patterning the film to form a pixel definition layer 579. A hole is formed in the pixel definition layer 579, and the anode electrode 577 is exposed at the bottom of the hole. The pixel definition layer 579 separates the light-emitting regions of each sub-pixel. The manufacturing of the TFT substrate 10 further includes depositing an organic light-emitting material for each of the RGB colors to form an organic light-emitting film (not shown) on the anode electrode 577, and then forming a cathode electrode (not shown) over the entire surface of the substrate.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily modify, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

1 OLED display device, 10 TFT substrate, 11 reference voltage supply line, 14 cathode electrode forming area, 15 data line, 16 scanning line, 17 emission control line, 18 power supply line, 19 reset control line, 20 sealing substrate, 25 display area, 30 junction, 31 scanning driver, 32 emission driver, 36 demultiplexer, 103, 109, 303, 309, 403, 409 channel area, 105, 111, 113, 305, 311, 313, 405, 407, 411, 551 source/drain area, 115, 117 top gate insulating film, 121 interlayer insulating layer, 123, 125, 167 top gate electrode, 127, 129, 131, 161 source/drain electrode, 151, 351 contact portion, 153, 168 Bottom gate electrode, 155, 355, 540 Bottom gate insulating layer, 163 Oxide semiconductor film, 165 Insulating film, 210, 260, 510 Switch TFT, 220, 223, 226, 240, 270, 520 Drive TFT, 230, 250, 280, 290, 530 Storage capacitor, 541 Lower insulating layer, 543 Upper insulating layer, 561, 562 Hole, 571 Passivation layer, 573 Overcoat layer, 577 Anode electrode, 579 Pixel definition layer, C1 Storage capacitor, E1 OLED element, 34 Driver IC, T1 Drive transistor, T2 Selection (switch) transistor, T3 Emission transistor, T4 Reset transistor

Claims (12)

a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
a portion of the second source/drain region and the bottom gate electrode overlap in a stacking direction , and the portion of the second source/drain region is in direct contact with the bottom gate electrode within a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
Thin film devices. 2. The thin film device of claim 1 ,
The bottom gate insulating film is thicker than the top gate insulating film.
Thin film devices. 2. The thin film device of claim 1 ,
The second oxide semiconductor thin film transistor further includes a top gate electrode;
a top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the third and fourth source/drain regions of the second oxide semiconductor thin film transistor so as to have the same potential;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
The second oxide semiconductor thin film transistor further includes a top gate electrode;
a top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the third and fourth source/drain regions of the second oxide semiconductor thin film transistor so as to have the same potential;
The retention capacity is
a metal oxide film included in the same layer as the first metal oxide film and the second metal oxide film, the metal oxide film being stacked on and in contact with the portion of the bottom gate electrode;
a structure including an insulating film included in the same layer as the top gate insulating film and laminated on and in contact with the metal oxide film; and a part of a top gate electrode of the second oxide semiconductor thin film transistor laminated on and in contact with the insulating film,
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
The second oxide semiconductor thin film transistor further includes a top gate electrode;
a top gate electrode of the second oxide semiconductor thin film transistor is connected to one of the third and fourth source/drain regions of the second oxide semiconductor thin film transistor so as to have the same potential;
The retention capacity is
a structural portion including an insulating film included in the same layer as the top gate insulating film of the first oxide semiconductor thin film transistor and stacked on the part of the bottom gate electrode in contact therewith; and a part of the top gate electrode of the second oxide semiconductor thin film transistor stacked on the insulating film in contact therewith;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
The bottom gate insulating layer includes a lower insulating layer and an upper insulating layer;
the bottom gate insulating film includes a part of the upper insulating layer and a part of the lower insulating layer,
the lower insulating layer has a higher dielectric constant than the upper insulating layer;
the storage capacitor includes a structural portion including a part of the lower insulating layer laminated on and in contact with a part of the bottom gate electrode, and a second electrode formed on and in contact with the part of the lower insulating layer,
Thin film devices. 2. The thin film device of claim 1 ,
the storage capacitor includes an insulating film included in the bottom gate insulating layer;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
the storage capacitor includes an insulating film included in the bottom gate insulating layer,
a second electrode of the storage capacitor including at least a portion of the third source/drain region;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
a capacitance per unit area of the bottom gate insulating film is smaller than a capacitance per unit area of the top gate insulating film;
the storage capacitor includes an insulating film included in the bottom gate insulating layer,
a second electrode of the storage capacitor including at least a part of a source/drain region of a third oxide semiconductor thin film transistor connected in series to the first oxide semiconductor thin film transistor;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
the second source/drain region and the bottom gate electrode are in contact with each other through a contact hole in the bottom gate insulating layer;
The first channel region and the second channel region each include a lower layer having a low mobility and an upper layer having a high mobility.
Thin film devices. 11. The thin film device of claim 10,
a density of indium elements contained in the lower oxide semiconductor layer is lower than a density of indium elements contained in the upper oxide semiconductor layer;
Thin film devices. a first oxide semiconductor thin film transistor including a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film;
a second oxide semiconductor thin film transistor including a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the second metal oxide film and the bottom gate electrode;
a bottom gate insulating layer including the bottom gate insulating film;
a storage capacitor for storing a signal voltage to be applied to the bottom gate electrode;
Including,
the first metal oxide film includes a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region;
the second metal oxide film includes a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region;
a first electrode of the storage capacitor includes a part of the bottom gate electrode;
a portion of the second source/drain region and the bottom gate electrode overlap in a stacking direction , and the portion of the second source/drain region is in direct contact with the bottom gate electrode within a contact hole in the bottom gate insulating layer;
The first channel region and the second channel region are each composed of a lower layer and an upper layer having different constituent elements or different composition ratios of constituent elements.
Thin film devices.

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