JP7635090B2 - Semiconductor device and method for controlling the semiconductor device - Google Patents

Description

Embodiments of the present invention relate to a semiconductor device and a method for controlling the semiconductor device.

Semiconductor devices such as insulated gate bipolar transistors (IGBTs) are used as switching elements. In order to reduce the on-resistance of an IGBT, it is effective to increase the carrier concentration in the drift region in the on-state. On the other hand, if the discharge of carriers from the drift region becomes slow when the IGBT is turned off, the turn-off time becomes longer and switching losses increase.

In semiconductor devices, there is a demand for suppressing element breakdown, reducing on-resistance, and reducing switching losses.

JP 2020-47790 A

The problem that the present invention aims to solve is to provide a semiconductor device that can reduce switching losses and suppress element breakdown, and a method for controlling the semiconductor device.

The semiconductor device according to the embodiment includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a first gate electrode, and a second gate electrode. The second electrode is provided apart from the first electrode in a first direction. The first semiconductor region of a first conductivity type is provided between the first electrode and the second electrode in the first direction. The second semiconductor region of a second conductivity type is provided between the first semiconductor region and the second electrode. The third semiconductor region of the second conductivity type is provided between the first semiconductor region and the first electrode and is electrically connected to the first electrode. The first gate electrodes face the second semiconductor region via a first insulating film in a second direction intersecting the first direction, and are insulated from the second electrode via a third insulating film in contact with the first insulating film. The second gate electrodes face the second semiconductor region via the second insulating film in the second direction, are insulated from the second electrode via a third insulating film in contact with the second insulating film, and are applied with a voltage different from that of the first gate electrode. The fourth semiconductor region of the first conductivity type is provided between the second semiconductor region and the second electrode, and faces the first gate electrode via the first insulating film or the third insulating film. The fifth semiconductor region of the second conductivity type is provided between the second semiconductor region and the second electrode, faces the second gate electrode via the second insulating film or the third insulating film, and has a boundary portion electrically in contact with the second electrode. The distance between the upper surface of the fourth semiconductor region and the first electrode is greater than the distance between the boundary portion and the first electrode.

1A is a plan view of the semiconductor device 100 according to the first embodiment; (b) a cross-sectional view taken along line A-A' in FIG. 1A; (c) a partial plan view of the semiconductor device 100 according to the first embodiment; (d) a schematic diagram of the semiconductor device circuit according to the first embodiment; 3A to 3C are explanatory diagrams of a method of driving the semiconductor device 100 according to the first embodiment. FIG. 1 is a cross-sectional view of a semiconductor device 500 according to a comparative example. FIG. 11 is a cross-sectional view of a semiconductor device 101 according to a modified example of the first embodiment. FIG. 11 is a cross-sectional view of a semiconductor device 200 according to a modified example of the second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device 201 according to a modified example of the second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device 300 according to a third embodiment. FIG. 11 is a cross-sectional view of a semiconductor device 400 according to a fourth embodiment. FIG. 11 is a plan view of a semiconductor device 400 according to a fourth embodiment. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment.

The following describes an embodiment of the present invention with reference to the drawings. In this description, common parts are given common reference numerals throughout the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the ratios shown in the drawings. Note that the present embodiment does not limit the present invention.

[First embodiment]
(Structure of the semiconductor device 100)
A semiconductor device 100 according to the first embodiment will be described with reference to Fig. 1. Fig. 1(a) is a plan view of the semiconductor device 100 according to the first embodiment, Fig. 1(b) is a cross-sectional view taken along line A-A' in Fig. 1(a), Fig. 1(c) is a partial plan view of the semiconductor device 100 according to the first embodiment, and Fig. 1(d) is a schematic diagram of the semiconductor device circuit according to the first embodiment.

The semiconductor device according to the first embodiment is a trench-gate type IGBT having a gate electrode in a trench formed in a semiconductor layer. The semiconductor device 100 according to the first embodiment is an IGBT capable of double gate drive. Below, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. In addition, in the following description, the notations n+, n, n-, p+, p, p- indicate the relative impurity concentration of each conductivity type. That is, n+ indicates that the n-type impurity concentration is relatively higher than n, and n- indicates that the n-type impurity concentration is relatively lower than n. Also, p+ indicates that the p-type impurity concentration is relatively higher than p, and p- indicates that the p-type impurity concentration is relatively lower than p. Note that n+ type and n- type may be simply referred to as n-type, and p+ type and p- type may be simply referred to as p-type.

The semiconductor device 100 according to the first embodiment has a collector electrode (first electrode) 11, an emitter electrode (second electrode) 12, a first gate electrode 13, a second gate electrode 14, a first gate electrode pad 21, a second gate electrode pad 22, an n- type drift region (first semiconductor region) 31, a p- type base region (second semiconductor region) 32, a p- type collector region (third semiconductor region) 33, an n+ type emitter region (fourth semiconductor region) 34, an n- type buffer region 35, a p+ type contact region (fifth semiconductor region) 36, a first gate insulating film (first insulating film) 51, a second gate insulating film (second insulating film) 52, and an interlayer insulating film (third insulating film) 53.

In the semiconductor device 100, the direction from the collector electrode 11 to the emitter electrode 12 is the Z direction (first direction). The direction perpendicular to the Z direction is the X direction (second direction), and the direction perpendicular to the X and Z directions is the Y direction. The semiconductor device 100 shown in Figures 1(a), 1(c), and 1(d) is a plan view in the X-Y plane, and the semiconductor device 100 shown in Figure 1(b) is a cross-sectional view in the X-Z plane. Note that the X direction, Y direction, and Z direction are shown in an orthogonal relationship in this embodiment, but are not limited to being orthogonal, and may be in a mutually intersecting relationship. For the sake of explanation, the direction from the collector electrode 11 to the emitter electrode 12 is referred to as "up" and the opposite direction is referred to as "down".

The collector electrode 11 is spaced apart from the emitter electrode 12 in the Z direction. A collector voltage is applied to the collector electrode 11. The collector voltage is, for example, 200 V or more and 6500 V or less.

An emitter voltage is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V.

The collector electrode 11 and the emitter electrode 12 are made of, for example, aluminum (Al).

The collector region 33 is a p-type semiconductor region provided between the collector electrode 11 and the emitter electrode 12 in the Z direction. The collector region 33 is in contact with and electrically connected to the collector electrode 11. The collector region 33 serves as a source of holes when the semiconductor device 100 is in the on state.

The drift region 31 is an n-type semiconductor region provided between the collector region 33 and the emitter electrode 12. The drift region 31 serves as a path for an on-current when the semiconductor device 100 is in the on-state. When the semiconductor device 100 is in the off-state, the drift region 31 is depleted by a depletion layer that spreads from the interface with the base region 32, and has the function of maintaining the breakdown voltage of the semiconductor device 100.

The base region 32 is a p-type semiconductor region provided between the drift region 31 and the emitter electrode 12. When the semiconductor device 100 is in the on state, an inversion layer is formed in the base region 32, and the base region 32 functions as a channel region of the transistor.

The buffer region 35 is an n-type semiconductor region provided between the collector region 33 and the drift region 31. The buffer region 35 has a function of suppressing the extension of a depletion layer extending from the base region 32 to the drift region 31 when the semiconductor device 100 is in an off state. In this embodiment, the buffer region 35 may not be provided.

The contact region 36 is a p+ type semiconductor region provided between the base region 32 and the emitter electrode 12. As described below, the contact region 36 contacts the second gate insulating film 52 and is separated from the first gate insulating film 51. The contact region 36 contacts the emitter electrode 12 and is electrically connected to the emitter electrode 12.

The first gate trench 41 penetrates the base region 32 and reaches the drift region 31. The first gate insulating film 51 is provided on the bottom and sides of the first gate trench 41. The first gate insulating film 51 contacts the drift region 31, the base region 32, and the emitter region 34. The first gate insulating film 51 is, for example, silicon oxide.

The first gate electrode 13 is provided in the first gate insulating film 51 and faces at least the base region 32 via the first gate insulating film 51. The first gate electrode 13 is electrically connected to a first gate electrode pad 21 described later. The first gate electrode 13 is, for example, polysilicon containing impurities. As shown in Figures 1(a) and 1(c), the first gate electrode 13 extends in the Y direction and has a stripe shape provided in multiple locations in the X direction.

The second gate trench 42 penetrates the base region 32 and reaches the drift region 31. The second gate trench 42 is provided between adjacent first gate trenches 41 in the X direction. The second gate insulating film 52 is provided at the bottom and side of the second gate trench 42. The second gate insulating film 52 is in contact with the drift region 31, the base region 32, and the contact region 36. The second gate insulating film 52 is, for example, silicon oxide.

The second gate electrode 14 is provided in the second gate insulating film 52. The second gate electrode 14 is provided so as not to be adjacent to the emitter region 34 in the X direction. The second gate electrode 14 is electrically connected to the second gate electrode pad 22. As with the first gate insulating film 51, as shown in Figures 1(a) and 1(c), the second gate electrode 14 extends in the Y direction and has a stripe shape provided in multiple locations in the X direction. The second gate electrode 14 is, for example, polysilicon containing impurities.

The interlayer insulating film 53 is provided between the base region 32 and the emitter electrode 12, between the first gate electrode 13 and the emitter electrode 12, and between the second gate electrode 14 and the emitter electrode 12.

The emitter region 34 is an n+ type semiconductor region provided between the base region 32 and the interlayer insulating film 53. In FIG. 1B, the interlayer insulating film 53 is shown to be provided between the entire upper surface of the emitter region 34 and the emitter electrode 12. However, as shown in FIGS. 10 and 11, the entire upper surface or a part of the emitter region 34 may be provided so as to be in direct contact with the emitter electrode 12. A part of the emitter region 34 contacts and is electrically connected to the emitter electrode 12. The emitter region 34 contacts the first gate insulating film 51 and is separated from the second gate insulating film 52. The emitter region 34 becomes a supply source of electrons when a transistor having the first gate electrode 13 is in an on state.

The distance from the collector electrode 11 to the boundary where the contact region 36 and the emitter electrode 12 contact in the Z direction is distance 1 (L1). The distance from the collector electrode 11 to the upper surface of the emitter region 34 in the Z direction is distance 2 (L2). In the semiconductor device 100 of this embodiment, distance 1 is smaller than distance 2. That is, the interlayer insulating film 53 provided in the first gate trench 41 is located closer to the emitter electrode 12 than the interlayer insulating film 53 provided in the second gate trench 42.

In addition, the interface between the emitter electrode 12 and the contact region 36 is located closer to the collector electrode 11 than the interface between the emitter region 34 and the interlayer insulating film 53. Therefore, the side of the emitter region 34 is in contact with the emitter electrode 12.

The drift region 31, base region 32, collector region 33, emitter region 34, buffer region 35, and contact region 36 are made of, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

In addition, the first gate electrodes 13 and the second gate electrodes 14 may be arranged alternately in a multiple number fashion, rather than being arranged alternately one by one in the X direction as in FIG. 1.

As shown in FIG. 1(a), the region where the IGBT channel is formed, i.e., the region where current flows, is defined as cell region 60. In FIG. 1(a), cell region 60 is the region surrounded by a dashed line. The region surrounding cell region 60 where no channel is formed is defined as termination region 61. In the X direction, the part of cell region 60 that is close to termination region 61 is defined as the cell end of cell region 60, and the part of cell region 60 that is close to termination region 61 is defined as the cell center.

The first gate electrode pad 21 is provided in the terminal region of the semiconductor device 100, and is provided on the emitter electrode 12 side in the Z direction. A first gate voltage (Vg1) is applied to the first gate electrode pad 21 and the first gate electrode 13.

The second gate electrode pad 22 is provided in the terminal region of the semiconductor device 100, and is provided on the emitter electrode 12 side in the Z direction. The second gate electrode pad 22 is also provided at a distance from the first gate electrode pad 21. A second gate voltage (Vg2) is applied to the second gate electrode pad 22 and the second gate electrode 14.

As shown in FIG. 1(d), the first gate electrode pad 21 and the second gate electrode pad 22 are electrically connected to a gate driver 70. The gate driver 70 controls the voltages applied to the first gate electrode pad 21 and the second gate electrode pad 22. The gate driver 70 applies a first gate voltage (Vg1) to the first gate electrode pad 21 and a second gate voltage (Vg2) to the second gate electrode pad 22.

(Operation of the Semiconductor Device 100)
The operation of the semiconductor device 100 will now be described.

Figure 2 is a timing chart of the first gate voltage (Vg1) applied to the first gate electrode pad 21 and the second gate voltage (Vg2) applied to the second gate electrode pad 22. The vertical axis of Figure 2 shows the voltages applied to the first gate voltage (Vg1) and the second gate voltage (Vg2). The horizontal axis of Figure 2 shows time, which progresses in the order of time t0, time t1 (first timing), time t2 (second timing), time t3 (third timing), and time t4.

When the semiconductor device 100 is in the off state, an emitter voltage is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V. A collector voltage is applied to the collector electrode 11. The collector voltage is, for example, 200 V or more and 6500 V or less.

From time t0 to time t1, the semiconductor device 100 is in the off state. When the semiconductor device 100 is in the off state, a turn-off voltage (Voff) is applied to the first gate electrode pad 21. That is, from time t0 to time t1, the first gate voltage (Vg1) is the off voltage (Voff). The off voltage (Voff) is a voltage smaller than the threshold voltage (Vth) at which an n-type inversion layer is formed in the base region 32 in contact with the first gate insulating film 51, and is, for example, 0 V or a negative voltage.

An initial voltage (V0) is applied to the second gate electrode pad 22. That is, from time t0 to time t1, the second gate voltage (Vg2) is the initial voltage (V0). The initial voltage (V0) is a voltage at which a p-type inversion layer is not formed in the drift region 31 in contact with the second gate insulating film 52, and is, for example, 0 V or a positive voltage.

At time t1, the semiconductor device 100 turns on. At time t1, an on-voltage (Von) is applied to the first gate electrode pad 21, and the semiconductor device 100 turns on. The on-voltage (Von) is a positive voltage that exceeds the threshold voltage (Vth), for example, 15 V. That is, at time t1, the first gate voltage (Vg1) becomes the on-voltage (Von). At this time, an n-type inversion layer is formed in the base region 32 that contacts the first gate insulating film 51, and the semiconductor device 100 turns on.

Between time t1 and time t3, the semiconductor device 100 is in the on state. That is, from time t1 to time t3, the first gate voltage (Vg1) becomes the on voltage (Von). In the on state, electrons are injected from the emitter region 34 to the base region 32 (n-type inversion layer), and then the electrons flow in the order of the drift region 31, the buffer region 35, the collector region 33, and the collector electrode 11. On the other hand, holes are injected from the collector region 33 to the buffer region 35, and the holes flow in the order of the drift region 31, the base region 32, the emitter region 34 or the contact region 36, and the emitter electrode 12.

At time t1, a first voltage (V1) is applied to the second gate electrode pad 22. The first voltage (V1) is, for example, 0 V or a positive voltage. That is, at time t1, the second gate voltage (Vg2) becomes the first voltage (V1). The first voltage (V1) may be the same as the initial voltage (V0).

At time t3, the semiconductor device 100 is turned off. At time t3, an off voltage (Voff) is applied to the first gate electrode pad 21, and the semiconductor device 100 is in an off state. That is, after time t3, the first gate voltage (Vg1) becomes the off voltage (Voff).

Time t2 is the timing before the voltage of the first gate electrode pad 21 is changed from the on voltage (Von) to the off voltage (Voff), i.e., before time t3. At time t2, the second gate voltage (Vg2) switches from the first voltage (V1) to the second voltage (V2). The second voltage (V2) is a negative voltage, for example, greater than or equal to -15 V and less than 0 V. As a result, a p-type inversion layer is formed in the drift region 31 in contact with the second gate insulating film 52, and holes in the drift region 31 are discharged to the emitter electrode 12 through the p-type inversion layer.

The time between time t2 and time t3 is, for example, 0.1 microseconds or more and 10 microseconds or less.

Finally, at time t4, the second gate voltage (Vg2) is set to the initial voltage (V0).

(Effects of the First Embodiment)
The effects of the semiconductor device 100 according to the first embodiment will be described using a semiconductor device 500 according to a comparative example shown in FIG.

Figure 3 shows a cross-sectional view of a semiconductor device 500 according to a comparative example. The same parts as those in the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals.

The semiconductor device 500 of the comparative example differs from the semiconductor device 100 of the first embodiment in that distance 1 (L1) and distance 2 (L2) are the same.

In the semiconductor device 100 according to the first embodiment and the semiconductor device 500 according to the comparative example, the second gate voltage (Vg2) is changed from the first voltage (V1) to the second voltage (V2) at time t2. At this time, a p-type inversion layer is formed in the drift region 31 that contacts the second gate insulating film 52. Between time t2 and time t3, holes pass through the drift region 31 and the p-type inversion layer and are discharged to the emitter electrode 12.

Here, in the semiconductor device 100 according to the first embodiment, distance 1 is smaller than distance 2, and the distance that holes pass through the drift region 31 and the p-type inversion layer from time t2 to time t3 is smaller than that of the semiconductor device 500 according to the comparative example. That is, in the semiconductor device 100 according to the first embodiment, the electrical resistance in the path that holes pass through the drift region 31 and the p-type inversion layer is smaller. Therefore, the semiconductor device 100 according to the first embodiment can efficiently discharge holes to the emitter electrode 12, thereby making it possible to reduce switching losses at the time of turn-off.

In addition, in the semiconductor device 100 according to the first embodiment and the semiconductor device 500 according to the comparative example, holes tend to concentrate in the drift region 31 that contacts the bottom of the second gate trench 42. The concentrated holes cause a phenomenon called dynamic avalanche, in which the breakdown voltage decreases, and the semiconductor element may be destroyed. In the semiconductor device 100 according to the first embodiment, the concentrated holes are more efficiently discharged through the contact region than in the semiconductor device 500. This improves the breakdown resistance of the semiconductor element.

As described above, the semiconductor device 100 according to the first embodiment can reduce switching losses and improve breakdown resistance.

[Modification of the first embodiment]
A semiconductor device 101 according to a modification of the first embodiment will be described with reference to Fig. 4. Fig. 4 shows a cross-sectional view of the semiconductor device 101 according to the modification of the first embodiment. Descriptions that overlap with the first embodiment will be omitted.

The semiconductor device 101 differs from the semiconductor device 100 in that the length of the second gate electrode 14 in the Z direction is the same as the length of the first gate electrode 13. However, like the semiconductor device 100, the semiconductor device 101 has a smaller distance 1 than distance 2, and the distance that holes travel through the drift region 31 and the p-type inversion layer between time t2 and time t3 is smaller than that of the semiconductor device 500. Therefore, the semiconductor device 101 can obtain the same effect as the semiconductor device 100.

Second Embodiment
A semiconductor device 200 according to a second embodiment will be described with reference to Fig. 5. Fig. 5 shows a cross-sectional view of the semiconductor device 200 according to the second embodiment.

The semiconductor device 200 according to the second embodiment is different from the semiconductor device 100 in that at least one of the first gate electrodes 13 provided in the semiconductor device 100 is changed to a dummy electrode 15. In the semiconductor device 200, the base region 32 provided between the second gate electrode 14 and the dummy electrode 15 is insulated from the emitter electrode 12 by an interlayer insulating film 53 provided on the base region 32. In other words, in the semiconductor device 200, only the second gate insulating film 52, the drift region 31, and the base region 32 are formed between the second gate electrode 14 and the dummy electrode 15. Here, the description of the points that overlap with the first embodiment will be omitted.

The dummy electrode 15 is, for example, electrically connected to the emitter electrode 12. That is, the dummy electrode 15 has the same potential as the emitter electrode 12.

The dummy electrodes 15 do not function as gate electrodes. Therefore, by changing the number of dummy electrodes 15, the semiconductor device 200 can adjust the channel density. Changing the channel density leads to adjustment of the on-voltage and turn-off loss. Therefore, by adjusting the number of dummy electrodes 15, the semiconductor device 200 can appropriately adjust the on-voltage and turn-off loss.

The dummy electrode 15 of the semiconductor device 200 is connected to the emitter electrode 12. The channel density can be adjusted even if the dummy electrode 15 is floating. However, if the dummy electrode 15 is floating, the semiconductor device 200 may malfunction or generate heat due to potential instability of the dummy electrode 15. On the other hand, if the dummy electrode 15 is at the emitter potential, the semiconductor device 200 can be prevented from malfunctioning and generating heat. Therefore, the semiconductor device 200 can prevent the destruction of element characteristics.

The channel density can be adjusted even when the dummy electrode 15 is at the gate potential. When the dummy electrode 15 is at the gate potential, the switching speed may decrease due to an increase in gate capacitance, but the voltage change and current change between the collector electrode 11 and the emitter electrode 12 can be suppressed. As a result, the semiconductor device 200 in which the dummy electrode 15 is at the gate potential can suppress surge voltages and surge currents.

Furthermore, in the semiconductor device 200, the drift region 31 and base region 32 located between the second gate electrode 14 and the dummy electrode 15 are insulated from the emitter electrode 12 by the interlayer insulating film 53. Therefore, holes are not discharged from the drift region 31 and base region 32 located between the second gate electrode 14 and the dummy electrode 15 but are accumulated therein. As a result, the semiconductor device 200 is able to reduce the on-voltage.

Other than the points described above, the semiconductor device 200 according to the second embodiment is similar to the semiconductor device 100 according to the first embodiment, and distance 1 is smaller than distance 2. Therefore, holes are efficiently discharged to the emitter electrode 12, and switching loss at turn-off is reduced. Also, like the semiconductor device 100 according to the first embodiment, damage to the semiconductor element due to holes generated by dynamic avalanche can be suppressed.

In FIG. 5, one dummy electrode 15 is shown sandwiched between the second gate electrodes 14, but multiple dummy electrodes 15 may be provided.

In addition, in FIG. 5, there are two base regions 32 provided between the second gate electrode 14 and the dummy electrode 15, and the base regions 32 are shown as being insulated from the emitter electrode 12 by an interlayer insulating film 53 provided on the base regions 32. However, any one of the multiple base regions 32 provided between the second gate electrode 14 and the dummy electrode 15 may be connected to the emitter electrode 12 that penetrates the interlayer insulating film 53. In that case, the effect described above can be adjusted by changing the contact area with the emitter electrode 12.

[Modification of the second embodiment]
A semiconductor device 201 according to a modification of the second embodiment will be described with reference to Fig. 6. Fig. 6 shows a cross-sectional view of the semiconductor device 201 according to the modification of the second embodiment. Descriptions that overlap with the second embodiment will be omitted.

In the semiconductor device 201 according to the modified example of the second embodiment, at least one of the second gate electrodes 14 provided in the first embodiment is replaced with a dummy electrode 15. In the semiconductor device 201, the base region 32 provided between the first gate electrode 13 and the dummy electrode 15 is insulated from the emitter electrode 12 by an interlayer insulating film 53 provided on the base region 32. In other words, in the semiconductor device 201, only the first gate insulating film 51, the drift region 31, and the base region 32 are formed between the first gate electrode 13 and the dummy electrode 15. Here, the description of the points that overlap with the first embodiment is omitted.

In the semiconductor device 201, like the semiconductor device 200 of the second embodiment, the dummy electrodes 15 do not function as gate electrodes. Therefore, the semiconductor device 200 can appropriately adjust the on-voltage and turn-off loss by adjusting the number of dummy electrodes 15. Furthermore, the semiconductor device 200 can suppress the destruction of element characteristics. Furthermore, the semiconductor device 200 can reduce the on-voltage.

In addition, similar to the semiconductor device 100 according to the first embodiment, distance 1 is smaller than distance 2. Therefore, in the semiconductor device 200, holes are efficiently discharged to the emitter electrode 12, and switching loss during turn-off is reduced. Furthermore, the semiconductor device 200 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

[Third embodiment]
A semiconductor device 300 according to a third embodiment will be described with reference to Fig. 7. Fig. 7 shows a cross-sectional view of a cell region 60 near a termination region 61 of a semiconductor device 300 according to a third embodiment. Fig. 7 shows the structure of an element region, with the left side of the page being the termination region 61 side. Descriptions of points that overlap with the second embodiment will be omitted.

In the semiconductor device 300 according to the third embodiment, the dummy electrode 15 is provided in the cell region 60 close to the termination region 61 of the cell region 60 in the second embodiment. In the semiconductor device 300, the base region 32 provided between the second gate electrode 14 and the dummy electrode 15 is insulated from the emitter electrode 12 by the interlayer insulating film 53 provided on the base region 32. That is, in the semiconductor device 300, only the second gate insulating film 52, the drift region 31, and the base region 32 are formed between the second gate electrode 14 and the dummy electrode 15. Here, the description of the points that overlap with the first embodiment will be omitted. Furthermore, the second gate electrode 14 adjacent to the dummy electrode 15 is adjacent to the contact region 36 via the second gate insulating film 52 in the X direction and is electrically connected to the emitter electrode 12 that penetrates the interlayer insulating film 53.

In the termination region 61, holes spread during the on state. When turned off, holes are concentrated in the second gate electrode 14 close to the termination region 61 and are discharged, resulting in a localized high current density. This may result in destruction of the semiconductor device.

On the other hand, the semiconductor device 300 of the third embodiment has a dummy electrode 15 in the cell region 60 close to the termination region 61. Furthermore, the second gate electrode 14 adjacent to the dummy electrode 15 is adjacent to the contact region 36 in the X direction via the second gate insulating film 52, and is electrically connected to the emitter electrode 12 that penetrates the interlayer insulating film 53. This makes it easier to discharge holes in the termination region 61 when the semiconductor device is turned off.

The drift region 31 and base region 32 located between the second gate electrode 14 and the dummy electrode 15 are insulated from the emitter electrode 12 by the interlayer insulating film 53. Therefore, holes are not discharged from the drift region 31 and base region 32 located between the second gate electrode 14 and the dummy electrode 15 but are accumulated therein. As a result, the semiconductor device 300 is capable of lowering the on-voltage and suppressing hole concentration in the second gate electrode 14 near the termination region 61 when turned off.

In the semiconductor device 300, like the semiconductor device 200 according to the second embodiment, the dummy electrodes 15 do not function as gate electrodes. Therefore, the semiconductor device 300 is capable of appropriately adjusting the on-voltage and turn-off loss by adjusting the number of dummy electrodes 15. Furthermore, the semiconductor device 300 is capable of suppressing the breakdown of element characteristics. Furthermore, the semiconductor device 300 is capable of lowering the on-voltage.

In addition, similar to the semiconductor device 100 according to the first embodiment, distance 1 is smaller than distance 2. Therefore, in the semiconductor device 300, holes are efficiently discharged to the emitter electrode 12, and switching loss during turn-off is reduced. Furthermore, the semiconductor device 300 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

[Fourth embodiment]
A semiconductor device 400 according to the fourth embodiment will be described with reference to FIG. 8. FIG. 8 shows a cross-sectional view of a cell region 60 near a termination region 61 of a semiconductor device 400 according to the fourth embodiment. FIG. 8 shows the structure of an element region, with the termination region 61 side being on the left side of the page. FIG. 9 is a plan view of the semiconductor device 400 according to the fourth embodiment. FIG. 9 shows only the outer edge of the semiconductor device 400 and the second gate electrode 14 in a schematic manner, with other components omitted. In addition, in order to make the drawing easier to see, the second gate electrode 14 is shown in gray. Here, the description of points that overlap with the first embodiment will be omitted.

The semiconductor device 400 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment in that a plurality of second gate electrodes 14 are formed in the cell region 60 close to the termination region 61. In detail, the semiconductor device 400 has a higher proportion of second gate electrodes 14 formed in the cell region 60 close to the termination region 61 than in the central region of the cell region 60.

As described above, the semiconductor device 400 has a cell region 60 and a termination region 61. The termination region 61 surrounds the cell region 60. The first gate electrode 13 and the second gate electrode 14 are arranged in the cell region 60. In the cell region 60, the regions located at both ends in the X direction (second direction) have a higher array density of the second gate electrodes 14 than the region located in the center of the X direction.

Therefore, among the multiple second gate electrodes 14 arranged in the cell region 60, the distance between the first second gate electrode 14a closest to the termination region 61 in the X direction (second direction) and the second second gate electrode 14b arranged next to the first second gate electrode 14a is defined as the first distance D1, and the distance between the third second gate electrode 14c arranged closer to the center of the cell region 60 than the second second gate electrode 14b and the fourth second gate electrode 14d arranged next to the third second gate electrode 14c is defined as the second distance D2. The first distance D1 is shorter than the second distance D2. Note that the center of the cell region 60 is the intersection of the diagonals of the cell region 60 when the shape of the cell region 60 is rectangular when viewed from the Z direction, and approximately coincides with the intersection of the diagonals of the semiconductor device 400, for example.

The semiconductor device 400 according to the fourth embodiment has a plurality of second gate electrodes 14 formed on the cell region 60 side. This makes it easier to discharge holes present in the termination region 61 when the device is turned off, and makes it possible to prevent an increase in current density. Therefore, the semiconductor device 400 can suppress the destruction of the semiconductor element.

The semiconductor device 400 according to the fourth embodiment is similar to the semiconductor device 100 according to the first embodiment except for the points described above, and the distance 1 is smaller than the distance 2. Therefore, in the semiconductor device 400, holes are efficiently discharged to the emitter electrode 12, and the switching loss at the time of turn-off is reduced. In addition, the semiconductor device 400 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

11 Collector electrode (first electrode)
12 Emitter electrode (second electrode)
13 First gate electrode 14 Second gate electrode 14a First second gate electrode 14b Second second gate electrode 14c Third second gate electrode 14d Fourth second gate electrode 15 Dummy electrode 21 First gate electrode pad 22 Second gate electrode pad 31 Drift region (first semiconductor region)
32 base region (second semiconductor region)
33 Collector region (third semiconductor region)
34 Emitter region (fourth semiconductor region)
35 Buffer region 36 Contact region 41 First gate trench 42 Second gate trench 51 First gate insulating film (first insulating film)
52 Second gate insulating film (second insulating film)
53 Interlayer insulating film (third insulating film)
60 Cell region 61 Termination region 70 Gate driver 100, 101, 200, 201, 300, 400, 500 Semiconductor device t1 First timing t2 Second timing t3 Third timing

Claims (12)

A first electrode;
a second electrode spaced apart from the first electrode in a first direction;
a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode in the first direction;
a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second electrode;
a third semiconductor region of a second conductivity type provided between the first semiconductor region and the first electrode and electrically connected to the first electrode;
a plurality of first gate electrodes facing the second semiconductor region via a first insulating film in a second direction intersecting the first direction and insulated from the second electrode via a third insulating film in contact with the first insulating film;
a plurality of second gate electrodes opposed to the second semiconductor region via a second insulating film in the second direction and insulated from the second electrode via the third insulating film in contact with the second insulating film, and to which a voltage different from that of the first gate electrodes is applied;
a fourth semiconductor region of the first conductivity type provided between the second semiconductor region and the second electrode and facing the first gate electrode via the first insulating film or the third insulating film;
a fifth semiconductor region of a second conductivity type provided between the second semiconductor region and the second electrode, facing the second gate electrode via the second insulating film or the third insulating film, and having a boundary portion electrically contacting the second electrode;
A semiconductor device, wherein the distance between an upper surface of the fourth semiconductor region and the first electrode is greater than the distance between the boundary portion and the first electrode. a third electrode that faces the second semiconductor region via a fourth insulating film in the second direction and faces the second electrode via the third insulating film that is in contact with the fourth insulating film, and to which a voltage different from that of the first gate electrode and the second gate electrode is applied;
The semiconductor device according to claim 1 . The third electrode is electrically connected to the second electrode.
The semiconductor device according to claim 2 . the fourth insulating film faces the first insulating film in the second direction, with the second semiconductor region interposed therebetween;
The semiconductor device according to claim 2 . the fourth insulating film faces the second insulating film in the second direction with the second semiconductor region therebetween;
The semiconductor device according to claim 2 . The semiconductor device according to claim 1, wherein the area of the fifth semiconductor region located between the first first gate electrode and the first gate electrode or the second gate electrode adjacent to the first first gate electrode and the second electrode is different from the area of the fifth semiconductor region located between the second first gate electrode and the first gate electrode or the second gate electrode adjacent to the second first gate electrode and the second electrode. a cell region having the first gate electrode and the second gate electrode;
a termination region surrounding the cell region;
having
the third electrode is adjacent to the second gate electrode in a region of the cell region that is closer to the termination region than to a center of the cell region in the second direction;
6. The semiconductor device according to claim 2 . a cell region having the first gate electrode and the second gate electrode;
a termination region surrounding the cell region;
having
7. The semiconductor device according to claim 1, wherein, among the plurality of second gate electrodes arranged in the cell region, a first distance between a first second gate electrode that is closest to the termination region in the second direction and a second second gate electrode arranged adjacent to the first second gate electrode is shorter than a second distance between a third second gate electrode that is arranged closer to the center of the cell region than the second second gate electrode and a fourth second gate electrode arranged adjacent to the third second gate electrode. The semiconductor device according to claim 7, characterized in that the cell region that is closer to the termination region in the second direction has more second gate electrodes provided therein than the cell region that is farther from the termination region in the second direction. A method for controlling a semiconductor device according to any one of claims 1 to 9, comprising:
At a first timing, a first gate voltage applied to the first gate electrode is changed from a voltage less than a threshold voltage to a voltage equal to or greater than the threshold voltage;
At a second timing subsequent to the first timing, a second gate voltage applied to the second gate electrode is changed from a first voltage to a second voltage;
A method for controlling a semiconductor device, comprising: changing the first gate voltage from a voltage equal to or greater than the threshold voltage to a voltage less than the threshold voltage at a third timing subsequent to the second timing. The method for controlling a semiconductor device according to claim 10, wherein the second voltage is a negative voltage when the first conductivity type is n-type, and a positive voltage when the first conductivity type is p-type. The method for controlling a semiconductor device according to claim 10 or 11, wherein an inversion layer is formed in the first semiconductor region in contact with the second insulating film by applying the second voltage to the second gate electrode.

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