JP7634925B2 - Imaging device and electronic device - Google Patents

Description

One aspect of the present invention relates to an imaging device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a driving method thereof, or a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Literature 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used for a pixel circuit.

JP 2011-119711 A

2. Description of the Related Art With imaging devices such as CMOS image sensors, technological advances have made it possible to easily capture high-quality images. In the next generation, imaging devices are required to have even higher functionality.

On the other hand, since imaging devices are incorporated into various devices, there is also a demand for miniaturization. Therefore, even when functions are added, it is desirable to miniaturize the sensor chip. Therefore, it is preferable to arrange elements for adding functions to the imaging device in a stacked manner.

However, when stacking multiple devices using silicon semiconductors (hereinafter, Si devices), it is necessary to perform polishing and bonding processes multiple times, which makes it difficult to improve the yield.

Therefore, an object of one embodiment of the present invention is to provide a high-performance imaging device. Another object is to provide a small imaging device. Another object is to provide an imaging device or the like that can operate at high speed. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc.

One embodiment of the present invention relates to an imaging device having a layered structure.

One embodiment of the present invention includes a first circuit, a second circuit, a third circuit, a photoelectric conversion device, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer. The first circuit has a region overlapping with the second insulating layer through the first insulating layer and the second circuit. The first insulating layer is provided between the first circuit and the second circuit. The first conductive layer has a region embedded in the second insulating layer. The photoelectric conversion device overlaps with the fourth insulating layer through the third insulating layer and the third circuit. the third insulating layer is provided between a photoelectric conversion device and a third circuit, the second conductive layer has a region embedded in the fourth insulating layer, the first conductive layer is electrically connected to the first circuit, the first circuit is electrically connected to the second circuit, the second conductive layer is electrically connected to the third circuit, the third circuit is electrically connected to the photoelectric conversion device, the first conductive layer and the second conductive layer are directly bonded, and the second insulating layer and the fourth insulating layer are directly bonded.

It is preferable that the first circuit has a transistor having silicon in a channel formation region, the second circuit and the third circuit have transistors having metal oxide in a channel formation region, and the photoelectric conversion device is a photodiode having silicon in a photoelectric conversion layer. The metal oxide preferably has In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

It is preferable that the first conductive layer and the second conductive layer are made of the same metal material, and the second insulating layer and the fourth insulating layer are made of the same insulating material.

The third circuit and the photoelectric conversion device have a function of a pixel circuit, and the first circuit can have a function of a readout circuit for the pixel circuit.

The light-shielding layer may be provided between the photoelectric conversion device and the third circuit.

Further, the semiconductor device may have a fourth circuit and a fifth circuit, the fourth circuit and the fifth circuit being provided on the same substrate as the first circuit, the fourth circuit being electrically connected to the second circuit, and the fifth circuit being electrically connected to the second circuit.

The fourth circuit and the fifth circuit preferably have a transistor having silicon in a channel formation region.

The second circuit can have a function of a memory circuit, the fourth circuit can have a function of a column driver that drives the memory circuit, and the fifth circuit can have a function of a row driver that drives the memory circuit.

The third circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor, and one of the source or drain of the first transistor is electrically connected to one of the electrodes of the photoelectric conversion device, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor and one of the source or drain of the third transistor, the other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor and one of the electrodes of the capacitor, and one of the source or drain of the fourth transistor can be electrically connected to one of the source or drain of the fifth transistor.

The first transistor, the second transistor, the fourth transistor, and the fifth transistor may each be a transistor having silicon in a channel formation region, and the third transistor may be a transistor having a metal oxide in a channel formation region. The metal oxide preferably contains In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

By using one embodiment of the present invention, a highly functional imaging device can be provided. An imaging device that can be manufactured with fewer steps can be provided. An imaging device that can be manufactured with a high yield can be provided. A small-sized imaging device can be provided. An imaging device capable of high-speed operation can be provided. An imaging device with high reliability can be provided. A novel imaging device or the like can be provided. A method for driving the imaging device can be provided. A novel semiconductor device or the like can be provided.

FIG. 1 is a cross-sectional perspective view illustrating an imaging device.
2A to 2C are diagrams illustrating a method for producing a laminate.
3A and 3B are block diagrams illustrating an imaging device.
4A to 4C are circuit diagrams illustrating pixel circuits.
5A and 5B are circuit diagrams illustrating a pixel circuit.
6A and 6B are diagrams for explaining the layout of a pixel circuit.
FIG. 7 is a circuit diagram and a block diagram illustrating a read circuit.
8A is a block diagram illustrating a memory circuit, and FIGS. 8B to 8E are circuit diagrams illustrating a memory cell.
9A and 9B are diagrams illustrating the operation of a rolling shutter and a global shutter, respectively.
10A to 10C are timing charts illustrating the operation of the pixel circuit.
FIG. 11 is a cross-sectional view illustrating a pixel.
12A to 12C are diagrams illustrating a Si transistor.
13A to 13D illustrate OS transistors.
14A and 14B are cross-sectional views illustrating a pixel.
15A and 15B are cross-sectional views illustrating a pixel.
FIG. 16 is a cross-sectional view illustrating a pixel.
FIG. 17 is a cross-sectional view illustrating a pixel.
FIG. 18 is a cross-sectional view illustrating a pixel.
FIG. 19 is a cross-sectional view illustrating a pixel.
20A and 20B are cross-sectional views illustrating a pixel.
FIG. 21 is a cross-sectional view illustrating a pixel.
FIG. 22 is a cross-sectional view illustrating a pixel.
23A1 to 23A3 and 23B1 to 23B3 are perspective views of a package and a module that house an imaging device.
24A to 24F are diagrams illustrating an electronic device.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

In addition, even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

(Embodiment 1)
In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

One aspect of the present invention is an imaging device having a plurality of stacked devices. The imaging device is formed by bonding a first stack in which a plurality of devices are stacked and a second stack in which a plurality of devices are stacked. Therefore, even if a configuration in which multiple circuits with different functions are stacked, it is possible to reduce a polishing process and a bonding process, and to improve a yield.

For example, a pixel circuit, a pixel driving circuit, etc. can be provided in the first stack, and a pixel circuit readout circuit, a memory circuit, a memory circuit driving circuit, etc. can be provided in the second stack. By using such a configuration, a small-sized imaging device can be formed. In addition, by stacking each circuit, wiring delays can be suppressed, and high-speed operation can be performed.

<Layered structure>
1 is a cross-sectional perspective view illustrating an imaging device according to one embodiment of the present invention. The imaging device includes layers 201, 202, 203, 204, and 205.

In this embodiment, for the sake of clarity, the imaging device is divided into the above five layers, but the types, quantities, and positions of elements included in each layer are not limited to those described in this embodiment. For example, elements such as insulating layers, wiring, and plugs near the boundaries between layers may belong to layers different from those described in this embodiment. Each layer may also include elements different from those described in this embodiment.

The layer 201 has a region 210. In the region 210, for example, a read circuit of a pixel circuit, a driver circuit of a memory circuit, and the like can be provided.

The layer 202 has a region 220. The region 220 can be provided with, for example, a memory circuit.

The layer 203 has a region 230. In the region 230, for example, a pixel circuit (excluding the photoelectric conversion device 240) and a driver circuit for the pixel circuit can be provided.

The layer 204 includes a photoelectric conversion device 240. The photoelectric conversion device 240 may be, for example, a photodiode. The photoelectric conversion device 240 is an element of a pixel circuit.

The layer 205 includes an optical conversion layer 250. For example, a color filter or the like can be used for the optical conversion layer 250. The layer 205 can also include a microlens array 255.

As described above, the imaging device of one embodiment of the present invention includes the photoelectric conversion device 240, a pixel circuit and a driver circuit for the pixel circuit provided in the region 230, a memory circuit provided in the region 220, a readout circuit for the pixel circuit and a driver circuit for the memory circuit provided in the region 210, and the like.

Here, it is preferable that the photoelectric conversion device 240 has sensitivity to visible light. For example, the photoelectric conversion device 240 may be a Si photodiode that uses silicon for a photoelectric conversion layer.

For components such as pixel circuits and driver circuits for pixel circuits, it is preferable to use transistors using metal oxide in their channel formation regions (hereinafter, referred to as OS transistors). OS transistors have an extremely small off-state current and can suppress unnecessary outflow of data from pixel circuits. Therefore, a global shutter operation in which data is simultaneously acquired by a plurality of pixel circuits and sequentially read out can be performed with a simple circuit configuration. In addition, the driver circuits for the pixels can be formed in a process common to the pixel circuits.

It is also preferable to use an OS transistor in a memory circuit. By using an OS transistor as a cell transistor in a memory circuit, unnecessary data leakage can be suppressed and the frequency of refresh can be reduced, thereby reducing power consumption.

In the readout circuit of the pixel circuit and the drive circuit of the memory circuit, etc., high-speed operation is required, so it is preferable to use a transistor with high mobility. For example, it is preferable to use a transistor using silicon in the channel formation region (hereinafter, Si transistor). Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single crystal silicon). Note that the drive circuit of the pixel circuit may be formed of a Si transistor.

When multiple Si devices are stacked, polishing and bonding steps are required multiple times. This leads to problems such as a large number of steps, the need for dedicated equipment, low yield, and high manufacturing costs. In one embodiment of the present invention, a circuit using an OS transistor is formed over a Si device, so that the polishing and bonding steps can be reduced.

An OS transistor can be formed over a Si device (a Si transistor or a Si photodiode) with an insulating layer therebetween, without using complicated processes such as bonding or bump bonding.

Thus, in one embodiment of the present invention, the layer 201 is a layer including a silicon substrate, and a circuit having a Si transistor is formed in a region 210. Then, as shown in Fig. 2A, a layer 202 is formed over the layer 201. A circuit having an OS transistor is formed in a region 220 of the layer 202.

The layer 204 is a layer including a silicon substrate, and a Si photodiode is formed as a photoelectric conversion device 240 in the layer 204. Then, as shown in FIG 2B, a layer 203 is formed over the layer 204. In a region 230 of the layer 203, a circuit having an OS transistor is formed.

2C, the layer 202 and the layer 203 are attached to each other at the surface A, thereby forming a stacked structure in which the layers 201 to 204 are stacked. FIG 1 shows a structure in which a layer 205 is further provided on the layer 204 of the stack shown in FIG 2C.

In the case of stacking Si devices, if four layers are stacked, the polishing step and the bonding step will each need to be performed at least three times. However, in one embodiment of the present invention, the polishing step can be performed once or twice, and the bonding step can be performed once.

<Circuit>
3A is a simplified block diagram for explaining electrical connections of elements included in the layers 201 to 203. Note that the photoelectric conversion device 240 included in the layer 204 is not shown here because it is included in the pixel circuit 331 (PIX) on the circuit.

The pixel circuits 331 are arranged in a matrix and electrically connected to a driver circuit 332 (Driver) via wiring 351. The driver circuit 332 can control data acquisition and selection operations of the pixel circuits 331. The driver circuit 332 can be, for example, a shift register.

In addition, the pixel circuit 331 is electrically connected to a readout circuit 311 (RC) via a wiring 352. The readout circuit 311 has a correlated double sampling circuit (CDS circuit) that reduces noise and an A/D converter that converts analog data into digital data.

The reading circuit 311 is electrically connected to a memory circuit 321 (MEM) through a wiring 353. The memory circuit 321 can hold digital data output from the reading circuit 311. Alternatively, the reading circuit 311 can directly output digital data to the outside.

The memory circuit 321 is electrically connected to a row driver 312 (RD) via a wiring 354. The memory circuit 321 is also electrically connected to a column driver 313 (CD) via a wiring 355. The row driver 312 is a drive circuit for the memory circuit 321 and can control writing and reading of data. The column driver 313 is a drive circuit for the memory circuit 321 and can control reading of data.

The details of the connection relationship between the pixel circuits 331, the readout circuits 311, and the memory circuits 321 will be described with reference to the block diagram of FIG. 3B. The number of readout circuits 311 can be the same as the number of pixel circuits 331, and one readout circuit 311 is electrically connected to one pixel circuit 331 via a wiring 352. The readout circuit 311 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a. A data retention circuit may be provided between the readout circuit 311 and the memory circuit 321.

The A/D converter in the read circuit 311 outputs binary data of a predetermined number of bits in parallel. Therefore, the A/D converter is connected to memory cells 321a of the number of bits. For example, if the output of the A/D converter is 8 bits, the A/D converter is connected to eight memory cells 321a.

With the above-described configuration, in the imaging device of one embodiment of the present invention, analog data acquired in all pixel circuits 331 can be A/D converted in parallel, and the converted digital data can be directly written to the memory circuit 321. In other words, the process from imaging to storage in the memory circuit can be performed at high speed. In addition, the imaging operation, the A/D conversion operation, and the read operation can be performed in parallel.

<Pixel circuit>
4A is a circuit diagram illustrating an example of a pixel circuit 331. The pixel circuit 331 can include a photoelectric conversion device 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. Note that a configuration in which the capacitor 108 is not provided is also possible.

One electrode (cathode) of the photoelectric conversion device 240 is electrically connected to one of the source or drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.

Here, a wiring that connects the other of the source and the drain of the transistor 103, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node FD can function as a charge detection portion.

The other electrode (anode) of the photoelectric conversion device 240 is electrically connected to a wiring 121. The gate of the transistor 103 is electrically connected to a wiring 127. The other of the source and drain of the transistor 104 is electrically connected to a wiring 122. The other of the source and drain of the transistor 105 is electrically connected to a wiring 123. The gate of the transistor 104 is electrically connected to a wiring 126. The gate of the transistor 106 is electrically connected to a wiring 128. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source and drain of the transistor 106 is electrically connected to a wiring 352.

The wirings 127, 126, and 128 can function as signal lines for controlling the conduction of each transistor. The wiring 352 can function as an output line.

4A, the cathode side of the photoelectric conversion device 240 is electrically connected to the transistor 103 and the node FD is reset to a high potential for operation, so the wiring 122 has a high potential (a higher potential than the wiring 121).

FIG. 4A shows a configuration in which the cathode of the photoelectric conversion device 240 is electrically connected to the node FD. However, as shown in FIG. 4B, the anode side of the photoelectric conversion device 240 may be electrically connected to one of the source or drain of the transistor 103.

In this configuration, the node FD is reset to a low potential for operation, so the wiring 122 is set to a low potential (a lower potential than the wiring 121).

The transistor 103 has a function of controlling the potential of the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as an element of a source follower circuit and can output the potential of the node FD as image data to the wiring 352. The transistor 106 has a function of selecting a pixel to which image data is output.

It is preferable to use OS transistors as the transistors 103 to 106 in the pixel circuit 331. OS transistors have characteristics of extremely low off-state current. In particular, by using transistors with low off-state current as the transistors 103 and 104, the period during which charge can be held at the node FD can be made extremely long. Therefore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method.

Moreover, the pixel circuit 331 may have a configuration shown in Fig. 4C. The pixel circuit 331 shown in Fig. 4C has a configuration in which a transistor 107 is added to the configuration in Fig. 4A.

One of the source or the drain of the transistor 107 is electrically connected to the other of the source or the drain of the transistor 103 and the other of the source or the drain of the transistor 104. The other of the source or the drain of the transistor 107 is electrically connected to the gate of the transistor 105 and one electrode of the capacitor 108. The gate of the transistor 107 is electrically connected to a wiring 129. The wiring 129 can function as a signal line that controls conduction of the transistor.

In this configuration, a wiring that connects the other electrode of the transistor 107, the gate of the transistor 105, and one electrode of the capacitor 108 is a node FD.

The transistor 107 has a function of suppressing outflow of charge from the node FD. Therefore, an OS transistor with low off-state current is preferably used as the transistor 107. Note that it can also be said that the transistor 107 and the capacitor 108 constitute a memory circuit MEM.

With this structure, even if Si transistors with relatively high off-state current are used as the transistors 103 and 104, charge outflow from the node FD can be suppressed.

Therefore, if the transistor 107 is an OS transistor, the node FD has excellent retention characteristics even if the other transistors are all Si transistors. For example, when the leakage current of the OS transistor is 1 zA, the leakage current of the Si transistor is 30 fA, and the capacitance of the capacitor 108 is 20 fF, the potential drop of the node FD is estimated to be 25 mV without the transistor 107 at a frame rate of 60 Hz, whereas the potential drop of the node FD is estimated to be 0.83 nV with the transistor 107.

In this manner, the pixel circuit 331 having this configuration can improve the data retention function of the pixel by using an OS transistor as the transistor 107, and is suitable for operation in a global shutter system. In addition, a Si transistor can be used for the transistor other than the transistor 107, enabling high-speed operation.

5A and 5B, a back gate may be provided in the transistor. Fig. 5A shows a configuration in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-current. Fig. 5B shows a configuration in which the back gate is electrically connected to a wiring that can supply a constant potential, which can control the threshold voltage of the transistor.

5A and 5B may be combined so that each transistor can operate appropriately. The pixel circuit 331 may include a transistor that does not have a back gate. Although FIGS. 5A and 5B show an example in which a back gate is provided in the pixel circuit 331 shown in FIG. 4A, the pixel circuit 331 may be applied to the pixel circuit 331 shown in FIGS. 4B and 4C.

6A and 6B are top views showing an example of the layout of the pixel circuit 331 shown in FIG. 5B. FIG. 6A shows the layers up to the upper electrode of the capacitor 108 so that each element of the pixel circuit 331 can be clearly seen. FIG. 6B also shows wiring that connects each element between elements or each element to a driving circuit. FIG. 6A and 6B show an example in which the transistor size is W/L=60 nm/60 nm, and the elements can be accommodated in an area of 1.2 μm×1.3 μm.

<Readout circuit>
7 is a diagram for explaining an example of a readout circuit 311 connected to a pixel circuit 331, and shows a circuit diagram of a CDS circuit 400 and a block diagram of an A/D converter 410 electrically connected to the CDS circuit 400. Note that the CDS circuit and the A/D converter shown in FIG. 7 are merely examples, and other configurations may be used.

The CDS circuit 400 can have a configuration including a voltage conversion transistor 401, a capacitive coupling capacitor 402, a transistor 403 that supplies a potential _V0 , a transistor 404 that holds a potential to be supplied to the A/D converter 410, and a potential holding capacitor 405. The CDS circuit 400 has an input electrically connected to the pixel circuit 331 and an output electrically connected to a comparator circuit (COMP) of the A/D converter 410.

When the potential of the wiring 352 is V _res + V _data (reset potential + potential of image data), the potential of the node N (the connection point of the transistors 403, 404 and the capacitor 402) is _V0 . Then, when the node N is floating and the potential of the wiring 352 is V _res (reset potential), a change in the potential of the wiring 352 is added to the node N due to the capacitive coupling of the capacitor 402. Therefore, the potential of the node N is _V0 + ((V _res + V _data ) - V _res ), and when V0 ₌ 0, only the term V _data remains. Since V _res includes a noise component associated with the operation of the transistor, the noise component can be reduced.

The A/D converter 410 may have a configuration including a comparator circuit (COMP) and a counter circuit (COUNTER). In the A/D converter 410, a signal potential input from the CDS circuit 400 to the comparator circuit (COMP) is compared with a reference potential (RAMP) to be swept. Then, the counter circuit (COUNTER) operates according to the output of the comparator circuit (COMP), and digital signals are output to a plurality of wirings 353.

<Memory circuit>
8A is a diagram showing the connection relationship between a memory cell 321a included in a memory circuit 321, a row driver 312, and a column driver 313. An OS transistor can be used as a transistor forming the memory cell 321a.

The memory circuit 321 has m (m is an integer of 1 or more) memory cells 321a in one column and n (n is an integer of 1 or more) memory cells 321a in one row, totaling m×n memory cells 321a arranged in a matrix. In FIG. 8A, the addresses of the memory cells 321a are also indicated. For example, [1,1] indicates the memory cell 321a located at the address of the first row and the first column, and [i,j] (i is an integer of 1 to m, j is an integer of 1 to n) indicates the memory cell 321a located at the address of the i-th row and the j-th column. The number of wirings connecting the memory circuit 321 and the row driver 312 is determined by the configuration of the memory cells 321a, the number of memory cells 321a included in one column, and the like. The number of wirings connecting the memory circuit 321 and the column driver 313 is determined by the configuration of the memory cells 321a, the number of memory cells 321a included in one row, and the like.

8B to 8E are diagrams for explaining memory cells 321aA to 321aD that can be applied to the memory cell 321a. In the following description, the bit lines can be connected to a column driver 313. The word lines can be connected to a row driver 312. The bit lines are also electrically connected to a read circuit 311, but this is not shown here.

For example, a decoder or a shift register can be used for the row driver 312 and the column driver 313. Note that a plurality of row drivers 312 and a plurality of column drivers 313 may be provided.

[DOSRAM]
8B shows an example of a circuit configuration of a DRAM memory cell 321aA. In this specification, a DRAM using an OS transistor is called a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 321aA includes a transistor M11 and a capacitor Cs.

A first terminal of the transistor M11 is connected to a first terminal of the capacitor Cs, a second terminal of the transistor M11 is connected to a wiring BIL, a gate of the transistor M11 is connected to a wiring WL, and a back gate of the transistor M11 is connected to a wiring BGL. A second terminal of the capacitor Cs is connected to a wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (reference potential).

The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. The threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Data is written and read by applying a high-level potential to the wiring WL to turn on the transistor M11 and electrically connect the wiring BIL and the first terminal of the capacitor Cs.

The transistor M11 is preferably an OS transistor. In addition, an oxide semiconductor containing any one of indium, an element M (the element M is one or more of aluminum, gallium, yttrium, and tin), and zinc is preferably used for a semiconductor layer of the OS transistor. In particular, an oxide semiconductor containing indium, gallium, or zinc is preferably used.

An OS transistor using an oxide semiconductor containing indium, gallium, or zinc has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M11, the leakage current of the transistor M11 can be made extremely low. That is, since written data can be held by the transistor M11 for a long time, the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be eliminated.

[NOSRAM]
8C shows an example of a circuit configuration of a gain cell type (also called "2Tr1C type") memory cell 321aB having two transistors and one capacitor. The memory cell 321aB has a transistor M11, a transistor M3, and a capacitor Cs.

A first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, a second terminal of the transistor M11 is connected to the wiring WBL, a gate of the transistor M11 is connected to the wiring WL, and a back gate of the transistor M11 is connected to the wiring BGL. A second terminal of the capacitor Cs is connected to the wiring RL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitor Cs.

The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor Cs. When writing data and while the data is being held, it is preferable to apply a reference potential to the wiring RL.

The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

Data is written by applying a high-level potential to the wiring WL, turning on the transistor M11, and electrically connecting the wiring WBL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WL, turning off the transistor M11, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M3.

Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, so the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M3). Alternatively, it is possible to know whether or not information is written in this memory cell.

8D, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. The memory cell 321aC shown in FIG. 8D is configured such that the wiring WBL and the wiring RBL of the memory cell 321aB are combined into a single wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 321aC is configured to operate the write bit line and the read bit line as a single wiring BIL.

Note that an OS transistor is preferably used as the transistor M11 in the memory cells 321aB and 321aC as well. A storage device using an OS transistor as the transistor M11 and using a 2Tr1C type memory cell such as the memory cells 321aB and 321aC is called a non-volatile oxide semiconductor random access memory (NOSRAM).

8D shows an example of a circuit configuration of a 3-transistor, 1-capacitor gain cell type (also called "3Tr1C type") memory cell 321aD. The memory cell 321aD has a transistor M11, a transistor M5, a transistor M6, and a capacitor Cs.

A first terminal of the transistor M11 is connected to a first terminal of the capacitor Cs, a second terminal of the transistor M11 is connected to the wiring BIL, a gate of the transistor M11 is connected to the wiring WL, and a back gate of the transistor M11 is electrically connected to the wiring BGL. A second terminal of the capacitor Cs is electrically connected to a first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to a first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor Cs. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RL.

The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and the wiring RL functions as a read word line.

The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

Data is written by applying a high-level potential to the wiring WL, turning on the transistor M11, and connecting the wiring BIL to the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M5. After that, a low-level potential is applied to the wiring WL, turning off the transistor M11, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M5.

Data is read by precharging the wiring BIL with a predetermined potential, then putting the wiring BIL in an electrically floating state, and applying a high-level potential to the wiring RL. Since the wiring RL is at a high-level potential, the transistor M6 is in a conductive state, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). Here, by reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). Or, the presence or absence of information written in this memory cell can be known.

Note that in the memory cell 321aD, it is also preferable to use an OS transistor as the transistor M11. The 3Tr1C memory cell 321aD in which an OS transistor is used as the transistor M11 is one mode of the above-mentioned NOSRAM. The circuit configuration of the memory cell can be changed as appropriate.

<Operation method of imaging device>
Fig. 9A is a schematic diagram of the operation method of the rolling shutter method, and Fig. 9B is a schematic diagram of the global shutter method. En represents the exposure (accumulation operation) of the nth column (n is a natural number), and Rn represents the readout operation of the nth column. Figs. 9A and 9B show the operations from the 1st row (Line [1]) to the Mth row (Line [M], M is a natural number).

The rolling shutter method is an operation method in which exposure and data readout are performed sequentially, overlapping the readout period of one row with the exposure period of another row. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration in which the data retention period is relatively short. However, since one frame of image is composed of data that is not simultaneously captured, distortion occurs in the image when capturing a moving object.

On the other hand, the global shutter method is a method of operation in which all pixels are exposed simultaneously, data is stored in each pixel, and the data is read out row by row, making it possible to obtain images without distortion even when capturing a moving object.

When a transistor having a relatively high off-state current, such as a Si transistor, is used in a pixel circuit, a rolling shutter system is often used because charge tends to flow out from a charge detection unit. To realize the global shutter system using a Si transistor, a complex operation, such as storing data in a separate memory circuit, must be performed at high speed. On the other hand, when an OS transistor is used in a pixel circuit, the global shutter system can be easily realized because there is almost no flow of data potential from the charge detection unit. Note that the imaging device of one embodiment of the present invention can also be operated using the rolling shutter system.

Note that the pixel circuit 331 may have a structure in which OS transistors and Si transistors are combined in any order, or all the transistors may be Si transistors.

<Pixel Circuit Operation>

Next, an example of the operation of the pixel circuit 331 shown in Fig. 4A will be described with reference to the timing chart of Fig. 10A. In the description of the timing chart in this specification, a high potential is represented by "H" and a low potential is represented by "L." It is assumed that "L" is constantly supplied to the wiring 121, and "H" is constantly supplied to the wirings 122 and 123.

In the period T1, when the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistors 103 and 104 are turned on, and the potential of the wiring 122 is supplied to the node FD (reset operation).

In the period T2, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistor 104 is turned off and the supply of the reset potential is cut off. In addition, the potential of the node FD decreases in response to the operation of the photoelectric conversion device 240 (storage operation).

In the period T3, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "L", the transistor 103 is turned off, and the potential of the node FD is determined and held (holding operation). At this time, by using OS transistors with low off-state current as the transistors 103 and 104 connected to the node FD, unnecessary outflow of charge from the node FD can be suppressed, and the data retention time can be extended.

In the period T4, when the potential of the wiring 126 is set to “L”, the potential of the wiring 127 is set to “L”, and the potential of the wiring 128 is set to “H”, the transistor 106 is turned on, and the potential of the node FD is read out to the wiring 352 by the source follower operation of the transistor 105 (read operation).

The above is an example of the operation of pixel circuit 331 shown in FIG. 4A.

The pixel circuit 331 shown in Fig. 4B can be operated according to the timing chart of Fig. 10B. Note that "H" is constantly supplied to the wirings 121 and 123, and "L" is constantly supplied to the wiring 122. The basic operation is the same as that described above with reference to the timing chart of Fig. 10A.

The pixel circuit 331 shown in Fig. 4C can be operated according to the timing chart of Fig. 10C. In the pixel circuit 331 in Fig. 4C, the wiring 129 can be controlled for each row to easily perform a read operation in the CDS circuit 400. Therefore, the operation of the CDS circuit 400 will also be described. It is assumed that an appropriate analog potential is supplied to the gate of the transistor 401 (see Fig. 7).

In the period T1, the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "L", and the potential of the wiring 129 is set to "H", so that the transistor 107 is turned on.

Next, in the period T2, when the potential of the wiring 126 is set to “H”, the potential of the wiring 127 is set to “L”, the potential of the wiring 128 is set to “L”, and the potential of the wiring 129 is set to “H”, the transistor 104 becomes conductive, and the potential of the wiring 122 (reset potential) is supplied to the node FD (reset operation).

In the period T3, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "L", and the potential of the wiring 129 is set to "H", the transistor 104 is turned off and the node FD is held at the reset potential.

In period T4, when the potential of the wiring 126 is set to “L”, the potential of the wiring 127 is set to “H”, the potential of the wiring 128 is set to “L”, and the potential of the wiring 129 is set to “H”, the transistor 103 becomes conductive, and the potential of the node FD decreases in response to the operation of the photoelectric conversion device 240 (transfer operation).

In the period T5, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "L", and the potential of the wiring 129 is set to "H", the transistor 103 is turned off, and the potential of the node FD is determined.

In the period T6, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "L", and the potential of the wiring 129 is set to "L", the transistor 107 is turned off, and the potential of the node FD is held (holding operation). At this time, by using an OS transistor with low off-state current as the transistor 107 connected to the node FD, unnecessary outflow of charge from the node FD can be suppressed, and the data retention time can be extended.

In the period T7, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "H", the potential of the wiring 129 is set to "L", and the potential of the wiring 431 (see Figure 7) is set to "H", the transistor 106 is turned on, and the potential of the node FD is read out to the wiring 352 by the source follower action of the transistor 105 (read operation).

In the CDS circuit 400 (see FIG. 7), the transistor 403 is turned on, and the node N is reset to the potential "Vr" of the wiring 432. That is, when the pixel circuit 331 is outputting image data, the potential of one electrode of the capacitor 402 electrically connected to the wiring 352 is initialized to the potential "Vr" at the node N (the other electrode of the capacitor 402).

At time T8, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", the potential of the wiring 128 is set to "H", the potential of the wiring 129 is set to "H", and the potential of the wiring 431 is set to "L", the transistor 107 is turned on. The potential of the node N is held at the potential "Vr".

At time T9, when the potential of wiring 126 is set to “H”, the potential of wiring 127 is set to “L”, the potential of wiring 128 is set to “H”, the potential of wiring 129 is set to “H”, and the potential of wiring 431 is set to “L”, the transistor 104 becomes conductive, and the potential of wiring 122 (reset potential) is supplied to node FD.

At time T10, the potential of the wiring 126 is set to "L", and at time T11, the potential of the wiring 129 is set to "L". This makes the transistors 104 and 107 non-conductive and holds the potential of the node FD at the reset potential.

Then, the potential of one electrode of the capacitor 402 changes due to a source follower operation accompanying the potential change of the node FD, and the change Y is added to the potential "Vr" of the node N by capacitive coupling. Therefore, the potential of the node N becomes "Vr+Y." Here, Y is image data that does not include a reset potential component, and data with reduced noise components is read out.

<Layer structure 1>
Next, the layered structure of the imaging device will be described with reference to a cross-sectional view.

FIG. 11 is an example of a cross-sectional view of a stack including layers 201 to 205 and a bonding surface between the layer 202 and the layer 203. In FIG.

<Layer 201>
The layer 201 has a read circuit 311, a row driver 312, and a column driver 313 provided on a silicon substrate 211. Here, as parts of the above circuits, a capacitor 402 and a transistor 403 included in the CDS circuit of the read circuit 311, a transistor 115 included in the A/D converter of the read circuit 311, and a transistor 116 included in the row driver 312 are shown. One electrode of the capacitor 402 and one of the source or drain of the transistor 403 are electrically connected.

The layer 201 is provided with insulating layers 212, 213, 214, 215, 216, 217, and 218. The insulating layer 212 functions as a protective film. The insulating layers 212, 213, 214, and 217 function as an interlayer insulating film and a planarizing film. The insulating layer 216 functions as a dielectric layer of the capacitor 402. The insulating layer 218 functions as a blocking film.

As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarizing film, for example, an inorganic insulating film such as a silicon oxide film, and an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the blocking film, it is preferable to use a film having a function of preventing the diffusion of hydrogen.

In a Si device, hydrogen is required to terminate dangling bonds, but hydrogen near an OS transistor is one of the factors that generates carriers in an oxide semiconductor layer and reduces reliability. Therefore, a hydrogen blocking film is preferably provided between a layer in which a Si device is formed and a layer in which an OS transistor is formed.

As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia (YSZ), or the like can be used.

The Si transistor shown in Fig. 11 is a fin type having a channel formation region in a silicon substrate 211, and a cross section in the channel width direction (cross section A1-A2 shown in Fig. 11) is shown in Fig. 12A. The Si transistor may be a planar type as shown in Fig. 12B.

12C, the transistor may have a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 211.

The conductor that can be used as wiring, electrodes, and plugs for electrical connection between devices may be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be multiple layers composed of different materials.

<Layer 202>
The layer 202 is formed over the layer 201. The layer 202 includes a memory circuit 321 including an OS transistor. Here, the transistor 111 and the capacitor 112 included in a memory cell 321a are shown as part of the memory circuit 321.

The layer 202 is provided with insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. In addition, a conductive layer 131 is provided.

The insulating layers 221, 224, 225, 227, and 228 function as an interlayer insulating film and a planarizing film. The insulating layer 222 functions as a gate insulating film. The insulating layer 223 functions as a protective film, and the insulating layer 226 functions as a dielectric layer of a capacitor. The insulating layer 229 and the conductive layer 131 function as bonding layers.

The gate insulating film may be a silicon oxide film, etc. The lamination layer will be described later.

The conductive layer 131 is electrically connected to the other electrode of the capacitor 402 in the layer 201. One of the source or the drain of the transistor 111 is electrically connected to the one of the source or the drain of the transistor 115 in the layer 201. The gate of the transistor 111 is electrically connected to the one of the source or the drain of the transistor 116 in the layer 201. The other of the source or the drain of the transistor 111 is electrically connected to one electrode of the capacitor 112.

13A illustrates the details of an OS transistor. The OS transistor illustrated in FIG 13A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

The OS transistor can have a structure including a channel formation region, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the groove.

As shown in FIG. 13B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

Alternatively, as shown in FIG. 13C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701 .

Although the OS transistor has a structure including a back gate 535, the OS transistor may have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of a transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 13D. Note that FIG. 13D shows the cross section taken along line B1-B2 in FIG. 13A as an example, but the same applies to transistors having other structures. In addition, the back gate 535 may be supplied with a fixed potential different from that of the front gate.

As a semiconductor material for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting a crystal, and is suitable for transistors in which reliability is important. In addition, CAC-OS has high mobility, and is therefore suitable for transistors that operate at high speed.

Since the energy gap of the semiconductor layer is large, the OS transistor exhibits extremely low off-current characteristics of several yA/μm (current value per 1 μm of channel width). In addition, the OS transistor has characteristics different from those of a Si transistor, such as no impact ionization, no avalanche breakdown, and no short channel effect, and can form a highly reliable circuit with high withstand voltage. In addition, the variation in electrical characteristics caused by non-uniformity of crystallinity, which is a problem in a Si transistor, is unlikely to occur in an OS transistor.

A semiconductor layer included in an OS transistor can be, for example, a film expressed as an In-M-Zn-based oxide containing indium, zinc, and M (one or more metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

The atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide by the sputtering method preferably satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

For the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, an oxide semiconductor with a carrier density of 1×10 ¹⁷ /cm ³ or less, preferably 1×10 ¹⁵ /cm ³ or less, more preferably 1×10 ¹³ /cm ³ or less, more preferably 1×10 ¹¹ /cm ³ or less, and further preferably less than 1×10 ¹⁰ /cm ³ , and with a carrier density of 1×10 ^-9 /cm ³ or more can be used for the semiconductor layer. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect states and has stable characteristics.

Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of a transistor. In order to obtain the required semiconductor characteristics of a transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, and the like of the semiconductor layer.

When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the elements of Group 14, oxygen vacancies increase and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Furthermore, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons serving as carriers are generated, and the carrier density increases, making the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably 5×10 ¹⁸ atoms/cm ³ or less.

Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are contained in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , and further preferably less than 1×10 ¹⁸ atoms/cm ^3. By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

The semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a stacked structure including two or more of the above-mentioned regions.

A structure of a CAC (Cloud-Aligned Composite)-OS, which is one mode of a non-single-crystal semiconductor layer, will be described below.

CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and a region containing the metal elements is mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is a mosaic-like structure formed by separation of materials such as indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter, GaO _X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O _Z4 ( _X4 , Y4, and Z4 are real numbers greater than ₀ ) ₎ , and the like. _Z2 is uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

That is, CAC-OS is a complex oxide semiconductor having a structure in which a region mainly composed of GaO _X3 is mixed with a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 . Note that in this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, it is defined that the first region has a higher In concentration than the second region.

Incidentally, IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. Representative examples include crystalline compounds expressed as InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1-x0) O ₃ (ZnO) _m0 (-1≦x0≦1, m0 is an arbitrary number).

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the a-b plane.

On the other hand, CAC-OS refers to a material structure of an oxide semiconductor. CAC-OS refers to a structure in which a part of a material structure containing In, Ga, Zn, and O is observed to have nanoparticle-like regions mainly composed of Ga and a part of a nanoparticle-like region mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more films having different compositions, for example, a two-layer structure including a film containing In as a main component and a film containing Ga as a main component.

In addition, there are cases where a clear boundary cannot be observed between the region containing GaO _X3 as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component.

In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained instead of gallium, the CAC-OS has a structure in which regions observed to be in the form of nanoparticles mainly composed of the metal element and regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, and for example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

CAC-OS has a characteristic that no clear peak is observed when it is measured using a θ/2θ scan by an out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it is found from the X-ray diffraction measurement that no orientation in the a-b plane direction or the c-axis direction is observed in the measurement region.

In addition, in an electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also referred to as a nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright points are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that has no orientation in the planar and cross-sectional directions.

For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region mainly composed of GaO _X3 and a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of an IGZO compound. That is, CAC-OS has a structure in which a region mainly composed of GaO _X3 or the like is phase-separated from a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 , and the regions mainly composed of each element are arranged in a mosaic pattern.

Here, the region mainly composed of _InX2ZnY2OZ2 or _InOX1 has higher conductivity than the region mainly composed of _{GaOX3 or the like} . That is, the conductivity of an oxide semiconductor is expressed by carriers flowing through the region mainly composed of _InX2ZnY2OZ2 or _{InOX1 .} Therefore, a high field effect mobility (μ) can be realized by distributing the region mainly composed _{of InX2ZnY2OZ2} or _InOX1 in a cloud shape in the oxide semiconductor _.

On the other hand, a region mainly composed of GaO _X3 or the like has higher insulating properties than a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 . That is, when a region mainly composed of GaO _X3 or the like is distributed in an oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

Therefore, when CAC-OS is used in a semiconductor element, the insulating property due to GaO _X3 or the like and the conductivity due to In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, so that a high on-current (I _on ) and a high field-effect mobility (μ) can be realized.

Furthermore, a semiconductor element using the CAC-OS has high reliability and is therefore suitable as a component material for various semiconductor devices.

<Layer 203>
The layer 203 is formed over the layer 202. The layer 203 includes a pixel circuit 331 having an OS transistor. Here, the transistor 103 and the transistor 104 are shown as part of the pixel circuit 331.

The layer 203 is provided with insulating layers 231, 232, 233, 234, 235, 236, and 237. In addition, a conductive layer 132 is provided.

The insulating layer 231 and the conductive layer 132 function as bonding layers. The insulating layers 232, 233, 234, and 237 function as interlayer insulating films and planarizing films. The insulating layer 235 functions as a protective film. The insulating layer 236 functions as a gate insulating film.

The conductive layer 132 is electrically connected to a wiring 352 that functions as an output line of the pixel circuit 331 .

Layer 204
Layer 204 includes a photoelectric conversion device 240 and insulating layers 241 , 242 , and 245 .

The photoelectric conversion device 240 is a pn junction type photodiode formed on a silicon substrate, and has a p-type region 243 and an n-type region 244. The photoelectric conversion device 240 is a buried type photodiode, and the thin p-type region 243 provided on the surface side (current extraction side) of the n-type region 244 can suppress dark current and reduce noise.

The insulating layer 241 functions as a blocking layer, the insulating layer 242 functions as an element isolation layer, and the insulating layer 245 functions to suppress the outflow of carriers.

The silicon substrate is provided with grooves for separating pixels, and the insulating layer 245 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 245, it is possible to prevent carriers generated in the photoelectric conversion device 240 from flowing out to adjacent pixels. The insulating layer 245 also has a function of suppressing the intrusion of stray light. Therefore, the insulating layer 245 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 245.

The element isolation layer can be formed by using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 245. The insulating layer 245 may have a multi-layer structure.

An n-type region 244 (corresponding to a cathode) of the photoelectric conversion device 240 is electrically connected to one of the source and drain of the transistor 103 in the layer 203. A p-type region 243 (anode) is electrically connected to the wiring 121 in the layer 203 that functions as a power supply line.

<Layer 205>
The layer 205 is formed on the layer 204. The layer 205 includes a light-shielding layer 251, an optical conversion layer 250, and a microlens array 255.

The light-shielding layer 251 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

A color filter can be used for the optical conversion layer 250. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.

Furthermore, if a wavelength cut filter is used in the optical conversion layer 250, an imaging device capable of obtaining images in various wavelength regions can be obtained.

For example, if a filter that blocks light with wavelengths equal to or shorter than visible light is used in the optical conversion layer 250, it can be used as an infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or shorter than near-infrared light is used in the optical conversion layer 250, it can be used as a far-infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or longer than visible light is used in the optical conversion layer 250, it can be used as an ultraviolet imaging device.

Furthermore, if a scintillator is used for the optical conversion layer 250, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 240. An imaging device having this configuration may also be used for a radiation detector or the like.

The scintillator includes a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light when irradiated with the radiation. _{For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S : Eu , BaFCl} : _Eu , NaI, CsI, _CaF2 , _BaF2 , _CeF3 , LiF, LiI, ZnO, or the like dispersed in a resin or ceramic can be used.

A microlens array 255 is provided on the optical conversion layer 250. Light passing through each lens of the microlens array 255 passes through the optical conversion layer 250 directly below, and is irradiated onto the photoelectric conversion device 240. By providing the microlens array 255, concentrated light can be incident on the photoelectric conversion device 240, so that photoelectric conversion can be performed efficiently. The microlens array 255 is preferably formed of a resin or glass that is highly translucent to visible light.

<Lamination>
Next, the bonding of the layer 202 and the layer 203 will be described.

The layer 202 is provided with an insulating layer 229 and a conductive layer 131. The conductive layer 131 has a region buried in the insulating layer 229. The surfaces of the insulating layer 229 and the conductive layer 131 are flattened so that they are at the same height.

The layer 203 is provided with an insulating layer 231 and a conductive layer 132. The conductive layer 132 has a region buried in the insulating layer 231. The surfaces of the insulating layer 231 and the conductive layer 132 are flattened so that they are at the same height.

Here, the conductive layers 131 and 132 preferably contain the same metal element as a main component, and the insulating layers 229 and 231 preferably contain the same component.

For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 131 and 132. In view of ease of bonding, Cu, Al, W, or Au is preferably used. Furthermore, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 229 and 231.

That is, the same metal material as described above is preferably used for each of the conductive layers 131 and 132. The same insulating material as described above is preferably used for each of the insulating layers 229 and 231. With this structure, the layer 202 and the layer 203 can be bonded to each other at the boundary between them.

The conductive layers 131 and 132 may have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 229 and 231 may also have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

This bonding can provide electrical connection between the conductive layer 131 and the conductive layer 132. In addition, the insulating layer 229 and the insulating layer 231 can be connected to each other with sufficient mechanical strength.

To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

In addition, for bonding insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing, etc., and then the surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment. Hydrophilic bonding also produces bonds at the atomic level, and therefore can provide mechanically excellent bonds.

When the layer 202 and the layer 203 are bonded to each other, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

By the above-described bonding, the pixel circuit 331 included in the layer 203 and the readout circuit 311 included in the layer 201 can be electrically connected to each other.

<Modification 1 of laminate structure 1>
Fig. 14A shows a modification in which the configuration of layer 204 is different from that of stacked structure 1 shown in Fig. 11. In modification 1 shown in Fig. 14A, a light-shielding layer 300 and an insulating layer 246 functioning as an interlayer insulating film are provided between insulating layer 241 of layer 204 and layer 237 of layer 203. Note that layers 201, 202, and 205 are not shown in the figure.

The light-shielding layer 300 can be formed of a conductive film such as a metal film. The light-shielding layer 300 can block irradiation of the layer 203 with light that cannot be absorbed by the photoelectric conversion device 240. In addition, the sensitivity of the photoelectric conversion device 240 can be increased by the light reflected by the light-shielding layer 300. Note that an opening 301 may be provided in a region where a plug or the like that connects to the photoelectric conversion device 240 is provided.

Irradiation of the OS transistor in the layer 203 with light can cause noise, such as an increase in off-state current. Therefore, the noise can be reduced. Furthermore, the light-shielding layer 300 can function as an electromagnetic shield by fixing the potential of the light-shielding layer 300 to a GND potential or the like. Therefore, the noise can be further reduced.

<Modification 2 of laminate structure 1>
Alternatively, as shown in FIG. 14B, the light-shielding layer 300 may be used as a cathode electrode of the photoelectric conversion device 240.

<Modification 3 of laminate structure 1>
15A , the light-shielding layer 300 may be used as the other electrode of the capacitor 108 included in the pixel circuit 331. In this case, the layer 204 is provided with an insulating layer 247 that acts as a dielectric layer of the capacitor 108. In addition, the layer 203 is provided with a conductive layer 238 that acts as one electrode of the capacitor 108.

The conductive layer 238 can be manufactured in a process common to the back gate electrode of the OS transistor. The conductive layer 238 can be electrically connected to the transistor 103 and the transistor 104 through a plug 239a, a connection electrode 239b, and a plug 239c. The plug 239c is a plug electrically connected to the conductive layer 238 at a position not shown in the cross section shown in FIG. 15A.

Note that a parasitic capacitance is formed between the back gate of the OS transistor included in the pixel circuit 331 and the light-shielding layer 300. For this reason, an opening 302 may be provided in a region of the light-shielding layer 300 that overlaps with the back gate, as shown in FIG.

<Modification 4 of laminate structure 1>
Fig. 16 shows a modification in which the configurations of the layer 203 and the layer 204 are different from those of the stacked structure 1 shown in Fig. 11. Modification 4 shown in Fig. 16 has a configuration in which the transistor 103 included in the pixel circuit 331 is provided in the layer 204. In the layer 204, the transistor 103 is formed of a Si transistor. One of the source or the drain of the transistor 103 is directly connected to the photoelectric conversion device 240, and the other of the source or the drain acts as a node FD.

In this case, the layer 203 includes transistors that constitute the pixel circuit 331, except for the transistor 103. In FIG.

<Modification 5 of laminate structure 1>
Fig. 17 shows a modification in which the configurations of the layer 201 and the layer 203 are different from those of the stacked structure 1 shown in Fig. 11. Modification 5 shown in Fig. 17 has a configuration in which a CDS circuit 400, which is a component of the readout circuit 311, is provided in the layer 203. Note that, although Fig. 17 shows a configuration in which the CDS circuit 400 is stacked on the pixel circuit 331, the CDS circuit 400 may be provided on the same surface as the pixel circuit 331.

In the above-described configuration, the layer 201 is provided with an A/D converter 410, which is another component of the read circuit 311. In FIG. 17, a transistor 117 that functions as an input transistor of the A/D converter 410 is illustrated. A gate of the transistor 117 is electrically connected to a conductive layer 131 included in the layer 202.

The layer 203 includes a CDS circuit 400 in addition to the pixel circuit 331. Here, a capacitor 402 and transistors 403 and 404 that are elements of the CDS circuit 400 are illustrated. The transistors 403 and 404 can be formed using OS transistors. In addition, the layer 203 includes insulating layers 421, 422, 423, 424, 425, 426, and 427.

The insulating layers 421, 423, 424, and 427 function as an interlayer insulating film and a planarizing film. The insulating layer 422 functions as a dielectric layer of the capacitor 402. The insulating layer 425 functions as a protective film. The insulating layer 426 functions as a gate insulating film.

The other electrode of the capacitor 402 is electrically connected to the wiring 352 to which the pixel circuit 331 is connected, and one electrode of the capacitor 402 is electrically connected to one of the source or drain of the transistor 403 and one of the source or drain of the transistor 404. The other of the source or drain of the transistor 404 is connected to the conductive layer 132. By attaching the conductive layer 132 to the conductive layer 131 included in the layer 202, the CDS circuit 400 and the A/D converter 410 can be electrically connected to each other.

<Layer structure 2>
In the laminate structure 1 and its modified example, the layer 202 and the layer 203 are bonded to each other, but other layers may be bonded to each other. The laminate structure 2 shown in FIG. 18 has a bonding surface between the layer 203 and the layer 204.

In this case, the layer 203 is provided with a conductive layer 135 electrically connected to one of the source and drain of the transistor 103. Also, a conductive layer 136 electrically connected to the wiring 121 is provided. The conductive layers 135 and 136 have a region buried in the insulating layer 231. The surfaces of the insulating layer 231 and the conductive layers 135 and 136 are planarized so that they are at the same height.

The layer 204 is provided with a conductive layer 133 electrically connected to an n-type region 244 (corresponding to a cathode) of the photoelectric conversion device 240. Also, a conductive layer 134 is provided electrically connected to a p-type region 243 (anode). Also, an insulating layer 249 is provided on the insulating layer 246. The conductive layers 133 and 134 have regions buried in the insulating layer 249. Also, the surfaces of the insulating layer 249 and the conductive layers 133 and 134 are flattened so that they are at the same height.

Here, the conductive layers 133, 134, 135, and 136 are the same bonding layer as the conductive layers 131 and 132 described above. The insulating layer 249 is the same bonding layer as the insulating layers 229 and 231 described above.

Therefore, by bonding the conductive layer 133 and the conductive layer 135 together, it is possible to electrically connect the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device to one of the source or drain of the transistor 103. Also, by bonding the conductive layer 134 and the conductive layer 136 together, it is possible to electrically connect the p-type region 243 (corresponding to the anode) of the photoelectric conversion device to the wiring 121. Also, by bonding the insulating layer 231 and the insulating layer 249 together, it is possible to electrically and mechanically bond the layer 203 and the layer 204.

<Layer structure 3>
The laminated structure 2 shown in FIG. 19 has a configuration in which a bonding surface is provided between a layer 201 and a layer 202 .

In this case, the layer 201 is provided with a conductive layer 141 electrically connected to the other electrode of the capacitor 402. A conductive layer 142 electrically connected to one of the source or drain of the transistor 115 is provided. A conductive layer 143 electrically connected to one of the source or drain of the transistor 116 is also provided. An insulating layer 219 is provided over the insulating layer 218. The conductive layers 141, 142, and 143 have regions buried in the insulating layer 219. The surfaces of the insulating layer 219 and the conductive layers 141, 142, and 143 are planarized so that they are at the same height.

The layer 202 is provided with a conductive layer 137 electrically connected to a wiring 352 included in the layer 203. A conductive layer 138 is provided to be electrically connected to one of a source and a drain of a transistor 111 included in the layer 202. A conductive layer 139 is provided to be electrically connected to a gate of the transistor 111. The conductive layers 137, 138, and 139 each have a region buried in an insulating layer 229. The surfaces of the insulating layer 229 and the conductive layers 137, 138, and 139 are planarized so that they are all at the same height.

Here, the conductive layers 137, 138, 139, 141, 142, and 143 are the same bonding layer as the conductive layers 131 and 132 described above. The insulating layer 219 is the same bonding layer as the insulating layers 229 and 231 described above.

Therefore, by bonding the conductive layer 137 and the conductive layer 141 together, the read circuit 311 and the pixel circuit 331 can be electrically connected. In addition, by bonding the conductive layer 138 and the conductive layer 142 together, the column driver 313 and the memory circuit 321 can be electrically connected. In addition, by bonding the conductive layer 139 and the conductive layer 143 together, the row driver 312 and the memory circuit 321 can be electrically connected.

In this embodiment, the readout circuit of the pixel circuit and the driving circuit of the memory circuit are provided in the layer 201, and the memory circuit is provided in the layer 202. However, the present invention is not limited to this. For example, a driving circuit of the pixel circuit, a neural network, a communication circuit, a CPU, and the like may be provided in the layer 201 or the layer 202.

A normally-off CPU (also referred to as a "Noff-CPU") can be realized using an OS transistor and a Si transistor. Note that a Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when a gate voltage of 0 V is applied.

The Noff-CPU can stop the power supply to circuits in the Noff-CPU that are not required to operate, and put the circuits into a standby state. The power supply is stopped and the circuits in the standby state do not consume power. Therefore, the Noff-CPU can minimize the amount of power consumption. Furthermore, the Noff-CPU can hold information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

<Layer structure 4>
4C, when the transistor 107 is an OS transistor and the other transistors are Si transistors, the pixel circuit 331 may have the structure shown in FIG. 20A. In FIG. 20A, the transistors 103, 104, 105, and 106, which are Si transistors, are provided in the layer 204, and the transistor 107, which is an OS transistor, is provided in the layer 203. The layer 203 shown in FIG. 20A can be connected to a circuit included in the layer 202, as in other stacked structures. Alternatively, the layer 202 may not be provided and the layer 203 may be connected to a circuit included in the layer 201.

The pixel circuit 331 shown in Fig. 4C may have a stacked structure shown in Fig. 20B. The stacked structure shown in Fig. 20B is configured to irradiate the photoelectric conversion device 240 with light from the wiring side. This configuration has a low light utilization efficiency, but has the advantage of a high degree of freedom in the process. In the configuration shown in Fig. 20B, a layer 205 is stacked on a layer 203.

One embodiment of the present invention may have a stacked structure shown in Fig. 21. The stacked structure shown in Fig. 21 shows a driver circuit 332 provided outside the pixel circuit 331 and the pixel array shown in Fig. 4C. Although a structure including a Si transistor and an OS transistor is shown as the driver circuit 332, the driver circuit 332 may be formed of either one of them. With this structure, a bonding process may be unnecessary.

<Organic photoelectric conversion device>
In one embodiment of the present invention, an organic photoelectric conversion device can be used as a photoelectric conversion device instead of a Si photodiode. A photoelectric conversion device 240 shown in Fig. 22 is an example of an organic photoconductive film, in which a layer 567a is a lower electrode, a layer 567e is a light-transmitting upper electrode, and layers 567b, 567c, and 567d correspond to a photoelectric conversion portion.

One of the layers 567b and 567d in the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

For example, molybdenum oxide can be used as the hole transport layer, and for example, fullerene such as C ₆₀ or C ₇₀ , or a derivative thereof can be used as the electron transport layer.

As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

22 shows the configuration of the pixel circuit 331 shown in FIG. 4C, in which case the transistors 103, 104, 105, and 106 can be provided on the silicon substrate of the layer 206. In this configuration, a bonding process can be unnecessary.

This embodiment mode can be appropriately combined with the descriptions of other embodiment modes or examples.

(Embodiment 2)
In this embodiment, an example of a package and a camera module including an image sensor chip will be described. The image sensor chip can have the same structure as the imaging device of one embodiment of the present invention.

23A1 is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 610 for fixing an image sensor chip 650, a cover glass 620, and an adhesive 630 for bonding the two together.

23A2 is an external perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball Grid Array) with solder balls as bumps 640. Note that the package is not limited to a BGA, and may have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc.

23A3 is a perspective view of the package with a portion of the cover glass 620 and the adhesive 630 omitted. Electrode pads 660 are formed on the package substrate 610, and the electrode pads 660 and the bumps 640 are electrically connected via through holes. The electrode pads 660 are electrically connected to the image sensor chip 650 by wires 670.

23B1 is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 611 for fixing an image sensor chip 651, a lens cover 621, and a lens 635. An IC chip 690 having functions such as a drive circuit and a signal conversion circuit for an imaging device is also provided between the package substrate 611 and the image sensor chip 651, and the camera module has a configuration as a SiP (System in Package).

23B2 is an external perspective view of the bottom side of the camera module. The bottom and side surfaces of the package substrate 611 have a QFN (Quad Flat No-Lead Package) configuration with mounting lands 641. Note that this configuration is one example, and a QFP (Quad Flat Package) or the above-mentioned BGA may also be provided.

23B3 is a perspective view of the module in which a part of the lens cover 621 and the lens 635 is omitted. The land 641 is electrically connected to the electrode pad 661, and the electrode pad 661 is electrically connected to the image sensor chip 651 or the IC chip 690 by a wire 671.

By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

This embodiment mode can be appropriately combined with the descriptions of other embodiment modes or examples.

(Embodiment 3)
Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Figures 24A to 24F.

24A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger, a stylus, or the like. The imaging device of one embodiment of the present invention and its operating method can be applied to an element for acquiring an image in the mobile phone.

24B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as voice through the speaker 913. The imaging device of one embodiment of the present invention and its operating method can be applied to an element for acquiring an image in the portable data terminal.

24C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on a ceiling to enable imaging of the entire periphery. The imaging device and the operation method of one embodiment of the present invention can be applied to an element for acquiring an image in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

24D shows a video camera having a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An imaging device and an operation method thereof according to one embodiment of the present invention can be applied to elements for acquiring an image in the video camera.

24E illustrates a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to elements for acquiring an image in the digital camera.

24F shows a wristwatch-type information terminal, which includes a display unit 932, a housing/wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing/wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to an element for acquiring an image in the information terminal.

This embodiment mode can be appropriately combined with the descriptions of other embodiment modes or examples.

102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: transistor, 108: capacitor, 111: transistor, 112: capacitor, 115: transistor, 116: transistor, 117: transistor, 121: wiring, 122: wiring, 123: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 131: conductive layer, 132: conductive layer , 133: conductive layer, 134: conductive layer, 135: conductive layer, 136: conductive layer, 137: conductive layer, 138: conductive layer, 139: conductive layer, 141: conductive layer, 142: conductive layer, 143: conductive layer, 201: layer, 202: layer, 203: layer, 204: layer, 205: layer, 206: layer, 210: region, 211: silicon substrate, 212: insulating layer, 213: insulating layer, 214: insulating layer, 215: insulating layer, 216: insulating layer, 217: insulating layer, 218: insulating layer, 219: Insulating layer, 220: region, 221: insulating layer, 222: insulating layer, 223: insulating layer, 224: insulating layer, 225: insulating layer, 226: insulating layer, 227: insulating layer, 228: insulating layer, 229: insulating layer, 230: region, 231: insulating layer, 232: insulating layer, 233: insulating layer, 234: insulating layer, 235: insulating layer, 236: insulating layer, 237: layer, 238: conductive layer, 239a: plug, 239b: connecting electrode, 239c: plug, 240: photoelectric conversion device, 2 41: insulating layer, 242: insulating layer, 243: p-type region, 244: n-type region, 245: insulating layer, 246: insulating layer, 247: insulating layer, 249: insulating layer, 250: optical conversion layer, 251: light-shielding layer, 255: microlens array, 300: light-shielding layer, 301: opening, 302: opening, 311: circuit, 312: row driver, 313: column driver, 321: memory circuit, 321a: memory cell, 321aA: memory cell, 321aB: memory cell 321aC: memory cell, 321aD: memory cell, 331: pixel circuit, 332: drive circuit, 351: wiring, 352: wiring, 353: wiring, 354: wiring, 355: wiring, 400: CDS circuit, 401: transistor, 402: capacitor, 403: transistor, 404: transistor, 405: capacitor, 410: A/D converter, 421: insulating layer, 422: insulating layer, 423: insulating layer, 424: insulating layer, 425: insulating layer , 426: insulating layer, 427: insulating layer, 431: wiring, 432: wiring, 535: back gate, 545: semiconductor layer, 546: insulating layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 610: package substrate, 611: package substrate, 620: cover glass, 621: lens cover, 630: adhesive, 635: lens, 640: bump, 641: land, 650: image sensor chip, 651: image Sensor chip, 660: electrode pad, 661: electrode pad, 670: wire, 671: wire, 690: IC chip, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing/wristband, 939: camera, 951: Support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting section, 971: housing, 972: housing, 973: display section, 974: operation keys, 975: lens, 976: connection section, 977: speaker, 978: microphone, 981: housing, 982: display section, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera

Claims (11)

a first circuit, a second circuit, a third circuit, a photoelectric conversion device, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer;
the first circuit has a region overlapping with the second insulating layer via the first insulating layer and the second circuit;
the first insulating layer is provided between the first circuit and the second circuit;
the first conductive layer has a region embedded in the second insulating layer;
the photoelectric conversion device has a region overlapping with the fourth insulating layer via the third insulating layer and the third circuit;
the third insulating layer is provided between the photoelectric conversion device and the third circuit;
the second conductive layer has a region embedded in the fourth insulating layer;
the first conductive layer is electrically connected to the first circuit;
the first circuit is electrically connected to the second circuit;
the second conductive layer is electrically connected to the third circuit;
the third circuit is electrically connected to the photoelectric conversion device;
the first conductive layer and the second conductive layer are directly bonded to each other;
the second insulating layer and the fourth insulating layer are directly bonded to each other ;
the first circuit includes a first transistor having silicon in a channel formation region and a second transistor having silicon in a channel formation region;
the second circuit includes a third transistor having a second metal oxide in a channel formation region, and a first capacitor electrically connected to the third transistor;
the third circuit includes fourth to eighth transistors and a second capacitor;
the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are transistors having silicon in a channel formation region,
the sixth transistor is a transistor having a first metal oxide in a channel formation region,
one of a source and a drain of the fourth transistor is electrically connected to one electrode of the photoelectric conversion device;
the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor;
the other of the source and the drain of the sixth transistor is electrically connected to the gate of the seventh transistor and to one electrode of the second capacitor;
one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor;
an imaging device, wherein, in a cross-sectional view, the first capacitor has a region overlapping with the first transistor, a region overlapping with the second transistor, and a region overlapping with any one of the fourth to eighth transistors . In claim 1,
The imaging device, wherein the photoelectric conversion device is a photodiode having silicon in a photoelectric conversion layer. In claim 2,
The first metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf). In any one of claims 1 to 3,
the first conductive layer and the second conductive layer are made of the same metal material;
The imaging device, wherein the second insulating layer and the fourth insulating layer are made of the same insulating material. In any one of claims 1 to 4,
the third circuit and the photoelectric conversion device have a function of a pixel circuit;
The first circuit is an imaging device having a function of a readout circuit. In any one of claims 1 to 5,
Further, the light-shielding layer is provided,
The imaging device, wherein the light-shielding layer is provided between the photoelectric conversion device and the third circuit. In any one of claims 1 to 6,
Further, the fourth circuit and the fifth circuit are included,
the fourth circuit and the fifth circuit are provided on the same substrate as the first circuit;
the fourth circuit is electrically connected to the second circuit;
The fifth circuit is electrically connected to the second circuit. In claim 7,
The fourth circuit and the fifth circuit are an imaging device including a transistor having silicon in a channel formation region. In claim 7 or 8,
the second circuit has a function of a memory circuit;
the fourth circuit has a function of a column driver that drives the memory circuit;
The fifth circuit is an imaging device having a function of a row driver that drives the memory circuit. In any one of claims 1 to 9 ,
The second metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf). An imaging device comprising: the imaging device according to any one of claims 1 to 10 ; and a display unit;
An electronic device capable of displaying an image captured by the imaging device on the display unit.

Images