JP7634812B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device. The present invention also relates to a system having a semiconductor device.

As semiconductor devices become smaller, there are cases where fine position adjustments and fine processing of 100 μm or less, or even 1 μm or less, are required in the manufacturing process. For example, Patent Document 1 describes a method for manufacturing a thin-film transistor, in which a gate electrode pattern formed on a substrate is covered with a gate insulating film, an organic semiconductor layer and an electrode layer are formed on the gate insulating film, a negative photosensitive resist film is deposited, and a resist pattern is formed by exposing the back surface of the substrate side to light using the gate electrode as a light-shielding mask. Furthermore, it is described that the resist pattern is used as a mask for etching the electrode layer to form a source and drain, and that the source and drain are self-aligned with respect to the gate electrode.

For example, Patent Document 2 describes a method for manufacturing a semiconductor device in which a film forming a channel protection layer is formed on a light-transmitting oxide layer, a positive photoresist is formed on the film forming the channel protection layer, and a backside exposure method is used to selectively form a channel protection layer on a channel formation region in an oxide semiconductor layer, thereby reducing the number of photomasks.

On the other hand, in the manufacturing process of a semiconductor device, for example, when epitaxially growing a crystal on a heterogeneous substrate (heteroepitaxial growth), there is a problem that defects such as dislocations and cracks occur due to lattice mismatch between the substrate and the crystal. In response to this problem, a film formation method using ELO is being considered as described in Patent Document 3. In addition, Non-Patent Document 1 describes that an α-Ga ₂ O ₃ film with a dislocation density of 1.0×10 ⁶ /cm ² or less can be obtained by the ELO technique.

As semiconductors, for example, silicon carbide, gallium nitride, indium nitride, aluminum nitride, and gallium nitride nitride semiconductors including mixed crystals thereof are known, and are used in various semiconductor devices such as blue LEDs and power semiconductors. In recent years, gallium oxide (Ga ₂ O ₃ ) has been attracting attention as a new semiconductor.

As a next-generation switching element capable of realizing high voltage resistance, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga ₂ O ₃ ) with a large band gap have been attracting attention, and are expected to be applied to power semiconductor devices such as inverters. In addition, a wide range of applications as light receiving and emitting devices such as LEDs and sensors with short wavelengths due to the wide band gap are also expected. In particular, α-Ga ₂ O ₃ and the like having a corundum structure among gallium oxides can control the band gap by mixing indium and aluminum, respectively or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors refer to In _x Al _y Ga _z O ₃ (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5-2.5) (Patent Document 4, etc.), and can be viewed as the same material system containing gallium oxide.

In addition, boron nitride and diamond are also attracting attention as semiconductor materials.

However, when epitaxially growing the above-mentioned materials as crystals on a crystalline substrate to obtain a semiconductor device, there are still many challenges to be overcome in efficiently aligning the necessary layers, regions, and/or trenches to be placed on the crystal during the manufacturing process of the semiconductor device.

Patent No. 5429454 Patent No. 5615540 Patent Publication 2016-100592 International Publication No. 2014/050793

KAWARA, Katsuaki, et al. Elimination of threading dislocations in α-Ga2O3 by double-layered epitaxial lateral overgrowth. Applied Physics Express, 2020, 13.7: 075507.

One of the objectives of the present invention is to provide a semiconductor device in which, when a semiconductor layer includes at least a drift region and a channel region, the channel region is disposed in a region with a lower dislocation density.

As a result of intensive research into achieving the above object, the present inventor has found that by manufacturing a semiconductor device having at least a semiconductor layer including a drift region and a channel region by a method including disposing a light-shielding portion to cover a portion of the first surface of a crystalline substrate, epitaxially growing a crystal on the first surface of the crystalline substrate to form a stack, forming a photosensitive layer on the crystal side of the stack, and selectively removing the photosensitive layer by photolithography including irradiating light from the second surface side of the crystalline substrate, the channel region can be disposed in a region with a lower dislocation density, the on-resistance can be further reduced, and a semiconductor device with excellent semiconductor characteristics can be obtained, thereby solving the above-mentioned conventional problems in one fell swoop.

After obtaining the above findings, the inventors conducted further research and completed the present invention.

That is, the present invention relates to the following inventions.
[1] A semiconductor device comprising at least a semiconductor layer including a drift region and a channel region, the channel region having a lower dislocation density than the drift region.
[2] The semiconductor device according to [1], wherein the semiconductor layer further has a source region, and the dislocation density of the source region is lower than the dislocation density of the drift region.
[3] The semiconductor device according to [1] or [2], wherein the semiconductor layer has a corundum structure.
[4] The semiconductor device according to [3], wherein the channel length direction of the channel region is the a-axis direction or the m-axis direction.
[5] The semiconductor device according to [3] or [4], wherein the direction of a drift current in the drift region is the m-axis direction.
[6] The semiconductor device according to any one of [1] to [5], wherein the semiconductor layer contains at least gallium.
[7] The semiconductor device according to any one of [1] to [6], further comprising a gate electrode, the gate electrode being adjacent to the channel region directly or via another layer.
[8] The semiconductor device according to [7], wherein the semiconductor layer has a trench, and at least a portion of the gate electrode is located within the trench.
[9] The semiconductor device according to [7] or [8], wherein the gate electrode is adjacent to the channel region via a gate insulating film.
[10] The semiconductor device according to any one of [1] to [9], which is a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET) or an insulated gate bipolar transistor (IGBT).
[11] A power conversion device having the semiconductor device according to any one of [1] to [10].
[12] A control system comprising the semiconductor device according to any one of [1] to [10] above.

As a first aspect of the present invention, a semiconductor device is provided that includes at least a semiconductor layer including a drift region and a channel region, and the dislocation density of the channel region is smaller than the dislocation density of the drift region. As a second aspect of the present invention, a semiconductor device is provided that includes at least a semiconductor layer including a drift region, a channel region, and a source region, and the dislocation density of the channel region is smaller than the dislocation density of the drift region, and the dislocation density of the source region is smaller than the dislocation density of the drift region. According to the embodiment of the present invention, the channel region and the source region can be arranged in a position with fewer dislocations, and a semiconductor device with excellent semiconductor characteristics can be obtained with industrial advantage.

1 shows a schematic plan view of a semiconductor device according to a first embodiment of the present invention. 1A is a schematic cross-sectional view taken along line Ib-Ib of the semiconductor device shown in FIG. FIG. 11 is a schematic plan view showing an example of a semiconductor device as a second embodiment of the present invention. 2B is a schematic cross-sectional view taken along line IIb-IIb of the semiconductor device shown in FIG. FIG. 1 is a side view showing an example of a crystalline base preferably used in an embodiment of a method for manufacturing a semiconductor device of the present invention, and shows an example in which the crystalline base is a crystal substrate. FIG. 1 is a side view showing an example of a crystalline base preferably used in an embodiment of a method for manufacturing a semiconductor device according to the present invention, in which the crystalline base includes a crystalline substrate and a crystalline layer disposed on the crystalline substrate. FIG. 1 is a side view showing an example of a crystalline base preferably used in an embodiment of a method for manufacturing a semiconductor device according to the present invention, in which the crystalline base includes a crystalline substrate and two or more crystalline layers disposed on the crystalline substrate. FIG. 1 is a side view showing an example of a crystalline substrate preferably used in an embodiment of the method for manufacturing a semiconductor device of the present invention, showing one embodiment in which the crystalline substrate includes at least a first crystal layer and a second crystal layer disposed on the first crystal layer. FIG. 2 is a diagram illustrating a halide vapor phase epitaxy (HVPE) apparatus that can be used to grow a crystal layer and/or a semiconductor layer, as an example, in an embodiment of a method for manufacturing a semiconductor device of the present invention. FIG. 2 is a diagram illustrating a mist CVD apparatus that can be used to grow a crystal layer and/or a semiconductor layer as an example in an embodiment of a method for manufacturing a semiconductor device of the present invention. As one embodiment of the present invention, this is a schematic cross-sectional view showing a method for manufacturing a laminated structure, in which a light-shielding portion is placed to cover a portion of a first surface of a crystalline base, and a crystal is epitaxially grown on the first surface of the crystalline base. This shows an embodiment in which a layer is formed on the crystal side of the laminate shown in FIG. 2-a. FIG. 2 shows a diagram in which light is irradiated from the second surface side of the crystalline base. 1 shows the selective removal of said layers by photolithography. 1 shows an embodiment of a laminate structure including a layer (eg, a mask layer or an electrode layer) formed in a desired shape (pattern). As one embodiment of the present invention, this is a schematic cross-sectional view showing a method for manufacturing a laminated structure, in which a light-shielding portion is placed to cover a portion of a first surface of a crystalline base, and a cross-sectional view of one embodiment of a laminate in which a crystal is epitaxially grown on the first surface of the crystalline base is shown. 3-a的图中的一实施例中，上一层是在上一个晶体上的光杂层。 FIG. 3-a is a cross-sectional view of one embodiment of a layer formed on the crystal side of the laminate. In this embodiment, the layer is a photosensitive layer disposed on the crystal and a light-shielding portion. FIG. 2 is a cross-sectional view illustrating the crystalline base body irradiated with light from its second surface side. 1 shows a cross-sectional view of the layer selectively removed by photolithography, in which a positive photosensitive layer is disposed, and the layer is removed in the areas irradiated with light, leaving the layer in the areas not irradiated with light. 1 shows an embodiment of a laminate structure including a layer (eg, a mask layer or an electrode layer) formed into a desired shape. As one embodiment of the present invention, a photograph of a laminate having a negative photosensitive layer disposed on a crystal is shown taken from the first side. 8 is a photograph showing a cross section taken along line VIII-VIII of the laminate shown in FIG. 7. As one embodiment of the present invention, a photograph of a laminate having a positive photosensitive layer disposed on a crystal is shown taken from the first side. 10 is a photograph showing the XX cross section of the laminate shown in FIG. 9. 1 is a photograph showing a cross section of a crystalline substrate on which light-shielding portions 12 are periodically arranged, as one embodiment of the present invention. As one embodiment of the present invention, a photograph shows the top surface of a laminated structure in which crystals are grown on a crystalline base having light-shielding portions 12 arranged periodically, and a mask layer is then formed on the crystals by photolithography, which includes irradiating light from the second surface side of the crystalline base, and a cross-section of a portion cut out from the top surface of the laminated structure. 13 is an enlarged photograph of a part of the photograph shown in FIG. 12. The photograph shown in FIG. 13 is enlarged and labeled with a reference number. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1A to 1C are partial cross-sectional explanatory views showing a method for manufacturing a semiconductor device as one embodiment of the present invention. 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention.

As a first embodiment of the semiconductor device of the present invention, a schematic plan view of the semiconductor device is shown in FIG.
FIG. 1-b shows a cross-sectional view of the semiconductor device shown in FIG. 1-a taken along line Ib-Ib. The semiconductor device 100 at least includes a semiconductor layer 157 including a drift region 160 and a channel region 161, an insulating film 154 disposed on the semiconductor layer 157, and a gate electrode 155a disposed on the insulating film 154, and the dislocation density of the channel region 161 is smaller than the dislocation density of the drift region 160. By adopting such a structure, the semiconductor device with reduced on-resistance can be obtained. The gate electrode 155a is disposed at a position close to the first surface 157a side of the semiconductor layer 157, and the semiconductor device 100 further includes a source electrode 155b at a position close to the first surface 157a side. At least a portion of the source electrode 155b is covered with the insulating film 154. The semiconductor device 100 also includes a drain electrode 155c disposed at a position close to the second surface 157b opposite to the first surface 157a side. Here, a first surface 156a of a semiconductor layer 156 (also referred to as a second semiconductor layer) is disposed in contact with the second surface 157b of the semiconductor layer 157 (also referred to as a first semiconductor layer).

In addition, the drain electrode 155c is specifically arranged on the second surface 156b of the second semiconductor layer 156. In this case, the second semiconductor layer 156 is an n+ type semiconductor layer, and the first semiconductor layer 157 is an n- type semiconductor layer. The semiconductor device 100 has a semiconductor region 158 having a conductivity type different from the conductivity type of the n- type semiconductor layer 157 in the n- type semiconductor layer 157. Here, the semiconductor region 158 is a p-type semiconductor region, and is arranged in the first semiconductor layer 157 so as to have a portion overlapping the end of the gate electrode 155a in a plan view, as shown in FIG. 1-a and FIG. 1-b. The first semiconductor layer 157 is located directly below the gate electrode 155a, and this portion becomes the drift region 160. In addition, a semiconductor region 159 having a conductivity type different from that of the p-type semiconductor region 158 is located in the p-type semiconductor region 158, and the semiconductor region 159 is an n+ type semiconductor region. The p-type semiconductor region 158 has a portion overlapping the end of the gate electrode 155a in a plan view, which becomes the channel region 161. As shown in the cross-sectional view of FIG. 1-b, the channel region 161 is located outside the drift region 160 located directly below the gate electrode 155a, and is also located below the end of the gate electrode 155a. In addition, the n+ type semiconductor region 159 becomes a source region 162. As shown in the cross-sectional view of FIG. 1-b, the source region 162 is located outside the channel region 161. In addition, the source region 162 does not overlap with the gate electrode in a plan view. The dislocation density of the source region 162 is smaller than the dislocation density of the drift region 160. By adopting such a configuration, it is possible to more effectively reduce the on-resistance of the semiconductor device. In this embodiment, the semiconductor layer 157 has a corundum structure. The semiconductor layer may be a _{Ga2O3 semiconductor} layer having a corundum structure, or may be a mixed crystal oxide semiconductor layer containing Ga.

In this embodiment, when the semiconductor layer 157 has a corundum structure, the semiconductor layer 156 may have an m-plane as the main surface. In an embodiment of the present invention, in the manufacturing process of the semiconductor device described later, it is possible to arrange the drift region in a place where dislocations extend, and arrange the channel region and the source region in a place where dislocations are few. In this case, the dislocation density of the channel region and/or the source region is, for example, 5.0×10 ⁶ /cm ² or less. The drift region 160 is located in a region with more dislocations than the channel region 161, but since the direction in which the dislocations extend can be predicted as described later, it is possible to arrange the drift region 160 so that the direction in which the dislocations extend and the direction in which the current (drift current) flows are aligned. The drift current refers to a current flowing from the drain electrode 155c to the source electrode 155b, and when the main surface of the semiconductor layer 157 is an m-plane, the direction in which the drift current flows is substantially parallel to the m-axis direction of the semiconductor layer 157 (the Y-Y direction shown in FIG. 1-b). Here, "substantially parallel" includes the m-axis of the semiconductor layer being parallel to the direction of the drift current, but does not have to be completely parallel. It means "substantially parallel" as long as the angle between the m-axis direction of the semiconductor layer and the direction of the drift current is 0° or more and 10° or less.

In addition, it is preferable that the channel length direction of the channel region is the a-axis direction or the m-axis direction of the semiconductor layer 157. In one embodiment of the semiconductor device, the channel length direction is the a-axis direction of the semiconductor layer 157, meaning that when the main surface of the semiconductor layer 157 is an m-plane, the direction parallel to the m-plane (X-X direction shown in FIG. 1-b) is the channel length direction, as shown in FIG. 1-b. In another embodiment of the semiconductor device, the channel length direction is the m-axis direction of the semiconductor layer 157, meaning that the semiconductor layer 157 has a trench, and when the main surface is an m-plane, it is preferable that the semiconductor layer 157 has a trench in which the channel length direction is a direction parallel to the m-axis of the semiconductor layer 157 (Y-Y direction shown in FIG. 1-b). In yet another embodiment, the semiconductor layer having a corundum structure may be a semiconductor layer of a mixed crystal having a corundum structure containing gallium oxide and aluminum and/or indium. The semiconductor layer may contain a dopant. In another embodiment, the semiconductor device may include a light-shielding portion used in the process of the embodiment of the manufacturing method. In this case, it is preferable that the semiconductor device has a light-shielding portion having an opening, and the opening of the light-shielding portion overlaps at least a portion of the drift region 160 in a plan view. As described below, the light-shielding portion may be removed during the manufacturing process, and therefore may not be included in the semiconductor device.

As a second embodiment of the semiconductor device of the present invention, FIG. 2-a shows a schematic plan view of the semiconductor device. FIG. 2-b is a partial cross-sectional view of the semiconductor device shown in FIG. 2-a, shown at IIb-IIb. The semiconductor device 200 has at least a semiconductor layer 13 including a drift region 160 and a channel region 161, an insulating film 35 (gate insulating film) arranged on the semiconductor layer 13, and a gate electrode 36' arranged on the insulating film 35, and the dislocation density of the channel region 161 is smaller than the dislocation density of the drift region 160. By adopting such a structure, the semiconductor device with reduced on-resistance can be obtained. The gate electrode 36' is arranged in a position close to the first surface side of the semiconductor layer 13, and the semiconductor device 200 further has a source electrode 64 in a position close to the first surface side of the semiconductor layer 13. Insulating layers 62', 63' are arranged between the gate electrode 36' and the source electrode 64. The semiconductor device 200 also has a drain electrode 65 arranged in a position close to the opposite side of the first surface side. Here, the first surface of semiconductor layer 3 (also called the second semiconductor layer) is arranged in contact with the second surface of semiconductor layer 13 (also called the first semiconductor layer).

In addition, the drain electrode 65 is specifically arranged on the second surface of the second semiconductor layer 3. In this case, the second semiconductor layer 3 is an n+ type semiconductor layer, and the first semiconductor layer 13 is an n- type semiconductor layer. In the semiconductor device 200, a semiconductor region 60 having a conductivity type different from that of the n- type semiconductor layer 13 is located in the n- type semiconductor layer 13. Here, the semiconductor region 60 is a p- type semiconductor region. Also, a semiconductor region 61 having a conductivity type different from that of the p- type semiconductor region 60 is located in the p- type semiconductor region 60. The semiconductor region 61 is an n+ type semiconductor region. A p+ type semiconductor region 66 is arranged in the n+ type semiconductor region 61 with at least a part of it being in contact with the p- type semiconductor region 60 and the semiconductor region 61. The semiconductor layer 13 further includes a source region 162 including at least a part of the p+ type semiconductor region 66 and at least a part of the n+ type semiconductor region 61, and the dislocation density of the source region 162 is smaller than the dislocation density of the drift region 160. With this configuration, the on-resistance of the semiconductor device can be reduced more effectively. In this embodiment, the semiconductor layer 13 has a corundum structure. The semiconductor layer may be a _{Ga2O3 semiconductor} layer having a corundum structure.

In this embodiment, when the semiconductor layer 13 has a corundum structure, the semiconductor layer 13 may have an m-plane as a main surface. In this embodiment, in the manufacturing process of the semiconductor device described later, it is possible to arrange the drift region in a place where dislocations extend, and arrange the channel region and the source region in a place where dislocations are few. In this case, the dislocation density of the channel region and/or the source region is, for example, 5.0×10 ⁶ /cm ² or less. The drift region 160 is located in a region with more dislocations than the channel region 161, but can be arranged so that the direction in which the dislocations extend and the direction in which the current (drift current) flows are aligned. That is, the drift current is arranged so that the drift current flows in the direction in which the dislocations extend. In this embodiment, the drift current refers to a current flowing from the drain electrode 65 to the source electrode 64, and when the main surface of the semiconductor 13 is an m-plane, the direction in which the drift current flows is the m-axis direction of the semiconductor layer 13. In this embodiment, the semiconductor layer 13 is preferably single crystal. The insulating films 62' and 63' are interlayer insulating films. As described as an example of the embodiment of the semiconductor device 100, when the main surface of the semiconductor layer 13 is an m-plane, it is preferable that the channel length direction of the channel region 161 is the a-axis direction or the m-axis direction of the semiconductor layer 13. As another embodiment, the semiconductor layer having a corundum structure may be a mixed crystal semiconductor layer having a corundum structure containing gallium oxide and aluminum and/or indium. The semiconductor layer may also contain a dopant. In this embodiment, the semiconductor device 200 includes a light shielding portion 12 having an opening used in the process of the embodiment of the manufacturing method, and it is preferable that at least a part of the opening of the light shielding portion 12 overlaps with the drift region 160 in a plan view. It is to be noted that, as described later, the light shielding portion can be removed during the manufacturing process together with at least a part of the crystalline base, so it goes without saying that it does not have to be included in the semiconductor device.

As one embodiment of the present invention, for example, a method for manufacturing a semiconductor device includes disposing a light-shielding portion to cover a portion of a first surface of a crystalline substrate, epitaxially growing a crystal on the first surface of the crystalline substrate to form a stack, forming a layer on the crystal side of the stack, and selectively removing the layer by photolithography including irradiating light from the second surface side of the crystalline substrate. Figures 5-a to 5-e show schematic diagrams of a method for manufacturing a semiconductor device. As shown in Figure 5-a, a light-shielding portion 12 is disposed to cover a portion of the first surface 11a of the crystalline substrate 11. A crystal 13 is formed by epitaxial growth on the first surface 11a of the crystalline substrate 11 that is not covered by the light-shielding portion 12. The crystal may be a semiconductor layer. In this way, a laminate 14 can be obtained, which includes a crystalline base 11 that transmits light and has at least a first surface 11a and a second surface 11b opposite to the first surface 11a, a light-shielding portion 12 that is arranged to cover a portion of the first surface 11a of the crystalline base 11 and blocks light, and a crystal 13 that is epitaxially grown on the first surface 11a of the crystalline base 11. In this embodiment, the crystalline base 11 has a band gap of 4 eV or more. In one embodiment, the light-shielding portion may have a band gap lower than the band gap of the crystalline base. For example, the band gap of the light-shielding portion may be a band gap of 2.5 eV or less. As shown in FIG. 5-a, the epitaxially grown crystal 13 is grown to cover at least a portion of the light-shielding portion 12, and may be grown to cover the entire light-shielding portion 12. Next, a layer 17 is formed on the crystal 13. The layer 17 may be one layer, two layers, or three or more layers depending on the purpose. In this embodiment, forming the layer 17 includes forming a first layer 15 on the crystal 13 and forming a second layer 16 on the first layer 15. The layer 17 has a first layer 15 arranged on the crystal 13 and the light-shielding portion 12, and a second layer 16 arranged on the first layer 15. In this embodiment, for example, the first layer 15 is a mask layer or an electrode layer, and the second layer 16 is a photosensitive layer, to prepare a laminate 14. Next, as shown in FIG. 5-c, light is irradiated from the second surface 11b side, which is the opposite side of the first surface 11a of the crystalline base 11, that is, the second surface 14b side of the laminate 14, and the layer 17 is selectively removed by photolithography as shown in FIG. 5-d. The photolithography exposes a part of the photosensitive layer 16, and in the non-exposed region other than the exposed region, the photosensitive layer 16 is removed by exposure and development, and the first layer 15 is removed by etching, resulting in the removal of the layer 17. In this case, the photosensitive layer 16 is a negative photosensitive layer, and the region not irradiated with light is removed, leaving the layer 17' (here, the layer 17' includes the first layer 15' and the second layer 16') in the region irradiated with light. Next, as shown in FIG. 5-e, the remaining first layer 16' is removed to obtain a laminated structure having the first layer 15' (here, for example, an electrode layer, etc.) arranged in a desired shape. Note that at least a part of the crystalline base and the light shielding portion 12 can also be removed in the manufacturing method of the semiconductor device. FIG. 7 shows a planar photograph of a laminate formed by arranging a negative photosensitive layer arranged on a crystal as one embodiment of the present invention, and FIG. 8 shows a photograph showing the VIII-VIII cross section of the laminate shown in FIG. 7. In this embodiment, the crystalline base 11 is a sapphire substrate, a light-shielding portion 12 having an opening is disposed on the first surface 11a of the crystalline base, crystals 13 are epitaxially grown from the first surface 11a of the crystalline base, and a negative photoresist is formed at a position that overlaps with the opening of the light-shielding portion 12 in a planar view.

As shown in Fig. 5-a to Fig. 5-e, a negative photosensitive layer has been used in the description. However, as another embodiment of the present invention, Fig. 6-a to Fig. 6-e show schematic diagrams of a method for manufacturing a semiconductor device using a positive photosensitive layer. As shown in Fig. 6-a, a light-shielding portion 12 is arranged to cover a part of the first surface 11a of the crystalline base 11. A crystal 13 is formed by epitaxial growth on the first surface 11a of the crystalline base 11 that is not covered by the light-shielding portion 12. As shown in Fig. 6-a, the epitaxially grown crystal 13 is grown to cover at least a part of the light-shielding portion 12, and may be grown to cover the entire light-shielding portion 12. Next, a layer 17 is formed on the crystal 13. The layer 17 may be a single layer, or may be arranged in two or more layers depending on the purpose. In this embodiment, a laminate 14 including multiple layers is prepared as the layer 17, which is a photosensitive layer 16 arranged on the crystal 13 and the light-shielding portion 12. Next, as shown in FIG. 6-c, light is irradiated from the second surface 11b side of the crystalline base 11, i.e., the second surface 14b side of the laminate 14, which is opposite to the first surface 11a side of the crystalline base 11, i.e., the first surface 14a side of the laminate 14, and as shown in FIG. 6-d, the layer 17 is selectively removed by photolithography. By exposing a part of the layer 17 by the photolithography, the layer 17 can be removed in the exposed area where the exposure was performed. In this case, the photosensitive layer 16 is a positive type photosensitive layer 16 arranged as the layer 17, and the photosensitive layer 16 in the area irradiated with light is removed, leaving the photosensitive layer 16' in the area not irradiated with light. In this embodiment, after forming a thin film on the remaining photosensitive layer 16', the photosensitive layer 16' and the thin film thereon are removed, so that a mask layer can be formed in the area where the photosensitive layer 16 has been removed, and as shown in FIG. 6-e, the same laminate structure as the laminate structure 18 shown in FIG. 5-e can be obtained. By combining the above-mentioned negative and/or positive photosensitive layers, the formation and/or alignment of layers to be placed on the crystal can be easily performed, and can be repeated as necessary. At the stage where a good quality crystal is obtained, the light shielding portion can be used again to form and align the electrode layer. FIG. 9 shows a planar photograph of a laminate formed by placing a positive photosensitive layer on a crystal as one embodiment of the present invention, and FIG. 10 is a photograph showing the X-X cross section of the laminate shown in FIG. 9. In this embodiment, the crystalline base 11 is a sapphire substrate, a light-shielding portion 12 having an opening is disposed on the first surface 11a of the crystalline base, crystals 13 are epitaxially grown from the first surface 11a of the crystalline base, and a positive photoresist is formed at a position that overlaps with the light-shielding portion 12 in a planar view.

As one embodiment of the present invention, Fig. 15-a to Fig. 15-n are partial cross-sectional views showing an example of a process of a method for manufacturing a semiconductor device, and for example, refer to the schematic cross-sectional portion cut along IIb-IIb of the semiconductor device in Fig. 2-b. In this embodiment, the crystalline base 11 is a buffer layer formed by disposing a crystal layer 2 (first crystal layer) of α-Ga ₂ O ₃ on a sapphire substrate 1, and further, a crystal layer ₃ (second crystal layer) of α-Ga 2 O ₃ is disposed on the crystal layer 2 (first crystal layer). As an example of the crystalline base, as shown in Fig. 3-a to Fig. 3-d, the crystalline base may have one layer or two or more layers. In this embodiment, as shown in Fig. 15-a, a light shielding portion 12 is disposed in a stripe shape on the first surface 11a of the crystalline base 11 (here, the first surface 3a of the crystal layer 3 of α-Ga ₂ O ₃ ). The crystal layer 3 may be an oxide semiconductor layer (first oxide semiconductor layer) containing a dopant. Furthermore, a single crystal 13 is epitaxially grown on the first surface 3a of the crystal layer 3 to form an epitaxial film, which is an oxide semiconductor layer (second oxide semiconductor layer) 13. The second oxide semiconductor layer 13 has a first region 13A located on the first surface 3a of the crystal layer 3 and a second region 13B located on the light-shielding portion 12, and the second oxide semiconductor layer 13 includes lateral growth in the second region 13B, so that the dislocation density of the second region 13B is smaller than the dislocation density of the first region 13A. The first surface 13a of the second oxide semiconductor layer 13 is planarized by polishing or the like, and a photosensitive layer 16 is disposed on the first surface 13a of the second oxide semiconductor layer 13 as shown in FIG. 15-b. Next, light is applied from the second surface 11b side, which is the opposite side of the first surface 11a side of the crystalline base 11, that is, the second surface 14b side of the laminate 14. Furthermore, as shown in FIG. 15-c, the photosensitive layer 16 is selectively removed by development in a photolithography process to form a patterned photosensitive layer 16'. In the photolithography, a part of the photosensitive layer 16 is exposed to light, so that the photosensitive layer 16 can be removed in a non-exposed area other than the exposed area where the exposure was performed. In this case, the photosensitive layer 16 is a negative type photosensitive layer, and the area where the light was not irradiated is removed by development. The first surface 13a of the second oxide semiconductor layer 13 is exposed from the photosensitive layer 16'. A recess is provided on the first surface 13a of the second oxide semiconductor layer 13 by etching, and an uneven shape is formed on the first surface 13a of the second oxide semiconductor layer 13, thereby obtaining the laminate of FIG. 15-d. Similarly, it is also possible to form trenches at positions where there is a high dislocation density, for example.

In this embodiment, as shown in Figure 15-e, a third semiconductor layer 60 (here, a p-type semiconductor layer) is formed on the first surface 13a of the second oxide semiconductor layer 13 having the uneven shape. Furthermore, a fourth semiconductor layer 61 (here, an n+ type semiconductor layer) is formed on the third semiconductor layer 60. A fifth semiconductor layer 66 (p+ type semiconductor layer) is formed on the fourth semiconductor layer 61, and the uneven shape of the first surface of the fifth semiconductor layer 61 is flattened by polishing or the like, so that a semiconductor region 60 (p-type semiconductor region) at least partially embedded in the oxide semiconductor layer 13, a semiconductor region 61 (n+ type semiconductor region) at least partially embedded in the semiconductor region 60 (p-type semiconductor region), and the semiconductor region (p+ type semiconductor region) 66 at least partially embedded in the semiconductor region 61 (n+ type semiconductor region) can be formed in a self-aligned manner so as to at least partially overlap with the light-shielding portion 12 in a planar view. As shown in FIG. 15-f, the first surface 13a of the oxide semiconductor layer 13, the first surface of the semiconductor region (p-type semiconductor region) 60 at least partially embedded in the oxide semiconductor layer 13, the first surface of the semiconductor region (n+ type semiconductor region) 61 at least partially embedded in the semiconductor region (p-type semiconductor region) 60, and the semiconductor region (p+ type semiconductor region) 66 at least partially embedded in the semiconductor region (n+ type semiconductor region) 61 can be made flush with each other by polishing or the like. Also, as shown in FIG. 15-f, a gate insulating film 35 is further formed on the first surfaces of the oxide semiconductor layer 13, the semiconductor region (p-type semiconductor region) 60, the semiconductor region (n+ type semiconductor region) 61, and the semiconductor region (p+ type semiconductor region) 66 that are flush with each other.

Next, a photosensitive layer (negative type) 16 is disposed on the gate insulating film 35, and photolithography including backside exposure is performed in the same manner as in FIG. 15-b, to form a gate electrode 36' (gate electrode pattern) disposed on the gate insulating film 35 and having an end overlapping an end of the light shielding portion 12, an end of the semiconductor region (p-type semiconductor region) 60, and an end of the semiconductor region (n+ type semiconductor region) 61 in a plan view. Next, as shown in FIG. 15-i and FIG. 15-j, a first interlayer insulating film 62 (e.g., a SiN film) is formed on the gate insulating film 35 on which the gate electrode 36' is formed, and anisotropic etching is performed to partially expose the gate insulating film 35 between the first interlayer insulating film 62' between the ends of the gate electrode 36', leaving the first interlayer insulating film 62' only at the portion in contact with the end of the gate electrode 36'. Next, a second interlayer insulating film 63 (e.g., _SiO2 film) was formed on the gate insulating film 35, the first interlayer insulating film 62, and the gate electrode 36'. Then, as shown in FIG. 15-k, a photosensitive layer (positive type) 16 was formed on the second interlayer insulating film 63, and as shown in FIG. 15-l and FIG. 15-m, the gate insulating film 35 was partially exposed between the first interlayer insulating film 62' between the ends of the gate electrode 36' and between the second interlayer insulating film 63' by exposure and etching using a normal exposure mask by light irradiation from above. At this time, the interlayer insulating film 62' becomes a mask for the etching, and the etching conditions are selected so that only the second interlayer insulating film 63 is etched, thereby forming a self-aligned contact. Next, as shown in FIG. 15-n, a source electrode 64 was arranged to cover the second interlayer insulating film 63' and to contact the partially exposed gate insulating film 62. Next, at least a portion of the crystalline base 11 (the sapphire substrate 1 and the buffer layer 2) is removed, and a drain electrode 65 is formed on the second surface 3b side of the crystalline layer 3 (here, the first crystalline semiconductor layer), thereby obtaining, for example, the semiconductor device 200 shown in Figures 2-a and 2-b.

(Base)
The substrate is not particularly limited as long as it is a crystalline substrate and transmits light having a wavelength in the range of 10 nm to 500 nm. The substrate may be a crystalline substrate, or the crystalline substrate may have a crystalline substrate and a crystalline layer disposed on the crystalline substrate. In addition, as one embodiment, the crystalline substrate may be a crystalline layer or a semiconductor crystal. The material of the crystalline substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate may be any shape, and is effective for all shapes, for example, a plate shape such as a flat plate or a disk, a fiber shape, a rod shape, a column shape, a prism shape, a tube shape, a spiral shape, a sphere shape, a ring shape, etc., but in one embodiment of the present invention, it is preferable that the substrate is a crystalline substrate 1 as shown in FIG. 3(a). In another embodiment of the present invention, it is also preferable that the crystalline substrate 11 includes a crystalline layer. The crystalline layer may be a semiconductor layer. For example, as shown in FIG. 3(b), the crystalline base 11 may have a crystalline substrate 1 and a crystalline layer (including a semiconductor layer) 2 formed on the crystalline substrate 1. The thickness of the crystalline substrate is not particularly limited in the present invention. In addition, as shown in FIG. 3(c), the crystalline base may include a first crystalline layer 2 arranged on the crystalline substrate 1 and a second crystalline layer 3 arranged on the first crystalline layer 2. That is, the crystalline base 11 may be formed by stacking a plurality of crystalline layers including other layers such as a buffer layer. Furthermore, a semiconductor layer having a different electrical conductivity may be included in the crystalline base, and the crystalline base itself may be a semiconductor layer. Also, FIG. 3(d) shows an embodiment in which the crystalline base 11 includes at least a first crystalline layer and a second crystalline layer arranged on the first crystalline layer. For example, in an embodiment of the present invention, a crystalline substrate 11 may include a first crystal layer 2 (e.g., an n+ type semiconductor layer) and a second crystal layer 3 (e.g., an n- type semiconductor layer) disposed on the first crystal layer 2.

(Crystal Substrate)
When the crystalline substrate includes a crystalline substrate or when the crystalline substrate is a crystalline substrate, the crystalline substrate is not particularly limited as long as it is a substrate containing a crystalline substance as a main component, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. The crystalline substrate may contain at least one material selected from, for example, gallium oxide, aluminum oxide, gallium nitride, aluminum nitride, boron nitride, and diamond. Examples of the crystalline substrate include a gallium oxide substrate, a sapphire substrate, a GaN substrate, an AlN substrate, an AlGaN substrate, and a substrate containing a crystalline substance having a corundum structure at least on the surface. As one embodiment of the present invention, it is preferable that the crystalline substrate contains a metal oxide as a main component. The "main component" refers to a crystalline substrate containing 50% or more of the metal oxide in terms of composition ratio, preferably 70% or more, and more preferably 90% or more. In another embodiment of the present invention, when the crystalline substrate contains a metal nitride as a main component, the "main component" refers to a crystalline substrate containing 50% or more of the metal nitride in terms of composition ratio, preferably 70% or more, and more preferably 90% or more.

As one embodiment of the present invention, the crystalline substrate may be a substrate containing a crystal having a corundum structure as a main component. Examples of the substrate containing a crystal having a corundum structure as a main component include a sapphire substrate and an α-type gallium oxide substrate. Examples of the substrate containing a crystal having a β-gallium structure as a main component include a β-Ga ₂ O ₃ substrate, or a mixed crystal substrate containing β-Ga ₂ O ₃ and Al _{2 O 3.} A suitable example of the mixed crystal substrate containing β-Ga _{2 O 3} and Al ₂ O ₃ is a mixed crystal substrate containing more than 0% and 60% or less of Al 2 O 3 in atomic ratio.

As one embodiment of the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, and an a-plane sapphire substrate. The sapphire substrate may have an off-angle. The off-angle is not particularly limited, but is preferably 0° to 15°. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 200 to 800 μm.

(Light shielding part)
The light-shielding portion is not particularly limited as long as it has a light transmittance of 10% or less for wavelengths in the range of 10 nm to 500 nm. The light-shielding portion may contain a metal, or may contain silicon (Si). As one embodiment of the present invention, a crystal can be epitaxially grown using the light-shielding portion disposed on a crystalline substrate as a mask.

(light source)
The light source for irradiating the laminate with light is not particularly limited as long as it can irradiate light with a wavelength of 10 nm to 500 nm. In an embodiment of the present invention, however, a light source capable of irradiating light with a wavelength of 300 nm to 500 nm, which is a wavelength that efficiently reacts with the photosensitive layer, is preferred.

(crystal)
The crystal is not particularly limited as long as it is a single crystal, and in one embodiment, it may be a single crystal containing a rotation domain or may contain a polycrystal. However, in an embodiment of the present invention, it is preferable that the single crystal is an epitaxial crystal.

(Photosensitive Layer)
In an embodiment of the present invention, the photosensitive layer is not particularly limited as long as it is a layer of a composition whose physical properties change with light of a wavelength of 300 nm to 500 nm, and the photosensitive layer may be formed using a known photosensitive material. The photosensitive layer is given development selectivity by changing the polarity or molecular weight of the polymer through a chemical reaction at the portion exposed to the light. The portion chemically reacted by the light is selectively removed (positive type) or the portion chemically reacted by the light is selectively left (positive type), and a required layer pattern can be formed according to the image of the irradiated light. After the light irradiation, it is also possible to dissolve the exposed portion of the photosensitive layer (in the case of a positive type) and leave the unexposed portion by using, for example, a dilute alkaline aqueous solution as a developer. It is also possible to dissolve the unexposed portion of the photosensitive layer (in the case of a negative type) and leave the exposed portion. In an embodiment of the present invention, the photosensitive layer is preferably a photoresist layer.

It can be seen that the crystal (Ga ₂ O ₃ ) has a light transmittance of 75% or more for the transmission spectrum of the irradiated light, and the light transmittance of the light-shielding part arranged on the base is 5% or less. In an embodiment of the present invention, the crystalline base and the crystal preferably transmit 50% or more of light with a wavelength of 300 nm to 500 nm, and more preferably transmit 70% or more.

In addition, in an embodiment of the present invention, the light-shielding portion is preferably formed periodically on a crystalline substrate, and more preferably is patterned periodically and regularly. The shape of the light-shielding portion is not particularly limited, and examples thereof include a stripe shape, a dot shape, a mesh shape, and a random shape, but in the present invention, a stripe shape is preferred.

The material of the light shielding part is not particularly limited and may be a known material. It may be an insulating material, a conductive material, or a semiconductor material. The material may be amorphous, single crystal, or polycrystalline. In an embodiment of the present invention, the material of the light shielding part is preferably Si. In addition, a Si-containing compound containing SiO ₂ , SiN, or polycrystalline silicon as a main component containing light shielding particles such as carbon black can be arranged as the light shielding part. Examples of other materials of the light shielding part include metals (e.g., precious metals such as platinum, gold, silver, palladium, rhodium, iridium, and ruthenium) having a melting point higher than the crystal growth temperature of the crystalline oxide semiconductor. The content of the material in the light shielding part is preferably 50% or more, more preferably 70% or more, and most preferably 90% or more, in terms of composition ratio.

The means for forming the light-shielding portion may be a known means, for example, a known patterning processing means such as photolithography, electron beam lithography, laser patterning, and subsequent etching (e.g., dry etching or wet etching, etc.). In the present invention, the light-shielding portion is preferably striped or dotted, and more preferably striped. In addition, in the present invention, it is also preferable that the crystal substrate is a PSS (Patterned Sapphire Substrate) substrate. The pattern shape of the PSS substrate is not particularly limited and may be a known pattern shape. Examples of the pattern shape include a cone shape, a bell shape, a dome shape, a hemisphere shape, a square or a triangular pyramid shape, and the like, but in the present invention, the pattern shape is preferably a cone shape. In addition, the pitch interval of the pattern shape is not particularly limited, but in the present invention, it is preferably 5 μm or less, and more preferably 1 μm to 3 μm.

The thickness of the light-shielding portion is not particularly limited, but in an embodiment of the present invention, the thickness of the light-shielding portion can be as thin as 150 nm or less, so that the necessary layers (mask layers, electrode layers, etc.) and/or trenches, etc. can be easily formed repeatedly on the crystal in the appropriate positions and with the necessary sizes without significantly affecting the thickness of the laminated structure.

As one embodiment of the present invention, as shown in the cross-sectional view of Fig. 11, a crystalline base 11 is formed by forming a crystal layer 2 (α-Ga ₂ O ₃ ) on a sapphire substrate 1. Light-shielding parts 12 are periodically arranged on a first surface 11a (here, the crystal layer 2) of the crystalline base 11, and α-Ga ₂ O ₃ is epitaxially grown on the first surface of the crystalline base 11 to form a crystal 13. α-Ga ₂ O ₃ (here, the crystal layer 2 and the crystal 13) is epitaxially grown (here, heteroepitaxially grown) on a sapphire substrate, which is a heterogeneous substrate, and it can be seen that dislocations extend from the first surface of the crystalline base 11 (a portion not covered by the light-shielding parts 12) in a substantially vertical direction (a direction including a vertical direction and ±30° with respect to the vertical direction). Since the extension of dislocations can be predicted from the plane orientation, it is possible to form, for example, a mask layer for ELO growth by deposition using an electron beam to align with the dislocations by photolithography including irradiating light from the second surface 11b of the crystalline base 11. It is also possible to form trenches to align with the positions where the dislocations extend.

As one embodiment of the present invention, as shown in the cross-sectional view of FIG. 12, the light shielding portion 12 is arranged in a stripe shape on the first surface 11a of the crystalline base 11. FIG. 13 shows a photograph in which a part of the photograph shown in FIG. 12 is enlarged, and FIG. 14 shows a further enlargement of the photograph shown in FIG. 13, with reference numbers added. In detail, in this embodiment, the crystalline base 11 is a sapphire substrate 1 on which a crystal layer 2 of α-Ga ₂ O ₃ is arranged. The light shielding portion 12 is arranged in a stripe shape on the first surface 11a of the crystalline base 11 (here, the crystal layer 2 of α-Ga ₂ O ₃ ). Note that the light shielding portion 12 in this embodiment includes two layers, a SiO ₂ layer arranged on the first surface 11a of the crystalline base 11 and a Si layer arranged on the SiO ₂ layer. The light shielding portion 12 has a low band gap of 2.5 eV or less. A crystal 13 was grown on the first surface 11a of the crystalline base 11 on which the light shielding portion 12 was arranged in the stripe shape. As in the embodiment shown in FIG. 11, in this embodiment, α-Ga ₂ O ₃ (here, the crystal layer 2 and the crystal 13) was heteroepitaxially grown on a sapphire substrate, which is a heterogeneous substrate. In this embodiment, a positive photosensitive layer 16 was formed on the first surface 11a of the crystalline base 11 on which the crystal 13 was located, to cover the crystal 13. The crystalline base 11 (here, the sapphire substrate 1 and the crystal layer 2 of α-Ga ₂ O ₃ ) and the crystal 13 have a band gap of 4 eV or more. By irradiating the second surface 11b of the crystalline base 11 with light having a wavelength in the range of 10 nm to 500 nm, the light is incident on the exposed area of the crystalline base 11 adjacent to the light-shielding portion 12, and the light is incident not only perpendicularly but also obliquely at an angle to the second surface 11b of the crystalline base 11, so that the exposed area of the photosensitive layer 16 can be shifted in the direction of the arrow (or in the opposite direction to the arrow) as shown in FIG. 14. By changing the angle at which the light is incident, the exposed area can be freely changed. In this embodiment, the exposed area of the photosensitive layer 16 is developed and removed, and a layer 17 is further formed. In this embodiment, a SiO ₂ layer is formed as the layer 17 by evaporating it with an electron beam. As shown in the photograph of FIG. 11, it is possible to form layer 17 in accordance with the position where dislocations extend, and after the crystal is regrown to reduce dislocations, the layer 17 is a layer that transmits light with a wavelength in the range of 10 nm to 500 nm, so that the light-shielding portion 12 can be used as a mask and photolithography can be used again to align the necessary layers, trenches, etc. In this embodiment, photolithography can be performed repeatedly, so it is particularly suitable for manufacturing a semiconductor device including a heteroepitaxially grown crystal. It is preferable that the light-shielding portion is regularly patterned (here, arranged in a periodic stripe shape) as in this embodiment. The Pt coating on the SiO ₂ and semiconductor film is provided for the purpose of facilitating observation.

In an embodiment of the present invention, as shown in FIG. 3(b), a buffer layer including a stress relaxation layer or the like may be provided as the crystal layer 2 on the crystal substrate as at least a part of the crystalline base, and when a buffer layer is provided, the light-shielding portion may also be formed on the buffer layer. In addition, an uneven shape having a higher light transmittance than the light-shielding portion may be provided on the crystal layer 2. In addition, as one embodiment of the present invention, it is also preferable that the crystal substrate has a buffer layer on a part or all of the surface. The method of forming the buffer layer is not particularly limited and may be a known means. Examples of the forming method include a spray method, a mist CVD method, a HVPE method, a MBE method, a MOCVD method, a sputtering method, and the like. In the present invention, the buffer layer is preferably formed by a mist CVD method, since the quality of the crystal film formed on the buffer layer can be improved, and in particular, crystal defects such as tilt can be suppressed. Below, a preferred embodiment of forming the buffer layer by a mist CVD method will be described in more detail.

The buffer layer can be preferably formed, for example, by atomizing the raw material solution to obtain atomized droplets (atomization process), transporting the obtained atomized droplets to the substrate using a carrier gas (transport process), and thermally reacting the atomized droplets on a part or all of the surface of the substrate and/or base body (buffer layer formation process).

(Atomization process)
In the atomization step, the raw solution is atomized to obtain atomized droplets. The method of atomizing the raw solution is not particularly limited as long as it can atomize the raw solution, and may be a known means, but in the present invention, an atomization method using ultrasonic waves is preferred. The atomized droplets obtained using ultrasonic waves are preferable because they have an initial velocity of zero and float in the air, and are not sprayed like a spray, but are mist that floats in space and can be transported as a gas, so there is no damage due to collision energy, which is very suitable. The droplet size is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 0.1 to 10 μm.

(raw material solution)
The raw material solution is not particularly limited as long as it is a solution that can obtain the buffer layer, crystal, crystal layer, and/or semiconductor layer by mist CVD. Examples of the raw material solution include an aqueous solution of an organometallic complex (e.g., acetylacetonate complex, etc.) of a metal for atomization, or a halide (e.g., fluoride, chloride, bromide, or iodide, etc.). The metal for atomization is not particularly limited, and examples of such a metal for atomization include one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In an embodiment of the present invention, the metal for atomization preferably contains at least gallium, indium, or aluminum, and more preferably contains at least gallium. The content of the metal for atomization in the raw material solution is not particularly limited as long as it does not hinder the object of the present invention, but is preferably 0.001 mol% to 50 mol%, and more preferably 0.01 mol% to 50 mol%.

It is also preferable that the raw material solution contains a dopant. By including a dopant in the raw material solution, the conductivity of the buffer layer, the crystal layer, and/or the semiconductor layer can be easily controlled without ion implantation or the like and without destroying the crystal structure. In the present invention, the dopant is preferably tin, germanium, or silicon, more preferably tin or germanium, and most preferably tin. The concentration of the dopant may usually be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , or the dopant concentration may be a low concentration of, for example, about 1×10 ¹⁷ /cm ³ or less, or the dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more. In an embodiment of the present invention, the dopant concentration is preferably 1×10 ²⁰ /cm ³ or less, and more preferably 5×10 ¹⁹ /cm ³ or less.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol, and most preferably water. More specifically, examples of the water include pure water, ultrapure water, tap water, well water, mineral water, hot spring water, spring water, fresh water, and seawater, and in the present invention, ultrapure water is preferred.

(Transportation process)
In the transport step, the atomized droplets are transported into the film-forming chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include oxygen, ozone, inert gas such as nitrogen or argon, or reducing gas such as hydrogen gas or forming gas. The type of carrier gas may be one type, but may be two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as a second carrier gas. The supply point of the carrier gas may be not only one but also two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L/min, and more preferably 1 to 10 L/min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L/min, and more preferably 0.1 to 1 L/min.

(Process for forming buffer layer, crystal, crystal layer and/or semiconductor layer)
In the process of forming a buffer layer, a crystal, a crystal layer and/or a semiconductor layer (hereinafter also referred to as a crystal layer), the mist droplets are thermally reacted in a film formation chamber to form the crystal layer on the substrate. The thermal reaction may be performed as long as the mist droplets react with heat, and the reaction conditions are not particularly limited as long as the object of the present invention is not hindered. In this process, the thermal reaction is usually performed at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (for example, 1000°C) or lower, more preferably 650°C or lower, and most preferably 400°C to 650°C. In addition, the thermal reaction may be performed under any atmosphere, such as a vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, or an oxygen atmosphere, as long as the object of the present invention is not hindered. In addition, the thermal reaction may be performed under any condition, such as atmospheric pressure, pressurized pressure, or reduced pressure, but in the present invention, it is preferable to perform the thermal reaction under atmospheric pressure. The thickness of the crystal layer can be set by adjusting the formation time.

As described above, a crystal can be formed on a part or all of the surface of the crystal substrate to form a base having a buffer layer, the above-mentioned light-shielding portion can be disposed on the buffer layer of the base, and the crystal can be epitaxially grown using the above-mentioned method. The light-shielding portion disposed on the base forms uneven portions on the base, so that a crystal including lateral growth can be obtained, and by forming a layer on the crystal, defects such as tilt in the crystal can be further reduced, resulting in a crystal film with superior film quality. As described above, the crystal film can also be used as a semiconductor layer of a semiconductor device, and the light-shielding portion can be used to form a pattern such as an electrode on the semiconductor layer.

In addition, the crystal is not particularly limited, but in one embodiment of the present invention, it is preferable that the crystal contains a metal oxide as a main component. Examples of the metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and/or gallium, and most preferably contains at least gallium. In one embodiment of the film formation method of the present invention, the buffer layer may contain a metal oxide as a main component, and the metal oxide contained in the buffer layer may contain gallium and a smaller amount of aluminum than gallium. In one embodiment of the film formation method of the present invention, the buffer layer may contain a superlattice structure. In addition, in the embodiment of the present invention, the "main component" means that the metal oxide is preferably contained in an amount of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the crystal, and may be 100%. Furthermore, the main components of the crystal and the buffer layer may be the same or different, as long as the object of the present invention is not hindered, but in this embodiment of the present invention, it is preferable that they are the same.

In the present invention, a metal-containing raw material gas, an oxygen-containing raw material gas, a reactive gas, and optionally a dopant-containing gas are supplied onto the crystal substrate on which the buffer layer may be provided, and a film is formed under the flow of the reactive gas. In the present invention, it is preferable that the film is formed on a heated substrate. The film formation temperature is not particularly limited as long as it does not impede the object of the present invention, but is preferably 900°C or less. When the crystal has a corundum structure, it is preferably 400°C to 700°C. In addition, the film formation may be performed under any atmosphere, such as a vacuum, a non-vacuum, a reducing gas atmosphere, an inert gas atmosphere, or an oxidizing gas atmosphere, as long as it does not impede the object of the present invention. In addition, the film formation may be performed under any condition, such as normal pressure, atmospheric pressure, pressurized pressure, or reduced pressure, but in the present invention, it is preferable that the film is formed under normal pressure or atmospheric pressure. The film thickness can be set by adjusting the film formation time.

In addition, the crystals in the embodiments of the present invention are formed by at least one method selected from the spray method, the mist CVD method, the HVPE method, the MBE method, the MOCVD method, and the sputtering method.

As an example of the method for forming the crystal, a case where a crystal is formed using the HVPE apparatus shown in FIG. 4-a will be described. For example, a metal source containing a metal is gasified to form a metal-containing source gas, and then the metal-containing source gas and the oxygen-containing source gas are supplied to a crystalline substrate in a reaction chamber, part of which is arranged with a light-shielding portion, to epitaxially grow the crystal. In addition, when epitaxially growing the crystal, the metal-containing source gas, the oxygen-containing source gas, and the reactive gas are supplied to a crystalline substrate in a part of which is arranged with a light-shielding portion, to perform epitaxial growth of the crystal. The HVPE apparatus 50 includes, for example, a reaction chamber 51, a heater 52a for heating the metal source 57, and a heater 52b for heating the substrate fixed to the substrate holder 56. Furthermore, the reaction chamber 51 may include an oxygen-containing source gas supply pipe 55b, a reactive gas supply pipe 54b, and a substrate holder 56 for placing the substrate. The reactive gas supply pipe 54b is provided with a metal-containing source gas supply pipe 53b, forming a double pipe structure. The oxygen-containing source gas supply pipe 55b is connected to the oxygen-containing source gas supply source 55a, and constitutes a flow path of the oxygen-containing source gas so that the oxygen-containing source gas can be supplied from the oxygen-containing source gas supply source 55a to the substrate fixed to the substrate holder 56 through the oxygen-containing source gas supply pipe 55b. The reactive gas supply pipe 54b is connected to the reactive gas supply source 54a, and constitutes a flow path of the reactive gas so that the reactive gas can be supplied from the reactive gas supply source 54a to the substrate fixed to the substrate holder 56 through the reactive gas supply pipe 54b. The metal-containing source gas supply pipe 53b is connected to the halogen-containing source gas supply source 53a, and the halogen-containing source gas is supplied to the metal source to become a metal-containing source gas, which is then supplied to the substrate fixed to the substrate holder 56. The reaction chamber 51 is provided with a gas exhaust section 59 for discharging used gas, and the inner wall of the reaction chamber 51 is fitted with a protective sheet 58 to prevent the reaction product from precipitating.

(Metal Source)
The metal source is not particularly limited as long as it contains a metal and can be gasified, and may be a metal element or a metal compound. Examples of the metal include one or more metals selected from gallium, aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In an embodiment of the present invention, the metal is preferably one or more metals selected from gallium, aluminum, and indium, more preferably gallium, and the metal source is most preferably gallium element. The metal source may be gas, liquid, or solid, but in an embodiment of the present invention, for example, when gallium is used as the metal, the metal source is preferably liquid.

The gasification means is not particularly limited and may be a known means as long as it does not impede the object of the present invention. In an embodiment of the present invention, the gasification means is preferably carried out by halogenating the metal source. The halogenating agent used for the halogenation is not particularly limited and may be a known halogenating agent as long as it can halogenate the metal source. Examples of the halogenating agent include halogen and hydrogen halide. Examples of the halogen include fluorine, chlorine, bromine, and iodine. Examples of the hydrogen halide include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. In the present invention, it is preferable to use hydrogen halide for the halogenation, and more preferably hydrogen chloride. In the present invention, it is preferable to carry out the gasification by supplying a halogen or hydrogen halide as a halogenating agent to the metal source and reacting the metal source with the halogen or hydrogen halide at a temperature equal to or higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited, but in the present invention, for example, when the metal source is gallium and the halogenating agent is HCl, it is preferably 900°C or less. When a crystal containing β-Ga ₂ O ₃ as a main component is epitaxially grown (in this case, homoepitaxial growth), the temperature is preferably higher than 650°C. When a crystal containing α-Ga ₂ O ₃ as a main component is epitaxially grown (in this case, heteroepitaxial growth), the reaction temperature is preferably 650°C or less, and most preferably 400°C to 650°C. When the crystal has a corundum structure and contains metal oxides of gallium and aluminum as main components, the reaction temperature is preferably 500°C to 750°C, depending on the ratio of gallium and aluminum. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal of the metal source. Examples of the metal-containing source gas include halides (fluorides, chlorides, bromides, iodides, etc.) of the metals.

In an embodiment of the present invention, a metal source containing a metal is gasified to obtain a metal-containing source gas, and then the metal-containing source gas and the oxygen-containing source gas are supplied onto the substrate in the reaction chamber. In addition, in the present invention, a reactive gas is supplied onto the substrate. Examples of the oxygen-containing source gas include _O2 gas, _CO2 gas, NO gas, _NO2 gas, _N2O gas, _H2O gas, and _O3 gas. In an embodiment of the present invention, the oxygen-containing source gas is preferably one or more gases selected from the group consisting of _O2 , _H2O , and _N2O , and more preferably contains _O2 . In addition, in one embodiment of the present invention, the oxygen-containing source gas may contain _CO2 . The reactive gas is usually a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. The reactive gas is not particularly limited, but may be, for example, an etching gas. The etching gas is not particularly limited as long as it does not hinder the object of the present invention, and may be a known etching gas. In an embodiment of the present invention, the reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more of these, and preferably contains a hydrogen halide gas, and most preferably contains hydrogen chloride. The metal-containing source gas, the oxygen-containing source gas, or the reactive gas may contain a carrier gas. Examples of the carrier gas include inert gases such as nitrogen and argon. The partial pressure of the metal-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 Pa to 1 kPa, and more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 times to 100 times the partial pressure of the metal-containing source gas, and more preferably 1 time to 20 times. The partial pressure of the reactive gas is not particularly limited, but in the present invention, it is preferably 0.1 to 5 times, and more preferably 0.2 to 3 times, the partial pressure of the metal-containing source gas.

In an embodiment of the present invention, it is also preferable to supply a dopant-containing gas to the substrate. The dopant-containing gas is not particularly limited as long as it contains a dopant. The dopant is also not particularly limited, but in the present invention, the dopant preferably contains one or more elements selected from germanium, silicon, titanium, zirconium, vanadium, niobium and tin, more preferably germanium, silicon or tin, and most preferably germanium. By using the dopant-containing gas in this way, the conductivity of the obtained film can be easily controlled. The dopant-containing gas preferably contains the dopant in the form of a compound (e.g., a halide, an oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but in an embodiment of the present invention, it is preferably 1×10 ⁻⁷ to 0.1 times the partial pressure of the metal-containing source gas, and more preferably 2.5×10 ⁻⁶ to 7.5×10 ⁻² times. In addition, in an embodiment of the present invention, it is preferable to supply the dopant-containing gas onto the substrate together with the reactive gas. The semiconductor may contain, as a main component, for example, silicon carbide (Silicon Carbide), gallium nitride (Gallium Nitride), indium nitride (Gallium Indium), aluminum nitride (Gallium Aluminum) and gallium nitride nitride semiconductors including mixed crystals thereof, or may contain, as a main component, a crystalline metal oxide. Examples of the crystalline metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the crystalline metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and/or gallium, and most preferably is gallium or a mixed crystal thereof. In addition, when the semiconductor film contains a crystalline metal oxide as a main component as one embodiment of the present invention, the "main component" means that the crystalline metal oxide is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the crystal film, and may be 100%. The crystal structure of the crystalline metal oxide is not particularly limited, but as one embodiment of the present invention, it is preferably a corundum structure or a β-gallium structure, more preferably a corundum structure, and most preferably the semiconductor film is a crystal growth film having a corundum structure. In one embodiment of the present invention, when the semiconductor film to be obtained contains the crystalline metal oxide as a main component, the buffer layer, the crystal layer, and/or the semiconductor layer can be formed using a substrate containing a corundum structure as at least a part of the base, thereby obtaining a crystal growth film having a corundum structure. The crystalline metal oxide may be single crystal or polycrystalline, but in the embodiment of the present invention, it is preferably single crystal. In addition, the film thickness of the crystal is not particularly limited, but is preferably 1 μm or more. In the embodiment of the present invention, the crystal is preferably 3 μm or more, more preferably 10 μm or more, and most preferably 20 μm or more.

The crystals obtained by the manufacturing method of the present invention can be suitably used as a semiconductor film, particularly in semiconductor devices, and are particularly useful in power devices. Examples of semiconductor devices formed using the crystal film include transistors such as MIS (Metal-Insulator-semiconductor) and HEMT (High Electron Mobility Transistor), TFTs (Thin Film Transistors), Schottky barrier diodes using semiconductor-metal junctions, PN or PIN diodes combined with other P layers, and light-emitting and receiving elements. In an embodiment of the present invention, the semiconductor film is epitaxially grown on the substrate on which the mask is formed, which has the advantage that it can be used as is in semiconductor devices, etc. In addition, it may be applied to semiconductor devices, etc. after using known means such as peeling it off from the substrate, etc.

The semiconductor device of the present invention described above can be applied to power conversion devices such as inverters and converters to achieve the above-mentioned functions. More specifically, it can be applied as a diode built into an inverter or converter, a switching element such as a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), or a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Figure 16 is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention, and Figure 17 is a circuit diagram of the same control system, which is particularly suitable for installation in an electric vehicle.

As shown in FIG. 16, the control system 500 has a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (drive object) 505, and a drive control unit 506, which are mounted on an electric vehicle. The battery 501 is, for example, a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and can store power by charging at a power supply station or by regenerative energy during deceleration, and can output a DC voltage required for the operation of the electric vehicle's driving system and electrical system. The boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and can boost a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and output it to the driving system such as the motor. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, but by stepping down the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, it can output the voltage to the electrical system, including the power windows, power steering, and on-board electrical equipment.

The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is driven to rotate by the three-phase AC voltage output from the inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission (not shown) or the like.

On the other hand, various sensors (not shown) are used to measure actual values such as the number of rotations of the wheels, torque, and the amount of depression of the accelerator pedal (acceleration amount) from the electric vehicle while it is running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, and uses the input measurement signal to generate a control signal and output it as a feedback signal to the inverter 504, thereby controlling the switching operation by the switching element. As a result, the AC voltage provided by the inverter 504 to the motor 505 is instantly corrected, allowing the driving control of the electric vehicle to be accurately performed, thereby realizing safe and comfortable operation of the electric vehicle. It is also possible to control the output voltage to the inverter 504 by providing a feedback signal from the drive control unit 506 to the boost converter 502.

Figure 17 shows the circuit configuration of Figure 16 excluding the step-down converter 503, that is, the circuit configuration showing only the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used for switching control by being adopted as, for example, a Schottky barrier diode in the step-up converter 502 and the inverter 504. In the step-up converter 502, it is incorporated in a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated in a switching circuit including an IGBT to perform switching control. In addition, the current is stabilized by interposing an inductor (such as a coil) in the output of the battery 501, and the voltage is stabilized by interposing a capacitor (such as an electrolytic capacitor) between the battery 501, the step-up converter 502, and the inverter 504.

As shown by the dotted lines in FIG. 17, the drive control unit 506 includes a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of a non-volatile memory. The signal input to the drive control unit 506 is given to the calculation unit 507, which performs the necessary calculations to generate feedback signals for each semiconductor device. The storage unit 508 also temporarily holds the results of calculations performed by the calculation unit 507, and accumulates physical constants and functions required for drive control in the form of a table and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and storage unit 508 can be configured as known in the art, and their processing capabilities can be selected as desired.

As shown in FIG. 16 and FIG. 17, in the control system 500, a diode or a switching element such as a thyristor, a power transistor, an IGBT, or a MOSFET is used for the switching operation of the boost converter 502, the buck converter 503, and the inverter 504. The switching characteristics are significantly improved by using gallium oxide (Ga ₂ O ₃ ), particularly corundum-type gallium oxide (α-Ga ₂ O ₃ ), as the material for these semiconductor devices. Furthermore, by applying the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the boost converter 502, the buck converter 503, and the inverter 504 can each be expected to achieve the effects of the present invention, and the effects of the present invention can be expected in any one of these, any combination of two or more of them, or in any form including the drive control unit 506.
The above-mentioned control system 500 can be applied not only to the control system of an electric vehicle using the semiconductor device of the present invention, but also to control systems for various purposes such as stepping up/down the power from a DC power source, converting DC to AC, etc. Also, a power source such as a solar cell can be used as the battery.

Figure 18 is a block diagram showing another example of a control system that employs a semiconductor device according to an embodiment of the present invention, and Figure 19 is a circuit diagram of the same control system, which is suitable for installation in infrastructure equipment and home appliances that operate on power from an AC power source.

As shown in FIG. 18, the control system 600 receives power from an external three-phase AC power source (power source) 601, and includes an AC/DC converter 602, an inverter 604, a motor (drive object) 605, and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.) of a power company, and its output is stepped down and supplied as an AC voltage via a substation. It is also installed in a building or a nearby facility in the form of a private generator, for example, and supplied with power via a power cable. The AC/DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage, and converts the AC voltage of 100V or 200V supplied from the three-phase AC power source 601 into a specified DC voltage. Specifically, the voltage is converted into a commonly used desired DC voltage, such as 3.3V, 5V, or 12V. If the drive object is a motor, conversion to 12V is performed. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, in which case the same system configuration can be achieved by using a single-phase input AC/DC converter.

The inverter 604 converts the DC voltage supplied from the AC/DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The form of the motor 604 varies depending on the controlled object, but if the controlled object is a train, it is a three-phase AC motor for driving wheels, if the controlled object is a factory equipment, it is a pump or various power sources, and if the controlled object is a home appliance, it is a three-phase AC motor for driving a compressor, etc., and is driven to rotate by the three-phase AC voltage output from the inverter 604, and transmits the rotational driving force to the driven object (not shown).

For example, in home appliances, there are many objects to be driven that can be supplied with the DC voltage output from the AC/DC converter 302 as is (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.), in which case the inverter 604 is not required in the control system 600, and as shown in FIG. 18, the DC voltage is supplied from the AC/DC converter 602 to the object to be driven. In this case, for example, a personal computer is supplied with a DC voltage of 3.3 V, and an LED lighting device is supplied with a DC voltage of 5 V.

Meanwhile, various sensors (not shown) are used to measure actual values such as the rotation speed and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching operation of the switching element. This allows the AC voltage provided by the inverter 604 to be instantly corrected, allowing accurate operation control of the driven object and achieving stable operation of the driven object. Also, as mentioned above, when the driven object can be driven by a DC voltage, it is also possible to feedback control the AC/DC converter 602 instead of feedback to the inverter.

Figure 19 shows the circuit configuration of Figure 18. As shown in the figure, the semiconductor device of the present invention is used as, for example, a Schottky barrier diode in an AC/DC converter 602 and an inverter 604 to perform switching control. The AC/DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting and rectifying the negative voltage of the input voltage into a positive voltage. In the inverter 604, the switching control is performed by incorporating it into a switching circuit in an IGBT. Note that the current is stabilized by interposing an inductor (such as a coil) between the three-phase AC power supply 601 and the AC/DC converter 602, and the voltage is stabilized by interposing a capacitor (such as an electrolytic capacitor) between the AC/DC converter 602 and the inverter 604.

As shown by the dotted line in FIG. 19, the drive control unit 606 includes a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of a non-volatile memory. The signal input to the drive control unit 606 is given to the calculation unit 607, which performs the necessary calculations to generate feedback signals for each semiconductor device. The storage unit 608 also temporarily holds the results of calculations performed by the calculation unit 607, and accumulates physical constants and functions required for drive control in the form of a table and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and storage unit 608 can be configured as known in the art, and their processing capabilities can be selected as desired.

In this control system 600, as in the control system 500 shown in FIG. 16 and FIG. 17, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC/DC converter 602 and the inverter 604. The switching characteristics are improved by using gallium oxide (Ga ₂ O ₃ ), particularly corundum-type gallium oxide (α-Ga ₂ O ₃ ), as the material for these semiconductor devices. Furthermore, by applying the semiconductor film and semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the effects of the present invention can be expected for each of the AC/DC converter 602 and the inverter 604, and the effects of the present invention can be expected for any one of them, a combination of them, or a form including the drive control unit 606.

Note that while a motor 605 is shown as an example of a driven object in Figures 18 and 19, the driven object is not necessarily limited to mechanically operated objects, and can be many devices that require AC voltage. The control system 600 can be applied as long as it inputs power from an AC power source to drive the driven object, and can be installed for drive control of equipment such as infrastructure equipment (e.g., power equipment in buildings and factories, communication equipment, traffic control equipment, water and sewage treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.).

The following describes examples of the present invention, but the present invention is not limited to these.

Example 1
1. Preparation of the substrate A crystalline substrate can be used as the substrate. In addition, for example, a film forming apparatus such as that shown in 3-1 below can be used to form a crystalline layer on a crystalline substrate to serve as a buffer layer, which can then be used as the substrate.

2. Formation of a light-shielding portion A light-shielding portion of silicon (Si) was formed by plasma-enhanced CVD using liquid tetraethyl orthosilicate so as to cover a part of the first surface of the sapphire substrate, which was the crystalline base obtained in the above 1. The film thickness of the light-shielding portion was 100 nm.

3. Formation of semiconductor film 3-1. Film forming apparatus With reference to FIG. 4-b, a mist CVD apparatus 19 will be described as a film forming apparatus used in this embodiment. The mist CVD apparatus 19 includes a carrier gas supply source 22a for supplying a carrier gas, a flow rate control valve 23a for controlling the flow rate of the carrier gas sent from the carrier gas supply source 22a, a carrier gas (dilution) source 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for controlling the flow rate of the carrier gas (dilution) sent from the carrier gas (dilution) source 22b, a mist generating source 24 in which a raw material solution 24a is contained, a container 25 in which water 25a is contained, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, a film forming chamber 30, a quartz supply pipe 27 connecting the mist generating source 24 to the film forming chamber 30, a hot plate 28 installed in the film forming chamber 30, and an exhaust port 29. An object (crystal substrate and/or crystalline base) 20 on which a film is to be formed is placed on a hot plate 28. Note that, as a film forming apparatus in the embodiment of the present invention, an apparatus capable of epitaxial growth can be used, and as an example of such an apparatus, a mist CVD apparatus shown in FIG.

3-2. Preparation of raw material solution (crystal formation)
Gallium bromide was mixed with ultrapure water to prepare an aqueous solution having a gallium concentration of 0.05 mol/L. Hydrobromic acid was further added to the aqueous solution to a volume ratio of 20% to prepare a raw material solution.

3-3. Preparation for film formation (crystal formation)
The raw material solution 24a obtained in 3-2 above was accommodated in the mist generating source 24. Next, the substrate on which the mask having the inclined surface obtained in 2-3 was placed was placed on the hot plate 28 as the film formation target 20, and the temperature of the substrate was raised to 630°C. Next, the flow rate control valves 23a and 23b were opened to supply carrier gas from the carrier gas source 22a and the carrier gas (dilution) source 22b into the film formation chamber 30, and the atmosphere in the film formation chamber 30 was sufficiently replaced with the carrier gas, and the flow rate of the carrier gas was adjusted to 0.8 L/min and the flow rate of the carrier gas (dilution) was adjusted to 0.2 L/min, respectively. Nitrogen was used as the carrier gas.

3-4. Film formation (crystal formation)
Next, the ultrasonic vibrator 26 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 24a through the water 25a, thereby atomizing the raw material solution 24a to generate raw material fine particles. The raw material fine particles were introduced into the film formation chamber 30 by the carrier gas, and reacted in the film formation chamber 30 at 630°C, causing epitaxial growth of crystals (Ga ₂ O ₃ ) 13 on the crystalline base 20 partially provided with a light-shielding portion obtained in 2. The film formation time was 3.5 hours. The crystals were identified by an X-ray diffraction device to be α-Ga ₂ O ₃ .

3-5. Formation of Layer Next, a layer 17 was formed on the crystal 13. As shown in Figures 7 and 8, a negative photosensitive layer 16 was used to form a stripe shape on the crystal 13 by photolithography. The photosensitive layer 16 was left in a position that did not overlap with the light-shielding portion in a planar view, and could be selectively removed from a position that overlapped with the light-shielding portion in a planar view.

Example 2
In the same manner as in 3-1. to 3-4. described in Example 1, a crystal (Ga ₂ O ₃ ) 13 was epitaxially grown on a crystalline base 20 on which a light-shielding portion was disposed. Next, a layer 17 was formed on the crystal 13. As shown in Figures 9 and 10, a positive-type photosensitive layer 16 was used, and the photosensitive layer 16 was left in a position overlapping with the light-shielding portion in a planar view, and was selectively removed from a position not overlapping with the light-shielding portion in a planar view. It was found that, according to the embodiment of the present invention, the light-shielding portion disposed on the base can be used to repeatedly form and align required layers.

The manufacturing method of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic and electrical equipment parts, optical and electrophotographic related devices, and industrial materials, but is particularly useful for manufacturing semiconductor devices including semiconductor devices with pn junctions and power semiconductors used in power sources, etc.

1 Crystal substrate 2 Crystal layer (first crystal layer)
3. Crystal layer (second crystal layer)
REFERENCE SIGNS LIST 11 crystalline base 11a first surface of crystalline base 11b second surface of crystalline base 12 light-shielding portion 12e end portion of light-shielding portion 13 semiconductor layer 13a first surface of semiconductor layer 13b second surface of semiconductor layer 13A first region 13B second region 14 laminate 14a first surface of laminate 14b second surface of laminate 15 first layer 15' formed pattern 16 photosensitive layer 16' photosensitive layer (after exposure)
17 Layer 17' Layer (after exposure)
DESCRIPTION OF SYMBOLS 18 Laminated structure 19 Mist CVD apparatus 20 Object to be film-formed 21 Sample stage 22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow rate control valve 23b Flow rate control valve 24 Mist source 24a Raw material solution 25 Container 25a Water 26 Ultrasonic vibrator 27 Supply pipe 28 Hot plate 29 Exhaust port 30 Film-formation chamber 33 Second single crystal 34 Third single crystal 35 Gate insulating film 36 Electrode layer 36' Formed pattern (gate electrode)
50 Halide vapor phase epitaxy (HVPE) apparatus 51 Reaction chamber 52a Heater 52b Heater 53a Metal-containing source gas supply source 53b Metal-containing source gas supply pipe 54a Reactive gas supply source 54b Reactive gas supply pipe 55a Oxygen-containing source gas supply source 55b Oxygen-containing source gas supply pipe 56 Substrate holder 57 Metal source 58 Protective sheet 59 Gas exhaust section 60 Semiconductor region (e.g., p-type semiconductor region)
61 Semiconductor region (e.g., n+ type semiconductor region)
62 First interlayer insulating film (SiN film)
63 Second interlayer insulating film ( _SiO2 film)
64 Source electrode 65 Drain electrode 66 Semiconductor region (e.g., p+ type semiconductor region)
100 Semiconductor device
130 Crystal film 154 Gate insulating film 155a Gate electrode 155b Source electrode 155c Source electrode 155d Drain electrode 156 Second semiconductor layer (n+ type semiconductor layer)
156a: first surface of second semiconductor layer; 156b: second surface of second semiconductor layer; 157: first semiconductor layer (n-type semiconductor layer);
157a: first surface of the first semiconductor layer; 157b: second surface of the first semiconductor layer; 158: semiconductor region (p-type semiconductor region);
159 Semiconductor region (n+ type semiconductor region)
160 Drift region 161 Channel region 162 Source region 200 Semiconductor device 500 Control system 501 Battery (power source)
502 Step-up converter 503 Step-down converter 504 Inverter 505 Motor (drive object)
506 Drive control unit 507 Calculation unit 508 Storage unit 600 Control system 601 Three-phase AC power supply (power supply)
602 AC/DC converter 604 Inverter 605 Motor (drive object)
606 Drive control unit 607 Calculation unit 608 Storage unit

Claims (12)

A semiconductor device comprising: at least a semiconductor layer including a drift region and a channel region, the semiconductor layer including a metal oxide including gallium, the channel region having a dislocation density of 5.0 x 106 ^/ cm2 ^or less, the dislocation density of the channel region being smaller than the dislocation density of the drift region. The semiconductor device according to claim 1, wherein the semiconductor layer further has a source region, and the dislocation density of the source region is smaller than the dislocation density of the drift region. The dislocation density of the source region is 5.0×10 ⁶ /cm ² 3. The semiconductor device according to claim 2, wherein: The semiconductor device according to any one of claims 1 to 3 , wherein the semiconductor layer has a corundum structure. 5. The semiconductor device according to claim 4 , wherein a channel length direction of the channel region is the a-axis direction or the m-axis direction. 6. The semiconductor device according to claim 4 , wherein a drift current direction in the drift region is the m-axis direction. The semiconductor device according to any one of claims 1 to 6, further comprising a gate electrode, the gate electrode being adjacent to the channel region directly or via another layer. The semiconductor device according to claim 7, wherein the semiconductor layer has a trench, and at least a portion of the gate electrode is located within the trench. The semiconductor device according to claim 7 or 8, wherein the gate electrode is adjacent to the channel region via a gate insulating film. The semiconductor device according to any one of claims 1 to 9, which is a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET) or an insulated gate bipolar transistor (IGBT). A power conversion device having a semiconductor device according to any one of claims 1 to 10. A control system having a semiconductor device according to any one of claims 1 to 10.