JP7623069B2 - COMMUNICATION SYSTEM, PROCESSING METHOD, AND PROGRAM - Google Patents

Description

The present disclosure relates to a communication system, a processing method, and a program.

Some communication systems use switches to change the connection destination (communication path) to communicate. Patent Document 1 discloses a related technology, a technology related to a bus system that communicates via a bus line.

JP 2003-242048 A

In a communication system that uses a switch to switch between connection destinations (communication paths), the pull-up resistor that holds the communication path at a high potential is generally a fixed value. When using a switch to switch between connection destinations (communication paths), the load capacity differs for each communication path, and the margin for communication errors also differs. As a result, communication errors are more likely to occur depending on the communication path.

Therefore, there is a demand for technology in communication systems that can reduce the occurrence of communication errors even when the communication connection destination (i.e., the communication path) is changed and the load capacity is changed.

One of the objectives of each aspect of the present disclosure is to provide a communication system, processing method, and program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, a communication system includes a first identification means for identifying a resistance value of a pull-up resistor corresponding to a load capacitance in a communication path for bus communication, a second identification means for identifying a resistor from among a plurality of resistors that achieves the resistance value by combining the plurality of resistors, and a configuration means for configuring a resistor of the resistance value using a control signal for combining the resistors identified by the second identification means .

In order to achieve the above object, according to another aspect of the present disclosure, a processing method executed by a communication system includes identifying a resistance value of a pull-up resistor corresponding to a load capacitance in a communication path for bus communication, identifying a resistor from among a plurality of resistors that achieves the resistance value by combining the plurality of resistors, and constructing a resistor of the resistance value using a control signal for combining the identified resistors .

In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer to specify a resistance value of a pull-up resistor corresponding to a load capacitance in a communication path for bus communication, specify a resistor from among a plurality of resistors that achieves the resistance value by combining the plurality of resistors, and configure a resistor with the resistance value using a control signal for combining the specified resistors .

According to each aspect of the present disclosure, the occurrence of communication errors can be reduced even when the communication connection destination (i.e., the communication path) is changed and the load capacity is changed.

FIG. 1 is a diagram illustrating an example of a configuration of a communication system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a table TBL0 according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a table TBL1 according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a processing flow of a communication system according to an embodiment of the present disclosure. FIG. 1 is a diagram illustrating a minimum configuration of a communication system according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a processing flow of a communication system having a minimum configuration according to an embodiment of the present disclosure. FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to at least one embodiment.

Hereinafter, the embodiments will be described in detail with reference to the drawings.
<Embodiment>
Fig. 1 is a diagram showing an example of a configuration of a communication system 1 according to an embodiment of the present disclosure. As shown in Fig. 1, the communication system 1 includes boards 10a, 10b, 10c, and 10d, cables 20a, 20b, 20c, and 20d, and a board 30. The boards 10a, 10b, 10c, and 10d are collectively referred to as boards 10. The cables 20a, 20b, 20c, and 20d are collectively referred to as cables 20.

As shown in FIG. 1, the board 10a includes devices 101a1 and 101a2, a terminal 102a, and a pull-up resistor 103a. Each of the devices 101a1 and 101a2 is a slave device that performs I2C communication with the board 30 via an Inter-Integrated Circuit (I2C) bus. The terminal 102a is connected to the devices 101a1 and 101a2, and the pull-up resistor 103a. The terminal 102a is also connected to the board 30 via the cable 20a. The pull-up resistor 103a holds the potential of the terminal 102a at a high potential. The location of the board 10a is A0.

As shown in FIG. 1, the board 10b includes devices 101b1 and 101b2, a terminal 102b, and a pull-up resistor 103b. Each of the devices 101b1 and 101b2 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102b is connected to the devices 101b1 and 101b2, and the pull-up resistor 103b. The terminal 102b is also connected to the board 30 via the cable 20b. The pull-up resistor 103b holds the potential of the terminal 102b at a high potential. The location of the board 10b is A1.

As shown in FIG. 1, the board 10c includes devices 101c1 and 101c2, a terminal 102c, and a pull-up resistor 103c. Each of the devices 101c1 and 101c2 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102c is connected to the devices 101c1 and 101c2, and the pull-up resistor 103c. The terminal 102c is also connected to the board 30 via the cable 20c. The pull-up resistor 103c holds the potential of the terminal 102c at a high potential. The location of the board 10c is A2.

As shown in FIG. 1, the board 10d includes devices 101d1, 101d2, 101d3, and 101d4, a terminal 102d, and a pull-up resistor 103d. Each of the devices 101d1, 101d2, 101d3, and 101d4 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102d is connected to the devices 101d1, 101d2, 101d3, and 101d4, and the pull-up resistor 103d. The terminal 102d is also connected to the board 30 via the cable 20d. The pull-up resistor 103d holds the potential of the terminal 102d at a high potential. The location of the board 10d is B.

Cable 20a connects board 10a to board 30. Specifically, it connects terminal 102a to terminal 301a of board 30, which will be described later.

Cable 20b connects board 10b to board 30. Specifically, cable 20b connects terminal 102b to terminal 301b of board 30, which will be described later.

Cable 20c connects board 10c to board 30. Specifically, cable 20c connects terminal 102c to terminal 301c of board 30, which will be described later.

Cable 20d connects board 10d to board 30. Specifically, cable 20d connects terminal 102d to terminal 301d of board 30, which will be described later.

1, the board 30 includes terminals 301a, 301b, 301c, 301d, bus selectors 302a, 302b, 302c, bus switches 303a, 303b, an inverting circuit 304, a resistor combiner 305, pull-up resistors 306a1, 306a2, ..., 306a(n-1), 306an, a resistor generation instruction circuit 307, a device configuration unit 308, and a bus master 309. The bus selectors 302a, 302b, 302c are collectively referred to as bus selector 302. The bus switches 303a and 303b are collectively referred to as bus switch 303.

The terminal 301a is connected to a P0 terminal of the bus selector 302b (described later) and a P0 terminal of the bus selector 302c (described later) via a wire A. The terminal 301a is also connected to a terminal 102a of the board 10a via a cable 20a.

The terminal 301b is connected to a P1 terminal of the bus selector 302b (described later) and a P1 terminal of the bus selector 302c (described later) via a wire B. The terminal 301b is also connected to a terminal 102b of the board 10b via a cable 20b.

The terminal 301c is connected to a P2 terminal of the bus selector 302b (described later) and a P2 terminal of the bus selector 302c (described later) via a wiring C. The terminal 301c is also connected to a terminal 102c of the board 10c via a cable 20c.

The terminal 301d is connected to a P3 terminal of the bus selector 302b (described later) and a P3 terminal of the bus selector 302c (described later) via a wiring D. The terminal 301d is also connected to a terminal 102d of the board 10d via a cable 20d.

Each bus selector 302 outputs a signal from one of terminals P0, P1, P2, or P3 depending on the input signal. This selects the bus through which the signal is to be propagated.

Specifically, the bus selector 302a receives a signal from the bus master 309 and outputs a signal from one of the terminals P0, P1, P2, and P3 of the bus selector 302a. The terminal P0 of the bus selector 302a is connected to the bus switches 303a and 303b, the resistor combiner 305, and a bus state determination unit 307a3 (described later) of the resistor generation instruction circuit 307.

More specifically, the bus selector 302b receives a signal from the bus switch 303a and outputs the signal from one of the terminals P0, P1, P2, and P3 of the bus selector 302b. More specifically, the bus selector 302c receives a signal from the bus switch 303b and outputs the signal from one of the terminals P0, P1, P2, and P3 of the bus selector 302c.

Each of the bus switches 303 receives a signal corresponding to a bus enable signal output by a bus switch switching circuit 307a2 (described later) of the resistor generation instruction circuit 307. Each of the bus switches 303 then connects or disconnects the bus in response to the input signal.

Specifically, the bus switch 303a directly inputs the bus enable signal output by the bus switch switching circuit 307a2, and connects or disconnects the bus according to the input bus enable signal. Specifically, the bus switch 303b inputs the bus enable signal output by the bus switch switching circuit 307a2 via the inversion circuit 304, and connects or disconnects the bus according to the input signal. In other words, the bus switches 303a and 303b receive inverted signals according to the bus enable signal. Therefore, when the bus switch 303a connects the bus, the bus switch 303b disconnects the bus. Also, when the bus switch 303b connects the bus, the bus switch 303a disconnects the bus. As a result, when the bus switch 303a connects the bus, the signal propagating through the bus is input to the bus selector 302b, but is not input to the bus selector 302c. Furthermore, when bus switch 303b connects the bus, the signal propagating through the bus is input to bus selector 302c, but is not input to bus selector 302b.

The inversion circuit 304 inverts the input signal and outputs it. As shown in FIG. 1, the inversion circuit 304 is provided between the bus switch switching circuit 307a2 and the bus switch 303b.

As shown in FIG. 1, the resistor combiner 305 includes bus switches 305a1, 305a2, ..., 305a(n-1), and 305an. Bus switches 305a1, 305a2, ..., 305a(n-1), and 305an are collectively referred to as bus switches 305a.

Each of the bus switches 305a receives a select signal output by a select signal generating unit 307a1 (described later) of the resistance generation instruction circuit 307. Each of the bus switches 305a connects or disconnects the bus in response to the input select signal. The select signal is a signal corresponding to the resistance to be generated, and an individual signal corresponding to each of the bus switches 305a is input to each of the bus switches 305a.

The input of each bus switch 305a is connected to terminal P0 of bus selector 302a. In addition, pull-up resistor 306a1 is connected to the output of bus switch 305a1, pull-up resistor 306a2 is connected to the output of bus switch 305a2, pull-up resistor 306a(n-1) is connected to the output of bus switch 305a(n-1), and pull-up resistor 306an is connected to the output of bus switch 305an.

A select signal corresponding to the resistance to be generated is input to each of the bus switches 305a, and each of the bus switches 305a connects or disconnects the bus in response to the select signal, so that the resistance generated by the pull-up resistors 306a1 to 306an becomes a resistance having the desired resistance value.

The pull-up resistors 306a1, 306a2, ..., 306a(n-1), and 306an become resistors having the desired resistance value by being connected or disconnected to each other in response to the connection or disconnection of the bus by each of the bus switches 305a. The pull-up resistors 306a1, 306a2, ..., 306a(n-1), and 306an are collectively referred to as pull-up resistors 306a. Each of the pull-up resistors 306a has a resistance value that is an element of a resistor having a desired resistance value, and the resistance value of each of the pull-up resistors 306a is determined to generate a resistor having the desired resistance value. Note that, as long as a resistor having the desired resistance value can be generated, the resistance values of each of the pull-up resistors 306a may be the same or different.

As shown in FIG. 1, the resistor generation instruction circuit 307 includes a select signal generation unit 307a1 (an example of a first determination means, an example of a second determination means, and an example of a configuration means), a bus switch switching circuit 307a2 (an example of a switching means), a bus state determination unit 307a3 (an example of a determination means), and a memory unit 307a4.

The select signal generating unit 307a1 generates a select signal that causes the resistors generated by the pull-up resistors 306a1 to 306an to have a desired resistance value. The select signal generating unit 307a1 then outputs the generated select signal to the resistor combiner 305.

The bus switch switching circuit 307a2 receives the determination result of whether or not a stall has occurred from the bus state determination unit 307a3. Then, based on the received determination result, the bus switch switching circuit 307a2 generates a bus enable signal for switching between the bus selector 302b and the bus selector 302c. The bus switch switching circuit 307a2 outputs the generated bus enable signal to the bus switch 303a and the inversion circuit 304.

The bus state determination unit 307a3 constantly monitors the state of the bus. In addition, the bus state determination unit 307a3 recognizes whether the bus selector 302b or 302c is selected. The bus state determination unit 307a3 determines whether the bus selector constituting part of the current path (i.e., either one of the bus selectors 302b and 302c) has stalled. If the bus state determination unit 307a3 determines that the bus selector has stalled, it outputs an instruction to the bus switch switching circuit 307a2 to switch to a bus selector other than the bus selector constituting part of the current path (i.e., bus selector 302b or 302c).

The memory unit 307a4 stores various information necessary for the processing performed by the resistance generation instruction circuit 307. For example, the memory unit 307a4 stores a table TBL0 and a table TBL1. The table TBL0 is a table that defines the correspondence between all connection destinations (paths) and the optimal resistance value for each connection destination. FIG. 2 is a diagram showing an example of the table TBL0 in one embodiment of the present disclosure. As shown in FIG. 2, in table TBL0, for example, for connection 1, the connection destinations are stored in the following order: bus master 309 (shown as [Bus Master] in FIG. 2) - bus selector 302a (shown as [Bus SEL (A)] in FIG. 2) - bus switch 303a (shown as [Bus SW (A)] in FIG. 2) - bus selector 302b (shown as [Bus SEL (B)] in FIG. 2) - board 10a (shown as [Board A (location: A0)] in FIG. 2), and 2.4 kΩ is stored as the optimum resistance value associated with the connection destination.

Table TBL1 is a table that defines the correspondence between each connection destination, the optimum resistance value for each connection destination, and the combination of resistors to achieve that optimum resistance value (i.e., the combination of pull-up resistors 306a1 to 306an). FIG. 3 is a diagram showing an example of table TBL1 in one embodiment of the present disclosure. As shown in FIG. 3, table TBL1 contains, for example, connection 1, an optimum resistance value of 2.4 kΩ for connection 1, and a combination of resistors to achieve that resistance value, 4 kΩ + 6 kΩ (4 kΩ and 6 kΩ connected in parallel).

The device configuration unit 308 recognizes all current connection states of the I2C bus in the communication system 1. The device configuration unit 308 then outputs all current connection states of the I2C bus in the communication system 1 to the resistor generation instruction circuit 307. The device configuration unit 308 also instructs the resistor generation instruction circuit 307 to update tables TBL0 and TBL1. The device configuration unit 308 is a control unit that instructs the generation of resistors having optimal pull-up resistance values.

The bus master 309 is an I2C bus master controller. The bus master 309 communicates with the devices 101a1, 101a2, 101b1, 101b2, 101c1, 101c2, 101d1, 101d2, 101d3, and 101d4, which are slave devices provided on each of the boards 10.

The above-mentioned processing performed by each processing unit in the communication system 1 is merely an example and is not limited to the above-mentioned processing. For example, the processing shown in the processing of the communication system 1 described below may be performed.

Next, the processing performed by the communication system 1 according to an embodiment of the present disclosure will be described. FIG. 4 is a diagram showing an example of a processing flow of the communication system 1 according to an embodiment of the present disclosure. Here, the processing performed by the communication system 1 will be described with reference to FIG. 4. Note that the load capacities of the cables 20a, 20b, 20c, and 20d are all different. In other words, the load capacities for the output terminals of the bus selectors 302b and 302c are different. Here, the processing of the communication system 1 will be described using an example in which the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a. Specifically, in the communication system 1, when the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a via the bus selector 302c, the bus selector 302c stalls, and the path is changed to the path of the bus master 309-bus selector 302a-bus switch 303a-bus selector 302b-board 10a (path 1 in the table TBL0 in FIG. 2), which communicates via the bus selector 302b. In this case, the bus selector 302a outputs a signal from the terminal P0 of the bus selector 302a. Also, the bus selector 302b outputs a signal from the terminal P0 of the bus selector 302b. Also, the bus switch switching circuit 307a2 outputs a bus enable signal to the bus switch 303a and the inversion circuit 304, which causes the bus switch 303a to connect the bus and the bus switch 303b to disconnect the bus.

When the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a, the device configuration unit 308 recognizes all the current connection states of the I2C bus in the communication system 1 (step S1). Then, the device configuration unit 308 outputs all the current connection states of the I2C bus in the communication system 1 to the resistor generation instruction circuit 307. The bus state determination unit 307a3 determines whether the bus selector 302c has stalled (step S2). If the bus state determination unit 307a3 determines that the bus selector 302c has not stalled (NO in step S2), it returns to the processing of step S2. Also, if the bus state determination unit 307a3 determines that the bus selector 302c has stalled (YES in step S2), it outputs an instruction to the bus switch switching circuit 307a2 to switch the bus selector (i.e., switch from the bus selector 302c to the bus selector 302b).

The bus switch switching circuit 307a2 receives the determination result of whether or not a stall has occurred from the bus state determination unit 307a3. Then, the bus switch switching circuit 307a2 generates a bus enable signal that switches the bus selector 302c to the bus selector 302b based on the received determination result (step S3). The bus switch switching circuit 307a2 outputs the generated bus enable signal to the bus switch 303a and the inversion circuit 304. As a result, the communication path in the communication system 1 becomes the path of bus master 309-bus selector 302a-bus switch 303a-bus selector 302b-board 10a (path 1 in table TBL0 in FIG. 2).

The device configuration unit 308 recognizes all current connection states of the I2C bus in the communication system 1, including the new path (step S4). The device configuration unit 308 outputs the current connection states, including the new path, to the resistance generation instruction circuit 307.

The select signal generating unit 307a1 generates a select signal that causes the resistance generated by the pull-up resistors 306a1 to 306an to have a desired resistance value based on the current path including the new path output by the device configuration unit 308. For example, the select signal generating unit 307a1 identifies an optimal resistance value corresponding to the current path including the new path in the table TBL0 (step S5). In the example shown here, the select signal generating unit 307a1 identifies the path 1 that matches the current path including the new path in the table TBL0 of FIG. 2, and identifies the resistance value 2.4 kΩ associated with the path 1. The select signal generating unit 307a1 identifies the combination of the pull-up resistors 306a1 to 306an associated with the identified resistance value in the table TBL1 (step S6). In the example shown here, the select signal generation unit 307a1 identifies a combination of resistance values that achieves the resistance value 2.4 kΩ associated with path 1 in table TBL1 of FIG. 2, that is, a combination of pull-up resistors 306a1 to 306an. Then, the select signal generation unit 307a1 generates a select signal that achieves the identified combination of pull-up resistors 306a1 to 306an (step S7).

Each of the bus switches 305a receives the select signal output by the select signal generating unit 307a1. Then, each of the bus switches 305a connects or disconnects the bus in response to the received select signal (step S8).

As described above, a select signal corresponding to the resistance to be generated is input to each of the bus switches 305a, and each of the bus switches 305a connects or disconnects the bus in response to the select signal, so that the resistance generated by the pull-up resistors 306a1 to 306an becomes a resistance having the desired resistance value.

(advantage)
As described above, in the communication system 1, the select signal generating unit 307a1 (an example of a first specifying means) specifies a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication. The select signal generating unit 307a1 (an example of a second specifying means) specifies a resistor that realizes the resistance value from among a plurality of resistors. The select signal generating unit 307a1 (an example of a configuring means) configures the specified resistor with the resistance value. In this way, even if the communication connection destination (i.e., the communication path) is changed and the load capacitance is changed, the occurrence of communication errors can be reduced.

In addition, in the communication system 1, the bus state determination unit 307a3 (an example of a determination means) determines whether or not the bus in the communication path has stalled based on the connection state of the communication path. In response to this, as described above, the select signal generation unit 307a1 configures a resistor with the resistance value. In this way, the communication system 1 can restore the bus by switching the switch bus without performing processes such as resetting the bus or various reconfigurations, thereby shortening the time until restoration.

FIG. 5 is a diagram showing a minimum configuration of a communication system 1 according to an embodiment of the present disclosure. As shown in FIG. 5, the communication system 1 includes a select signal generating unit 307a1 (an example of a first specifying means, an example of a second specifying means, and an example of a configuring means). The select signal generating unit 307a1 specifies a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication. The select signal generating unit 307a1 specifies a resistor that realizes the resistance value from among a plurality of resistors. The select signal generating unit 307a1 causes the specified resistor to configure a resistor with the resistance value.

Figure 6 is a diagram showing an example of a processing flow of a communication system 1 with a minimum configuration according to an embodiment of the present disclosure. Next, the processing of a communication system 1 with a minimum configuration according to an embodiment of the present disclosure will be described with reference to Figure 6.

The select signal generating unit 307a1 identifies the resistance value of a pull-up resistor according to the load capacitance in the communication path for bus communication (step S101). The select signal generating unit 307a1 identifies a resistor that realizes the resistance value from among multiple resistors (step S102). The select signal generating unit 307a1 configures the identified resistor as a resistor with the resistance value (step S103).

A minimum configuration communication system 1 according to an embodiment of the present disclosure has been described above. This communication system 1 can reduce the occurrence of communication errors even when the communication connection destination (i.e., the communication path) is changed and the load capacity is changed.

The order of the processes in the embodiments of the present disclosure may be changed as long as appropriate processing is performed.

Although the embodiments of the present disclosure have been described, the above-mentioned communication system 1, boards 10, 30, and other control devices may have a computer system inside. The above-mentioned process steps are stored in the form of a program on a computer-readable recording medium, and the above-mentioned process is performed by the computer reading and executing this program. Specific examples of computers are shown below.

Figure 7 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in Figure 7, the computer 5 includes a CPU 6, a main memory 7, a storage 8, and an interface 9.

For example, each of the above-mentioned communication system 1, boards 10, 30, and other control devices is implemented in a computer 5. The operation of each of the above-mentioned processing units is stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, expands it in the main memory 7, and executes the above-mentioned processing in accordance with the program. The CPU 6 also secures storage areas in the main memory 7 corresponding to each of the above-mentioned storage units in accordance with the program.

Examples of storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disc Read Only Memory), and semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. In addition, when this program is distributed to computer 5 via a communication line, computer 5 that receives the program may expand the program in main memory 7 and execute the above-mentioned process. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

The program may also realize some of the functions described above. Furthermore, the program may be a file that can realize the functions described above in combination with a program already recorded in the computer system, a so-called differential file (differential program).

Although several embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit and scope of the disclosure.

In addition, some or all of the above embodiments can be described as follows, but are not limited to the following:

(Appendix 1)
a first specifying means for specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
A second specifying means for specifying a resistor that realizes the resistance value from among a plurality of resistors;
A configuration means for configuring a resistor having the resistance value in the resistor specified by the second specification means;
A communication system comprising:

(Appendix 2)
a determination means for determining whether or not a bus in the communication path has stalled based on a connection state in the communication path;
2. The communication system of claim 1, comprising:

(Appendix 3)
a switching means for switching to a spare communication path when the determining means determines that the bus has stalled;
3. The communication system of claim 2, comprising:

(Appendix 4)
The backup communication path is
A bus switch and a bus selector are provided.
4. The communication system of claim 3.

(Appendix 5)
A processing method executed by a communication system, comprising:
Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
Identifying a resistor that realizes the resistance value from among a plurality of resistors;
configuring the identified resistor with a resistance of said resistance value;
A processing method comprising:

(Appendix 6)
On the computer,
Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
Identifying a resistor that realizes the resistance value from among a plurality of resistors;
configuring the identified resistor with a resistance of said resistance value;
A program that executes the following.

1... communication system 5... computer 6... CPU
7... Main memory 8... Storage 9... Interface 10, 30... Board 20... Cable 101... Device 102, 301... Terminal 103, 306... Pull-up resistor 302... Bus selector 303, 305a... Bus switch 304... Inverting circuit 305... Resistor combiner 307... Resistor generation instruction circuit 307a1... Select signal generating unit 307a2... Bus switch switching circuit 307a3... Bus state determination unit 308... Device configuration unit 309... Bus master

Claims (6)

a first specifying means for specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
a second specifying means for specifying , from among the plurality of resistors , a resistor that realizes the resistance value by combining the plurality of resistors;
a configuration means for configuring a resistor having the resistance value by using a control signal for combining the resistors specified by the second specification means;
A communication system comprising: a determination means for determining whether or not a bus in the communication path has stalled based on a connection state in the communication path;
The communication system of claim 1 . a switching means for switching to a spare communication path when the determining means determines that the bus has stalled;
The communication system of claim 2 . The backup communication path is
A bus switch and a bus selector are provided.
The communication system according to claim 3. A processing method executed by a communication system, comprising:
Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
identifying a resistor from among the plurality of resistors that achieves the resistance value by combining the plurality of resistors;
configuring a resistor of said resistance value using a control signal for combining the identified resistors;
A processing method comprising: On the computer,
Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication;
identifying a resistor from among the plurality of resistors that achieves the resistance value by combining the plurality of resistors;
configuring a resistor of said resistance value using a control signal for combining the identified resistors;
A program that executes the following.

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