JP7615598B2 - MEMORY CONTROL DEVICE AND METHOD - Google Patents

Description

The present invention relates to a memory control device and a control method.

When transferring data between central processing units (CPUs) or between a CPU and a device unit, the data may be transferred using a direct memory access (DMA) method. For example, the below-mentioned patent document 1 discloses a DMA circuit that checks whether a descriptor is correct when it is read, and determines whether or not DMA transfer of memory data is possible.

When transferring data using the DMA method, a descriptor describing the data to be transferred and the transfer amount must be prepared in the memory of the sending and/or receiving unit, and this descriptor must be read by the DMAC (DMA Controller). One such descriptor is required each time the DMAC transfers a chunk of data (e.g., one packet).

JP 2006-178795 A

However, when multiple transfer target data are transferred together as a packet, there is a risk that memory copies associated with packet creation will occur frequently in the control unit (e.g., CPU, MPU, etc.) that manages the sending unit. Also, there is a risk that memory copies associated with packet decompression will occur frequently in the control unit that manages the receiving unit.

Figure 6 is a diagram showing the process of packetizing data in a conventional data transfer method using the DMA method. The memory in the diagram is the memory of the unit that transmits the data (i.e., the transmitting unit).

When multiple pieces of data A to E exist at non-consecutive addresses in memory, the control unit of the transmitting unit first rearranges the pieces of data A to E in the order in which they are to be made into tags. For example, as shown in FIG. 6, the control unit copies pieces of data A to E to any area in memory so that they are stored at consecutive addresses (STEP: 1). Next, the CPU generates tag X from the rearranged and stored pieces of data A to E, and copies tag X to any area in memory (STEP: 2). For example, if there is tag Y that also needs to be packetized, tag X is copied to an address consecutive to tag Y. Finally, the tags stored at consecutive addresses (tags X and Y in the example of FIG. 6) are combined to generate a packet (STEP: 3).

In this way, when the storage addresses of the data to be transferred are not consecutive, in order to tag and/or packetize the data, it is necessary to organize the data and copy it back to memory so that it is stored in consecutive addresses in memory. This causes frequent memory copies in the CPU of the sending unit, which creates a problem of imposing a processing load on the CPU of the sending unit.

In addition, the CPU or MPU of the receiving unit that receives the packet or tag must decompress the packet and/or tag and copy the data contained therein to an appropriate area in memory. Specifically, the control unit of the receiving unit must copy each piece of data to an area in memory that can be used by the application of the receiving unit.

One aspect of the present invention has been developed in consideration of the above-mentioned problems, and aims to reduce memory reads and writes using methods other than the DMA method when data transfer is performed using the DMA method.

In order to solve the above problem, a memory control device according to one aspect of the present invention is a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method and transfers multiple transfer target data from the transmitting memory to the receiving memory, and the transmitting memory stores at least the multiple transfer target data and a transmission descriptor table including multiple transmission descriptors. The memory control device includes an identifier receiving unit that receives an identifier that specifies the transmission descriptor table from a transmitting control unit, a transmission descriptor reading unit that reads multiple transmission descriptors included in the transmission descriptor table from the transmission descriptor table specified by the identifier in the order specified by the transmission descriptor table, and a data reading unit that sequentially reads the multiple transfer target data from the transmitting memory according to the descriptions of the multiple transmission descriptors that are sequentially read from the transmitting memory.

In order to solve the above problem, a control method for a memory control device according to one aspect of the present invention is a control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method and transfers multiple transfer target data from the transmitting memory to the receiving memory, in which at least the multiple transfer target data and a transmission descriptor table including multiple transmission descriptors are stored in the transmitting memory, and includes an identifier receiving step of receiving an identifier specifying the transmission descriptor table from a transmitting control unit, a transmission descriptor reading step of reading multiple transmission descriptors included in the transmission descriptor table specified by the identifier in the order specified by the transmission descriptor table, and a data reading step of sequentially reading the multiple transfer target data from the transmitting memory according to the descriptions of the multiple transmission descriptors sequentially read from the transmitting memory.

According to the above configuration, the memory control device reads out the transmission descriptors in the order specified by the transmission descriptor table. The memory control device can then sequentially read out the data to be transferred from the transmission-side memory according to the descriptions in those transmission descriptors. Therefore, the memory control device can read out multiple pieces of data to be transferred simply by receiving an identifier from the transmission-side control unit. In other words, the transmission-side control unit does not need to access the transmission-side memory after initially transmitting an identifier to the memory control device. Therefore, according to the above configuration, it is possible to reduce the frequency with which the transmission-side control unit accesses the transmission-side memory.

Furthermore, the memory control device can read out the multiple data to be transferred separately, even if the multiple data to be transferred are stored in non-consecutive addresses in the transmitting memory. Therefore, the transmitting control unit does not need to consolidate the multiple data to be transferred into one packet or the like in advance. In other words, the transmitting control unit does not need to access the transmitting memory and copy data, etc., in order to generate packets and/or tags. Therefore, according to the above configuration, the transmitting control unit can reduce the frequency of accessing the transmitting memory compared to the case where multiple data to be transferred are consolidated into packets and/or tags, etc. and transferred.

In order to solve the above problem, a memory control device according to one aspect of the present invention is a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method and transfers multiple transfer target data from the transmitting memory to the receiving memory, and the receiving memory stores at least a receiving descriptor table including multiple receiving descriptors. The memory control device includes: an identifier receiving unit that receives an identifier that specifies the receiving descriptor table from a transmitting control unit; a receiving descriptor reading unit that reads multiple receiving descriptors included in the receiving descriptor table from the receiving descriptor table corresponding to the identifier determined by the transmitting control unit in the order specified by the receiving descriptor table; and a data writing unit that sequentially writes the multiple transfer target data read from the transmitting memory to the receiving memory according to the descriptions of the multiple receiving descriptors that are sequentially read from the receiving memory.

In order to solve the above problem, a control method for a memory control device according to one aspect of the present invention is a control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method and transfers multiple transfer target data from the transmitting memory to the receiving memory, in which at least a receiving descriptor table including multiple receiving descriptors is stored in the receiving memory, and includes an identifier receiving step of receiving an identifier that specifies the receiving descriptor table from a transmitting control unit, a receiving descriptor reading step of reading multiple receiving descriptors included in the receiving descriptor table according to the identifier determined by the transmitting control unit in the order specified by the receiving descriptor table, and a data writing step of writing the multiple transfer target data read from the transmitting memory to the receiving memory in sequence according to the descriptions of the multiple receiving descriptors that are sequentially read from the receiving memory.

According to the above configuration, the memory control device reads the receive descriptors in the order specified by the receive descriptor table. The memory control device can then write the data to be transferred to the receive memory sequentially according to the descriptions in those receive descriptors. This allows the receive control unit to write the data to be transferred without having to access the receive memory. Therefore, according to the above configuration, the frequency with which the receive control unit accesses the receive memory can be reduced.

The memory control device also writes multiple pieces of data to be transferred separately. Therefore, for example, specifically, the receiving control unit does not need to decompress the packets and/or tags that bundle multiple pieces of data to be transferred and recopy each piece of data to an appropriate area. Therefore, according to the above configuration, the frequency with which the receiving control unit accesses the receiving memory can be reduced compared to when multiple pieces of data to be transferred are bundled and transferred in packets and/or tags, etc.

The receiving memory may store at least a receiving descriptor table including a plurality of receiving descriptors, and the identifier may be an identifier that specifies the transmitting descriptor table and the receiving descriptor table corresponding to the transmitting descriptor table. The memory control device may further include a receiving descriptor reading unit that reads out the plurality of receiving descriptors included in the receiving descriptor table from the receiving descriptor table specified by the identifier in an order specified by the receiving descriptor table, and a data writing unit that sequentially writes the plurality of transfer target data read from the transmitting memory to the receiving memory according to the descriptions of the plurality of receiving descriptors sequentially read from the receiving memory.

According to the above configuration, the memory control device receives an identifier specifying a transmission descriptor table and a reception descriptor table from the transmission side control unit. This allows the memory control device to read the reception descriptor paired with the transmission descriptor from the reception descriptor table specified by the identifier in the order specified by the reception descriptor table. The memory control device can then write the data to be transferred sequentially to the reception side memory according to the descriptions of those reception descriptors. This allows the reception side control unit to write the data to be transferred without accessing the reception side memory. Therefore, according to the above configuration, it is possible to reduce both the frequency with which the transmission side control unit accesses the transmission side memory and the frequency with which the reception side control unit accesses the reception side memory.

The memory control device also reads out the multiple data items to be transferred separately from the transmitting memory and writes them separately. This eliminates the need for the transmitting control unit to access the transmitting memory to generate packets and/or tags, and the receiving control unit does not need to decompress the packets and/or tags that consolidate the multiple data items to be transferred and recopy each data item to an appropriate area. Therefore, with the above configuration, it is possible to reduce both the frequency with which the transmitting control unit accesses the transmitting memory and the frequency with which the receiving control unit accesses the receiving memory, compared to when multiple data items to be transferred are consolidated into packets and/or tags, etc.

In the memory control device, the transmitting memory may be provided in a first device, and the receiving memory may be provided in a second device that is different from the first device and communicates with the first device using a DMA method.

The above configuration makes it possible to reduce the frequency of accessing memory using methods other than the DMA method when transferring data between a sending memory and a receiving memory that are installed in different devices.

In the memory control device, the sending memory and the receiving memory may be the same. With the above configuration, it is possible to reduce the frequency of accessing the memory by methods other than the DMA method during data transfer within a single memory.

According to one aspect of the present invention, when data is transferred using the DMA method, the frequency of accessing memory using methods other than the DMA method can be reduced.

1 is a block diagram showing an example of a configuration of a main part of a data transfer system according to a first embodiment; 1A and 1B are diagrams illustrating data structures of a tag table and a descriptor table. FIG. 2 illustrates the data structures of a transmit descriptor and a receive descriptor. 4 is a sequence diagram showing a process flow of downstream data transfer in the data transfer system. FIG. FIG. 11 is a block diagram showing an example of a configuration of a main part of a data transfer system according to a second embodiment. FIG. 1 is a diagram illustrating a process for packetizing data in a conventional data transfer method using a DMA (Direct Memory Access) system.

[Embodiment 1]
§1. Application Example In this embodiment, as an example, a data transfer system capable of bidirectional data transfer between a first processing device 110 included in a first unit (first device, second device) 100 and a second processing device 210 included in a second unit (first device, second device) 200 will be described.

In the following description, the transfer of data from the first processing device 110 to the second processing device 210 is sometimes referred to as "downstream transfer." The transfer of data from the second processing device 210 to the first processing device 110 is sometimes referred to as "upstream transfer."

Figure 1 is a block diagram showing an example of the main configuration of a data transfer system 500 according to this embodiment. The data transfer system 500 includes a first unit 100 and a second unit 200. The first unit 100 includes a first processing device 110 and a first memory 120, and the second unit 200 includes a second processing device 210, a second memory 220, and a transfer device 230.

(First unit 100)
The first unit 100 is, for example, a unit that controls industrial equipment. The first unit 100 can be realized by a PLC (Programmable Logic Controller) or the like. The first processing device 110 is a processor in the first unit 100. The first processing device 110 may be, for example, a CPU (Central Processing Unit). The first memory 120 is a volatile storage device in the first unit 100. The first memory 120 may be, for example, a DRAM (Dynamic Random Access Memory).

(Second unit 200)
The second unit 200 is, for example, a unit for complementing or expanding the function of the first unit 100. More specifically, the second unit 200 may be a unit that performs functions such as a data statistical function, a router function, or a database function.

The second processing device 210 is a processor of the second unit 200. The second processing device 210 may be, for example, an MPU (Micro Processing Unit). The second memory 220 is a volatile storage device in the second unit 200. The second memory 220 may be, for example, a DRAM.

The transfer device 230 is a device for implementing data transfer by the DMA method between the first processing device 110 and the second processing device 210. The transfer device 230 can be implemented, for example, by an FPGA (Field-Programmable Gate Array). Note that in this embodiment, the transfer device 230 is provided in the second unit 200, but in the data transfer system 500, the transfer device 230 may be provided in the first unit 100.

In either case, the first processing device 110 and the transfer device 230, and the second processing device 210 and the transfer device 230 are each connected by a bus that complies with the PCIe (Peripheral Component Interconnect Express) standard. This allows the first processing device 110 and the second processing device 210 to communicate via the transfer device 230 using PCIe.

(Transfer of Data)
Although details will be described later, in the data transfer system 500, the transmitting unit transmits a certain identifier to the receiving unit. The identifier is information for specifying the transmitting descriptor table to be used in the transmitting unit, and is also information for specifying the receiving descriptor table to be used in the receiving unit.

The transmit descriptor table contains multiple transmit descriptors. The receive descriptor table contains multiple receive descriptors. Therefore, the above identifier can be said to specify the transmit and receive descriptor groups to be used when transferring multiple pieces of data to be transferred.

The transfer device 230 reads a transmit descriptor from the transmit descriptor table in the transmitting memory. The transfer device 230 also reads a receive descriptor from the receive descriptor table in the receiving memory. The transfer device 230 then transfers the data to be transferred from the transmitting memory to the receiving memory according to the description of one set of transmit and receive descriptors. The transfer device 230 repeats the reading of the transmit and receive descriptors and the transfer of the data to be transferred the number of times equal to the number of sets of transmit and receive descriptors.

According to the process shown in FIG. 4, in the data transfer system 500, the transmitting unit only needs to determine an identifier and transmit the identifier to the transfer device 230. Therefore, even if there are multiple pieces of data to be transferred, there is no need to tag and/or packetize the data to be transferred. Furthermore, there is no need to rearrange data in memory to tag and/or packetize the data to be transferred. Therefore, according to the data transfer system 500, the frequency of memory access by the control unit of the transmitting unit can be reduced.

In addition, in the data transfer system 500, the receiving unit receives the data to be transferred as is, not the packets or tags. Therefore, the process of writing the packets or tags to memory and then decompressing them does not occur. In addition, there is no need to move the decompressed data to be transferred back to the appropriate area in memory. Therefore, according to the data transfer system 500, the frequency of memory access by the control unit of the receiving unit can be reduced.

§2. Configuration example (first unit 100)
Next, a description will be given of the main configuration of the first unit 100 and the second unit 200 shown in Fig. 1. In the example of Fig. 1, the first unit 100 includes a first processing device 110 and a first memory 120. The first unit 100 may also include an input device, an output device, and a non-volatile storage device such as a ROM (Read Only Memory).

(First processing device 110)
The first processing device 110 (transmission side control unit) is a processor that controls the first unit 100 in an integrated manner. The first processing device 110 is realized by, for example, a CPU. The first processing device 110 loads a control program of the first unit 100 stored in a non-volatile storage device (not shown) in a first memory 120. The first processing device 110 then interprets and executes the control program loaded in the first memory 120 to control each component. As a result, as shown in FIG. 1, the first processing device 110 according to this embodiment functions as a first control unit 111, a first firmware (FW) 112, and a first PCIe interface 113.

The first control unit 111 controls the equipment (e.g., industrial equipment) connected to the first unit 100. The first control unit 111 may also periodically communicate with the connected equipment and acquire data from the various equipment to be processed in downstream processes. For example, the data acquired by the first control unit 111 may be transferred to the second unit 200 and then processed by the second unit 200.

The first firmware 112 executes various processes related to the transfer of data between the first unit 100 and the second unit 200. For example, the first firmware 112 determines a tag number for downstream data transfer and notifies the transfer device 230. The tag number will be described in detail later. In addition, before the start of data transfer between the first unit 100 and the second unit 200, the first firmware 112 also performs a process of creating or downloading a tag table, a transmission descriptor table, and a reception descriptor table in advance, and a process of writing the created or downloaded tag table, transmission descriptor table, and reception descriptor table to the first memory 120. In other words, the first firmware 112 prepares a tag table, a transmission descriptor table, and a reception descriptor table in advance and stores them in the first memory 120.

The first PCIe interface 113 is an interface for connecting the first processing device 110 to the transfer device 230 via PCIe through the PCIe bus.

(First memory 120)
The first memory 120 is a volatile storage area (RAM; Random Access Memory). The first memory 120 stores transmission data generated by the first processing device 110, reception data generated by the second processing device 210 to be processed by the first processing device 110, and various programs to be executed by the first processing device 110. The first memory 120 may also be used as a working memory when the first processing device 110 executes various programs. Typically, a dynamic random access memory (DRAM) can be used as the first memory 120.

The first memory 120 stores a transmission tag table, a transmission descriptor table, a reception tag table, a reception descriptor table, and data to be transferred (data 1 to m in FIG. 1).

The transmit descriptor of the first memory 120 is a descriptor that specifies part of the operation for the DMAC 233 (described later) of the transfer device 230 to realize downstream transfer. This enables the first firmware 112 of the first processing device 110 to transmit data to the second firmware 212 of the second processing device 210.

The receive descriptor of the first memory 120 specifies part of the operation for the DMAC 233 to realize the upstream transfer. This enables the first firmware 112 of the first processing device 110 to receive data sent from the second firmware 212 of the second processing device 210.

(Tag table and Descriptor table)
2 is a diagram showing the data structures of a tag table and a descriptor table. Note that the basic data structure of a tag table is the same whether it is a transmission tag table or a reception tag table. Also, the basic data structure of a descriptor table is the same whether it is a transmission descriptor table or a reception descriptor table.

A "tag table" is a list of the first addresses of the storage locations in memory for each of multiple descriptor tables. The transmit tag table is a table used when transmitting data, and is a list of the first addresses of the transmit descriptor tables. The receive tag table is a table used when receiving data, and is a list of the first addresses of the receive descriptor tables.

For convenience, in FIG. 2, the descriptors specified by the first addresses of a certain descriptor table (descriptor table 1) in the tag table are shown in correspondence with the tag table. However, the tag table and the descriptor table corresponding to that tag table may be stored at non-consecutive addresses in memory. Also, the tag table in FIG. 2 specifies the first addresses of the descriptor tables, and need not include the descriptor tables themselves.

In addition, the order of the top addresses of each descriptor table in the tag table of FIG. 2 is not particularly limited. For example, in the example of the same figure, the top addresses of X number of descriptor tables are arranged in a reverse order from descriptor table X to descriptor table 1, but the order may be such that the addresses are specified in order from descriptor table 1 to descriptor table X.

A "descriptor table" is a data table that stores multiple descriptors in the order in which they are used for data transfer. In the example of FIG. 2, the descriptor table includes descriptor 1 to descriptor i. A transmit descriptor table is a data table that stores multiple transmit descriptors in the order in which they are used for data transfer. A receive descriptor table is a data table that stores multiple receive descriptors in the order in which they are used for data transfer. For example, if the descriptor in FIG. 2 is a transmit descriptor, the transmit descriptors are used in order starting from descriptor 1 when reading data from the transmitting memory. Also, for example, if the descriptor in FIG. 2 is a receive descriptor, the receive descriptors are used in order starting from descriptor 1 when writing data to the receiving memory.

(Transmit Descriptor and Receive Descriptor)
3 is a diagram showing the data structures of a transmit descriptor and a receive descriptor. As shown in FIG. 2, the transmit descriptor includes the following (1) to (3).

(1) The storage address in memory of the data to be sent. (2) The size of the data to be sent. (3) Other data. Of these, the "other data" shown in (3) includes, for example, a transfer completion flag that is set when the transfer is completed successfully.

The receive descriptor contains the following (4) and (5), as shown in Figure 2.

(4) The destination address in memory of the data to be received. (5) Other data. The "other data" shown in (5) includes, for example, a transfer completion flag that is set when the transfer is completed successfully.

(Second unit 200)
In the example of FIG. 1, the second unit 200 includes a second processing device 210 , a second memory 220 , and a forwarding device 230 .

(Second Processing Device 210)
The second processing device (transmission side control unit) 210 controls the second unit 200 in an integrated manner. The second processing device 210 is realized by, for example, an MPU. The second processing device 210 loads a control program for the second unit 200 stored in a non-volatile storage device (not shown) in a second memory 220. The second processing device 210 then interprets and executes the control program loaded in the second memory 220 to control each component. As a result, as shown in FIG. 1, the second processing device 210 according to this embodiment functions as a second control unit 211, a second firmware 212, and a second PCIe interface 213.

The second control unit 211 executes processes related to the various functions performed by the second unit 200 itself. For example, the second control unit 211 may aggregate data obtained from the first unit 100.

The second firmware 212 executes various processes related to the transfer of data between the second unit 200 and the first unit 100. For example, the second firmware 212 determines the tag number for the upstream data transfer and notifies the transfer device 230. In addition, the second firmware 212 also performs a process of creating or downloading a tag table, a transmission descriptor table, and a reception descriptor table in advance before starting the data transfer between the second unit 200 and the first unit 100, and a process of writing the created or downloaded transmission descriptor table and reception descriptor table to the second memory 220. In other words, the second firmware 212 prepares the tag table, the transmission descriptor table, and the reception descriptor table in advance and stores them in the second memory 220.

The second PCIe interface 213 is an interface for connecting the second processing device 210 to the transfer device 230 via PCIe via the PCIe bus.

(Second memory 220)
The second memory 220 is a volatile storage area (RAM). The second memory 220 stores transmission data generated by the second processing device 210, reception data generated by the first processing device 110 to be processed by the second processing device 210, and various programs to be executed by the second processing device 210. The second memory 220 may also be used as a working memory when the second processing device 210 executes various programs. Typically, a DRAM or the like can be used as the second memory 220.

The second memory 220, like the first memory 120, stores a transmit tag table, a transmit descriptor table, a receive tag table, a receive descriptor table, and data to be transferred. The data structures of the tag table and the descriptor table are the same as the data of the same names described in the first memory 120.

The transmission descriptor of the second memory 220 is a descriptor that specifies part of the operation for the DMAC 233 of the transfer device 230 to realize an upstream transfer. This enables the second firmware 212 of the second processing device 210 to transmit data to the first firmware 112 of the first processing device 110.

The receive descriptor of the second memory 220 defines part of the operation for the DMAC 233 to realize downstream transfer. This enables the second firmware 212 of the second memory 220 to receive data transmitted from the first firmware 112 of the first processing device 110.

(Transfer device 230)
The transfer device (memory control device) 230 is a device for communicating with the first processing device 110 and the second processing device 210 via PCIe. The transfer device 230 controls downstream transfer between the first processing device 110 and the second processing device 210, and upstream transfer as necessary.

To realize downstream transfer, the transfer device 230 is equipped with at least a DMAC (Direct Memory Access Controller) 233, a downstream transmit descriptor controller (identifier receiver, transmit descriptor reader) 235, and a downstream receive descriptor controller (receive descriptor reader) 234.

The DMAC 233 (data reading unit, data writing unit) controls the data transfer from the first memory 120 of the first processing unit 110 to the second memory 220 of the second processing unit 210. The DMAC 233 reads the data to be transferred sequentially according to the description in the transmit descriptor. The DMAC 233 writes the read data to the second memory 220 according to the description in the receive descriptor.

The downstream transmit descriptor controller 235 receives a tag number from the first firmware 112 that specifies the transmit and receive descriptor tables to be used for transferring the data to be transferred.

Here, the "tag number" is an identifier that specifies the descriptor table within the tag table. Because the descriptor table contains descriptors, the "tag number" is essentially an identifier that specifies the group of descriptors to be used when transferring the data to be transferred. In other words, the "tag number" in the transmitting unit is an identifier that specifies the group of transmit descriptors to be used when receiving data. The "tag number" in the receiving unit is an identifier that specifies the group of receive descriptors to be used when receiving data.

The format of the tag number is not particularly limited. For example, the tag number may be an identifier that includes at least one of a number, a character string, a code, etc. In this embodiment, the tag number is a value that specifies a specific address in memory.

The downstream transmit descriptor controller 235 identifies the transmit descriptor table specified by the tag number from among the transmit descriptor tables stored in the first memory 120. The downstream transmit descriptor controller 235 references the identified transmit descriptor table and reads out the transmit descriptors in the order stored in the table (i.e., specified in the table). This transmit descriptor is the transmit descriptor for the address in the first memory 120 where the data to be transferred (i.e., the data to be read from the first memory 120) is stored.

The downstream receive descriptor controller 234 identifies the receive descriptor table specified by the tag number from among the receive descriptor tables stored in the second memory 220. The downstream receive descriptor controller 234 references the identified receive descriptor table and reads the receive descriptors in the order stored in the table (i.e., specified in the table). This receive descriptor is the receive descriptor related to the address in the second memory 220 where the data to be transferred (i.e., the data to be written to the second memory 220) should be stored.

To realize upstream transfer, the transfer device 230 may further include an upstream transmit descriptor controller (identifier receiver, transmit descriptor reader) 237 and an upstream receive descriptor controller (receive descriptor reader) 236.

When implementing an upstream transfer, the DMAC (data reading unit, data writing unit) 233 controls the data transfer from the second memory 220 of the second processing device 210 to the first memory 120 of the first processing device 110. The DMAC 233 reads the data to be transferred sequentially according to the description in the transmit descriptor. The DMAC 233 writes the read data to the first memory 120 according to the description in the receive descriptor.

The upstream transmit descriptor controller 237 receives a tag number from the second firmware 212 that specifies the transmit and receive descriptor tables to be used for transferring the data to be transferred.

The upstream transmit descriptor controller 237 identifies the transmit descriptor table specified by the tag number from among the transmit descriptor tables stored in the second memory 220. The upstream transmit descriptor controller 237 refers to the identified transmit descriptor table and reads out the transmit descriptors in the order stored in the table (i.e., specified in the table). This transmit descriptor is the transmit descriptor for the address in the second memory 220 where the data to be transferred (i.e., the data to be read from the second memory 220) is stored.

The upstream receive descriptor controller 236 identifies the receive descriptor table specified by the tag number from among the receive descriptor tables stored in the first memory 120. The upstream receive descriptor controller 236 references the identified receive descriptor table and reads the receive descriptors in the order stored in the table (i.e., specified in the table). This receive descriptor is the receive descriptor related to the address in the first memory 120 where the data to be transferred (i.e., the data to be written to the first memory 120) should be stored.

The first PCIe interface 231 is an interface for connecting the transfer device 230 to the first processing device 110 via PCIe through the PCIe bus.

The second PCIe interface 232 is an interface for connecting the transfer device 230 to the second memory 220 via PCIe via the PCIe bus.

§3. Processing flow Figure 4 is a sequence diagram showing the flow of downstream data transfer in the data transfer system 500. Note that, before the series of processes shown in Figure 4, the first firmware 112 of the first processing device 110 prepares at least a transmission tag table and a transmission descriptor table in the first memory 120 as an initial process. Also, the second firmware 212 of the second processing device 210 prepares at least a reception tag table and a reception descriptor table in the second memory 220. Also, it is assumed that a plurality of transfer target data are stored in the first memory 120.

When preparation of the various tag tables and descriptor tables is complete, the first firmware 112 of the first processing device 110 transmits the tag number to the downstream transmission descriptor controller 235 of the transfer device 230. The downstream transmission descriptor controller 235 receives the tag number (S100, identifier reception step) and outputs the tag number to the downstream reception descriptor controller 234 (S101). The downstream reception descriptor controller 234 accepts the input tag number (S201).

When the tag number notification of S101 to S201 is completed, the downstream transmission descriptor controller 235 identifies the transmission descriptor table (transmission DescT) corresponding to the tag number from the transmission tag table in the first memory 120 (S102). The downstream transmission descriptor controller 235 reads the transmission descriptor (transmission Desc) stored in the first position (i.e., the beginning) of the identified transmission descriptor table from the first memory 120 (S103, transmission descriptor reading step).

After receiving the tag number (S201), the downstream receive descriptor controller 234 identifies the receive descriptor table (receive DescT) corresponding to the tag number from the receive tag table in the second memory 220 (S202). The downstream receive descriptor controller 234 reads the receive descriptor (receive Desc) stored in the first position (i.e., the beginning) of the identified receive descriptor table from the second memory 220 (S203, receive descriptor reading step).

The DMAC 233 reads data (i.e., the first data) from the first memory 120 according to the information described in the transmit descriptor read by the downstream transmit descriptor controller 235 (S301, data read step). The DMAC 233 writes the read data to the second memory 220 according to the information described in the receive descriptor read by the downstream receive descriptor controller 234 (S302, data write step).

After the writing of the first data to the second memory 220 (S302) is completed, the downstream transmit descriptor controller 235 then reads the next stored transmit descriptor (i.e., the second transmit descriptor) from the transmit descriptor table identified in S102 (S104, transmit descriptor read step). After the processing of S302 is completed, the downstream receive descriptor controller 234 also reads the next stored receive descriptor (i.e., the second receive descriptor) from the receive descriptor table identified in S202 (S204, receive descriptor read step).

The DMAC 233 executes the same process as S301 to S302 based on the second transmit descriptor and the second receive descriptor. That is, the DMAC 233 reads the second data according to the information written in the second transmit descriptor (S303, data read step), and writes the second data to the second memory 220 based on the second receive descriptor (S304, data write step).

The downstream transmit descriptor controller 235, downstream receive descriptor controller 234, and DMAC 233 repeat the same process until all data to be transferred has been transferred. That is, the downstream transmit descriptor controller 235 reads the next stored transmit descriptor (the m-th transmit descriptor) from the transmit descriptor table identified in S102 (S105, transmit descriptor read step). The downstream receive descriptor controller 234 reads the next stored receive descriptor (i.e., the m-th receive descriptor) from the receive descriptor table identified in S202 (S205, receive descriptor read step).

The DMAC 233 executes the same processing as S301 to S302 based on the m-th transmit descriptor and the m-th receive descriptor. That is, the DMAC 233 reads the m-th data according to the information written in the m-th transmit descriptor (S305, data read step), and writes the m-th data to the second memory 220 based on the m-th receive descriptor (S306, data write step).

According to the process shown in FIG. 4, the transfer device 230 can reduce the frequency of access from the first processing device 110 to the first memory 120 in data transfer between the first memory 120 and the second memory 220 mounted on different devices. Also, according to the process shown in FIG. 4, the transfer device 230 can reduce the frequency of access from the second processing device 210 to the second memory 220 in data transfer between the first memory 120 and the second memory 220 mounted on different devices. In other words, the transfer device 230 can reduce the frequency of access to the memory by a method other than the DMA method.

According to the process shown in FIG. 4, the transfer device 230 reads out the transmission descriptors in the order specified by the transmission descriptor table. The transfer device 230 can then sequentially read out the data to be transferred from the first memory 120 according to the descriptions in those transmission descriptors. Therefore, the transfer device 230 can read out multiple pieces of data to be transferred simply by receiving a tag number from the first processing device 110. In other words, after the first processing device 110 transmits the tag number to the transfer device 230 for the first time, the first processing device 110 does not need to access the first memory 120. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced.

In addition, the transfer device 230 can read out the multiple data to be transferred separately, even if the multiple data to be transferred are stored in non-consecutive addresses in the first memory 120. Therefore, the first processing device 110 does not need to consolidate the multiple data to be transferred into one packet or the like in advance. In other words, the first processing device 110 does not need to access the first memory 120 to copy data, etc., in order to generate packets and/or tags. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced compared to the case in which multiple data to be transferred are consolidated into packets and/or tags, etc. and transferred.

According to the process shown in FIG. 4, the transfer device 230 reads the receive descriptors in the order specified by the receive descriptor table. The transfer device 230 can then write the data to be transferred to the second memory 220 sequentially according to the descriptions in those receive descriptors. This allows the second processing device 210 to write the data to be transferred without accessing the second memory 220. Therefore, according to the process shown in FIG. 4, the frequency with which the second processing device 210 accesses the second memory 220 can be reduced.

The transfer device 230 also writes multiple pieces of data to be transferred separately. Therefore, for example, specifically, the second processing device 210 does not need to decompress the packets and/or tags that consolidate multiple pieces of data to be transferred and recopy each piece of data to an appropriate area. Therefore, according to the process shown in FIG. 4, the frequency with which the second processing device 210 accesses the second memory 220 can be reduced compared to the case in which multiple pieces of data to be transferred are transferred together in packets and/or tags, etc.

The flow of upstream data transfer in the data transfer system 500 is the same as that of downstream data transfer, except for the subject of various processes. Specifically, in the case of upstream data transfer, the control device and memory on the transmitting side change to the second processing device 210 and the second memory 220, and the control device on the receiving side changes to the first processing device 110 and the first memory 120. In addition, in the case of upstream data transfer, the processes performed by the downstream transmission descriptor controller 235 and the downstream reception descriptor controller 234 can be executed by the upstream transmission descriptor controller 237 and the upstream reception descriptor controller 236, respectively. In addition, the DMAC 233 can write the data read from the second memory 220 to the first memory 120.

[Embodiment 2]
In the present invention, the sending memory and the receiving memory may be the same. In other words, the data transfer system according to the present invention may be applied not only to data transfer between two independent devices, but also to data transfer within a certain memory of a certain device (i.e., reading and writing data within a certain memory).

The second embodiment of the present invention will be described below. For ease of explanation, the same reference numerals are used for components having the same functions as those described in the previous embodiment, and their explanation will not be repeated. In this embodiment, as an example, data transfer within the device of the third unit 300 will be described.

Figure 5 is a block diagram showing an example of the main configuration of a data transfer system 600 according to this embodiment. The third unit 300 of the data transfer system 600 includes a first processing device (transmission side control unit) 110, a first memory 120, and a transfer device (memory control device) 330.

The transfer device 330 includes a DMAC (data reading unit, data writing unit) 331, a receive descriptor controller (receive descriptor reading unit) 332, a transmit descriptor controller (identifier receiving unit, transmit descriptor reading unit) 333, and a PCIe interface 334. The transmit descriptor controller 333 performs the same processing as the downstream transmit descriptor controller 235 and the upstream transmit descriptor controller 237. The receive descriptor controller 332 performs the same processing as the downstream receive descriptor controller 234 and the upstream receive descriptor controller 236.

The basic flow of upstream and downstream data transfer in the data transfer system 600 is the same as the flow of upstream and downstream data transfer in the data transfer system 500 according to the first embodiment. Specifically, in this embodiment, both the sending memory and the receiving memory are the first memory 120. That is, where information was read and written to the second memory 220 in the process shown in FIG. 4, similar information can be read and written to the first memory 120. Also, in this embodiment, the first firmware 112 of the first processing device 110 determines a tag number that specifies the sending descriptor table and the receiving descriptor table used to transfer the data to be transferred, and transmits it to the downstream sending descriptor controller 333.

The process performed by the downstream transmit descriptor controller 235 in FIG. 4 is now performed by the transmit descriptor controller 333. The process performed by the downstream receive descriptor controller 234 in FIG. 4 is now performed by the receive descriptor controller 332. The process performed by the DMAC 233 in FIG. 4 is now performed by the DMAC 331.

With the above configuration, when data is transferred using the DMA method, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced.

[Modifications]
Although the embodiment of the present invention has been described in detail above, the above description is merely an example of the present invention in every respect. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible. In the following, the same reference numerals are used for the same components as in the above embodiment, and the description of the same points as in the above embodiment is omitted as appropriate. The following modifications can be combined as appropriate.

The data transfer system 500 according to the first embodiment may include one first unit 100 and multiple second units 200. In this case, the first unit 100 may include one transfer device 230, or each of the multiple second units 200 may include one transfer device 230. This allows each of the multiple second units 200 to transmit and receive data to and from the first unit 100 via the transfer device 230.

[Software implementation example]
The control blocks of the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be realized by software.

In the latter case, the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 are provided with a computer that executes instructions of a program, which is software that realizes each function. This computer is provided with, for example, one or more processors, and a computer-readable recording medium that stores the above program. In the computer, the processor reads the above program from the recording medium and executes it, thereby achieving the object of the present invention. The processor can be, for example, a CPU (Central Processing Unit). The recording medium can be a "non-transient tangible medium", such as a ROM (Read Only Memory), as well as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, etc. In addition, a RAM (Random Access Memory) that expands the above program may also be provided. The above program may be supplied to the computer via any transmission medium (such as a communication network or a broadcast wave) that can transmit the program. Note that one aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in different embodiments.

100 First unit (first device, second device)
110 First processing device (transmission side control unit)
111 First control unit 112 First firmware 113, 213, 231, 232, 334 Interface 120 First memory (transmitting side memory, receiving side memory)
200 Second unit (first device, second device)
210 Second processing device (transmission side control unit)
211: Second control unit 212: Second firmware 220: Second memory (sending side memory, receiving side memory)
230, 330 Transfer device (memory control device)
233, 331 DMAC (data read unit, data write unit)
234 Downstream receive descriptor controller 235 Downstream transmit descriptor controller (identifier receiver, transmit descriptor reader)
236 Upstream receive descriptor controller (receive descriptor reader)
237 Upstream transmission descriptor controller (identifier receiver, transmission descriptor reader)
332 Reception Descriptor Controller (Reception Descriptor Reader)
333 Transmission Descriptor Controller (Identifier Receiving Unit, Transmission Descriptor Reading Unit)
300 Third unit 500, 600 Data transfer system

Claims (7)

A memory control device that accesses a transmitting side memory and a receiving side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmitting side memory to the receiving side memory,
the transmitting side memory stores at least the plurality of transfer target data and a transmission descriptor table including a plurality of transmission descriptors;
an identifier receiving unit that receives an identifier designating one of the plurality of transmission descriptor tables from a transmission side control unit;
a transmission descriptor reading unit that reads out a plurality of transmission descriptors included in the transmission descriptor table specified by the identifier in an order specified by the transmission descriptor table;
a data reading unit that sequentially reads the plurality of transfer target data from the transmission side memory in accordance with descriptions of the plurality of transmission descriptors that are sequentially read from the transmission side memory. A memory control device that accesses a transmitting side memory and a receiving side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmitting side memory to the receiving side memory,
the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors;
an identifier receiving unit that receives an identifier designating the reception descriptor table from a transmission side control unit;
a reception descriptor reading unit that reads out a plurality of reception descriptors included in the reception descriptor table corresponding to the identifier determined by the transmission side control unit in an order specified by the reception descriptor table;
a data writing unit that sequentially writes the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors that are sequentially read from the receiving side memory. the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors;
the identifier is an identifier for specifying the transmission descriptor table and the reception descriptor table corresponding to the transmission descriptor table,
a reception descriptor reading unit that reads, from the reception descriptor table designated by the identifier, a plurality of reception descriptors included in the reception descriptor table in an order designated by the reception descriptor table;
2. The memory control device according to claim 1, further comprising: a data writing unit that sequentially writes the plurality of transfer target data read from the transmitting side memory to the receiving side memory in accordance with descriptions of the plurality of receiving descriptors that are sequentially read from the receiving side memory. the sending memory is provided in a first device;
4. The memory control device according to claim 3, wherein the receiving memory is provided in a second device which is a device different from the first device and which communicates with the first device by a DMA method. The memory control device according to claim 3, characterized in that the sending memory and the receiving memory are the same. 1. A control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method to transfer a plurality of transfer target data from the transmitting memory to the receiving memory, comprising the steps of:
the transmitting side memory stores at least the plurality of transfer target data and a transmission descriptor table including a plurality of transmission descriptors;
an identifier receiving step of receiving an identifier designating one of the plurality of transmission descriptor tables from a transmission side control unit;
a transmission descriptor reading step of reading, from the transmission descriptor table designated by the identifier, a plurality of transmission descriptors included in the transmission descriptor table in an order designated by the transmission descriptor table;
a data reading step of sequentially reading the plurality of transfer target data from the transmitting side memory in accordance with descriptions of the plurality of transmission descriptors sequentially read from the transmitting side memory. 1. A control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method to transfer a plurality of transfer target data from the transmitting memory to the receiving memory, comprising the steps of:
the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors;
an identifier receiving step of receiving an identifier designating the reception descriptor table from a transmission side control unit;
a reception descriptor reading step of reading, from the reception descriptor table corresponding to the identifier determined by a transmission side control unit, a plurality of reception descriptors included in the reception descriptor table in an order specified by the reception descriptor table;
a data writing step of sequentially writing the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors sequentially read from the receiving side memory.

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