JP7613273B2 - Integrated circuits, power supply circuits - Google Patents

Description

The present invention relates to an integrated circuit and a power supply circuit.

A boost chopper type boost circuit generates a DC voltage of a predetermined voltage level from an AC voltage (for example, Patent Documents 1 to 4).

JP 2010-213423 A JP 2010-246204 A JP 2012-010574 A JP 2020-127282 A

When the effective value of the AC voltage is low, a boost chopper type boost circuit needs to increase the boost ratio to generate a DC voltage of a specified voltage level. However, increasing the boost ratio leads to increased power loss due to factors such as increased transistor conduction loss.

The present invention was made in consideration of the above-mentioned problems in the conventional technology, and its purpose is to provide an integrated circuit that can suppress power loss in a power supply circuit.

The integrated circuit according to the present invention, which solves the above-mentioned problems, includes an inductor to which a rectified voltage obtained by rectifying an AC voltage is applied, and a transistor that controls the inductor current flowing through the inductor, and is an integrated circuit that controls the switching of the transistor in a power supply circuit that generates an output voltage by boosting the rectified voltage. The integrated circuit includes a first error voltage generating circuit that outputs a first voltage corresponding to the duty ratio of a drive signal for switching the transistor and a first error voltage corresponding to the error between the first voltage and a first reference voltage, and a signal output circuit that outputs the drive signal for turning on the transistor when the inductor current reaches a predetermined current value, and outputs the drive signal for turning off the transistor based on the first error voltage so that the duty ratio becomes a predetermined value.

The power supply circuit according to the present invention, which solves the above-mentioned problems, is a power supply circuit that includes an inductor to which a rectified voltage obtained by rectifying an AC voltage is applied, and a transistor that controls the inductor current flowing through the inductor, and generates an output voltage by boosting the rectified voltage. The power supply circuit includes a switching control circuit that controls the switching of the transistor, and a smoothing circuit that smoothes a drive signal for switching the transistor. The switching control circuit includes a first error voltage generation circuit that outputs a first error voltage corresponding to the error between the output from the smoothing circuit and a first reference voltage, and a signal output circuit that outputs the drive signal for turning on the transistor when the inductor current reaches a predetermined current value, and outputs the drive signal for turning off the transistor based on the first error voltage so that the duty ratio of the drive signal becomes a predetermined value.

The present invention provides an integrated circuit that can reduce power loss in a power supply circuit.

FIG. 1 is a diagram illustrating an example of an AC-DC converter 10a. FIG. 2 is a diagram showing an example of an integrated circuit 30a. FIG. 4 is a diagram showing an example of an operational waveform of an integrated circuit 30a. 11 is a diagram showing an example of the operation of the integrated circuit 30a caused by a change in the duty ratio of the drive signal Vdr. FIG. 1 is a diagram showing the relationship between an AC voltage Vac (effective value), a peak voltage of the AC voltage Vac, an output voltage, and a step-up ratio. FIG. 1 is a diagram illustrating an example of an AC-DC converter 10b. FIG. 2 is a diagram showing an example of an integrated circuit 30b. 1 is a diagram showing the relationship between an AC voltage Vac (effective value), a peak voltage of the AC voltage Vac, an output voltage, and a step-up ratio. FIG. 11 is a diagram showing an example of an operational waveform of an integrated circuit 30b. FIG. 1 is a diagram illustrating an example of an AC-DC converter 10c. FIG. 13 is a diagram showing an example of an integrated circuit 30c. FIG. 13 is a diagram showing an example of an integrated circuit 30d.

At least the following points will become apparent from the description of this specification and the accompanying drawings.
== ...
1 is a diagram showing an example of an AC-DC converter 10a according to an embodiment of the present invention. The AC-DC converter 10a is a boost chopper type power supply circuit that generates an output voltage Vout from an AC voltage Vac of a commercial power supply 11.

The load 12 is, for example, a DC-DC converter or an electronic device that operates on DC voltage.

<<<Outline of AC-DC converter 10a>>>
The AC-DC converter 10a includes a full-wave rectifier circuit 20, capacitors 21 and 23, a coil L1, a diode 22, an NMOS transistor 24, a resistor 25, and a control block 26a.

The full-wave rectifier circuit 20 full-wave rectifies the AC voltage Vac and applies the rectified voltage Vrec1 to the capacitor 21 and the coil L1.

The rectified voltage Vrec1 is applied directly to one end of the coil L1, but may also be applied to the coil L1 via an element such as a resistor (not shown). In this embodiment, "application" includes not only the direct supply of a voltage to a specific node, but also the indirect supply of a voltage via an element such as a resistor (not shown), and the supply of a divided voltage.

Capacitor 21 is an element that filters the high-frequency ripple current flowing through the inductor and the switching noise generated by turning the MOSFET on and off.

The coil L1, together with the diode 22, the capacitor 23, and the NMOS transistor 24, constitutes a boost chopper circuit. Therefore, the charging voltage of the capacitor 23 becomes the DC output voltage Vout. The voltage of the node to which the other end of the coil L1, the anode of the diode 22, and the drain electrode of the NMOS transistor 24 are connected is defined as voltage Vx. At this time, the voltage Vx becomes the drain-source voltage of the NMOS transistor 24, since the source electrode of the NMOS transistor 24 is grounded.

The NMOS transistor 24 is a transistor for controlling the power to the load 12 of the AC-DC converter 10a. In this embodiment, the NMOS transistor 24 is a MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. The NMOS transistor 24 may be, for example, a bipolar transistor, as long as it is a transistor that can control power. In addition, the gate electrode of the NMOS transistor 24 is connected so as to be driven by a drive signal Vdr from a terminal OUT of the integrated circuit 30a described below.

The resistor 25 is a resistor for detecting the inductor current IL, and one end is connected to the source electrode of the NMOS transistor 24, and the other end is connected to a terminal CS of the integrated circuit 30a described later. In this embodiment, the voltage input to the terminal CS indicating the inductor current IL is defined as a voltage Vcs. This voltage Vcs may be, for example, a voltage applied to the terminal CS from an inverting amplifier circuit (not shown) that inverts and amplifies the voltage generated in the resistor 25, with the source electrode of the grounded NMOS transistor 24 as the reference (ground voltage). In this case, the voltage Vcs applied to the terminal CS increases in response to an increase in the inductor current IL. Such positive/negative inversion may be performed inside the integrated circuit 30a.

The control block 26a controls the NMOS transistor 24 based on the voltage generated across the resistor 25. The control block 26a includes an integrated circuit 30a, resistors 31, 32, and 34, and capacitors 33, 35, and 36.

The integrated circuit 30a controls the switching of the NMOS transistor 24 to generate the output voltage Vout from the AC voltage Vac. Specifically, the integrated circuit 30a drives the NMOS transistor 24 so that the duty ratio of the drive signal Vdr becomes a predetermined value based on the inductor current IL flowing through the coil L1 and the voltage Vfb described below. Here, the duty ratio is the ratio of the period during which the NMOS transistor 24 is on to the period during which the NMOS transistor 24 is on and off.

The integrated circuit 30a will be described in detail later, but the integrated circuit 30a has terminals FB, CS, COMP, and OUT. The integrated circuit 30a also has terminals other than the four terminals FB, CS, COMP, and OUT described above, but these are omitted here for convenience. The integrated circuit 30a also corresponds to a "switching control circuit."

The resistors 31 and 32 form a voltage divider circuit that divides the drive signal Vdr, and together with the capacitor 33 generate the voltage Vfb used when switching the NMOS transistor 24. The voltage Vfb generated at the node to which the resistors 31 and 32 are connected is applied to the terminal FB. The capacitor 33 forms a smoothing circuit together with the resistor 31, and smoothes the drive signal Vdr. The voltage Vfb corresponds to the "first voltage."

Resistor 34 and capacitors 35 and 36 are elements for phase compensation of the feedback-controlled integrated circuit 30a. Resistor 34 and capacitor 35 are provided in series between terminal COMP and ground, and capacitor 36 is provided in parallel with these.

<<<Configuration of Integrated Circuit 30a>>>
Fig. 2 is a diagram showing an example of an integrated circuit 30a. The integrated circuit 30a includes a signal output circuit 40a and an error voltage generating circuit 41. For convenience, terminals are drawn in different positions in Fig. 2 from those in Fig. 1, but the wiring, elements, etc. connected to each terminal are the same in Fig. 1 and Fig. 2.

The signal output circuit 40a outputs a drive signal Vdr based on the inductor current IL and the voltage Vcomp of the terminal COMP. Specifically, when the inductor current IL becomes almost zero, the signal output circuit 40a outputs a drive signal Vdr that turns on the NMOS transistor 24. On the other hand, when the voltage Vr from the oscillation circuit 54 described below becomes the voltage Vcomp, the signal output circuit 40a outputs a drive signal Vdr that turns off the NMOS transistor 24. The signal output circuit 40a includes a detection circuit 50, a delay circuit 51, a pulse circuit 52, an SR flip-flop 53, an oscillation circuit 54, a comparator 55, and a buffer 56.

The error voltage generating circuit 41 is a transconductance amplifier, and generates an error current Ie according to the error between the reference voltage VREF0 for setting the duty ratio to a predetermined value and the voltage Vfb. The error voltage generating circuit 41 also charges and discharges the capacitors 35 and 36 via the terminal COMP with the error current Ie1 to generate a voltage Vcomp. As a result, the error voltage generating circuit 41 generates a voltage Vcomp according to the error between the reference voltage VREF0 and the voltage Vfb according to the duty ratio of the drive signal Vdr. The error voltage generating circuit 41 corresponds to the "first error voltage generating circuit". In this embodiment, the voltage Vcomp corresponds to the "first error voltage".

The detection circuit 50 is a circuit that detects whether the current value of the inductor current IL has become a "current value Ia" indicating almost zero (hereinafter, for convenience, "almost zero" will be simply referred to as zero) based on the voltage Vcs of the terminal CS. Note that when the detection circuit 50 of this embodiment detects that the current value of the inductor current IL is the "current value Ia" which is "zero", it outputs a high level (hereinafter, "H level") signal Vz. Note that the detection circuit 50 is configured to include a comparator (not shown) that compares a predetermined voltage corresponding to the voltage generated in the resistor 25 when the inductor current IL becomes the "current value Ia" with a voltage corresponding to the voltage Vcs.

When the detection circuit 50 outputs a high-level signal Vz, the delay circuit 51 delays it by a predetermined time before outputting it.

When the delay circuit 51 outputs a high-level signal Vz, the pulse circuit 52 outputs a high-level pulse signal Vp1.

When the pulse circuit 52 outputs a high-level pulse signal Vp1, the SR flip-flop 53 outputs a high-level drive signal Vq1. On the other hand, when the comparator 55 (described below) outputs a high-level signal Vc1, the SR flip-flop 53 outputs a low-level (hereinafter referred to as "low level") drive signal Vq1.

The oscillator circuit 54 is a circuit that generates the oscillatory voltage Vr required to turn on and off the NMOS transistor 24. Specifically, when the inductor current IL becomes smaller than zero and the drive signal Vq1 is input at the "H" level, the oscillator circuit 54 outputs an oscillatory voltage Vr whose amplitude gradually increases at a predetermined gradient.

The comparator 55 is a circuit that compares the voltage Vcomp with the oscillation signal Vr. Specifically, the voltage Vcomp is applied to the inverting input terminal of the comparator 55, and the oscillation voltage Vr is applied to the non-inverting input terminal of the comparator 55. Therefore, when the level of the oscillation voltage Vr is lower than the level of the voltage Vcomp, the comparator 55 outputs a signal Vc1 of "L" level, and when the level of the oscillation voltage Vr is higher than the level of the voltage Vcomp, the comparator 55 outputs a signal Vc1 of "H" level.

The buffer 56 drives the NMOS transistor 24 based on the drive signal Vq1. Specifically, the buffer 56 drives the NMOS transistor 24, which has a large gate capacitance, with a signal Vdr that has the same logical level as the input signal. The buffer 56 also turns on the NMOS transistor 24 based on the drive signal Vq1 at the "H" level, and turns off the NMOS transistor 24 based on the drive signal Vq1 at the "L" level.

<<<Operation of Integrated Circuit 30a>>>
3 is a diagram showing an example of the operation of the integrated circuit 30a. First, at time t0, the inductor current IL decreases and reaches a current value Ia, and the detection circuit 50 outputs a signal Vz of "H" level. Then, at time t1, the delay circuit 51 outputs a delayed signal Vz, and the pulse circuit 52 outputs a pulse signal Vp1.

When the pulse signal Vp1 is output, the SR flip-flop 53 outputs the drive signal Vq1 at the "H" level, so that the drive signal Vdr also becomes "H" level. When the SR flip-flop 53 outputs the "H" level signal Vq1, the oscillator circuit 54 starts to output a ramp voltage Vr that gradually increases. When the integrated circuit 30a outputs the "H" level drive signal Vdr, the NMOS transistor 24 turns on. As a result, the voltage Vx becomes the ground voltage. The inductor current IL gradually increases at a slope that corresponds to the inductor value of the coil L1 and the rectified voltage Vrec1.

At time t2, when voltage Vr becomes voltage Vcomp, comparator 55 outputs "H" level signal Vc1. This causes SR flip-flop 53 to output "L" level signal Vq1, and drive signal Vdr also becomes "L" level. Furthermore, when integrated circuit 30a outputs "L" level drive signal Vdr, NMOS transistor 24 turns off. Furthermore, voltage Vx becomes a voltage corresponding to output voltage Vout. Then, a back electromotive force corresponding to inductor current IL when NMOS transistor 24 is on is generated in coil L1, and inductor current IL starts to be supplied to capacitor 23 via diode 22.

At time t3, when the inductor current IL reaches a current value Ia, the detection circuit 50 outputs a high-level signal Vz.

At time t4, the delay circuit 51 outputs the delayed signal Vx, and the pulse circuit 52 outputs the pulse signal Vp1. After that, the operation at time t1 is repeated.

<<<<Explanation regarding the duty ratio of the drive signal Vdr reaching the target value>>>
4 is a diagram showing an example of the operation of the integrated circuit 30a caused by a change in the duty ratio of the drive signal Vdr. The operation of the integrated circuit 30a at times t1, t2, and t4 is the same as that in FIG. 3. Times ta1, ta2, and ta4 correspond to times t1, t2, and t4, respectively, and times tb1, tb2, and tb4 also correspond to times t1, t2, and t4, respectively. The operation pattern shown at times t1, t2, and t4 is pattern A, the operation pattern shown at times ta1, ta2, and ta4 is pattern B, and the operation pattern shown at times tb1, tb2, and tb4 is pattern C.

Pattern A is an operating pattern when the duty ratio of the drive signal Vdr is the target value. In the case of pattern A, the voltage Vfb is approximately equal to the reference voltage VREF0. Furthermore, the voltage Vcomp is a voltage for turning on the NMOS transistor 24 so that the duty ratio of the drive signal Vdr is the target value.

Pattern B is an operation pattern when the duty ratio of the drive signal Vdr is smaller than the target value. Note that the voltage Vcomp when the duty ratio of the drive signal Vdr is smaller than the target value will be described as voltage Va.

In the case of pattern B, the smoothing circuit in FIG. 1 generates a voltage Vfb that is lower than when the duty ratio is at the target value. When the voltage Vfb becomes lower than the reference voltage VREF0, the error voltage generating circuit 41 supplies an error current Ie1 to charge the capacitors 35 and 36. Therefore, the voltage Va rises to be the same as the voltage Vcomp when the duty ratio is at the target value. As a result, the on-period of the NMOS transistor 24 becomes longer, so the duty ratio of the drive signal Vdr becomes larger and the voltage Vfb rises to approach the reference voltage VREF0.

Pattern C is an operation pattern when the duty ratio of the drive signal Vdr is greater than a predetermined value. Note that the voltage Vcomp when the duty ratio of the drive signal Vdr is greater than the target value will be described as voltage Vb.

In the case of pattern C, the smoothing circuit in FIG. 1 generates a higher voltage Vfb than when the duty ratio is at the target value. When the voltage Vfb becomes higher than the reference voltage VREF0, the error voltage generating circuit 41 supplies an error current Ie1 to discharge the capacitors 35 and 36. Therefore, the voltage Vb decreases to be the same as the voltage Vcomp when the duty ratio is at the target value. Accordingly, the on-period of the NMOS transistor 24 becomes shorter, so that the duty ratio of the drive signal Vdr becomes smaller and the voltage Vfb decreases to approach the reference voltage VREF0.

By the above operation, the integrated circuit 30a generates the drive signal Vdr so that the voltage Vfb obtained by smoothing the drive signal Vdr becomes the reference voltage VREF0. Therefore, the integrated circuit 30a outputs the drive signal Vdr whose duty ratio becomes the target value.

<<<<Relationship between AC voltage Vac and output voltage Vout, etc.>>>
5 is a diagram showing the relationship between the AC voltage Vac (effective value), the peak voltage of the AC voltage Vac, the output voltage, and the boost ratio. The dashed line indicates the peak voltage of the AC voltage Vac, and the solid line indicates the output voltage Vout. The dashed line indicates the boost ratio. The boost ratio is a ratio expressed as 1/(1-D) when the duty ratio is represented by D and the forward voltage of the diode 22 is ignored. As the effective value of the AC voltage Vac increases, the peak voltage of the AC voltage Vac increases.

Since the integrated circuit 30a operates to set the duty ratio to a target value, the boost ratio calculated from the duty ratio also becomes a predetermined value. Therefore, the output voltage Vout increases as the effective value and peak value of the AC voltage Vac increase.

<<<Outline of AC-DC converter 10b>>>
6 is a diagram showing an example of an AC-DC converter 10b. However, the capacitor 23 may be destroyed if the output voltage Vout greatly exceeds a predetermined level (for example, 450 V). Therefore, the AC-DC converter 10b changes the output voltage Vout according to the effective value of the AC voltage Vac when the effective value of the AC voltage Vac is small. On the other hand, when the effective value of the AC voltage Vac becomes large, the AC-DC converter 10b maintains the output voltage Vout at a predetermined level (for example, 400 V). The AC-DC converter 10b is a power supply circuit in which resistors 27 and 28 that divide the output voltage Vout are added to the AC-DC converter 10a, and the control block 26a is replaced with a control block 26b.

The control block 26b is obtained by replacing the integrated circuit 30a in the control block 26a with an integrated circuit 30b. The integrated circuit 30b is provided with terminals FB1, FB2, CS, COMP, and OUT, which will be described in detail later. The integrated circuit 30b is provided with terminals other than the five terminals FB1, FB2, CS, COMP, and OUT described above, but these are omitted here for convenience. The external circuits connected to the terminals CS, COMP, and OUT are the same as those in the integrated circuit 30a.

Similar to terminal FB of integrated circuit 30a, terminal FB1 receives voltage Vfb1 from a smoothing circuit consisting of resistors 31 and 32 and capacitor 33. Terminal FB2 receives voltage Vfb2 from the connection point of resistors 27 and 28. Terminal FB1 corresponds to the "first terminal", terminal FB2 corresponds to the "second terminal", and terminal COMP corresponds to the "third terminal".

<<<Configuration of integrated circuit 30b>>>
7 is a diagram showing an example of an integrated circuit 30b. The integrated circuit 30b includes a signal output circuit 40b and error voltage generating circuits 41 and 42. The signal output circuit 40b further includes a selection circuit 57 in addition to the signal output circuit 40a. The selection circuit 57 selects which of the error currents Ie1 and Ie2 supplied from the error voltage generating circuit 41 and an error voltage generating circuit 42 (described later) is used to generate the voltage Vcomp.

Specifically, the selection circuit 57 discharges the capacitors 35, 36 with the error current Ie1 or Ie2 depending on which of the diodes 60, 61 described below is turned on, and charges them with the bias current Ib of the constant current source 62 described below. Note that, for convenience, the terminals are drawn in different positions in FIG. 7 than in FIG. 6, but the wiring, elements, etc. connected to each terminal are the same in FIG. 6 and FIG. 7. Also, objects with the same reference symbols are the same as the integrated circuit 30a in FIG. 2.

The selection circuit 57 includes diodes 60 and 61, and a constant current source 62. The diode 60 has a cathode connected to the output of the error voltage generating circuit 41 and an anode connected to the terminal COMP. Similarly, the diode 61 has a cathode connected to the output of the error voltage generating circuit 42 described below and an anode connected to the terminal COMP. The constant current source 62 supplies a bias current Ib to the terminal COMP based on the power supply voltage Vdd from an internal power supply (not shown).

Therefore, the capacitors 35 and 36 are charged with the bias current Ib, while being discharged with the error current Ie1 from the error voltage generating circuit 41 or the error current Ie2 from the error voltage generating circuit 42 described below. In addition, the selection circuit 57 selects the output voltage of the error voltage generating circuit 41 or the output voltage of the error voltage generating circuit 42 as the selection result.

The error voltage generating circuit 41 has a terminal FB1 connected to its inverting input terminal, to which a voltage Vfb1 is applied. Also, the error voltage generating circuit 41 has a reference voltage VREF0 applied to its non-inverting input terminal. Note that the voltage Vfb1 corresponds to the "first voltage" and the diode 60 corresponds to the "first diode."

The error voltage generating circuit 41 also supplies an error current Ie1 based on the error between the voltage Vfb1 and the reference voltage VREF0 to the output. Specifically, the error voltage generating circuit 41 outputs a voltage lower than the voltage Vcomp by the forward voltage of the diode 60, and when the diode 60 is turned on, a current corresponding to the error current Ie1 flows through the terminal COMP to the capacitors 35 and 36. In this case, the capacitors 35 and 36 are discharged by a current corresponding to the error current Ie1, so the voltage Vcomp drops due to the current corresponding to the error current Ie1. The reference voltage VREF0 corresponds to the "first reference voltage". The voltage output from the error voltage generating circuit 41 corresponds to the "first error voltage".

On the other hand, when the diode 60 is off, the error voltage generating circuit 41 cannot pass a current corresponding to the error current Ie1 through the terminal COMP to the capacitors 35 and 36.

The error voltage generating circuit 42 has a terminal FB2 connected to its inverting input terminal, to which a voltage Vfb2 is applied. The error voltage generating circuit 42 also has a reference voltage VREF1 applied to its non-inverting input terminal. The reference voltage VREF1 is set to be the voltage Vfb2 that is generated at the connection point of the resistors 27 and 28 when the output voltage Vout reaches a predetermined level. The voltage Vfb2 corresponds to the "second voltage", and the diode 61 corresponds to the "second diode". The reference voltage VREF1 corresponds to the "second reference voltage".

The error voltage generating circuit 42 also supplies to its output an error current Ie2 based on the error between the voltage Vfb2 and the reference voltage VREF1. Specifically, the error voltage generating circuit 42 outputs a voltage lower than the voltage Vcomp by the forward voltage of the diode 61, and when the diode 61 is turned on, a current corresponding to the error current Ie2 flows through the terminal COMP to the capacitors 35 and 36. In this case, the capacitors 35 and 36 are discharged by a current corresponding to the error current Ie2, so that the voltage Vcomp drops due to the current corresponding to the error current Ie2. The voltage output by the error voltage generating circuit 42 corresponds to the "second error voltage".

On the other hand, when the diode 61 is off, the error voltage generating circuit 42 cannot pass a current corresponding to the error current Ie2 through the terminal COMP to the capacitors 35 and 36. The detection circuit 50 corresponds to the "current detection circuit", the signal Vz corresponds to the "detection result", and the SR flip-flop 53 corresponds to the "output circuit". The error voltage generating circuit 42 corresponds to the "second error voltage generating circuit".

<<<Operation of Integrated Circuit 30b>>>
The operation of the integrated circuit 30b will be described below. As described above, in the AC-DC converter 10a, the output voltage Vout is controlled to increase as the effective value of the AC voltage Vac increases. Therefore, when the output voltage Vout greatly exceeds a predetermined level, the capacitor 23 may be destroyed. In the AC-DC converter 10b, in order to prevent the capacitor 23 from being destroyed, when the output voltage Vout exceeds a predetermined level, the error voltage generating circuit 42 is operated to maintain the output voltage Vout at the predetermined level. Therefore, the constants of the circuits generating the voltages Vfb1 and Vfb2 and the reference voltages VREF0 and VREF1 are determined so that such an operation is established.

When the output voltage Vout is less than a predetermined level, the error voltage generating circuit 41 reduces the output voltage based on the voltage Vfb1 to turn on the diode 60. Also, the selection circuit 57 selects the output voltage of the error voltage generating circuit 41 because the diode 60 is turned on. Then, when the output voltage Vout exceeds a predetermined level, the error voltage generating circuit 42 operates to reduce the duty ratio, and the voltage Vfb1 decreases, so the error voltage generating circuit 41 increases the output voltage. As a result, the cathode voltage increases, and the diode 60 turns off.

As a result, the error voltage generating circuit 41 no longer generates the voltage Vcomp, and the selection circuit 57 no longer selects the output voltage of the error voltage generating circuit 41. When the selection circuit 57 selects the output voltage of the error voltage generating circuit 41, the operation of the integrated circuit 30b is the same as that of the integrated circuit 30a, and the integrated circuit 30b causes the AC-DC converter 10b to output an output voltage Vout that increases as the effective value increases, as shown in the region in FIG. 8 where the effective value of the AC voltage Vac is less than 200 V. In FIG. 8, the dashed line indicates the peak voltage of the AC voltage Vac, and the solid line indicates the output voltage Vout. Also, the dashed line indicates the step-up ratio.

When the output voltage Vout exceeds a predetermined level, the error voltage generating circuit 42 reduces the output voltage based on the voltage Vfb2 so as to turn on the diode 61. The selection circuit 57 selects the output voltage of the error voltage generating circuit 42. When the output voltage Vout falls below the predetermined level, the voltage Vfb2 decreases, and the error voltage generating circuit 42 increases the output voltage. This increases the cathode voltage, turning off the diode 61.

As a result, the error voltage generating circuit 42 no longer generates the voltage Vcomp, and the selection circuit 57 no longer selects the voltage at the output of the error voltage generating circuit 42. Furthermore, when the selection circuit 57 selects the voltage at the output of the error voltage generating circuit 42, the integrated circuit 30b maintains the output voltage Vout at a predetermined level. In this case, the integrated circuit 30b causes the AC-DC converter 10b to output a predetermined level of output voltage Vout even if the effective value becomes large, as shown in the region in FIG. 8 where the effective value of the AC voltage Vac is 200 V or more. The operation of the integrated circuit 30b in such a case will be described below with reference to FIG. 9.

Figure 9 shows an example of the operating waveforms of integrated circuit 30b. First, at time t10, when inductor current IL decreases and reaches current value Ia, detection circuit 50 outputs "H" level signal Vz. Then, at time t11, delay circuit 51 outputs delayed signal Vz, and pulse circuit 52 outputs pulse signal Vp1.

When the pulse signal Vp1 is output, the SR flip-flop 53 outputs the drive signal Vq1 at the "H" level, so that the drive signal Vdr also becomes "H" level. When the SR flip-flop 53 outputs the "H" level signal Vq1, the oscillator circuit 54 starts to output a ramp voltage Vr that gradually increases. When the integrated circuit 30b outputs the "H" level drive signal Vdr, the NMOS transistor 24 turns on. As a result, the voltage Vx becomes the ground voltage. The inductor current IL gradually increases at a slope that corresponds to the inductor value of the coil L1 and the rectified voltage Vrec1.

At time t12, when voltage Vr becomes voltage Vcomp, comparator 55 outputs "H" level signal Vc1. This causes SR flip-flop 53 to output "L" level signal Vq1, and integrated circuit 30b outputs "L" level drive signal Vdr. When integrated circuit 30b outputs "L" level drive signal Vdr, NMOS transistor 24 turns off. Voltage Vx becomes a voltage corresponding to output voltage Vout. Then, a back electromotive force corresponding to inductor current IL when NMOS transistor 24 is on is generated in coil L1, and inductor current IL starts to be supplied to capacitor 23 via diode 22.

At time t13, when the inductor current IL based on the back electromotive force from coil L1 decreases and reaches a current value Ia, the detection circuit 50 outputs a high-level signal Vz.

At time t14, when the delay circuit 51 outputs the delayed signal Vx, the pulse circuit 52 outputs the pulse signal Vp1. After that, the operation from time t11 is repeated.

As a result of the above operations, when the effective value of the AC voltage Vac is large, the integrated circuit 30b generates the drive signal Vdr so that the voltage Vfb2 corresponding to the output voltage Vout becomes the reference voltage VREF1. Therefore, the integrated circuit 30b outputs the drive signal Vdr so that the output voltage Vout becomes a predetermined level.

====Modifications====
10 is a diagram showing an example of an AC-DC converter 10c. The AC-DC converter 10c is a modified example of the AC-DC converter 10b. In the AC-DC converter 10c, the control block 26b in the AC-DC converter 10b is replaced with a control block 26c.

Compared to control block 26b, control block 26c further includes diodes 37 and 38 that perform full-wave rectification of AC voltage Vac, and uses integrated circuit 30c instead of integrated circuit 30b. The details of integrated circuit 30c will be described later, but integrated circuit 30c is provided with terminals FB1, FB2, CS, COMP, OUT, and VH.

Diodes 37 and 38 form a full-wave rectifier circuit that full-wave rectifies AC voltage Vac, and generates rectified voltage Vrec2 from AC voltage Vac. The rectified voltage Vrec2 is applied to terminal VH. In this embodiment, rectified voltage Vrec2 is generated by diodes 37 and 38 and applied to terminal VH, but the voltage generated in capacitor 21 to which rectified voltage Vrec1 is applied may be applied to terminal VH via a resistor (not shown).

In addition, integrated circuit 30c has terminals other than the six terminals FB1, FB2, CS, COMP, OUT, and VH described above, but these are omitted here for convenience. Also, the external circuits connected to terminals FB1, FB2, CS, COMP, and OUT are the same as those in integrated circuit 30b.

<<<Configuration of Integrated Circuit 30c>>>
Fig. 11 is a diagram showing an example of an integrated circuit 30c. The integrated circuit 30c is a modified example of the integrated circuit 30b, and includes a signal output circuit 40c, error voltage generating circuits 41 and 42, and a discrimination circuit 43. The signal output circuit 40c includes a switch circuit 58 instead of the selection circuit 57 of the signal output circuit 40b. For convenience, the terminals are depicted in Fig. 11 at positions different from those in Fig. 10, but the wiring, elements, etc. connected to each terminal are the same in Figs. 10 and 11. Also, the same reference symbols are attached to the same objects as those in the integrated circuit 30b in Fig. 6.

The switch circuit 58 selects which output of the error voltage generating circuit 41 or 42 to connect to the terminal COMP based on a signal Sdet from the discrimination circuit 43 described below.

The discrimination circuit 43 discriminates the voltage level of the effective value of the AC voltage Vac based on the rectified voltage Vrec2 obtained by rectifying the AC voltage Vac by the diodes 37 and 38. Specifically, when the voltage level of the effective value of the AC voltage Vac is level VL1, the discrimination circuit 43 outputs a signal Sdet that causes the switch circuit 58 to select the error voltage generating circuit 41. On the other hand, when the voltage level of the effective value of the AC voltage Vac is level VL2, the discrimination circuit 43 outputs a signal Sdet that causes the switch circuit 58 to select the error voltage generating circuit 42. Note that level VL1 corresponds to the "first level" and level LV2 corresponds to the "second level". Also, level VL2 is higher than level VL1.

<<<Configuration of Integrated Circuit 30d>>>
Fig. 12 is a diagram showing an example of an integrated circuit 30d. The integrated circuit 30d is a modified example of the integrated circuits 30b and 30c, and includes a signal output circuit 40a, error voltage generating circuits 41 and 42, a discrimination circuit 43, and an enable circuit 44. For convenience, the terminals are depicted in Fig. 12 at positions different from those in Fig. 10, but the wiring, elements, etc. connected to each terminal are the same in Fig. 10 and Fig. 12. Also, the objects denoted by the same reference symbols are the same as those in the integrated circuit 30c in Fig. 10.

The enable circuit 44 outputs signals S1 and S2 based on the signal Sdet from the identification circuit 43. Specifically, when the identification circuit 43 outputs the signal Sdet that causes the switch circuit 58 to select the error voltage generation circuit 41, the enable circuit 44 outputs the signal S1 that selects the error voltage generation circuit 41. When the enable circuit 44 outputs the signal S1 that selects the error voltage generation circuit 41, the error voltage generation circuit 41 operates and outputs the error current Ie1 according to the voltage Vfb1. On the other hand, when the enable circuit 44 outputs the signal S1 that does not select the error voltage generation circuit 41, the error voltage generation circuit 41 does not operate and does not output the error current Ie1.

When the discrimination circuit 43 outputs a signal Sdet to cause the switch circuit 58 to select the error voltage generation circuit 42, the enable circuit 44 outputs a signal S2 to select the error voltage generation circuit 42. When the enable circuit 44 outputs a signal S2 to select the error voltage generation circuit 42, the error voltage generation circuit 42 operates and outputs an error current Ie2 according to the voltage Vfb2. On the other hand, when the enable circuit 44 outputs a signal S2 not to select the error voltage generation circuit 42, the error voltage generation circuit 42 does not operate and does not output the error current Ie2. Note that the signal S1 to select the error voltage generation circuit 41 and the signal S2 to select the error voltage generation circuit 42 are output exclusively.

====Summary====
The AC-DC converters 10a, 10b, and 10c of this embodiment have been described above. The integrated circuit 30a includes a signal output circuit 40a and an error voltage generating circuit 41. The error voltage generating circuit 41 generates a voltage Vcomp corresponding to the error between the voltage Vfb corresponding to the duty ratio of the drive signal Vdr and the reference voltage VREF0. The signal output circuit 40a also maintains the duty ratio at a target value to determine the on-period of the NMOS transistor 24 based on the voltage Vcomp. As a result, the integrated circuit 30a sets the step-up ratio based on the duty ratio to a predetermined value, thereby suppressing power loss caused by an increase in the step-up ratio. Therefore, it is possible to provide an integrated circuit capable of suppressing power loss in a power supply circuit.

The integrated circuit 30b also includes a signal output circuit 40b and error voltage generating circuits 41 and 42. The error voltage generating circuit 42 generates a voltage Vcomp corresponding to the error between the voltage Vfb2 corresponding to the output voltage Vout and the reference voltage VREF1. When the output voltage Vout is higher than a predetermined level, the signal output circuit 40b outputs a drive signal Vdr that turns off the NMOS transistor 24 based on the voltage Vfb2 (in other words, the voltage Vcomp generated by the error voltage generating circuit 42) so that the output voltage Vout becomes a predetermined level. When the step-up ratio is a predetermined value, if the effective value of the AC voltage Vac becomes high, the output voltage becomes higher than the predetermined level, but the integrated circuit 30b maintains the output voltage Vout at a predetermined level even if the effective value of the AC voltage Vac becomes high. This prevents the output voltage Vout from exceeding the withstand voltage of the capacitor 23 even if the effective value of the AC voltage Vac becomes high, and allows the AC-DC converter 10b to use an inexpensive capacitor 23.

The signal output circuit 40b also includes a detection circuit 50, an SR flip-flop 53, and a selection circuit 57. The selection circuit 57 selects whether to generate the voltage Vcomp with the error current Ie1 or Ie2 generated by the error voltage generation circuit 41 or 42, based on whether the output voltage Vout is at a predetermined level. This allows the integrated circuit 30b to change the method of generating the drive signal Vdr depending on the effective value of the AC voltage Vac.

In addition, integrated circuit 30b has terminals FB1 and FB2. This allows integrated circuit 30b to output drive signal Vdr based on either voltage Vfb1 or Vfb2.

In addition, the integrated circuit 30b further includes a terminal COMP, and the selection circuit 57 includes diodes 60 and 61 and a constant current source 62. This allows the integrated circuit 30b to control, with a simple circuit, whether the drive signal Vdr is to be output based on the voltage Vfb1 or Vfb2.

The integrated circuit 30c also includes a signal output circuit 40c, error voltage generation circuits 41 and 42, and an identification circuit 43. The signal output circuit 40c also outputs a drive signal Vdr whose duty ratio becomes a target value or whose output voltage Vout becomes a predetermined level according to the voltage level of the effective value of the AC voltage Vac. This allows the integrated circuit 30c to identify the effective value of the AC voltage Vac, which differs depending on the country, and output the drive signal Vdr appropriately.

The integrated circuit 30d also includes a signal output circuit 40a, error voltage generating circuits 41 and 42, a discrimination circuit 43, and an enable circuit 44. The error voltage generating circuit 41 or 42 is enabled by a signal S1 or S2 from the enable circuit 44. The signal output circuit 40a outputs a drive signal Vdr based on a voltage Vcomp generated by an error current Ie1 or Ie2 from the enabled error voltage generating circuit 41 or 42. That is, the integrated circuit 30d operates only one of the error voltage generating circuits 41 or 42 that is required according to the effective value of the AC voltage Vac. This allows the integrated circuit 30d to reduce power consumption.

The above embodiments are intended to facilitate understanding of the present invention, and are not intended to limit the scope of the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents.

10a, 10b, 10c AC-DC converter 11 Commercial power supply 12 Load 20 Full-wave rectifier circuit 21, 23, 33, 35, 36 Capacitor 22, 37, 38, 60, 61 Diode 24 NMOS transistor 25, 27, 28, 31, 32, 34 Resistor 26a, 26b, 26c Control block 30a, 30b, 30c, 30d Integrated circuits 40a, 40b, 40c Signal output circuit 41, 42 Error voltage generating circuit 43 Identification circuit 44 Enable circuit 50 Detection circuit 51 Delay circuit 52 Pulse circuit 53 SR flip-flop 54 Oscillator circuit 55 Comparator 56 Buffer 57 Selection circuit 58 Switch circuit 62 Constant current source

Claims (8)

1. An integrated circuit for controlling switching of a transistor in a power supply circuit that generates an output voltage by boosting the rectified voltage, the integrated circuit comprising: an inductor to which a rectified voltage obtained by rectifying an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor, the integrated circuit comprising:
a first error voltage generating circuit that generates a first error voltage corresponding to an error between a first voltage corresponding to a duty ratio of a drive signal for switching the transistor and a first reference voltage;
a signal output circuit that outputs the drive signal for turning on the transistor when the inductor current reaches a predetermined current value, and outputs the drive signal for turning off the transistor based on the first error voltage so that the duty ratio becomes a predetermined value;
1. An integrated circuit comprising: 2. The integrated circuit of claim 1,
a second error voltage generating circuit that generates a second error voltage according to an error between a second voltage corresponding to a level of the output voltage and a second reference voltage,
The signal output circuit includes:
When the output voltage is higher than a predetermined level, the drive signal for turning off the transistor is output based on the second error voltage so that the output voltage becomes the predetermined level.
Integrated circuits. 3. An integrated circuit according to claim 2, comprising:
The signal output circuit includes:
a current detection circuit for detecting whether the inductor current has reached the predetermined current value;
a selection circuit that selects the first error voltage when the output voltage is lower than the predetermined level, and selects the second error voltage when the output voltage is higher than the predetermined level;
an output circuit that outputs the drive signal for turning on the transistor based on a detection result of the current detection circuit, and outputs the drive signal for turning off the transistor based on a selection result of the selection circuit;
[0023] An integrated circuit including 4. An integrated circuit according to claim 3,
a first terminal to which the first voltage is applied;
a second terminal to which the second voltage is applied;
1. An integrated circuit comprising: 5. An integrated circuit according to claim 4,
a third terminal to which the capacitor is connected;
The selection circuit includes:
a current source for charging the capacitor;
a first diode connected between the third terminal and the first error voltage generating circuit;
a second diode connected between the third terminal and the second error voltage generating circuit;
[0023] An integrated circuit including 2. The integrated circuit of claim 1,
a discrimination circuit for discriminating whether a voltage level of the effective value of the AC voltage is a first level or a second level higher than the first level;
a second error voltage generating circuit that generates a second error voltage corresponding to an error between a second voltage corresponding to a level of the output voltage and a second reference voltage;
Further comprising:
The signal output circuit includes:
when the voltage level of the effective value is identified as the first level, outputting the drive signal for turning off the transistor so that the duty ratio becomes a predetermined value, and when the voltage level of the effective value is identified as the second level, outputting the drive signal for turning off the transistor so that the output voltage becomes a predetermined level.
Integrated circuits. 7. An integrated circuit according to claim 6, comprising:
the identification circuit operates the first error voltage generating circuit when it identifies that the voltage level of the effective value is the first level, and operates the second error voltage generating circuit when it identifies that the voltage level of the effective value is the second level.
Integrated circuits. 1. A power supply circuit comprising: an inductor to which a rectified voltage obtained by rectifying an AC voltage is applied; and a transistor for controlling an inductor current flowing through the inductor, the power supply circuit generating an output voltage by boosting the rectified voltage,
a switching control circuit for controlling switching of the transistor;
a smoothing circuit for smoothing a drive signal for switching the transistor;
Equipped with
The switching control circuit includes:
a first error voltage generating circuit that generates a first error voltage according to an error between an output from the smoothing circuit and a first reference voltage;
a signal output circuit that outputs the drive signal for turning on the transistor when the inductor current reaches a predetermined current value, and outputs the drive signal for turning off the transistor based on the first error voltage so that a duty ratio of the drive signal reaches a predetermined value;
A power supply circuit including:

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