JP7611784B2 - Semiconductor Device - Google Patents

Description

The technology disclosed in this specification relates to semiconductor devices.

An overcurrent may flow through the main transistor that constitutes a semiconductor device. For example, if a malfunction such as a short circuit occurs in the load connected to the main transistor, an overvoltage equivalent to the power supply voltage is applied to the main transistor, and the current flowing through the main transistor increases to the saturation current. If the state in which the saturation current continues to flow, there is a risk that the main transistor will be thermally destroyed.

Patent document 1 discloses a semiconductor device in which a thermistor element whose electrical resistance has a negative temperature characteristic is connected between the control terminal and low-voltage side terminal of a main transistor. The thermistor element is arranged so as to be thermally coupled to the main transistor. When an overcurrent flows through the main transistor and the temperature of the main transistor rises, the temperature of the thermally coupled thermistor element also rises, and the electrical resistance value of the thermistor element decreases. This semiconductor device is configured so that when an overcurrent flows through the main transistor, the electrical resistance value of the thermistor element decreases, causing a short circuit between the control terminal and low-voltage side terminal of the main transistor, and turning off the main transistor. In this way, the semiconductor device of Patent document 1 is configured so that when an overcurrent flows through the main transistor, the main transistor is forcibly turned off, protecting it from thermal destruction.

Japanese Patent Application Publication No. 7-263459

In such a semiconductor device, it is desirable that the main transistor operates when the operating temperature is at a steady operating temperature, and that the main transistor quickly stops when the operating temperature becomes higher than the maximum rated operating temperature. That is, in such a semiconductor device, it is desirable that the protective operation be activated using the maximum rated operating temperature as a threshold value. Generally, thermistor elements have a small change in electrical resistance value in response to temperature changes. For this reason, in the technology of Patent Document 1, it is difficult for the thermistor element to respond sensitively to temperature, and therefore it is difficult to activate the protective operation using the maximum rated operating temperature as a threshold value. This specification provides a technology that can activate the protective operation using the maximum rated operating temperature as a threshold value.

One embodiment of the semiconductor device disclosed in this specification may include a main transistor and a protective diode. The main transistor has a control terminal, a high-voltage side terminal, and a low-voltage side terminal. The protective diode is connected between the control terminal and the low-voltage side terminal of the main transistor. The protective diode has an anode connected to the control terminal of the main transistor, a cathode connected to the low-voltage side terminal of the main transistor, and is configured to be thermally coupled to the main transistor. The protective diode includes a semiconductor substrate having a p-type anode layer, an n-type cathode layer, and an n-type drift layer between the anode layer and the cathode layer, the n-type drift layer having a lower donor concentration than the cathode layer. When the acceptor concentration in the anode layer is Na, the Fermi level is Eρ, the valence band upper end energy is Ev, the energy difference between the energy level of the acceptor in the anode layer and the upper end of the valence band is ΔEa, and the electron concentration in the drift layer is n _n- , when the operating temperature is a steady operating temperature Tc, Na/(1+exp(ΔEa/kTc)exp(-(Eρ-Ev)/kTc))<n _n- is satisfied, and when the operating temperature is higher than a maximum rated operating temperature Tm, Na/(1+exp(ΔEa/kTm)exp(-(Eρ-Ev)/kTm))>n _n- is satisfied. In this semiconductor device, the protective diode is connected in a forward direction from the control terminal of the main transistor to the low-voltage side terminal. However, the protective diode is configured such that the hole concentration of the anode layer is lower than the electron concentration of the drift layer when the operating temperature is the steady operating temperature Tc. Therefore, the protective diode is configured such that the hole injection efficiency is low and the current does not substantially flow when the operating temperature is the steady operating temperature Tc. On the other hand, the protective diode is configured such that the hole concentration of the anode layer is higher than the electron concentration of the drift layer when the operating temperature is higher than the maximum rated operating temperature Tm. Therefore, the protective diode is configured such that the hole injection efficiency is high and the current flows when the operating temperature is higher than the maximum rated operating temperature Tm. In this way, the above semiconductor device can operate the protective operation with the maximum rated operating temperature Tm as a threshold value.

In the semiconductor device of the above embodiment, the semiconductor substrate may be a wide band gap semiconductor. Furthermore, the semiconductor substrate may be gallium oxide. When the semiconductor substrate is gallium oxide, the acceptor contained in the anode layer may be bismuth or zinc. When the semiconductor substrate is a wide band gap semiconductor, the energy difference ΔEa between the energy level of the acceptor in the anode layer and the valence band edge is large. This makes it easier for the semiconductor device to satisfy the formula Na/(1+exp(ΔEa/kTc)exp(-(Eρ-Ev)/kTc))<n _n- at the steady-state operating temperature Tc.

1 shows an equivalent circuit diagram of the semiconductor device of the present embodiment. 1 is a schematic cross-sectional view of a main portion of a protective diode of a semiconductor device according to an embodiment of the present invention;

As shown in FIG. 1, the semiconductor device 1 includes a main transistor 2 and a protective diode 3. The main transistor 2 and the protective diode 3 are formed in the same semiconductor substrate. The main transistor 2 is an n-channel field effect transistor, specifically an n-type MOSFET. The main transistor 2 has a gate terminal G, which is a control terminal, a drain terminal D, which is a high-voltage side terminal, and a source terminal S, which is a low-voltage side terminal. The main transistor 2 may be an n-channel IGBT. The protective diode 3 has an anode electrically connected to the gate terminal G of the main transistor 2, and a cathode electrically connected to the source terminal S of the main transistor 2. In this way, the protective diode 3 is connected in a forward direction from the gate terminal G to the source terminal S of the main transistor 2.

As shown in FIG. 2, the protective diode 3 has a semiconductor substrate 10, a cathode electrode 22 that covers the back surface of the semiconductor substrate 10, and an anode electrode 24 that covers the front surface of the semiconductor substrate 10.

The semiconductor substrate 10 is not particularly limited, and may be, for example, gallium oxide ( _Ga2O3 ). Alternatively, the semiconductor substrate 10 may be a wide band gap semiconductor such as a nitride semiconductor or silicon _carbide . The semiconductor substrate 10 has an n ⁺ type cathode layer 12, an ^n- type drift layer 14, and a p-type anode layer 16.

The cathode layer 12 is an n-type region containing a donor. The donor is not particularly limited, but may be, for example, silicon, tin, or germanium. The cathode layer 12 is provided in the rear layer portion of the semiconductor substrate 10, disposed at a position exposed on the rear surface of the semiconductor substrate 10, and in ohmic contact with the cathode electrode 22. As described above, the cathode electrode 22 is electrically connected to the source terminal S of the main transistor 2. The donor concentration of the cathode layer 12 is not particularly limited, but may be, for example, 10 ¹⁸ to 10 ²⁰ cm ^-3 . The thickness of the cathode layer 12 is not particularly limited, but may be, for example, 1 to 5 μm.

The drift layer 14 is an n-type region having a lower donor concentration than the cathode layer 12. The donor is not particularly limited, but may be, for example, silicon, tin, or germanium. The drift layer 14 is provided between the cathode layer 12 and the anode layer 16, and separates the cathode layer 12 from the anode layer 16. The donor concentration of the drift layer 14 is not particularly limited, but may be, for example, 10 ¹³ to 10 ¹⁷ cm ^-3 . The thickness of the drift layer 14 is not particularly limited, but may be, for example, 5 to 10 μm.

The anode layer 16 is a p-type region containing an acceptor. The acceptor is not particularly limited, but may be, for example, bismuth or zinc. The anode layer 16 is provided in the surface layer portion of the semiconductor substrate 10, disposed at a position exposed on the surface of the semiconductor substrate 10, and is in ohmic contact with the anode electrode 24. As described above, the anode electrode 24 is electrically connected to the gate terminal G of the main transistor 2. The acceptor concentration of the anode layer 16 is not particularly limited, but may be, for example, 10 ¹⁸ to 10 ²⁰ cm ⁻³ . The thickness of the anode layer 16 is not particularly limited, but may be, for example, 1 to 5 μm.

The protective diode 3 is configured so that the hole concentration in the anode layer 16 is lower than the electron concentration in the drift layer 14 when the operating temperature is the steady-state operating temperature Tc, and the hole concentration in the anode layer 16 is higher than the electron concentration in the drift layer 14 when the operating temperature is higher than the maximum rated operating temperature Tm. Specifically, the protective diode 3 is configured so that the following formula 1 holds when the operating temperature is the steady-state operating temperature Tc, and the following formula 2 holds when the operating temperature is higher than the maximum rated operating temperature Tm.

Here, "Na" is the acceptor concentration in the anode layer 16, "Eρ" is the Fermi level, "Ec" is the conduction band bottom energy, "Ev" is the valence band top energy, "ΔEa" is the energy difference between the energy level of the acceptor in the anode layer 16 and the top of the valence band, "Nd" is the donor concentration in the drift layer 14, "ΔEd" is the energy difference between the energy level of the donor in the drift layer 14 and the conduction band bottom, and "k" is the Boltzmann constant.

The activation energy of the drift layer 14 is sufficiently low, and the donor concentration and the electron concentration of the drift layer 14 are substantially equal. Therefore, when the electron concentration of the drift layer 14 is “ _nn- ”, Equation 1 can be rewritten as Equation 3, and Equation 2 can be rewritten as Equation 4.

In this manner, the protection diode 3 is configured so that both of the above-mentioned formulas 3 and 4 are satisfied by adjusting the acceptor concentration Na in the anode layer 16, the energy difference ΔEa between the energy level of the acceptor in the anode layer 16 and the valence band edge, and the donor concentration Nd (i.e., the electron concentration n _n− ) in the drift layer 14.

Next, the operation of the semiconductor device 1 will be described. First, the behavior of the semiconductor device 1 during normal operation will be described. When a positive voltage is applied to the drain terminal D, the source terminal S is grounded, and a drive voltage that is more positive than the source terminal S is applied to the gate terminal G, the main transistor 2 turns on. When the operating temperature of the semiconductor device 1 is the steady operating temperature Tc, formula 3 is established, and the hole concentration of the anode layer 16 is lower than the electron concentration of the drift layer 14. Therefore, when the operating temperature of the semiconductor device 1 is the steady operating temperature Tc, the hole injection efficiency of the protective diode 3 is low, and substantially no current flows through the protective diode 3. Therefore, since there is no short circuit between the gate terminal G and the source terminal S, the main transistor 2 can operate normally. In this way, even if the protective diode 3 is provided in the semiconductor device 1, the normal operation of the main transistor 2 is not hindered.

Next, the behavior of the semiconductor device 1 during abnormal operation will be described. When a malfunction such as a short circuit occurs in the load connected to the semiconductor device 1, an overcurrent flows through the main transistor 2. When an overcurrent flows through the main transistor 2, the temperature of the semiconductor substrate 10 rises. Therefore, the temperature of the protective diode 3 formed in the semiconductor substrate 10 also rises. When the operating temperature of the semiconductor device 1 is higher than the maximum rated operating temperature Tm, the formula 4 is established, and the hole concentration of the anode layer 16 is higher than the electron concentration of the drift layer 14. Therefore, when the operating temperature of the semiconductor device 1 is higher than the maximum rated operating temperature Tm, the hole injection efficiency of the protective diode 3 is high, and a current flows through the protective diode 3. Therefore, since a short circuit occurs between the gate terminal G and the source terminal S, the main transistor 2 is forcibly turned off. By forcibly turning off the main transistor 2, the temperature rise of the semiconductor substrate 10 stops, and the main transistor 2 is protected from thermal destruction.

As described above, when both the above formulas 3 and 4 are satisfied, the semiconductor device 1 can activate a protective operation with the maximum rated operating temperature Tm as a threshold value.

The protective diode 3 is connected in the forward direction from the gate terminal G of the main transistor 2 to the source terminal S. However, the protective diode 3 is configured so that, by satisfying the above formula 3, no current actually flows when the operating temperature is the steady operating temperature Tc. In order to satisfy the above formula 3, it is desirable that the energy difference ΔEa between the energy level of the acceptor of the anode layer 16 and the valence band edge is large. Since the semiconductor substrate 10 of the protective diode 3 is a wide band gap semiconductor, the energy difference ΔEa is large. In particular, since the semiconductor substrate 10 of the protective diode 3 is gallium oxide, the energy difference ΔEa is extremely large. For example, when bismuth is used as the acceptor of the semiconductor substrate which is gallium oxide, the energy difference ΔEa becomes a large value of 0.8 eV. In this way, by using a wide band gap semiconductor for the semiconductor substrate 10, it is possible to easily satisfy the above formula 3. From this point of view, the energy difference ΔEa is not particularly limited, but may be, for example, 0.8 eV or more.

Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of those objectives is itself technically useful.

1: Semiconductor device 2: Main transistor 3: Protective diode 10: Semiconductor substrate 12: Cathode layer 14: Drift layer 16: Anode layer 22: Cathode electrode 24: Anode electrode D: Drain terminal G: Gate terminal S: Source terminal

Claims (4)

a main transistor having a control terminal, a high-side terminal and a low-side terminal;
a protection diode connected between the control terminal and the low-voltage side terminal of the main transistor, the protection diode having an anode connected to the control terminal of the main transistor and a cathode connected to the low-voltage side terminal of the main transistor and configured to be thermally coupled to the main transistor;
the protection diode includes a semiconductor substrate having a p-type anode layer, an n-type cathode layer, and an n-type drift layer between the anode layer and the cathode layer, the drift layer having a lower donor concentration than the cathode layer;
When the acceptor concentration in the anode layer is Na, the Fermi level is Eρ, the valence band top energy is Ev, the energy difference between the energy level of the acceptor in the anode layer and the top of the valence band is ΔEa, and the electron concentration in the drift layer is _n
When the operating temperature is the steady-state operating temperature Tc,
Na/(1+exp(ΔEa/kTc)exp(-(Eρ-Ev)/kTc))<n _n-
Fulfilling
When the operating temperature is higher than the maximum rated operating temperature Tm,
Na/(1+exp(ΔEa/kTm)exp(-(Eρ-Ev)/kTm))>n _n-
The semiconductor device is configured to satisfy the above. The semiconductor device according to claim 1, wherein the semiconductor substrate is a wide band gap semiconductor. The semiconductor device according to claim 2, wherein the semiconductor substrate is gallium oxide. The semiconductor device according to claim 3, wherein the acceptor contained in the anode layer is bismuth or zinc.

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