JP7604779B2 - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device.

Power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are used as switching devices for power conversion. In the package structure of semiconductor chips, the components between the semiconductor chip and the insulating circuit board are joined with a joining material such as solder or sintered material. In recent years, with the increasing performance of semiconductor chips, the joining materials between components are also required to have high continuous heat resistance and high reliability, and sintered materials, which have higher thermal conductivity and durability than solder, are increasingly being used.

When joining parts with a sintered material, the joining is achieved by inducing a sintering reaction in the sintered material. It is possible to induce a sintering reaction in the sintered material by heating alone without applying pressure, but if pressure is not applied, air bubbles will remain and properties such as thermal conductivity and strength will decrease. For this reason, a semiconductor chip is mounted on an insulated circuit board via a sintered material, and a pressure device is used to heat the semiconductor chip while applying pressure to the top surface with a mold, thereby inducing a sintering reaction in the sintered material and joining the parts. At this time, a uniform load must be applied to the sintered material to ensure the quality of the joint.

Patent Document 1 describes that an expandable membrane made of a sheet material, particularly a rubber-like material, is pressurized by fluid pressure to apply approximately the same contact pressure to the members regardless of the height difference between the members. Patent Document 2 describes that a convex portion is formed at the joint between the substrate electrode and the end face of the semiconductor element, and that this convex portion has a cut-off shape in the outer periphery direction. A buffer material is placed on the semiconductor element, and the sintered metal bonding material on the outer periphery of the semiconductor element is in contact with the buffer material. Patent Document 3 describes that the pressurizing unit includes a pair of transfer members that sandwich the assembly to transfer pressure and heat to the assembly, and a guide portion that movably connects the pair of transfer members.

Patent document 4 describes a method in which a bonding jig having a bonding material escape portion is used, and bonding material that protrudes from the outer periphery of the semiconductor element is pushed toward the substrate when the bonding material is pressure-bonded with the jig, and is forced into a groove in the excess bonding material absorption portion. Patent document 5 describes the provision of a pressure means for applying pressure to the semiconductor chip and wiring metal, a heating means for heating them, and a pressing means for pressing the discharged material discharged from the bonding interfaces of both to the outside of the semiconductor chip to a predetermined thickness.

Patent document 6 describes a bonding device including a stamp, a soft pad arranged on the stamp, and a pressure shaft arranged on the soft pad, in which the soft pad distributes pressure from the pressure shaft and the stamp presses the semiconductor chip to bond the semiconductor chip to an insulating circuit board with a sintered material. Patent document 7 describes a device for connecting a semiconductor chip to an insulating circuit board with a metal connection layer, which includes a buffer film on the semiconductor chip, a plunger arranged on the buffer film, a film made of polyurethane elastomer arranged on the plunger, and a pressure pad arranged on the film.

Special table 2017-525163 publication International Publication No. 2017/195399 International Publication No. 2016/157465 JP 2011-216772 A JP 2015-074001 A US Patent Application Publication No. 2012/0312864 US Patent Application Publication No. 2008/0096311

When bonding multiple semiconductor chips onto an insulated circuit board with a sintering material, a pressure device is used to simultaneously pressurize multiple semiconductor chips with a heated die. However, insulated circuit boards are becoming smaller, making it difficult to press the semiconductor chips individually at the same time using servos, hydraulics, etc. Furthermore, if the semiconductor chip is pressurized and heated alone while it is coated with a sintering material, the other sintering materials before bonding will undergo a sintering reaction without being pressurized. Furthermore, if the sintering material is applied and heated and pressurized for each semiconductor chip, heat and stress are applied to the components, resulting in quality degradation such as deterioration of strength.

In addition, when applying pressure to a large number of semiconductor chips with varying component dimensions, there is a problem of variation in the applied pressure. In addition, the sintered material that is exposed around the semiconductor chip is not pressurized, leaving many air bubbles and making it prone to chipping without being bonded to the electrodes. As a result, the chipped sintered material during manufacturing may fly around as foreign dust, reducing manufacturing quality.

In view of the above problems, the present invention aims to provide a semiconductor manufacturing device and a method for manufacturing a semiconductor device that can apply a uniform load to a sintered material when bonding multiple semiconductor chips to an insulated circuit board with the sintered material.

The gist of one aspect of the present invention is that it is a semiconductor manufacturing device that includes (a) a lower jig on which an insulating circuit board is placed when multiple semiconductor chips are bonded to the insulating circuit board with a sintered material, (b) an upper jig that is disposed opposite the lower jig and has an opening, (c) a first elastic member that is held in the opening of the upper jig, and (d) a buffer layer that is disposed between the lower jig and the first elastic member and is thinner than the first elastic member, and that sinters the sintered material by heating while applying pressure to the top surfaces of the multiple semiconductor chips with the first elastic member, thereby bonding the insulating circuit board and the multiple semiconductor chips.

Another aspect of the present invention is a method for manufacturing a semiconductor device, using a semiconductor manufacturing apparatus including a lower jig, an upper jig arranged opposite the lower jig and having an opening, a first elastic member held in the opening of the upper jig, and a buffer layer arranged between the lower jig and the first elastic member and thinner than the first elastic member, the method including: (a) placing an insulating circuit board on the lower jig when bonding multiple semiconductor chips to an insulating circuit board with a sintering material; (b) applying pressure to the top surfaces of the multiple semiconductor chips with the first elastic member; and (c) heating the board in a pressurized state to sinter the sintering material, thereby bonding the insulating circuit board and the multiple semiconductor chips.

The present invention provides a semiconductor manufacturing device and a method for manufacturing a semiconductor device that can apply a uniform load to the sintered material when bonding multiple semiconductor chips to an insulating circuit board with the sintered material.

1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention. 4 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view showing still another example of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing still another example of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view showing still another example of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing still another example of the semiconductor device according to the first embodiment. FIG. FIG. 11 is a cross-sectional view showing a state before pressure is applied to a semiconductor manufacturing apparatus according to a comparative example. FIG. 11 is a cross-sectional view showing a state during pressurization of a semiconductor manufacturing apparatus according to a comparative example. FIG. 2 is a cross-sectional view showing a forward warping state of an insulating circuit board. FIG. 2 is a cross-sectional view showing a negative warpage state of an insulating circuit board. FIG. 4 is a cross-sectional view showing a wavy state of an insulating circuit board. 2 is a cross-sectional view showing a state before pressure is applied to the semiconductor manufacturing apparatus according to the first embodiment. FIG. 1 is a graph showing the relationship between elastic body thickness and load variation rate depending on component area and member thickness tolerance. 4 is a cross-sectional view showing a state during pressurization of the semiconductor manufacturing apparatus according to the first embodiment. FIG. FIG. 11 is a cross-sectional view showing a state before pressure is applied to a semiconductor manufacturing apparatus according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a state during pressurization of the semiconductor manufacturing apparatus according to the second embodiment. FIG. 11 is a cross-sectional view showing a state before pressure is applied to a semiconductor manufacturing apparatus according to a third embodiment of the present invention. FIG. 11 is a cross-sectional view showing a state during pressurization of the semiconductor manufacturing apparatus according to the third embodiment. FIG. 13 is a cross-sectional view showing a state before pressure is applied to a semiconductor manufacturing apparatus according to a fourth embodiment of the present invention. FIG. 13 is a cross-sectional view showing a state during pressurization of the semiconductor manufacturing apparatus according to the fourth embodiment.

The first to fourth embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicate explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Furthermore, the first to fourth embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

In addition, the definitions of up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.

First Embodiment
<Semiconductor Device>
First, an example of a semiconductor device (semiconductor module) that can be manufactured by a semiconductor manufacturing apparatus according to a first embodiment of the present invention and a semiconductor manufacturing method using the same will be described with reference to Figures 1 to 6. The semiconductor device shown in Figure 1 includes a metal plate (metal base) 1 and an insulating circuit board 3 bonded onto the metal plate 1 via a bonding material 2a. The material of the metal plate 1 can be, for example, a metal such as copper (Cu).

The insulating circuit board 3 includes an insulating substrate 31, a first circuit layer 32 disposed on the lower surface of the insulating substrate 31, and a second circuit layer 33 disposed on the upper surface of the insulating substrate 31. The insulating circuit board 3 may be, for example, a direct copper bonded (DCB) substrate or an activated metal deposition (AMD) substrate. The insulating substrate 31 is composed of, for example, a ceramic substrate made of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), or a resin insulating substrate using a polymer material. The first circuit layer 32 and the second circuit layer 33 may be made of, for example, a conductor foil of copper (Cu), aluminum (Al), or the like.

The semiconductor chips 4a and 4b may be, for example, insulated gate bipolar transistors (IGBTs), field effect transistors (FETs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, etc., but here, the semiconductor chips 4a and 4b are FETs. The semiconductor chips 4a and 4b may be, for example, silicon (Si) substrates, or compound semiconductor substrates made of wide band gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga ₂ O ₃ ).

Although not shown, the semiconductor chips 4a and 4b each have a first main electrode (drain electrode) on the lower surface side, and a control electrode (gate electrode) and a second main electrode (source electrode) on the upper surface side. The first main electrodes of the semiconductor chips 4a and 4b are bonded to the second circuit layer 33 of the insulating circuit board 3 via the bonding materials 2b and 2c. Since the first main electrodes of the semiconductor chips 4a and 4b have the same potential, they may be bonded with a common bonding material instead of being bonded individually with the bonding materials 2b and 2c. The control electrodes and second main electrodes of the semiconductor chips 4a and 4b are connected to the second circuit layer 33 of the insulating circuit board 3 via the bonding wires 5a and 5b. The second circuit layer 33 of the insulating circuit board 3 is connected to the external terminals 6a and 6b via the bonding materials 2d and 2e.

As the joining materials 2a to 2e, for example, solder or sintered material can be used. As the solder, for example, tin (Sn)-based solder can be used. As the sintered material, for example, metal particle paste (conductive paste) containing metal particles such as silver (Ag)-based or copper (Cu)-based in a solvent can be used. The metal particles have a fine particle size of about several nm to several μm.

A sealing member 7 that seals the periphery of the semiconductor chips 4a and 4b is disposed on the metal plate 1. The sealing member 7 can be made of a resin material such as a hard thermosetting resin that has high heat resistance, and specifically, epoxy resin, maleimide resin, cyanate resin, etc. A terminal case 8 made of an insulating material is disposed on the metal plate 1 so as to surround the periphery of the sealing member 7.

The semiconductor device shown in FIG. 2 differs from the semiconductor device shown in FIG. 1 in that the semiconductor chip 4a is connected to the external terminal 6a via the bonding wire 5c, and the second circuit layer 33 of the insulating circuit board 3 is connected to the external terminal 6b via the bonding wire 5d. The semiconductor device shown in FIG. 3 differs from the semiconductor device shown in FIG. 1 in that the metal plate 1 is not provided on the lower surface of the insulating circuit board 3, and the first circuit layer 32 of the insulating circuit board 3 is exposed from the lower surface of the sealing member 7. The semiconductor device shown in FIG. 4 differs from the semiconductor device shown in FIG. 2 in that the metal plate 1 is not provided on the lower surface of the insulating circuit board 3, and the first circuit layer 32 of the insulating circuit board 3 is exposed from the lower surface of the sealing member 7.

The semiconductor device shown in FIG. 5 differs from the semiconductor device shown in FIG. 3 in that it includes implant substrates (9a, 9b, 9c, 10) arranged on the semiconductor chips 4a and 4b. The implant substrates (9a, 9b, 9c, 10) are composed of a printed circuit board 10 into which multiple pins 9a, 9b, and 9c are inserted. The printed circuit board 10 includes an insulating layer 11, a first wiring layer 12 arranged on the lower surface of the insulating layer 11, and a second wiring layer 13 arranged on the upper surface of the insulating layer 11.

_The insulating layer 11 is made of an insulating material such as a ceramic or a resin whose main component is, for example, _alumina ( _Al2O3 ), aluminum nitride (AlN), silicon nitride ( _Si3N4 ), etc. The insulating layer 11 may be a resin substrate made of a combination of glass fiber and epoxy resin, etc.

The first wiring layer 12 and the second wiring layer 13 are composed of a conductor foil made of, for example, copper (Cu) or aluminum (Al). The first wiring layer 12 and the second wiring layer 13 may be plated with copper (Cu), nickel (Ni), tin (Sn), or the like.

The multiple pins 9a, 9b are bonded to the semiconductor chips 4a, 4b via bonding materials 2f, 2g. The multiple pins 9c are bonded to the second circuit layer 33 of the insulating circuit board 3 via bonding material 2h. The multiple pins 9a, 9b, 9c are made of a metal material such as copper (Cu).

The semiconductor device shown in FIG. 6 differs from the semiconductor device shown in FIG. 5 in that it does not have a terminal case 8 and has a full mold structure in which the entire device is covered with a sealing member 7.

In the semiconductor device shown in Figures 1 to 6, as described above, solder or sintered material can be used as the bonding materials 2b, 2c used to bond the insulating circuit board 3 and the semiconductor chips 4a, 4b. Solder has low thermal conductivity and a low melting point, and its shear strength at the operating temperature of the semiconductor device is low. For example, tin (Sn)-based solder has a thermal conductivity of about 60 W/mK, a melting point of about 220°C to 280°C, and a shear strength of about 30 MPa to 40 MPa at 175°C.

On the other hand, since the melting point of the metal particles in the sintered material is high, the shear strength does not decrease at operating temperatures of about 150°C to 175°C, and therefore it can be used at even higher temperatures such as SiC chips and GaN chips. For example, the thermal conductivity of a silver (Ag)-based sintered material is about 400 W/mk, the thermal expansion coefficient is about 19×10 ^-6 /°C, and the melting point is about 960°C, so that the strength at the operating temperature is stable. Therefore, in the first embodiment, a case where a sintered material is used as the bonding materials 2b and 2c between the insulating circuit board 3 and the semiconductor chips 4a and 4b will be described.

Comparative Example
A method for manufacturing a semiconductor device according to a comparative example will be described below. In the method for manufacturing a semiconductor device according to the comparative example, as shown in Fig. 7, a sintered material 2 is applied onto an insulating circuit board 3, and multiple semiconductor chips 4a, 4b are mounted on the insulating circuit board 3 via the sintered material 2. Here, a case where the insulating circuit board 3 and the multiple semiconductor chips 4a, 4b are bonded with a common sintered material 2 is illustrated, but as in the semiconductor device shown in Figs. 1 to 6, the insulating circuit board 3 and the multiple semiconductor chips 4a, 4b may be bonded with individual bonding materials (sintered materials) 2b, 2c.

Then, the insulating circuit board 3 on which the multiple semiconductor chips 4a, 4b are mounted is placed on the lower die 201 of a pressure device (press machine). A sheet-like or film-like buffer layer 203 is placed on the multiple semiconductor chips 4a, 4b, and the upper die 202 of the press machine is placed on the buffer layer 203 so as to face the lower die 201.

As shown in FIG. 8, the upper die 202 of the press is lowered and the upper surfaces of the semiconductor chips 4a and 4b are heated while being pressed through the buffer layer 203, causing a sintering reaction (solid-phase sintering) in the sintering material 2 to bond the insulating circuit board 3 and the semiconductor chips 4a and 4b. Solid-phase sintering refers to the phenomenon in which the particles do not melt as a whole at temperatures below the melting point, but rather bonds are formed between the particles due to atomic diffusion, resulting in bonding.

In the manufacturing method of the semiconductor device according to the comparative example, when applying pressure to the top surfaces of the semiconductor chips 4a, 4b, it is difficult to apply uniform pressure to the sintered material 2 because of steps between areas on the sintered material 2 where there are multiple semiconductor chips 4a, 4b and areas where there are not, and steps due to multiple semiconductor chips 4a, 4b of different heights. As a result, the thickness and density of the sintered material 2 vary, the joining quality becomes unstable, and this leads to a shortened lifespan of the semiconductor device.

Furthermore, in the manufacturing method of the semiconductor device according to the comparative example, when pressure is applied to the top surfaces of the semiconductor chips 4a, 4b while the insulating circuit board 3 is warped, the thickness of the sintered material 2 becomes non-uniform, which may result in unstable bonding quality. Figure 9A shows the positive warpage state of the insulating circuit board 3. The amount of warping W1 of the insulating circuit board 3 is, for example, about 200 μm. Figure 9B shows the negative warpage state of the insulating circuit board 3. Figure 9C shows the undulating state of the insulating circuit board 3.

Furthermore, in the manufacturing method of the semiconductor device according to the comparative example, the sintered material 2 exposed around the semiconductor chips 4a and 4b is not pressurized. As a result, the sintered material 2 is prone to chipping (falling off) in later processes, and the chipped sintered material 2 may cause defects.

<Semiconductor manufacturing equipment>
The semiconductor manufacturing apparatus according to the first embodiment will be described below. As shown in Fig. 10, the semiconductor manufacturing apparatus according to the first embodiment is attached to a press machine and includes a lower mold 111 and an upper mold 112 that face each other in parallel. The semiconductor manufacturing apparatus according to the first embodiment may be configured not to include the lower mold 111 and the upper mold 112. Alternatively, the semiconductor manufacturing apparatus according to the first embodiment may be configured to include a part or the whole of the press machine to which the lower mold 111 and the upper mold 112 are attached.

As shown in FIG. 10, in the semiconductor manufacturing apparatus according to the first embodiment, a component is placed on an insulating circuit board 3 with multiple semiconductor chips 4a, 4b mounted thereon via a sintered material 2. The sintered material 2 is applied to the insulating circuit board 3 and dried, but is not sintered, and the multiple semiconductor chips 4a, 4b and the insulating circuit board 3 are not yet joined. The sintered material 2 is formed with an area larger than the multiple semiconductor chips 4a, 4b, and is exposed beyond the periphery of the multiple semiconductor chips 4a, 4b. There is no particular limit to the number of semiconductor chips mounted on the insulating circuit board 3, and it may be three or more.

The semiconductor manufacturing apparatus according to the first embodiment includes a lower jig 101 and an upper jig 102 arranged on the lower jig 101 so as to face it. The lower jig 101 is provided with a recess 101x. A component having multiple semiconductor chips 4a, 4b mounted on an insulating circuit board 3 via a sintered material 2 is placed in the recess 101x of the lower jig 101. The depth of the recess 101x is set so that the insulating substrate 31 of the insulating circuit board 3 fits within the recess 101x. The depth of the recess 101x may be the same as the thickness of the insulating circuit board 3, for example.

The lower jig 101 is placed on the lower die 111 of the press. The press has a built-in heating mechanism (heater), and the lower die 111 is heated by the heating mechanism. The position of the heating mechanism is not particularly limited, and the heating mechanism may be arranged separately from the press. The thickness of the central part around the recess 101x of the lower jig 101 is, for example, about 1 mm or more and 10 mm or less, but is not limited to this. The height of the outer periphery 101y surrounding the central part of the lower jig 101 is set higher than the central part in order to align it with the upper jig 102. The material of the lower jig 101 can be metal such as copper (Cu) or aluminum (Al), or carbon.

The upper jig 102 may be made of a metal such as copper (Cu) or aluminum (Al). The upper jig 102 is cylindrical with an opening, and holds a chip pressure mechanism (103, 104) in the opening. The chip pressure mechanism (103, 104) can move up and down within the opening of the upper jig 102.

The chip pressure mechanism (103, 104) has an elastic member 103 and a pressure block 104 arranged on the elastic member 103. The elastic member 103 and the pressure block 104 are arranged in contact with the inner peripheral surface of the opening of the upper jig 102, or arranged with a gap of about 1 mm or less from the inner peripheral surface of the opening. By surrounding the periphery of the elastic member 103 with the upper jig 102, it is possible to prevent the elastic member 103 from expanding horizontally in response to vertical pressure applied to the elastic member 103, thereby preventing the pressure from diffusing.

The elastic member 103 is, for example, cylindrical or rectangular. Heat-resistant rubber such as silicon (Si) rubber can be used as the elastic member 103. Examples of Si rubber include vinyl methyl silicone rubber (VMQ). Springs such as leaf springs and coil springs can also be used as the elastic member 103. The elastic member 103 elastically deforms to match the shapes of the semiconductor chips 4a, 4b and the sintered material 2 when pressure is applied to the top surfaces of the semiconductor chips 4a, 4b, and returns to its original shape after pressure is applied, so it can be used repeatedly.

The lower surface of the elastic member 103 is set so as to cover the entire upper surface of the semiconductor chips 4a, 4b. The lower surface of the elastic member 103 may be set so as to cover the entire upper surface of the insulating circuit board 3. The thickness T1 of the elastic member 103 in the up-down direction (vertical direction) is about 30 mm or more. The thickness T1 of the elastic member 103 may be, for example, about 30 mm or more and 50 mm or less, or may be about 50 mm or more. The static shear modulus of the elastic member 103 is, for example, about 0.3 MPa or more and 1.63 MPa or less, and is, for example, about 0.66 MPa for general Si rubber.

Here, the static spring constant Ks [N/m] of the elastic body is expressed by the following formula (1).

Ks=W/δ=Eap×AL/h…(1)

In formula (1), W is the load [N], δ is the deflection [m], Eap is the apparent Young's modulus [MPa], AL is the pressure-receiving area [ ^m2 ], h is the height of the elastic body [m], and G is the static shear modulus [MPa]. The apparent Young's modulus Eap for a cylinder and the apparent Young's modulus Eap for a rectangular prism are expressed by the following formulas (2) and (3), respectively.

Eap=G(3+4.94S ² )...(2)
Eap=G(3+6.58S ² )...(3)

In the formulas (2) and (3), S is the shape factor, and is expressed by the following formula (4).

S=AL/AF...(4)

In formula (4), AF is the free area [ ^m2 ], which is the total area of the part that can deform when a load is applied. Using formula (1), the thickness of the elastic body required to keep the load fluctuation rate caused by the step (about 1 mm) and tolerance (about 150 μm) of the part within 1% is calculated to be 30 μm or more.

Figure 11 shows the relationship between the elastic (rubber) thickness and the load fluctuation rate depending on the component area and component thickness tolerance. As shown in Figure 11, the larger the component area, the thicker the elastic body tends to be, but if the elastic body thickness is 30 μm or more, the load fluctuation rate caused by the component step (approximately 1 mm) and tolerance (approximately 150 μm) can be kept within 1%. The thickness T1 of the elastic member 103 and the material of the elastic member 103 can be selected appropriately depending on the type of semiconductor chips 4a, 4b, etc.

The material of the pressure block 104 shown in FIG. 10 can be a metal such as copper (Cu) or aluminum (Al). The upper die 112 of the press is placed on the pressure block 104.

Between the lower jig 101 and the upper jig 102, a buffer layer 105 is disposed. The buffer layer 105 corresponds to the buffer layer 203 used in the manufacturing method of the semiconductor device according to the comparative example shown in FIG. 8. The thickness of the buffer layer 105 is thinner than the thickness T1 of the elastic member 103, for example, about 50 μm or more and 500 μm or less. The buffer layer 105 has a function of preventing components such as the semiconductor chips 4a, 4b and the sintered material 2 from adhering to the elastic member 103, and also prevents damage to the components such as the semiconductor chips 4a, 4b due to dust fragments adhering to the elastic member 103 side. The buffer layer 105 also has a heat insulating function between the lower jig 101 and the upper jig 102. That is, since the semiconductor manufacturing apparatus according to the first embodiment is a bottom heating type that heats the lower jig 101 side, the buffer layer 105 blocks the transfer of heat from the lower jig 101 side to the upper jig 102 side.

The buffer layer 105 is made of a film material or ductile material that is difficult to stick to the semiconductor chips 4a, 4b and the sintered material 2, difficult to break, and has high flexibility and heat resistance. For example, a resin film such as polytetrafluoroethylene (PTFE) or a silicon (Si) film can be used as the buffer layer 105. The buffer layer 105 is plastically deformed when the semiconductor chips 4a, 4b are pressurized, and does not return to its original shape after pressurization, making it difficult to use repeatedly and requiring replacement after each use. Note that, since gas is generated from the sintered material 2, it is preferable that the buffer layer 105 does not seal the semiconductor chips 4a, 4b and the sintered material 2.

<Method of Manufacturing Semiconductor Device>
Next, an example of a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the first embodiment will be described.

As shown in FIG. 10, the sintered material 2 is applied to the insulating circuit board 3 by screen printing or the like. Then, the semiconductor chips 4a and 4b are mounted on the sintered material 2.

The insulating circuit board 3 on which the semiconductor chips 4a and 4b are mounted is mounted in the recess 101x of the lower jig 101, which is disposed between the lower die 111 and the upper die 112 of the press. A buffer layer 105 is disposed above the semiconductor chips 4a and 4b between the lower jig 101 and the upper jig 102.

Next, as shown in FIG. 12, the upper die 112 of the press is lowered, and the chip pressure mechanism (103, 104) presses and presses the upper surfaces of the semiconductor chips 4a, 4b. At this time, the elastic member 103 elastically deforms to match the shapes of the semiconductor chips 4a, 4b and the sintered material 2. Therefore, the sintered material 2 exposed around the semiconductor chips 4a, 4b is also pressurized and compacted by the elastic member 103. Furthermore, the elastic member 103 also presses the insulating circuit board 3 around the semiconductor chips 4a, 4b, thereby correcting the warping of the insulating circuit board 3 and flattening the insulating circuit board 3.

With the semiconductor chips 4a, 4b pressed, the lower jig 101 is heated by the heating mechanism, and the pressure and heat cause a sintering reaction in the sintered material 2. For example, the pressure is set to about 1 MPa or more and 60 MPa or less, the heating temperature is set to about 150°C or more and 350°C or less, and the heating time is set to about 1 to 5 minutes. This bonds the insulating circuit board 3 and the semiconductor chips 4a, 4b via the sintered material 2.

Then, the chip pressure mechanism (103, 104) and the upper jig 102 are removed, and the component with the semiconductor chips 4a, 4b bonded to the insulating circuit board 3 is taken out. Next, as shown in FIGS. 1 to 4, the semiconductor chips 4a, 4b are electrically connected to the external terminals 6a, 6b by wire bonding, and molded with a sealing member 7, or other normal processes can be used to realize the semiconductor device shown in FIGS. 1 to 4. Alternatively, as shown in FIGS. 5 and 6, the implant substrate (9a, 9b, 9c, 10) is mounted on the insulating circuit board 3 and the semiconductor chips 4a, 4b, and molded with a sealing member 7, or other normal processes can be used to realize the semiconductor device shown in FIGS. 5 and 6.

According to the semiconductor manufacturing apparatus of the first embodiment and the method of manufacturing a semiconductor device using this semiconductor manufacturing apparatus, the elastic member 103 applies pressure to the semiconductor chips 4a, 4b while elastically deforming, thereby suppressing variations in the pressure force due to variations in the dimensions of the components, and allowing for uniform pressure application. Furthermore, by making the thickness T1 of the elastic member 103 30 mm or more, it is possible to absorb the dimensional tolerance of the components and suppress the fluctuation rate of the pressure load to within 1%.

Furthermore, the elastic member 103 can also apply pressure to the sintered material 2 exposed around the semiconductor chips 4a and 4b to compress it, preventing the sintered material 2 from falling off the insulating circuit board 3 in later processes.

Furthermore, the elastic member 103 can also apply pressure to the insulating circuit board 3 around the semiconductor chips 4a and 4b to correct any warping of the insulating circuit board 3, and pressure can be applied to the sintered material 2 while the insulating circuit board 3 is flattened. This makes it possible to make the thickness of the sintered material 2 uniform, stabilizing the joining quality.

Furthermore, if the lower jig 101 does not have a recess 101x and the insulating circuit board 3 is placed on the lower jig 101 and pressure is applied, the protruding portion (creeping portion) of the insulating board 31 located on the outer periphery of the insulating circuit board 3 may be damaged. In contrast, by providing the recess 101x in the lower jig 101, damage to the insulating board 31 can be prevented.

Second Embodiment
As shown in FIG. 13, the semiconductor manufacturing apparatus according to the second embodiment of the present invention differs from the configuration of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10 in that the width of the chip pressure mechanisms (103 a, 104 a) is narrower than the width of the chip pressure mechanisms (103, 104) of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG.

The chip pressure mechanism (103a, 104a) includes an elastic member 103a and a pressure block 104a arranged on the elastic member 103a. The elastic member 103a has a thickness T1 of 30 mm or more, similar to the elastic member 103 of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10, and can be made of the same material as the elastic member 103. The pressure block 104a can be made of the same material as the pressure block 104 of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10.

Furthermore, the semiconductor manufacturing apparatus according to the second embodiment differs from the configuration of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10 in that it includes an intermediate jig 106 disposed between the lower jig 101 and the upper jig 102. The intermediate jig 106 can be made of the same material as the lower jig 101 and the upper jig 102. The intermediate jig 106 has an opening that corresponds to the position of the elastic member 103a and allows the elastic member 103a to move in the vertical direction. Furthermore, a positioning pin 108 is disposed on the intermediate jig 106. The positioning pin 108 is disposed in correspondence with a portion of the upper surface of the insulating circuit board 3 where the second circuit layer 33 is not present.

Furthermore, the semiconductor manufacturing apparatus according to the second embodiment differs from the configuration of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10 in that the lower jig 101 does not have an outer periphery 101y, and is provided with axial pins 107a and 107b that penetrate the lower jig 101, the middle jig 106, and the upper jig 102. The axial pins 107a and 107b make it easier to align the lower jig 101, the middle jig 106, and the upper jig 102.

Furthermore, the semiconductor manufacturing apparatus according to the second embodiment differs from the configuration of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10 in that it includes multiple substrate pressure mechanisms (103b, 104b), (103c, 104c). The multiple substrate pressure mechanisms (103b, 104b), (103c, 104c) are arranged in positions facing the periphery of the opening of the intermediate jig 106. The substrate pressure mechanisms (103b, 104b) include an elastic member 103b and a pressure block 104b arranged on the elastic member 103b. The pressure mechanisms (103c, 104c) include an elastic member 103c and a pressure block 104c arranged on the elastic member 103c.

The elastic members 103b and 103c may be made of the same material as the elastic member 103a. The pressure blocks 104b and 104c may be made of the same material as the pressure block 104a. The other configurations of the semiconductor manufacturing apparatus according to the second embodiment are the same as those of the semiconductor manufacturing apparatus according to the first embodiment shown in FIG. 10, so duplicated descriptions will be omitted.

In the method of manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the second embodiment, as shown in FIG. 13, a component in which semiconductor chips 4a and 4b are mounted on an insulating circuit board 3 via a sintered material 2 is mounted in a recess 101x of a lower jig 101 arranged between a lower die 111 and an upper die 112 of a press machine. Then, as shown in FIG. 14, a plurality of board pressure mechanisms (103b, 104b), (103c, 104c) press the upper surface of the insulating circuit board 3 via a middle jig 106, thereby correcting the warpage of the insulating circuit board 3. In addition, the chip pressure mechanisms (103a, 104a) press and press the upper surfaces of the semiconductor chips 4a and 4b. At this time, the elastic member 103a elastically deforms according to the shapes of the semiconductor chips 4a and 4b and the sintered material 2. Therefore, the sintered material 2 exposed around the semiconductor chips 4a and 4b is also pressed and compacted by the elastic member 103a.

With the semiconductor chips 4a and 4b pressed, the lower jig 101 is heated by the heating mechanism, and the pressure and heat cause a sintering reaction in the sintered material 2. The other steps of the method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the second embodiment are similar to those of the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 12, so duplicated explanations will be omitted.

According to the semiconductor manufacturing apparatus of the second embodiment and the method of manufacturing a semiconductor device using this semiconductor manufacturing apparatus, as in the first embodiment, the elastic member 103a applies pressure to the semiconductor chips 4a, 4b while deforming, thereby suppressing variations in the pressure force due to variations in the dimensions of the components, and allowing for uniform pressure application. Furthermore, by making the thickness T1 of the elastic member 103 30 mm or more, it is possible to absorb the dimensional tolerance of the components and suppress the fluctuation rate of the pressure load to within 1%.

Furthermore, as the elastic member 103a deforms, it also applies pressure to the sintered material 2 exposed around the semiconductor chips 4a and 4b, thereby preventing the sintered material 2 from falling off from the insulating circuit board 3 in a later process.

Furthermore, the insulating circuit board 3 around the semiconductor chips 4a and 4b can be pressurized by the multiple board pressure mechanisms (103b, 104b), (103c, 104c) and the intermediate jig 106 to correct the warping of the insulating circuit board 3, and the sintered material 2 can be pressurized in a state where the insulating circuit board 3 is flattened. This makes it possible to make the thickness of the sintered material 2 uniform and stabilize the joining quality.

Third Embodiment
As shown in Fig. 15, the semiconductor manufacturing apparatus according to the third embodiment of the present invention is different from the semiconductor manufacturing apparatus according to the second embodiment shown in Fig. 13 in that an elastic member 103a holds a plurality of semiconductor chips 4a, 4b before pressure is applied. A plurality of recesses 103x, 103y are provided on the lower surface of the elastic member 103a, and a plurality of semiconductor chips 4a, 4b are disposed in each of the recesses 103x, 103y. The depth of the recesses 103x, 103y can be appropriately set according to the thickness of the semiconductor chips 4a, 4b. The other configurations of the semiconductor manufacturing apparatus according to the third embodiment are the same as those of the semiconductor manufacturing apparatus according to the second embodiment shown in Fig. 13, so that a duplicated description will be omitted.

In the method of manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the third embodiment, as shown in FIG. 15, multiple semiconductor chips 4a, 4b are attached to multiple recesses 103x, 103y on the lower surface of the elastic member 103a. Meanwhile, an insulating circuit board 3 coated with a sintering material 2 is mounted in the recess 101x of the lower jig 101 arranged between the lower die 111 and the upper die 112 of the press machine.

As shown in FIG. 16, the middle jig 106 applies pressure to the top surface of the insulating circuit board 3, thereby correcting the warpage of the insulating circuit board 3. The semiconductor chips 4a and 4b are brought into contact with the sintered material 2 and pressurized by the elastic member 103a. The other steps of the method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the third embodiment are the same as those of the method for manufacturing a semiconductor device according to the second embodiment shown in FIG. 14, so duplicated explanations will be omitted.

According to the semiconductor manufacturing apparatus of the third embodiment and the method of manufacturing a semiconductor device using this semiconductor manufacturing apparatus, as in the first and second embodiments, the elastic member 103a presses the semiconductor chips 4a, 4b, suppressing variations in the pressure force due to variations in the dimensions of the components, and allowing for uniform pressure application. Furthermore, by making the thickness T1 of the elastic member 103a 30 mm or more, the dimensional tolerance of the components can be absorbed and the fluctuation rate of the pressure load can be suppressed to within 1%.

Furthermore, the elastic member 103a also applies pressure to the sintered material 2 exposed around the semiconductor chips 4a and 4b, thereby preventing the sintered material 2 from falling off from the insulating circuit board 3 in a later process.

Furthermore, the intermediate jig 106 can apply pressure to the insulating circuit board 3 around the semiconductor chips 4a and 4b to correct any warping of the insulating circuit board 3, and pressure can be applied to the sintered material 2 while the insulating circuit board 3 is in a flattened state. This makes it possible to make the thickness of the sintered material 2 uniform, stabilizing the joining quality.

Fourth Embodiment
As shown in Fig. 17, the semiconductor manufacturing apparatus according to the fourth embodiment of the present invention is different from the configuration of the semiconductor manufacturing apparatus according to the second embodiment shown in Fig. 13 in that it includes a plurality of chip pressure mechanisms (103d, 104d, 104e), (103e, 104f, 104g). The plurality of chip pressure mechanisms (103d, 104d, 104e), (103e, 104f, 104g) are arranged to correspond to the plurality of semiconductor chips 4a, 4b, respectively.

The chip pressure mechanism (103d, 104d, 104e) includes an elastic member 103d and a pressure block (104d, 104e). The pressure block (104d, 104e) includes a pressure part 104d arranged below the elastic member 103d and a fixed part 104e that penetrates the elastic member 103d above the pressure part 104d. The chip pressure mechanism (103e, 104f, 104g) includes an elastic member 103e and a pressure block (104f, 104g). The pressure block (104f, 104g) includes a pressure part 104f arranged below the elastic member 103e and a fixed part 104g that penetrates the elastic member 103e above the pressure part 104f.

The pressure blocks (104d, 104e), (104f, 104g) can be made of the same material as the pressure block 104a of the semiconductor manufacturing apparatus according to the second embodiment shown in FIG. 13. The pressure units 104d, 104f apply pressure by directly contacting the semiconductor chips 4a, 4b.

The thickness T1 of the elastic members 103d and 103e is 30 mm or more, and the material of the elastic members 103d and 103e can be the same as that of the elastic member 103a of the semiconductor manufacturing apparatus according to the second embodiment shown in FIG. 13. The elastic members 103d and 103e indirectly pressurize the semiconductor chips 4a and 4b via the pressure members 104d and 104f without directly contacting the semiconductor chips 4a and 4b.

Furthermore, the semiconductor manufacturing apparatus according to the fourth embodiment differs from the configuration of the semiconductor manufacturing apparatus according to the second embodiment shown in FIG. 13 in that it includes multiple substrate pressure mechanisms (103f, 104h, 104i), (103g, 104j, 104k). The multiple substrate pressure mechanisms (103f, 104h, 104i), (103g, 104j, 104k) are disposed at positions corresponding to the periphery of the opening of the intermediate jig 106.

The substrate pressure mechanism (103f, 104h, 104i) includes an elastic member 103f and a pressure block (104h, 104i). The pressure block (104h, 104i) includes a pressure section 104h arranged below the elastic member 103f and a fixed section 104i that penetrates the elastic member 103f above the pressure section 104h. The substrate pressure mechanism (103g, 104j, 104k) includes an elastic member 103g and a pressure block (104j, 104k). The pressure block (104j, 104k) includes a pressure section 104j arranged below the elastic member 103g and a fixed section 104k that penetrates the elastic member 103g above the pressure section 104j.

The elastic members 103f and 103g may be made of the same material as the elastic members 103d and 103e. The pressure blocks (104h, 104i), (104j, 104k) may be made of the same material as the pressure blocks (104d, 104e), (104f, 104g). The other configurations of the semiconductor manufacturing apparatus according to the fourth embodiment are the same as those of the semiconductor manufacturing apparatus according to the second embodiment shown in FIG. 13, so duplicated explanations will be omitted.

In the method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the fourth embodiment, as shown in FIG. 17, a sintered material 2 is applied onto an insulating circuit board 3, and a part carrying semiconductor chips 4a and 4b is mounted in a recess 101x of a lower jig 101 arranged between a lower die 111 and an upper die 112 of a press machine.

18, the upper die 112 of the press is lowered to pressurize the upper jig 102, thereby pressurizing the chip pressurizing mechanisms (103d, 104d, 104e), (103e, 104f, 104g) and the board pressurizing mechanisms (103f, 104h, 104i), (103g, 104j, 104k). As a result, the board pressurizing mechanisms (103f, 104h, 104i), (103g, 104j, 104k) pressurize the insulated circuit board 3 via the middle jig 106, thereby correcting the warpage of the insulated circuit board 3. On the other hand, the chip pressure mechanisms (103d, 104d, 104e), (103e, 104f, 104g) have pressure sections 104d, 104f in contact with the semiconductor chips 4a, 4b, respectively, to pressurize the semiconductor chips 4a, 4b. At this time, the semiconductor chips 4a, 4b are heated in a pressurized state to sinter the sintered material 2. The other steps of the method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the fourth embodiment are the same as those of the method for manufacturing a semiconductor device according to the second embodiment shown in FIG. 14, so that repeated explanations will be omitted.

According to the semiconductor manufacturing apparatus of the fourth embodiment and the method of manufacturing a semiconductor device using this semiconductor manufacturing apparatus, as in the first to third embodiments, the chip pressure mechanisms (103d, 104d, 104e), (103e, 104f, 104g) apply pressure to the semiconductor chips 4a, 4b while deforming the elastic members 103d, 103e, thereby suppressing variations in pressure caused by variations in component dimensions and allowing for uniform pressure application. Furthermore, by making the thickness T1 of the elastic members 103a, 103b 30 mm or more, it is possible to absorb the dimensional tolerance of the components and suppress the fluctuation rate of the pressure load to within 1%.

Furthermore, by using multiple chip pressure mechanisms (103d, 104d, 104e), (103e, 104f, 104g), the elastic members 103d, 103e are deformed while the sintered material 2 exposed around the semiconductor chips 4a, 4b is also compressed and compacted, thereby preventing the sintered material 2 from falling off from the insulating circuit board 3 in a later process.

Furthermore, the substrate pressure mechanisms (103f, 104h, 104i), (103g, 104j, 104k) and the intermediate jig 106 can apply pressure to the insulating circuit board 3 around the semiconductor chips 4a and 4b to correct the warping of the insulating circuit board 3, and pressure can be applied to the sintered material 2 while the insulating circuit board 3 is flattened. This makes it possible to make the thickness of the sintered material 2 uniform, stabilizing the joining quality.

Other Embodiments
As described above, the present invention has been described by the first to fourth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

For example, the semiconductor device according to the first to fourth embodiments is exemplified as a case in which one component having multiple semiconductor chips 4a, 4b mounted on an insulating circuit board 3 via a sintered material 2, but the present invention is not limited to this. For example, multiple configurations similar to those of the semiconductor manufacturing apparatus according to the first to fourth embodiments may be arranged between the lower die 111 and upper die 112 of a press machine, and components may be placed on each of the multiple pieces to perform pressure and heat application.

In this way, if one of ordinary skill in the art understands the gist of the technical content disclosed in the above embodiment, it will be clear that various alternative embodiments, examples, and operational techniques can be included in the present invention. Furthermore, the present invention naturally includes various embodiments not described here, such as configurations that arbitrarily apply each configuration described in the above embodiment and each modified example. Therefore, the technical scope of the present invention is determined only by the invention-specific matters related to the claims that are appropriate from the above exemplary explanation.

1...Metal plate (metal base)
2...sintered material 2a to 2h...bonding material 3...insulating circuit board 4a, 4b...semiconductor chips 5a to 5d...bonding wires 6a, 6b...external terminal 7...sealing member 8...terminal cases 9a to 9c...pin 10...printed circuit board 11...insulating layer 12...first wiring layer 13...second wiring layer 31...insulating substrate 32...first circuit layer 33...second circuit layer 101...lower jig 101x...recess 101y...periphery 102...upper Jig 103, 103a to 103g...elastic member 103x, 103y...recess 104, 104a to 104c...pressure block 104d, 104f, 104h, 104j...pressure portion 104e, 104g, 104i, 104k...fixed portion 105, 203...buffer layer 106...intermediate jig 107a, 107b...axis pin 108...positioning pin 111, 201...lower mold 112, 202...upper mold

Claims (11)

a lower jig on which an insulating circuit board is placed when a plurality of semiconductor chips are bonded to the insulating circuit board with a sintered material;
An upper jig disposed on the lower jig so as to face the lower jig and having an opening;
A first elastic member held in the opening of the upper jig;
a buffer layer disposed between the lower jig and the first elastic member and thinner than the first elastic member;
Equipped with
the upper surfaces of the plurality of semiconductor chips are heated while being pressed by the first elastic member to sinter the sintered material, thereby bonding the insulating circuit board and the plurality of semiconductor chips;
the sintered material is exposed from the periphery of the plurality of semiconductor chips;
a lower end of the upper jig contacts the lower jig via the buffer layer, and the opening of the upper jig surrounds the periphery, including the lower end, of the first elastic member, and presses the sintered material exposed around the semiconductor chips together with the plurality of semiconductor chips. The semiconductor manufacturing device according to claim 1, characterized in that the thickness of the first elastic member is 30 mm or more. The semiconductor manufacturing device according to claim 1 or 2, characterized in that the lower jig is provided with a recess in which the insulating circuit board is placed. a lower jig on which an insulating circuit board is placed when a plurality of semiconductor chips are bonded to the insulating circuit board with a sintered material;
An upper jig disposed on the lower jig so as to face the lower jig and having an opening;
A first elastic member held in the opening of the upper jig;
a buffer layer disposed between the lower jig and the first elastic member and thinner than the first elastic member;
a middle jig disposed between the lower jig and the buffer layer, the middle jig having an opening at a position corresponding to the first elastic member;
A second elastic member held around the first elastic member of the upper jig;
Equipped with
the upper surfaces of the plurality of semiconductor chips are heated while being pressed by the first elastic member to sinter the sintered material, thereby bonding the insulating circuit board and the plurality of semiconductor chips;
a second elastic member and a middle jig for applying pressure to an upper surface of the insulating circuit board around a portion on which the semiconductor chip is mounted, The semiconductor manufacturing apparatus according to claim 4, further comprising an axial pin passing through the lower jig, the middle jig, and the upper jig. A plurality of recesses are provided on a lower surface of the first elastic member,
6. The semiconductor manufacturing apparatus according to claim 1, wherein the semiconductor chips are held in the recesses of the first elastic member before pressure is applied by the first elastic member. The first elastic member is divided into a plurality of parts,
6. The semiconductor manufacturing apparatus according to claim 1, wherein each of the plurality of first elastic members presses each of the plurality of semiconductor chips. The device further includes a plurality of pressure blocks respectively disposed on the lower surface sides of the plurality of first elastic members,
8. The semiconductor manufacturing apparatus according to claim 7, wherein each of the first elastic members presses each of the semiconductor chips via each of the pressure blocks. The semiconductor manufacturing device according to any one of claims 1 to 8, characterized in that the multiple semiconductor chips are bonded with a common sintered material. The semiconductor manufacturing device according to any one of claims 1 to 9, characterized in that the static shear modulus of the first elastic member is 0.3 MPa or more and 1.63 MPa or less. a semiconductor manufacturing apparatus including a lower jig, an upper jig disposed on the lower jig so as to face the lower jig and having an opening, a first elastic member held in the opening of the upper jig, and a buffer layer disposed between the lower jig and the first elastic member and thinner than the first elastic member,
When bonding a plurality of semiconductor chips onto an insulating circuit board with a sintered material, the insulating circuit board is placed on the lower jig;
Pressing the upper surfaces of the plurality of semiconductor chips with the first elastic member;
sintering the sintered material by heating under the pressure to bond the insulating circuit board and the semiconductor chips;
the sintered material is exposed from the periphery of the plurality of semiconductor chips;
a lower end of the upper jig contacts the lower jig via the buffer layer, and the opening of the upper jig surrounds the periphery, including the lower end, of the first elastic member, and presses the sintered material exposed around the semiconductor chips together with the multiple semiconductor chips.

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