JP7603440B2 - Solid-state imaging element and imaging device - Google Patents

Description

The present invention relates to a solid-state imaging element and an imaging device, and more specifically to a solid-state imaging element and an imaging device equipped with a photoelectric conversion means that can capture high-definition images by miniaturizing the pixel size to make the imaging element more compact and increase the number of pixels.

Conventionally, in solid-state imaging devices, for example CMOS imaging devices, pixel reset noise has been removed by combining a four-transistor type pixel with an analog CDS (see Non-Patent Document 1 below) so that high-quality images with less noise can be captured, and technological developments for improving image quality have been progressing.
A circuit diagram and driving waveforms of such a four-transistor type unit pixel 102'' will be described as Prior Art 1 (simply shown as Prior Art in FIGS. 13 and 14) with reference to FIGS.

FIG. 13 shows an n-type photoelectric conversion unit 1219 and an n-type floating diffusion capacitance 1213, and these n-type photoelectric conversion unit 1219 and n-type floating diffusion capacitance 1213 are sites that generate dark current in the four-transistor pixel.
The time for which the dark current of the n-type photoelectric conversion unit 1219 is accumulated is one imaging frame interval as shown in Fig. 14, and is 16.667 milliseconds when the frame frequency is 60 Hz. If the dark current value of the n-type photoelectric conversion unit 1219 is 10 electrons/second/pixel, the dark current value per frame is about 0.167 electrons/frame/pixel, which is a negative dark current value. In addition, the time for which the dark current of the n-type floating diffusion capacitance 1213 is accumulated is shorter than one horizontal scanning period (7680 pixels in the X direction and 4320 pixels in the Y direction, 3.7 microseconds when the frame frequency is 60 Hz), so if the dark current value of the n-type floating diffusion capacitance 1213 is 510 electrons/second/pixel, the dark current value per frame is about 0.002 electrons/frame/pixel or less, which is a negative dark current value (see Non-Patent Document 2 below).

On the other hand, as pixel sizes become smaller, the area of the photoelectric conversion section that converts light into an electrical signal becomes smaller, which leads to a problem of reduced sensitivity. To improve sensitivity, photoelectric conversion film stacking structures have attracted attention and research and development is underway (see Non-Patent Document 3 below). Among such photoelectric conversion film stacking type solid-state imaging devices, those in which each unit pixel is of a three-transistor type are known (see Patent Document 1 below).

Such a photoelectric conversion film stacked type three-transistor pixel will be described using its circuit diagram and driving waveforms as Prior Art 2. Note that, for convenience, the description will be given using Figs. 2 and 3 used in the examples.
FIG. 2 shows a photoelectric conversion film 211 and an n-type floating diffusion capacitance 213. The photoelectric conversion film 211 and the n-type floating diffusion capacitance 213 are portions that generate dark current in the photoelectric conversion film stacked three-transistor type.
The time for which the dark current of the photoelectric conversion film 211 is accumulated is one imaging frame interval as shown in Fig. 3, which is 16.667 milliseconds when the frame frequency is 60 Hz, so if the dark current value is 100 pA/ ^cm2 (see Non-Patent Document 4 below) and the pixel size is 2.8 x 2.8 ^µm2 , the dark current value per frame is about 0.8 electrons/frame/pixel. Also, unlike the four-transistor type, the time for which the dark current of the n-type floating diffusion capacitance 213 is accumulated is one imaging frame interval, so if the dark current value of the n-type floating diffusion capacitance 213 is 510 electrons/second/pixel, the dark current value per imaging frame is about 8.5 electrons/frame/pixel (see Non-Patent Document 2 below).

JP 2013-070181 A

M. H. White et al., “Characterization of Surface Channel CCD Image Arrays at Low Light Levels,” IEEE Journal of Solid-State Circuits, Vol. 9, No. 1, pp. 1-12, 1972. Arai et al., "Dark current evaluation of 3Tr pixel circuits for photoelectric conversion film stacked 8K imaging devices," Institute of Image Information and Television Engineers Annual Conference, 12C-5, 2018 S. Imura et al., “High-Sensitivity Image Sensors Overlaid With Thin-Film Gallium Oxide/Crystalline Selenium Heterojunction Photodiodes,” IEEE Transactions on Electron Devices, Vol. 63, No. 1, pp. 86-91, 2016. S. Imura et al., “Low-dark-current photodiodes comprising highly (100)-oriented hexagonal selenium with crystallinity-enhanced tellurium nucleation layers,” IEEE Sensors Journal, Vol. 18, No. 8, pp. 3108-3113, 2018.

In the case of the four-transistor pixel of prior art 1 described above, the dark current of the n-type photoelectric conversion unit 1219 is electrons, and the dark current of the n-type floating diffusion capacitance 1213 is also electrons, so the dark current value of the node where the n-type photoelectric conversion unit 1219 and the n-type floating diffusion capacitance 1213 are connected is approximately 0.169 electrons/frame/pixel, which is the sum of the dark current values of both, and the absolute value of this is even greater than the absolute value of each of them.

On the other hand, in the case of the photoelectric conversion film stacked type three-transistor pixel of prior art 2 described above, the dark current of the photoelectric conversion film 211 is electrons, and the dark current of the n-type floating diffusion capacitance 213 is also electrons, so the dark current value of the node where the photoelectric conversion film 211 and the n-type floating diffusion capacitance 213 are connected is approximately 9.3 electrons/frame/pixel, which is the sum of the dark current values of both, and the absolute value of this is even greater than the absolute value of each of them.

In this way, the dark current value of the n-type photoelectric conversion unit 1219 or the n-type photoelectric conversion film 211 and the dark current value of the n-type floating diffusion capacitance 1213, 213 are added at the connecting node, increasing the absolute value, and the charge amount of the increased dark current is added to the original signal charge amount generated by the photoelectric conversion operation of the n-type photoelectric conversion unit 1219 or the photoelectric conversion film 211, resulting in a problem that a value with an increased error from the original pixel output signal value is output.

The present invention has been made in consideration of the above circumstances, and aims to provide a solid-state imaging element and imaging device that can reduce errors in pixel output signal values by making the absolute value of the sum of dark currents at the node where the dark currents of the photoelectric conversion means and the floating diffusion capacitance join in each pixel smaller.

The solid-state imaging device according to the present invention comprises:
A CMOS-type solid-state imaging device in which a photoelectric conversion means, either a photoelectric conversion film made of a laminate or a photoelectric conversion unit made of a photodiode, is disposed on a pixel circuit, and is disposed for each unit pixel ,
The pixel circuit is configured to have a transistor portion disposed on a substrate, or to have a well disposed on a substrate and a transistor portion disposed in the well;
One of the electron-hole pairs generated by photoelectric conversion is used as a carrier for the photoelectric conversion means,
the dark current of the photoelectric conversion means has carriers of either holes or electrons, and the dark current of a floating diffusion capacitance formed from the source of the reset transistor has carriers of either holes or electrons,
a dark current from the photoelectric conversion means is configured to merge with a dark current generated in the floating diffusion capacitance without merging with a dark current from another photoelectric conversion means;
The total value of the dark currents at a node where the dark currents of the photoelectric conversion means and the floating diffusion capacitance join together is set to a desired absolute value that is smaller than the absolute values of the dark current value of the photoelectric conversion means and the dark current value of the floating diffusion capacitance.

In the solid-state imaging device according to the present invention, the photoelectric conversion means is a photoelectric conversion film made of a laminate disposed on the pixel circuit,
The photoelectric conversion film includes a photoelectric conversion layer that performs a photoelectric conversion process, and is configured to have a film electrode laminated on the top layer;
A predetermined membrane voltage is applied to the membrane electrode relative to the reset voltage of the pixel electrode,
The membrane voltage may be set so that the sum of the dark currents at the nodes is a desired absolute value .

In this case, the carriers of the dark current in the photoelectric conversion film are holes, and the absolute value of the dark current is small when the film voltage is low and large when the film voltage is high; on the other hand, the floating diffusion capacitance is n-type, the carriers of the dark current are electrons, and the magnitude of the dark current is constant regardless of the level of the film voltage;
The sum of the dark currents at the nodes can be configured to be negative when the membrane voltage is low and positive when the membrane voltage is high, and the membrane voltage can be set so that the sum of the dark currents at the nodes becomes the desired absolute value.

Furthermore, in the solid-state imaging device according to the present invention, the photoelectric conversion means is a photoelectric conversion unit formed of a photodiode,
The area of the photoelectric conversion portion and the area of the floating diffusion capacitance may be set so that the total value of the dark currents at the nodes has a desired absolute value .

In this case, the photoelectric conversion section is of p-type, the carriers of the dark current are holes, and the larger the area of the photoelectric conversion section, the larger the absolute value of the positive dark current becomes; on the other hand, the floating diffusion capacitance is of n-type, the carriers of the dark current are electrons, and the larger the area of the floating diffusion capacitance, the larger the absolute value of the negative dark current becomes;
The area of the photoelectric conversion portion and the area of the floating diffusion capacitance may be set so that the sum of the dark currents at the nodes becomes the desired absolute value.

In any of the solid-state imaging devices described above, it is preferable that the desired absolute value is zero.
An imaging device according to the present invention includes any one of the solid-state imaging elements described above, and includes means for outputting image information obtained by the solid-state imaging element.

In the solid-state imaging element and imaging device of the present invention, the carriers of one of the dark currents of the photoelectric conversion means and the dark current of the floating diffusion capacitance are holes and the carriers of the other are electrons, and the absolute value of the sum of these dark currents at the node where these two dark currents join together is set to a desired absolute value that is smaller than each of the absolute values of the two dark currents.
In other words, the carriers of the two dark currents, which are generated due to independent factors, are set as holes and electrons, and a specific element that can vary each dark current value is set to a specific value, so that the two dark currents cancel each other out in positive and negative, thereby reducing the absolute value of the total dark current value.

This makes it possible to obtain a solid-state imaging element and an imaging device that can reduce errors from the original signal values of the output signals caused by an increase in the absolute value of the dark current of the node and obtain pixel output signals with high accuracy.
It is desirable to set the absolute value of the sum of these dark currents to 0, but if the absolute value can be set to be smaller than the absolute values of the dark currents of the photoelectric conversion means and the floating diffusion capacitance, it is possible to obtain a solid-state imaging element and an imaging device that can reduce errors in pixel output signal values compared to conventional technology.

1 is a diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention (the same applies to a second embodiment). FIG. 2 is a circuit diagram showing an equivalent circuit of a film-stacked type three-transistor pixel circuit according to the first embodiment. 11 shows a time chart of signals input to pixel circuits when signal readout is performed in the solid-state imaging device according to the first embodiment (the same applies to the second embodiment). 4A to 4D are schematic diagrams showing energy bands at timings (a), (b), (c), and (d) of the signal timing chart shown in FIG. 3 in the solid-state imaging element according to the first embodiment. 1 is a schematic cross-sectional view of a pixel portion of a solid-state imaging element according to a first embodiment. FIG. 6 is a band diagram taken along the line AA' in FIG. 5, showing the state during resetting. 6 is a graph showing the relationship between the dark current value of the photoelectric conversion layer, the dark current value of the n-type floating diffusion capacitance, and the total value of the dark current at the node where the dark current from the photoelectric conversion layer and the dark current of the n-type floating diffusion capacitance join together, and the membrane voltage, in the pixel portion of the solid-state imaging element of the first embodiment shown in FIG. FIG. 11 is a circuit diagram showing an equivalent circuit of a three-transistor pixel circuit in which a p-type photoelectric conversion unit according to the second embodiment is arranged. 5A to 5D are schematic diagrams showing energy bands at timings (a), (b), (c), and (d) of the signal timing chart shown in FIG. 3 in a solid-state imaging element according to a second embodiment. 13 is a schematic cross-sectional view of a pixel portion of a solid-state imaging element according to a second embodiment. FIG. 13 is a table showing the total value of dark current in pixels A and B in which the areas and dark currents of the photoelectric conversion section and n-type floating diffusion capacitance are set to predetermined values for a solid-state imaging element according to the second embodiment. 11 is a table showing examples of the areas of the photoelectric conversion layer (portion) and the n-type floating diffusion capacitance, and the values of the dark current when the total value of the dark current is zero in the solid-state imaging element according to each embodiment. FIG. 1 is a diagram showing an equivalent circuit of a four-transistor type pixel circuit of a solid-state imaging device according to prior art 1. 11 is a diagram showing a time chart of signals input to a pixel circuit when a signal is read out in a solid-state imaging element according to Prior Art 1. FIG.

Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.
In the following description, a first embodiment using a photoelectric conversion film will be described in detail first, and then a second embodiment using a p-type photodiode will be described.
In addition, in each of the above embodiments, an example is shown in which the carriers of the dark current of the photoelectric conversion means are holes and the carriers of the dark current of the floating diffusion capacitance are electrons. However, in the solid-state imaging element of the present invention, the carriers of the dark current of the photoelectric conversion means can also be electrons and the carriers of the dark current of the floating diffusion capacitance (p-type) can also be holes.
Here, the technical terms described below will be briefly explained. That is, an n-type photoelectric conversion portion refers to an n-type having a low n ^- type impurity concentration, an n-type floating diffusion capacitance refers to an n ⁺ type having a high n-type impurity concentration, a photoelectric conversion film refers to a p ^- type or i-type having a low p-type impurity concentration, and a p-type floating diffusion capacitance refers to a p ⁺ type having a high p-type impurity concentration.

First Embodiment
1 shows a pixel array of unit pixels that is the premise of the solid-state imaging device of this embodiment (the same applies to the second embodiment described later), specifically, a system configuration diagram of a CMOS type solid-state imaging device 100. The CMOS type solid-state imaging device 100 has a pixel array 101 in which unit pixels 102 including photoelectric conversion elements are two-dimensionally arranged in an array and connected to pixel drive wiring 103 and vertical signal lines 104, and is also composed of a column-parallel signal processing circuit 105, an output circuit 106, control circuits (timing control circuit 107, reset signal control circuit 111), a horizontal scanning circuit 108, a vertical scanning circuit 109, and a multiplexer circuit 110 as peripheral circuits. The column-parallel signal processing circuit 105 is configured to include an analog-to-digital conversion circuit (ADC).

The reason why the column-parallel signal processing circuit 105 and the horizontal scanning circuit 108 are arranged at the top and bottom in FIG. 1 is that, compared to when they are arranged on one side, the layout width of the column-parallel signal processing circuit 105 can be made twice the unit pixel width, while one column of unit pixels can be arranged.

The imaging device according to the first embodiment of the present invention is, for example, a device that includes the solid-state imaging element 100 shown in FIG. 1 and further includes a signal output section that outputs a signal from the output circuit 106 to the outside either directly or after converting it into a desired signal form, and is, for example, an imaging device in the broad sense that includes a camera, a sensor, etc.

Figure 2 shows an equivalent circuit diagram of a unit pixel 102 used in the solid-state imaging device according to this embodiment. The equivalent circuit of the unit pixel 102 according to this embodiment shown in Figure 2 is a circuit configuration of an nMOS 3-transistor type unit pixel 102, in which the pixel circuit that reads out signal charges from the photoelectric conversion film (PL) 211 is composed of an n-type floating diffusion capacitance (FD) 213, a reset transistor (RT) 214, a source follower amplifier transistor (SF) 215, a selection transistor (SL) 216, a pixel output (OUT) 217, a source follower amplifier transistor power supply (SFVDD) 222, and a reset transistor power supply (RTVDD) 223.

2, the photoelectric conversion film (PL) 211 has a lower electrode connected to an n-type floating diffusion capacitance (FD) 213 through a via (VIA) 227. A reset transistor (RT) 214 that resets the n-type floating diffusion capacitance (FD) 213 is connected between the n-type floating diffusion capacitance (FD) 213 and a reset transistor power supply (RTVDD) 223. The n-type floating diffusion capacitance (FD) 213 is connected to a gate electrode of a source follower amplifier transistor (SF) 215. The source follower amplifier transistor (SF) 215 and a selection transistor (SL) 216 are connected between a source follower amplifier transistor power supply (SFVDD) 222 and a pixel output (OUT) 217.
Although FIG. 2 shows the pixel circuit of the unit pixel 102 of an nMOS three-transistor type, the circuit may have a feedback reset function as an additional function.

3 shows a time chart of input signals in the pixel circuit of the unit pixel 102 according to this embodiment. Specifically, a time chart of input signals to the selection transistor (SL) 216 and the n-type floating diffusion capacitance reset transistor (RT) 214 is shown.
Also, the symbols (1), (2), (n), etc. following these labels indicate which row the unit pixel is in in the pixel array 101 in Fig. 1. Also, a time chart of the sampling timing of an analog-to-digital conversion circuit (ADC) is shown.

Figure 4 shows energy band schematic diagrams at each timing (a), (b), (c), and (d) in Figure 3. Timing (a) in Figures 3 and 4 indicates the time of charge accumulation. A positive voltage is applied to the upper electrode (film electrode) of the photoelectric conversion film (PL) 211 with the voltage of the reset transistor power supply (RTVDD) 223 as a reference, and signal charge holes are generated in the photoelectric conversion film (PL) 211, and the signal charge holes move from the photoelectric conversion film (PL) 211 to the n-type floating diffusion capacitance (FD) 213 via the VIA 227, and the signal charge holes are accumulated in the n-type floating diffusion capacitance (FD) 213, increasing the potential.

At timing (b), the selection transistor (SL) 216 is turned on to select the pixel, and the signal charge accumulated in the n-type floating diffusion capacitance (FD) 213 is read out and converted from an analog value to a digital value in the analog-to-digital conversion circuit (ADC).
At the timing (c), the reset transistor (RT) 214 is turned on, and the n-type floating diffusion capacitance (FD) 213 is reset to the voltage value of the reset transistor power supply (RTVDD) 223 .
At the timing (d), the reset transistor (RT) 214 is turned off. Also, the reset noise mixed in the n-type floating diffusion capacitance (FD) 213 is read out and converted from an analog value to a digital value in an analog-to-digital conversion circuit (ADC).

In FIG. 3, after the unit pixel 102 in the first row of the M-1 frame is reset, the value of the reset noise is read out. The time until the first row of the M frame is read out is one accumulation time. After that, the unit pixel 102 is selected, and the signal with the reset noise superimposed thereon is analog-to-digital converted and read out. Since the reset noise is the same in the analog-to-digital converted value of the signal with the reset noise superimposed thereon in the first row of the M frame and the analog-to-digital converted value of the reset noise in the first row of the M-1 frame, the reset noise is offset by a digital correlated double sampling process outside the sensor, and only the signal can be separated and extracted (see JP 2015-167343 A).

5 shows a schematic cross-sectional view of a pixel structure of a solid-state imaging device according to this embodiment. This solid-state imaging device is formed by stacking a photoelectric conversion film 20 on a pixel circuit 30. The photoelectric conversion film 20 has a structure in which an electron injection blocking layer (e.g., 20 nm thick) 7, a photoelectric conversion layer (and charge multiplication layer) (e.g., 300 nm thick) 5, a hole injection blocking layer (e.g., 20 nm thick) 4, and an ITO layer (e.g., 30 nm thick) 6 as a film electrode are stacked in this order.
The pixel circuit 30 is constructed by forming an n-type MOS transistor portion on a p-type substrate 1. The pixel electrode 3 is electrically connected to an n-type floating diffusion capacitance 13. An insulating layer 9 is provided between the p-type substrate 1 and the pixel electrode 3.

FIG. 6 is a band diagram in the cross section taken along line AA' in FIG. 5, showing the state at the time of reset.
The band diagram in FIG. 6 is a relative potential diagram showing the state inside a pixel, and the lower end of the conduction band and the upper end of the valence band are shown for the hole injection blocking layer 4, the photoelectric conversion layer (which also serves as a charge multiplication layer) 5, the electron injection blocking layer 7, the n-type floating diffusion capacitance 13, and the p-type substrate 1 (silicon semiconductor material).
The potential between the pixel electrode 3 and the n-type floating diffusion capacitance 13 is 2.3 V, which is the reset voltage when the n-type floating diffusion capacitance 13 is reset. The potential of the film electrode (ITO layer) 6 is 15.3 V, which is +13.0 V based on the reset voltage of the pixel electrode 3, and the traveling carriers in the film are holes.

By inserting a hole injection blocking layer 4 between the film electrode 6 and the photoelectric conversion layer (and charge multiplication layer) 5, holes are prevented from being injected from the film electrode 6 into the photoelectric conversion layer (and charge multiplication layer) 5. By inserting an electron injection blocking layer 7 between the pixel electrode 3 and the photoelectric conversion layer (and charge multiplication layer) 5, electrons are prevented from being injected from the pixel electrode 3 into the photoelectric conversion layer (and charge multiplication layer) 5. By arranging an n-type floating diffusion capacitance 13 between the pixel electrode 3 and the p-type substrate 1, electrons are prevented from moving from the pixel electrode 3 to the p-type substrate 1.

(Setting the Total Value of Dark Current in the First Embodiment)
In this embodiment, as described above, a predetermined film voltage is applied to the film electrode 6 of the photoelectric conversion film 20 in relation to the reset voltage of the pixel electrode, and the total value of the dark current at the node (n-type floating diffusion capacitance 13) where the dark current of the p-type photoelectric conversion layer (and charge multiplication layer) 5 and the dark current of the n-type floating diffusion capacitance 13 join together is configured to be set to a desired absolute value by adjusting the film voltage.

FIG. 7 shows the relationship between the dark current value of the photoelectric conversion layer (and charge multiplication layer) 5, the dark current value of the n-type floating diffusion capacitance 13, and the total value of the dark current at the node where the dark current of the photoelectric conversion layer (and charge multiplication layer) 5 and the dark current of the n-type floating diffusion capacitance 13 join together, and the membrane voltage.
That is, the dark current value of the photoelectric conversion layer (cum charge multiplication layer) 5 is a positive value because the carriers are holes, and increases as the membrane voltage is increased. On the other hand, the dark current value of the n-type floating diffusion capacitance 13 is a negative value because the carriers are electrons, and is a constant value independent of the membrane voltage. Therefore, the total value of the dark current at the node connecting the photoelectric conversion layer (cum charge multiplication layer) 5 and the n-type floating diffusion capacitance 13 can be configured to be a negative value when the membrane voltage is low, and a positive value when the membrane voltage is high.
Since the solid-state imaging element of this embodiment has such a configuration, by adjusting the membrane voltage to a predetermined value, it is possible to cancel out the positive dark current value and the negative dark current value, and to set the total value of the dark current at the above node to a value close to zero, preferably to zero.
In the example shown in FIG. 7, when the membrane voltage is set to 3 (arb. unit), the dark current can be set to approximately zero.

In this embodiment, as described above, the total value of the dark current at the node can be set to a value close to zero, preferably to zero, by setting the membrane voltage to a predetermined value. However, before setting the membrane voltage, a rough adjustment may be performed to reduce the total value of the dark current in a short time by setting the area of the photoelectric conversion layer 5 and the area of the n-type floating diffusion capacitance 13.

Here, the "area" of the photoelectric conversion layer 5 means the area of a unit pixel, and the "area" of the n-type floating diffusion capacitance 13 means the area of the n-type floating diffusion capacitance itself.
The derivation of the dark current Jn of the n-type floating diffusion capacitance 13 is similar to that described in the second embodiment, and therefore will not be described again to avoid redundancy.

The upper part of the table in FIG. 12 shows examples of the area and dark current of the photoelectric conversion layer (cum charge multiplication layer) 5 and the n-type floating diffusion capacitance 13, which can set the total value of the dark current to zero in the first embodiment described above.

That is, since the dark current value Jp of the p-type photoelectric conversion unit 312 and the dark current value Jn of the n-type floating diffusion capacitance 313 are obtained from the description of FIG. 11 for the second embodiment, the upper part of the table in FIG. 12 shows the rough adjustment of the areas of the p-type photoelectric conversion layer 5 and the n-type floating diffusion capacitance 13 in the first embodiment. As an example, the former is set to 7.84 μm ² and the latter is set to 0.2584 μm ^2. Then, instead of the dark current value Jp in the second embodiment, the dark current value of the film and the value of the dark current value Jn are set in the first embodiment. Then, the dark current value of the film is adjusted by the film voltage so that the total value of the dark current of the node is 0. Of course, the areas of the p-type photoelectric conversion layer 5 and the n-type floating diffusion capacitance 13 can be combined in a different way.

The imaging device according to this embodiment is configured by including the solid-state imaging element 100 according to the first embodiment described above, and an output section that outputs image information obtained by this solid-state imaging element 100.

Second Embodiment
Next, a second embodiment of the present invention will be described.
In addition, this second embodiment has a configuration and action effects unique to the second embodiment, as well as a configuration and action effects similar to those of the first embodiment. Therefore, in the description of the second embodiment, it would normally be possible to omit the parts that are common to the first embodiment. However, in the following description, in order to facilitate an easy and smooth understanding of the invention, there are cases in which the parts that overlap with the first embodiment are not omitted.

Figure 8 shows an equivalent circuit diagram of a unit pixel 102' used in a solid-state imaging device according to the second embodiment. The equivalent circuit of the unit pixel 102' according to the second embodiment shown in Figure 8 has a pixel circuit that reads out signal charges from a p-type photoelectric conversion unit (p-PD) 512 surrounded by an n-type well (NWELL) 524, and is configured as an nMOS 3-transistor type unit pixel 102' circuit, which is composed of an n-type floating diffusion capacitance (FD) 513, a reset transistor (RT) 514, a source follower amplifier transistor (SF) 515, a selection transistor (SL) 516, a pixel output (OUT) 517, a source follower amplifier transistor power supply (SFVDD) 522, and a reset transistor power supply (RTVDD) 523.

As shown in FIG. 10, the p-type photoelectric conversion unit (p-PD) 312 (512) is surrounded by an n-type well (NWELL) 324 (524) and is connected to an n-type floating diffusion capacitance (FD) 313. A reset transistor (RT) 514 that resets the n-type floating diffusion capacitance (FD) 313 (513) is connected between the n-type floating diffusion capacitance (FD) 313 (513) and a reset transistor power supply (RTVDD) 523. The n-type floating diffusion capacitance (FD) 313 (513) is connected to the gate electrode of a source follower amplifier transistor (SF) 515. The source follower amplifier transistor (SF) 515 and a selection transistor (SL) 516 are connected between a source follower amplifier transistor power supply (SFVDD) 522 and a pixel output (OUT) 517.

The time chart of the input signals in the pixel circuit of the unit pixel 102' according to this embodiment (the time chart of the input signals of the selection transistor (SL) 516 and the n-type floating diffusion capacitance reset transistor (RT) 514) is shown in FIG. 3, as in the case of the first embodiment described above. Therefore, since the explanation of the time chart has been given when explaining the first embodiment, it will be omitted to avoid duplication.

9 shows energy band schematic diagrams at each of the timings (a), (b), (c), and (d) in FIG. 3. Timing (a) in FIG. 3 and FIG. 9 shows the time of charge accumulation. When holes of signal charge are generated in the p-type photoelectric conversion unit (p-PD) 512, electrons move from the n-type floating diffusion capacitance (FD) 513 to the p-type photoelectric conversion unit (p-PD) 512, the potential of the n-type floating diffusion capacitance (FD) 513 increases, and the signal potential fluctuates.
At the timing (b), the selection transistor (SL) 516 is turned on to select the pixel, and the potential fluctuation of the n-type floating diffusion capacitance (FD) 513 is read out and converted from an analog value to a digital value in the analog-to-digital conversion circuit (ADC).
At the timing (c), the reset transistor (RT) 514 is turned on, and the n-type floating diffusion capacitance (FD) 513 is reset to the voltage value of the reset transistor power supply (RTVDD) 523 .
At the timing (d), the reset transistor (RT) 514 is turned off. Also, the reset noise mixed in the n-type floating diffusion capacitance (FD) 513 is read out and converted from an analog value to a digital value in an analog-to-digital conversion circuit (ADC).

In FIG. 3, after resetting the unit pixel 102' in the first row of the M-1 frame, the value of the reset noise is read out. The time until the first row of the M frame is read out is one accumulation time. After that, the unit pixel 102' is selected, and the signal on which the reset noise is superimposed is analog-digital converted and read out. Since the reset noise is the same in the analog-digital converted value of the signal on which the reset noise is superimposed in the first row of the M frame and the analog-digital converted value of the reset noise in the first row of the M-1 frame, the reset noise is offset by a digital correlated double sampling process outside the sensor, and only the signal can be separated and extracted (see JP 2015-167343 A).

Here, Fig. 10 will be described again. Fig. 10 shows a schematic cross-sectional view of the pixel structure of the solid-state imaging element according to this embodiment. This solid-state imaging element is configured by arranging an n-type well 324 on the top of a p-type substrate 301, and arranging a p-type photoelectric conversion unit 312 in the n-type well 324. A metal 315 for a light-shielding mask is arranged on the pixel circuit 330, and an opening is provided directly above the p-type photoelectric conversion unit 312. The p-type photoelectric conversion unit 312 and the n-type floating diffusion capacitance 313 are connected by metal wiring.
Moreover, the pixel circuit 330 is configured by forming an n-type MOS transistor portion on a p-type substrate 301. An insulating layer 309 is provided between the p-type substrate 301 and the pixel electrode 303.

(Setting the Total Value of Dark Current in the Second Embodiment)
In this embodiment, as described above, the total value of the dark current at the node (n-type floating diffusion capacitance 313) where the dark current of the p-type photoelectric conversion unit 312 consisting of a photodiode and the dark current of the n-type floating diffusion capacitance 313 join together is configured to be set to a desired absolute value by adjusting the area of the p-type photoelectric conversion unit 312 and the area of the n-type floating diffusion capacitance 313.

That is, in the p-type photoelectric conversion section 312, the carriers of the dark current are holes, and the larger the area of the photoelectric conversion section 312, the larger the absolute value of the positive dark current becomes. On the other hand, in the n-type floating diffusion capacitance 313, the carriers of the dark current are electrons, and the larger the area of the n-type floating diffusion capacitance 313, the larger the absolute value of the negative dark current becomes. The areas of the p-type photoelectric conversion section 312 and the n-type floating diffusion capacitance 313 are adjusted so that the sum of the dark currents at the node has the desired absolute value.

This area adjustment will be described below with reference to FIG.
FIG. 11 is a table showing the relationship between the area of the p-type photoelectric conversion unit 312 and the dark current, the area of the n-type floating diffusion capacitance 313 and the dark current, and the total dark current of the node.
First, in pixel A, the area of the p-type photoelectric conversion portion 312 is set to 10.4244 μm ² , the area of the n-type floating diffusion capacitance 313 is set to 0.2584 μm ² , and the total value of the dark current (holes) at this time is 5.4 h/f.
On the other hand, in pixel B, the area of the p-type photoelectric conversion portion 312 is set to 10.4244 μm ² , the area of the n-type floating diffusion capacitance 313 is set to 0.7342 μm ² , and the total value of the dark current (holes) at this time is 3.2 h/f.

Thus, by setting the dark current value (holes) of p-type photoelectric conversion unit 312 ^as Jp h/f/ ^μm2 and the dark current value (electrons) of n-type floating diffusion capacitance 313 as Jn e/f/μm2 and solving the relationship in pixel A and pixel B using simultaneous equations, it is possible to obtain the dark current value Jp of p-type photoelectric conversion unit 312 and the dark current value Jn of n-type floating diffusion capacitance 313. Note that h and e in the above units represent holes and electrons, and f in the above units represents frames.

In the above explanation, it is shown that when the area of the n-type floating diffusion capacitance 313 is large, the amount of electrons generated (negative value), which is the dark current of the n-type floating diffusion capacitance 313, increases, and therefore the total value (positive value) of the dark current of the node decreases.
Moreover, the lower part of FIG. 12 shows an example of the areas of the p-type photoelectric conversion portion 312 and the n-type floating diffusion capacitance 313 that can set the total value of the dark current to zero in this embodiment.

That is, since the dark current value Jp of the p-type photoelectric conversion unit 312 and the dark current value Jn of the n-type floating diffusion capacitance 313 are found using Fig. 11 above, the values of these dark current values Jp and Jn are set in the lower part of the table in Fig. 12, and the areas of the p-type photoelectric conversion unit 312 and the n-type floating diffusion capacitance 313 are set so that the total value of the dark current of the node becomes 0. As an example, the former becomes 1.8886 µm ² and the latter becomes 0.2584 µm ^2. Of course, other combinations can be used for the areas of the p-type photoelectric conversion unit 312 and the n-type floating diffusion capacitance 313.

The imaging device according to this embodiment is configured by including the solid-state imaging element according to the second embodiment described above, and an output section that outputs image information obtained by this solid-state imaging element.

(Modifications)
As the solid-state imaging element and imaging device according to the present invention, in addition to the first and second embodiments described above, various other configurations can be adopted.
That is, in the solid-state imaging element and imaging device according to the present invention, the carriers generated in the photoelectric conversion means consisting of the photoelectric conversion film and the photoelectric conversion section may be either electrons or holes of electron-hole pairs, and when the carriers of the dark current of the photoelectric conversion means are either holes or electrons, the carriers of the dark current of the floating diffusion capacitance must be the other of holes or electrons. In other words, when the carriers of the dark current of the photoelectric conversion means are holes, the carriers of the dark current of the floating diffusion capacitance are electrons. Conversely, when the carriers of the dark current of the photoelectric conversion means are electrons, the carriers of the dark current of the floating diffusion capacitance are holes.

In addition, it is preferable that the sum of the dark currents at the node where the dark currents of the photoelectric conversion means and the floating diffusion capacitance join is zero, but it is necessary that the sum is set to a desired absolute value that is at least smaller than each of the absolute values of these two dark currents.

Furthermore, while the above-described first and second embodiments show typical solid-state imaging elements and imaging devices according to the present invention, it is of course possible to modify the respective configurations of the above-described embodiments in various ways in the solid-state imaging elements and imaging devices according to the present invention.
For example, in the first embodiment in FIG. 5 and the second embodiment in FIG. 10, the pixel circuit is constructed by forming an n-type MOS transistor in a p-type substrate, but instead, the pixel circuit may be constructed by forming a p-type well in a p-type substrate and forming an n-type MOS transistor in the p-type well, or by forming a p-type well in an n-type substrate and forming an n-type MOS transistor in the p-type well.

In the second embodiment shown in FIG. 10, the p-type photoelectric conversion section 312 is constructed by forming an n-type well 314 in a p-type substrate and forming the p-type photoelectric conversion section 312 in the n-type well 314. Alternatively, the p-type photoelectric conversion section 312 may be constructed by forming the p-type photoelectric conversion section 312 in an n-type substrate.

In addition, the photoelectric conversion film of the solid-state imaging device of the first embodiment described above is configured to have the electron injection blocking layer, the photoelectric conversion layer (also charge multiplication layer), the hole injection blocking layer, and the film electrode stacked in this order, but other layers may be inserted between these layers. For example, an independent electron transport layer or hole transport layer may be inserted between the layers. The photoelectric conversion layer and the charge multiplication layer may be separated into two layers. Another electron injection blocking layer or hole injection blocking layer may be inserted separately. The electron injection blocking layer and the hole injection blocking layer may be made of a different material from the photoelectric conversion layer (also charge multiplication layer), or may be made of the same material with different doping impurities.
The photoelectric conversion film of the solid-state imaging device according to the first and second embodiments may have a charge multiplication function, and may have a wavelength selectivity function by absorbing light of a specific wavelength.

In the first embodiment, indium phosphide can be used as the material of the photoelectric conversion layer (cum charge multiplication layer). There have been reports on excess noise during avalanche multiplication using indium phosphide as the material. In indium phosphide, the ionization rate β of holes is higher than the ionization rate α of electrons, and the ionization rate ratio k=α/β is about 0.25. The excess noise factor F is expressed as F=Mk+(1-k)(2-1/M) using the multiplication factor M and the ionization rate ratio k, and the smaller the ionization rate ratio k, the smaller the excess noise factor F becomes. Indium phosphide is used in avalanche photodiodes because it has a small excess noise factor with holes as traveling carriers. Therefore, if indium phosphide can be used in the photoelectric conversion layer (cum charge multiplication layer) of a solid-state imaging device, it is preferable because it can provide a good multiplication ratio with a good S/N ratio. In addition, it is generally possible to use a material in which the ionization rate of holes is higher than the ionization rate of electrons.
Also, instead of indium phosphide, germanium or indium gallium arsenide phosphide (wherein the phosphorus to arsenic composition is X:1-X, X is 0.7 or more) can be used.

In the first embodiment, the photoelectric conversion film 20 is laminated on the pixel circuit 30. Alternatively, the photoelectric conversion film 20 may be formed on a dummy support substrate and then bonded to the pixel circuit 30. This allows a single crystal material to be used as the material for the photoelectric conversion film 20. Also, amorphous materials and polycrystalline materials can be used. The photoelectric conversion film 20 and the film electrode 6 may be directly laminated on the pixel circuit 30 by deposition or sputtering. This allows an amorphous material or polycrystalline material to be used as the material for the photoelectric conversion film 20.

In the second embodiment, the p-type photoelectric conversion section of the solid-state imaging element may be made of a single crystal material. In the second embodiment, silicon may be used as the material for the p-type photoelectric conversion section.

1, 301 p-type substrate 3, 303 pixel electrode 4 hole injection blocking layer 5 photoelectric conversion layer 6 film electrode 7 electron injection blocking layer 9, 309 insulating layer 13, 213, 313, 513, 1213 n-type floating diffusion capacitance (FD)
20, 211 Photoelectric conversion film (PL)
30, 330 Pixel circuit 100 CMOS type solid-state imaging element 101 Pixel array 102, 102', 102'' Unit pixel 103, 103', 103'' Pixel drive wiring 104, 104', 104'' Vertical signal line 105 Column-parallel signal processing circuit 106 Output circuit 107 Timing control circuit 108 Horizontal scanning circuit 109 Vertical scanning circuit 110 Multiplexer circuit 111 Reset signal control circuit 312, 512 p-type photoelectric conversion unit (p-PD)
214, 514, 1214 Reset transistor (RT)
215, 515, 1215 Source follower amplifier transistor (SF)
216, 516, 1216 Select transistor (SL)
217, 517, 1217 pixel output (OUT)
1218 Transfer transistor (TX)
1219 n-type photoelectric conversion unit (n-PD)
222, 522, 1222 Source follower amplifier transistor power supply (SFVDD)
223, 523, 1223 Reset transistor power supply (RTVDD)
324, 524 n-type well (NWELL)
227 Via
315 Light shielding mask 316 Protective film ADC Analog-to-digital conversion circuit

Claims (7)

A CMOS type solid-state imaging device in which a photoelectric conversion means, either a photoelectric conversion film made of a laminate or a photoelectric conversion unit made of a photodiode, is disposed on a pixel circuit, and is disposed for each unit pixel ,
The pixel circuit is configured to have a transistor portion disposed on a substrate, or to have a well disposed on a substrate and a transistor portion disposed in the well;
One of the electron-hole pairs generated by photoelectric conversion is used as a carrier for the photoelectric conversion means,
the carriers of the dark current of the photoelectric conversion means are either holes or electrons, and the carriers of the dark current of the floating diffusion capacitance formed from the source of the reset transistor are either holes or electrons,
a dark current from the photoelectric conversion means is configured to merge with a dark current generated in the floating diffusion capacitance without merging with a dark current from another photoelectric conversion means;
a sum of the dark currents at a node where the dark currents of the photoelectric conversion means and the floating diffusion capacitance join together is set to a desired absolute value that is smaller than the absolute values of the dark current value of the photoelectric conversion means and the dark current value of the floating diffusion capacitance. the photoelectric conversion means is a photoelectric conversion film formed of a laminate disposed on the pixel circuit,
The photoelectric conversion film includes a photoelectric conversion layer that performs a photoelectric conversion process, and is configured to have a film electrode laminated on the top layer;
A predetermined membrane voltage is applied to the membrane electrode relative to the reset voltage of the pixel electrode,
2. The solid-state imaging device according to claim 1, wherein the membrane voltage is set so that the total value of the dark currents at the nodes has a desired absolute value . The carrier of the dark current of the photoelectric conversion film is a hole, and the absolute value of the dark current is small when the film voltage is low and is large when the film voltage is high. On the other hand, the floating diffusion capacitance is an n-type, the carrier of the dark current is an electron, and the magnitude of the dark current is constant regardless of the level of the film voltage.
3. A solid-state imaging element as described in claim 2, characterized in that the sum of the dark currents at the nodes is configured to be negative when the membrane voltage is low and positive when the membrane voltage is high, and the membrane voltage is set so that the sum of the dark currents at the nodes becomes the desired absolute value. The photoelectric conversion means is a photoelectric conversion unit formed of a photodiode,
2. The solid-state imaging device according to claim 1, wherein the area of the photoelectric conversion portion and the area of the floating diffusion capacitance are set so that the total value of the dark currents at the nodes has a desired absolute value . the photoelectric conversion section is of p-type, carriers of the dark current are holes, and the larger the area of the photoelectric conversion section, the larger the absolute value of the positive dark current; on the other hand, the floating diffusion capacitance is of n-type, carriers of the dark current are electrons, and the larger the area of the floating diffusion capacitance, the larger the absolute value of the negative dark current;
5. The solid-state imaging device according to claim 4, wherein the area of the photoelectric conversion portion and the area of the floating diffusion capacitance are set so that the sum of the dark currents at the nodes becomes the desired absolute value. The solid-state imaging device according to any one of claims 1 to 5, characterized in that the desired absolute value is 0. An imaging device comprising a solid-state imaging element according to any one of claims 1 to 6, and means for outputting image information obtained by the solid-state imaging element.

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