JP7600569B2 - NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application - Google Patents

Description

The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Japanese Patent Application Laid-Open No. 2003-133635, ... and Japanese Patent Application Laid-Open No. 2003-133635 describe semiconductor devices including a wide-gap semiconductor such as gallium nitride.
[Prior Art Literature]
[Patent Documents]
[Patent Document 1] JP 2016-54250 A [Patent Document 2] JP 2016-66641 A [Patent Document 3] JP 2016-72358 A

By adjusting the distribution of fixed charges in the insulating film, we provide a nitride semiconductor device with excellent characteristics such as mobility and threshold voltage.

A first aspect of the present invention provides a nitride semiconductor device comprising: a nitride semiconductor layer containing Ga; an insulating film stacked on an upper surface of the nitride semiconductor layer; and an electrode provided above the insulating film, wherein the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( /cm) or less when the fixed charge is positive , and the interface fixed charge density in the insulating film is 1E11 ( / ^cm2 ) or less when the fixed charge is positive .

The Ga concentration of the insulating film may be +4E17 cm ^-3 or less in a region 30 nm above the interface.

The insulating film may include an oxide containing Si.

The insulating film may include an oxynitride.

The insulating film may have a thickness of 30 nm or more and 100 nm or less.

The nitride semiconductor layer may contain GaN.

The nitride semiconductor layer may include Mg-doped p-type GaN.

The Mg concentration of the nitride semiconductor layer may be +1E16 cm ⁻³ or more and +1E18 cm ⁻³ or less.

The nitride semiconductor layer, the insulating film and the electrodes may form a field effect transistor having a MOS gate structure.

The field effect transistor may have a threshold voltage of +3V or greater.

The insulating film may have a C impurity concentration of +4E17 cm ⁻³ or less.

In a second aspect of the present invention, there is provided a method for manufacturing a nitride semiconductor device, comprising the steps of providing a nitride semiconductor layer containing Ga, providing an insulating film stacked on an upper surface of the nitride semiconductor layer, and providing an electrode above the insulating film, wherein the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( /cm) or less when the fixed charge is positive , and the interface fixed charge density in the insulating film is 1E11 ( / ^cm2 ) or less when the fixed charge is positive .

The step of providing the insulating film may be performed by plasma CVD.

The source gas in plasma CVD may contain monosilane or disilane.

The raw material gas in plasma CVD may include oxygen gas, water, or oxygen radicals.

In the step of providing the insulating film, the insulating film may be provided at a deposition rate of 25 nm/min or more.

During the step of providing the insulating film, the temperature of the nitride semiconductor layer may be set to 350°C or less.

Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions.

An example of the configuration of a nitride semiconductor device 100 is shown. An example of the relationship between the deposition rate of the insulating film 30 and the Ga concentration (cm ⁻³ ) is shown. An example of the carbon (C) concentration of the insulating film 30 is shown. 4 shows the relationship between the depth of the insulating film 30 and the Ga concentration. 4 shows the relationship between the Ga concentration in the insulating film 30 and the fixed charge density of the insulating film 30. 1 shows the relationship between the Ga concentration in the insulating film 30 and the fixed charge density/thickness of the insulating film 30. 1 shows an example of the configuration of a nitride semiconductor device 200 according to a second embodiment. A method for manufacturing the nitride semiconductor device 200 according to the second embodiment will be described. 1 shows the relationship between the fixed charge density _Neff of the insulating film 30 and the threshold voltage Vth. 1 shows the relationship between the film thickness d _ox and the fixed charge density N _eff when the film formation rate is changed. 1 shows the relationship between the interface fixed charge density of the insulating film 30 and the maximum value μ _max of the field effect mobility μ. 1 shows an example of the configuration of a nitride semiconductor device 300 according to a third embodiment. 1 shows an example of the configuration of a nitride semiconductor device 400 according to a fourth embodiment.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

Figure 1 shows an example of the configuration of a nitride semiconductor device 100 according to the first embodiment. The nitride semiconductor device 100 of this example includes a bottom electrode 42, a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, an insulating film 30, and a top electrode 40.

In the present example, the nitride semiconductor device 100 has an insulating film 30 provided between the bottom electrode 42 and the top electrode 40. In other words, the nitride semiconductor device 100 in this example forms a capacitor with the insulating film 30 as a dielectric.

In this example, the nitride semiconductor substrate layer 10 contains GaN. As an example, the nitride semiconductor substrate layer 10 is obtained using a method such as vapor phase growth or liquid phase growth.

The nitride semiconductor layer 20 is a layer obtained by epitaxial growth on the nitride semiconductor substrate layer 10. In this example, the nitride semiconductor layer 20 contains Ga.

The insulating film 30 is laminated on the upper surface 21 of the nitride semiconductor layer 20. The insulating film 30 may be a layer formed by a chemical vapor deposition (CVD) method. As an example, the insulating film 30 is provided by a plasma CVD method such as a microwave plasma CVD method, a remote plasma CVD method, or a radio frequency (RF) plasma CVD method. The insulating film 30 may be formed using monosilane or disilane as a Si source gas in the CVD method. Furthermore, oxygen gas, water, or oxygen radicals may be used as an oxygen source gas in the CVD method.

As an example, the insulating film 30 is an oxide layer containing Si. In this example, the insulating film 30 contains _SiO2 . In another example, the insulating film 30 may contain an oxynitride. As an example, the insulating film 30 has a thickness of 30 nm or more and 100 nm or less. When the insulating film 30 is a _SiO2 film, an insulating film 30 having a breakdown voltage of about 10 MV/cm can be used. In this case, if the thickness of the insulating film is set to 30 nm or more and 100 nm or less, an insulating film having a breakdown voltage of about 30 V or more and about 100 V or less can be manufactured.

The lower electrode 42 and the upper electrode 40 include a conductive material such as a metal. The lower electrode 42 and the upper electrode 40 may be made of the same metal or different metals. As an example, the material of the lower electrode 42 and the upper electrode 40 is aluminum (Al). The upper electrode 40 may be provided above the insulating film 30 by aluminum deposition. The lower electrode 42 is provided on the lower surface 11 of the nitride semiconductor substrate layer 10.

2 shows an example of the relationship between the deposition rate and Ga concentration (cm ⁻³ ) of the insulating film 30. In this example, a graph is shown with the deposition rate (nm/min) on the horizontal axis and the Ga concentration on the vertical axis.

Since GaN is easily thermally decomposed, when the insulating film 30 is formed on the upper surface of the nitride semiconductor layer 20 containing Ga, Ga is taken into the insulating film 30 from the nitride semiconductor layer 20. Furthermore, a GaOx interface layer is formed in the insulating film 30 near the upper surface 21 of the nitride semiconductor layer 20. When the concentration of Ga taken in increases, the absolute value of the charge of the GaOx interface layer also increases. By increasing the deposition rate of the insulating film 30, the time during which the nitride semiconductor layer 20 is exposed to plasma is shortened. As a result, when the insulating film 30 is formed at a high deposition rate, the Ga concentration taken into the insulating film 30 decreases. As an example, the insulating film 30 is formed at a deposition rate of 25 nm/min or more.

In addition, in the manufacture of the nitride semiconductor device 100, it may be possible to select whether or not to perform heat treatment for the purpose of thermally stabilizing the interface between the insulating film 30 and the nitride semiconductor layer 20. In this example, the Ga concentration of the insulating film 30 when heat treatment is performed and when heat treatment is not performed are shown. As an example, the heat treatment is performed at 800°C. When heat treatment is performed, Ga is more likely to diffuse from the nitride semiconductor layer 20 into the insulating film 30, and the Ga concentration increases. When heat treatment is not performed, the Ga concentration taken into the insulating film 30 decreases. When heat treatment is not performed, as an example, the temperature of the nitride semiconductor layer 20 is kept at 350°C or less when the insulating film 30 is provided.

In the insulating film 30, Ga acts as an impurity. The higher the impurity concentration in the insulating film 30, the smaller the magnitude of the electric field that causes dielectric breakdown in the insulating film 30, making dielectric breakdown more likely to occur. The Ga concentration of the insulating film 30 can be reduced by increasing the deposition speed of the insulating film 30 and not performing heat treatment, thereby improving resistance to dielectric breakdown.

In the figure, three deposition conditions, 2A, 2B, and 2C, are shown. The Ga concentration profiles under these three deposition conditions will be described later with reference to FIG. 4A.

Figure 3 shows an example of the carbon (C) concentration of the insulating film 30. When the insulating film 30 is formed by plasma CVD and monosilane is used as the Si source gas, the C concentration according to the depth of the insulating film 30 and the BG (Background) level that the insulating film 30 has as a background are shown.

When the insulating film 30 is formed by the CVD method, tetraethoxysilane (TEOS: tetraethyl orthosilicate), whose chemical formula is Si( _OC2H5 ), may be used as the Si source gas _. Since TEOS gas contains carbon as an element, when TEOS is used as the source gas, carbon is taken in as an impurity in the insulating film.

In the nitride semiconductor device 100, a gas that does not contain carbon, such as monosilane or disilane, is used as the Si source gas in the plasma CVD. This allows the C concentration in the SiO2 to be reduced.

In this example, a profile using monosilane as the source gas is shown. The C concentration of the insulating film 30 in this example can be kept at the order of the BG level except near the interface.

Figure 4A shows the relationship between the depth of the insulating film 30 and the Ga concentration. In this example, the horizontal axis is the length from the surface of the insulating film 30 toward the interface with the nitride semiconductor layer 20. The vertical axis corresponds to the Ga concentration in the insulating film 30. In each curve, the depth with the maximum Ga concentration is made to match. Note that the depth with the maximum Ga concentration roughly corresponds to the interface between the insulating film 30 and the nitride semiconductor layer 20. The three curves in the figure correspond to the Ga concentration profile under the film formation conditions corresponding to the three points 2A, 2B, and 2C shown in Figure 2.

In the Ga concentration profile, a region 30 nm from the surface in the insulating film 30 may show a value higher than the actual Ga concentration due to the influence of adsorbates such as Ga or C. At depths of 30 nm or more, the influence on the Ga concentration profile from the surface becomes small, and the Ga concentration profile becomes flat. Similarly, at depths of 30 nm or more from the interface between the insulating film 30 and the nitride semiconductor layer 20 toward the insulating film 30 side, the influence of Ga diffusing from the nitride semiconductor layer 20 becomes small, and the Ga concentration profile becomes flat.

4B shows the relationship between the Ga concentration in the insulating film 30 and the fixed charge density of the insulating film 30. The higher the concentration of Ga incorporated into the insulating film 30, the higher the fixed charge density of the insulating film 30. The relationship between them can be approximated by a straight line.

Figure 4C shows the relationship between the Ga concentration in the insulating film 30 and the fixed charge density/thickness of the insulating film 30. In Figure 4C, the average fixed charge density in the insulating film 30 is obtained by dividing the fixed charge density Neff on the vertical axis by the thickness of the insulating film 30.

The average fixed charge density on the vertical axis shows a value of approximately 30% relative to the Ga concentration on the horizontal axis. This means that the fixed charge in the insulating film 30 is largely due to Ga. In other words, it is presumed that in the insulating film 30, Ga taken in from the nitride semiconductor layer 20 becomes positively ionized within the insulating film 30, and contributes to the main cause of the fixed charge.

Figure 5 shows an example of the configuration of a nitride semiconductor device 200 according to the second embodiment. The nitride semiconductor device 200 constitutes a field effect transistor having a MOS (metal oxide semiconductor) gate structure, i.e., a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) device. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high concentration N-type region 26, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48. When the nitride semiconductor device 200 functions as a FET, it may be used as a power semiconductor element such as a power supply circuit or an inverter.

The nitride semiconductor substrate layer 10 contains GaN. The GaN contained in the nitride semiconductor substrate layer 10 may be Ga-plane GaN, N-plane GaN, a-plane GaN, or m-plane GaN.

The nitride semiconductor layer 20 in this example includes an N-type nitride semiconductor layer 22 and a P-type nitride semiconductor layer 24. Both of the nitride semiconductor layers 20 can be formed by epitaxially growing the nitride semiconductor substrate layer 10.

The N-type nitride semiconductor layer 22 may be a layer formed by epitaxial growth on the nitride semiconductor substrate layer 10. As an example, the N-type nitride semiconductor layer 22 is Nd-doped N-type GaN. The Nd concentration doped in the N-type nitride semiconductor layer 22 may be +5E15 cm ^-3 or more and +5E16 cm ^-3 or less. For example, the Nd concentration of the N-type nitride semiconductor layer 22 is set to +1E16 cm ^-3 .

The P-type nitride semiconductor layer 24 may be a layer formed by epitaxial growth on the N-type nitride semiconductor layer 22. As an example, the P-type nitride semiconductor layer 24 is Mg-doped P-type GaN. The Mg concentration doped in the P-type nitride semiconductor layer 24 may be +1E16 cm ^-3 or more and +1E18 cm ^-3 or less, or may be +1E16 cm ^-3 or more and +5E17 cm ^-3 or less. For example, the Mg concentration of the P-type nitride semiconductor layer 24 is set to +1E17 cm ^-3 .

The high-concentration N-type region 26 is an N-type semiconductor region with a higher doping concentration than the N-type nitride semiconductor layer 22. As an example, the high-concentration N-type region is obtained by adding Si and performing a heat treatment.

The insulating film 30 is formed above the P-type nitride semiconductor layer 24. The insulating film 30 may include an oxide containing Si, or may include an oxynitride. The insulating film 30 corresponds to the gate insulating film of a MOSFET device. As an example, the film thickness of the insulating film 30 is set to 100 nm.

The source electrode 44 corresponds to the source electrode of the MOSFET device. The source electrode 44 is formed above the high concentration N-type region 26. The high concentration N-type region 26 provided below the source electrode 44 corresponds to the source region of the MOSFET device.

The drain electrode 46 corresponds to the drain electrode of a MOSFET device. The high concentration N-type region 26 provided below the drain electrode 46 corresponds to the drain region of a MOSFET device. The nitride semiconductor device 200 of this example constitutes a planar type FET. In this example, the roles of the source electrode 44 and the drain electrode 46 can be interchanged by switching the voltages applied to them.

The gate electrode 48 corresponds to the gate electrode of a MOSFET device. When a gate voltage is applied to the gate electrode 48, an N-type channel is formed in the P-type nitride semiconductor layer 24, connecting the source region and the drain region with the N-type channel. This causes the nitride semiconductor device 200 to operate as a FET. The FET may have a threshold voltage Vth (V) of 3 V or more.

Figure 6 shows a method for manufacturing a nitride semiconductor device 200 according to the second embodiment. The method for manufacturing a nitride semiconductor device 200 includes steps S100 to S108.

In S100, an N-type nitride semiconductor layer 22 is provided. The N-type nitride semiconductor layer 22 may be formed as Nd-doped N-type GaN by epitaxial growth on the nitride semiconductor substrate layer 10 using MOCVD (Metal Organic Chemical Vapor Deposition).

The P-type nitride semiconductor layer 24 may be epitaxially grown above the N-type nitride semiconductor layer 22 and formed as Mg-doped P-type GaN. The semiconductor device may also be subjected to a heat treatment to activate the P-type nitride semiconductor layer 24.

In step S102, a high-concentration N-type region 26 is provided in the P-type nitride semiconductor layer 24. The step of providing the high-concentration N-type region 26 is performed by implanting N+ type ions into a portion of the P-type nitride semiconductor layer 24. As an example, the ions implanted are Si ions. However, a different N-type dopant such as Ge ions may also be implanted. Furthermore, the Si dopant is activated by performing a heat treatment step.

In S104, an insulating film 30 is provided on the upper surface of the P-type nitride semiconductor layer 24. The insulating film may be provided by a plasma CVD method. In the plasma CVD method, monosilane or disilane may be used as a Si source gas, and oxygen gas, water, or oxygen radicals may be used as an oxygen source gas. As an example, the insulating film 30 is provided across the P-type nitride semiconductor layer 24 and the high concentration N-type region 26. The insulating film 30 provided in areas other than the desired area is removed by etching such as wet etching. When providing the insulating film, the temperature of the nitride semiconductor layer may be set to 350° C. or less.

In step S106, a gate electrode 48 is provided above the insulating film 30. As an example, the gate electrode 48 is provided by aluminum deposition using a metal mask.

In step S108, a source electrode 44 and a drain electrode 46 are provided above a portion of the high concentration N-type region 26. As an example, the source electrode 44 and the drain electrode 46 are provided by aluminum deposition using a metal mask, similar to the gate electrode 48, but they may be provided by a different conductor, and the method of providing the electrodes is not limited to aluminum deposition.

The order of steps S106 and S108 may be reversed. Through the above steps, the nitride semiconductor device 200 is manufactured.

7 shows the relationship between the fixed charge density _Neff and the threshold voltage Vth of the insulating film 30. The vertical axis represents the threshold voltage Vth (V) of the MOS gate, and the horizontal axis represents the fixed charge density _Neff (cm ^-2 ) of the MOSFET device. In this example, a MOSFET device related to the nitride semiconductor device 200 will be used for explanation.

When the MOSFET device of this example is used as a power MOSFET device, it is preferable to achieve normally-off operation for the safety of the power MOSFET device. In this case, the threshold voltage Vth, which is the on/off boundary, may be set to +3 V or more to achieve operational reliability, and to 10 V or less to achieve voltage controllability. However, the range of Vth is not limited to values between +3 V and 10 V.

There is a linear relationship between the threshold voltage Vth and the fixed charge density _Neff of a MOSFET device. The condition for the fixed charge density _Neff to make the threshold voltage Vth greater than +3 V and smaller than +10 V is _Neff < 9.8E11 ( / ^cm2 ) when the fixed charge is positive .

Here, the threshold voltage Vth and the flat band voltage Vfb have the following relationship:
Vth=Vfb+2φb+√(2ε _s qNa(2φb))/Cox
N _eff =-Cox(Vfb-Vfb(ideal))
Here, ε _s is the relative dielectric constant of the semiconductor. In addition, the following formulas are satisfied: acceptor concentration Na=1E17 cm ^-3 , film thickness d _ox of the insulating film 30=100 nm, flat band voltage Vfb (ideal)=-3 V, and barrier height φb=1.53 V. In this case, (2ε _s qNa(2φb))/Cox=8.3 (V), and Vth+N _eff /Cox=8.4 (V). Also, from FIG. 7, Vth+N _eff /Cox is about 8.1 (V).

For values other than d _ox = 100 nm, the relationship Cox = εox/d _ox exists, and therefore the predetermined range of threshold voltage Vth is satisfied when the product of the fixed charge density N _eff of the insulating film 30 and the film thickness d _ox of the insulating film 30 is within a range of 1E7 ( /cm) or less when the fixed charge is positive .

Furthermore, the average fixed charge density _Neff / _dox in the film is ( _Neff / _dox ) < 1E17 ( / ^cm3 ), and if the Ga concentration is in the range of 4E17cm ^-3 or less, the effect on the threshold voltage Vth can be suppressed. In particular, in a region 30 nm above the interface where the effect of surface adsorbed Ga or diffused Ga is small, the Ga concentration may be 4E17cm ^-3 or less.

8A is a diagram showing the relationship between the film thickness d _ox and the fixed charge surface density N eff when the insulating film 30 is a SiO2 film, with the horizontal axis representing the film thickness d _ox (nm) of the insulating film 30, and the vertical axis representing the fixed charge _{density N eff (} cm ⁻² ) .

As described above, the higher the deposition rate, the shorter the time that the nitride semiconductor layer 20 is exposed to plasma, and the smaller the amount of Ga taken into the insulating film. The interface fixed charge density of the insulating film 30 can be derived from the film thickness dependency of the insulating film 30 of the fixed charge, and is the intercept of the vertical axis in FIG. 8A .

8B shows the relationship between the interface fixed charge density of the insulating film 30 and the maximum value μmax of the field effect mobility μ. The graph shows the interface fixed charge density (/ cm ⁻² ) of the insulating film 30 on the horizontal axis and the maximum value of the field effect mobility μ (cm ⁻² /Vs) on the vertical axis.

The field effect mobility μ (cm ⁻² /Vs) refers to the mobility of carriers in a channel region formed in the nitride semiconductor layer 20 near the interface with the insulating film 30. In a power MOSFET device, the larger the value of the field effect mobility μ, the larger the control output, so it is preferable that the field effect mobility μ be a large value. As an example, the field effect mobility μ (cm ² /Vs) is set to 50 (cm ² /Vs) or more, but may be set to 100 (cm ² /Vs) or more.

When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side in the P-type nitride semiconductor layer 24. On the other hand, near the boundary between the P-type nitride semiconductor layer 24 and the insulating film 30, roughness scattering due to the roughness of the boundary surface and scattering due to electromagnetic interactions such as Coulomb scattering due to Coulomb interactions occurring between carriers and charges at the interface in the insulating film 30 occur. These scatterings make the carrier mobility near the boundary smaller than the carrier mobility in the bulk of the semiconductor substrate.

In addition to the Coulomb interaction between carriers and the interface fixed charges, when an electrostatic potential exists at the interface, the interaction caused by the electrostatic potential also contributes to the scattering caused by the electromagnetic interaction at the interface. Here, the interface state density D _it occurring between the P-type nitride semiconductor layer 24 and the insulating film 30 is small. For example, when the P-type nitride semiconductor layer 24 is GaN and the insulating film 30 is SiO ₂ , the interface state density D _it occurring between GaN/SiO ₂ is 1E10 (cm ^-2 /eV) or less. In this case, the contribution of the interface state density D _it to the scattering is smaller than the contribution of the Coulomb scattering caused by the interface fixed charges.

The contribution of Coulomb scattering is reduced by reducing the interface fixed charge density, which therefore reduces the influence of scattering due to electromagnetic interactions at the interface and increases the field effect mobility μ (cm ² /Vs).

Experimental results showed that in order to achieve a field effect mobility μ (cm ² /Vs) of 50 (cm ² /Vs) or more, the interface fixed charge density was 1E11 (/ cm ² ) or less .

The positive or negative charge at the interface contributes to whether the Coulomb interaction is attractive or repulsive, but in terms of the contribution to carrier mobility due to Coulomb scattering, it is preferable that either interaction is small. Therefore, by reducing the absolute value of the interface fixed charge density, a desired field effect mobility μ (cm ² /Vs) can be obtained. In the insulating film 30 of this example, the interface fixed charge density may be 1E11 (/ cm ² ) or less when the fixed charge is positive , and more preferably 7E10 (/ cm ² ) or less.

Figure 9 shows an example of the configuration of a nitride semiconductor device 300 according to the third embodiment. The nitride semiconductor device 300 of this example constitutes a vertical MOSFET. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high concentration N-type region 26, an N-type well region 28, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48.

The nitride semiconductor layer 20 includes an N-type nitride semiconductor layer 22 and a P-type nitride semiconductor layer 24. As an example, the N-type nitride semiconductor layer 22 is an N-type GaN layer epitaxially grown on a GaN semiconductor substrate layer. In another example, the N-type nitride semiconductor layer 22 may be a layer of an N-type semiconductor substrate, and may include both an N-type semiconductor substrate and an N-type semiconductor layer epitaxially grown on the N-type semiconductor substrate. The P-type nitride semiconductor layer 24 may be formed by epitaxially growing the N-type nitride semiconductor layer 22.

In this example, each of the high concentration N-type regions 26 corresponds to a source region of a MOSFET device. A source electrode 44 is formed above a portion of the high concentration N-type region 26. The high concentration N-type region 26 may be doped with Si or Ge.

The N-type well region 28 is provided by adding an N-type dopant to a portion of the P-type nitride semiconductor layer 25. The N-type well region 28 may be doped with Si or O.

The drain electrode 46 is provided below the N-type nitride semiconductor layer 22. The drain electrode 46 functions as the drain electrode of the MOSFET device.

When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side of the P-type nitride semiconductor layer between the high-concentration N-type region 26 and the N-type well region 28. This allows carriers to flow between the high-concentration N-type region 26 and the N-type well region 28, and the carrier path through the N-type well region 28 and the N-type nitride semiconductor layer 22 becomes conductive. This causes the nitride semiconductor device 300 to operate as a MOSFET device.

Unlike the nitride semiconductor device 200, the nitride semiconductor device 300 has a conductive carrier path from the upper surface 21 to the drain electrode 46 below throughout the depth direction of the nitride semiconductor layer 20. Therefore, the nitride semiconductor device 300 can improve the breakdown voltage of the MOSFET device compared to the nitride semiconductor device 200.

Figure 10 shows an example of the configuration of a nitride semiconductor device 400 according to the fourth embodiment. The nitride semiconductor device 400 of this example constitutes a trench-gate type device. The nitride semiconductor device 400 of this example constitutes a trench-gate type MOSFET. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high-concentration N-type region 26, an N-type well region 28, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48. The following mainly describes the differences from the nitride semiconductor device 300.

In this example, after the high concentration N-type region 26 is provided above the P-type nitride semiconductor layer 24, the substrate is etched to provide a trench. An insulating film 30 and a gate electrode 48 are provided in the trench.

The gate electrode 48 may be made of metal or polysilicon. When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side in the P-type nitride semiconductor layer 24 between the high-concentration N-type region 26 and the N-type nitride semiconductor layer 22. This allows a carrier path from the source electrode 44 to the drain electrode 46 to be conductive through the high-concentration N-type region 26, the N-type channel, and the N-type nitride semiconductor layer 22. Therefore, the nitride semiconductor device 400 operates as a MOSFET device.

In the nitride semiconductor device 400, it is easier to provide a larger number of gate electrodes 48 than in the nitride semiconductor device 300. This increases the ratio of the area in the nitride semiconductor layer 20 that can be used as a channel, improving the operating efficiency of the semiconductor device.

The present invention has been described above using an embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiment. It is clear from the claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before" or "prior to," and it should be noted that the processes may be performed in any order, unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is necessary to perform the processes in this order.

10: nitride semiconductor substrate layer, 11: bottom surface, 20: nitride semiconductor layer, 21: top surface, 22: N-type nitride semiconductor layer, 24: P-type nitride semiconductor layer, 26: high concentration N-type region, 28: N-type well region, 30: insulating film, 40: top electrode, 42: bottom electrode, 44: source electrode, 46: drain electrode, 48: gate electrode, 100: nitride semiconductor device, 200: nitride semiconductor device, 300: nitride semiconductor device, 400: nitride semiconductor device

Claims (17)

a nitride semiconductor layer containing Ga;
an insulating film laminated on an upper surface of the nitride semiconductor layer;
an electrode provided above the insulating film;
Equipped with
the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( /cm) or less when the fixed charge is positive ;
The interface fixed charge density in the insulating film is 1E11 ( /cm ² ) or less when the fixed charge is positive .
Nitride semiconductor devices. The Ga concentration of the insulating film is +4E17 cm ⁻³ or less in a region 30 nm above the interface with the nitride semiconductor layer.
The nitride semiconductor device according to claim 1 . The insulating film includes an oxide containing Si.
3. The nitride semiconductor device according to claim 1 or 2. The insulating film includes an oxynitride.
The nitride semiconductor device according to claim 1 . The insulating film has a thickness of 30 nm or more and 100 nm or less.
The nitride semiconductor device according to claim 1 . The nitride semiconductor layer includes GaN.
The nitride semiconductor device according to claim 1 . The nitride semiconductor layer includes Mg-doped P-type GaN.
The nitride semiconductor device according to claim 1 . The Mg concentration of the nitride semiconductor layer is +1E16 cm ⁻³ or more and +1E18 cm ⁻³ or less.
The nitride semiconductor device according to claim 7 . the nitride semiconductor layer, the insulating film, and the electrode constitute a field effect transistor having a MOS gate structure;
The nitride semiconductor device according to claim 1 . The field effect transistor has a threshold voltage of +3V or more.
The nitride semiconductor device according to claim 9 . The C impurity concentration of the insulating film is +4E17 cm ⁻³ or less.
The nitride semiconductor device according to claim 1 . providing a Ga-containing nitride semiconductor layer;
providing an insulating film stacked on an upper surface of the nitride semiconductor layer;
providing an electrode above the insulating film;
the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( /cm) or less when the fixed charge is positive ;
The interface fixed charge density in the insulating film is 1E11 ( /cm ² ) or less when the fixed charge is positive .
A method for manufacturing a nitride semiconductor device. The step of providing the insulating film is performed by plasma CVD.
The method for manufacturing a nitride semiconductor device according to claim 12 . The source gas in the plasma CVD includes monosilane or disilane.
The method for manufacturing a nitride semiconductor device according to claim 13 . The raw material gas in the plasma CVD contains oxygen gas, water, or oxygen radicals;
The method for manufacturing a nitride semiconductor device according to claim 13 or 14. In the step of providing the insulating film,
The insulating film is formed at a deposition rate of 25 nm/min or more.
The method for manufacturing a nitride semiconductor device according to claim 12 . In the step of providing the insulating film, the temperature of the nitride semiconductor layer is set to 350° C. or less.
The method for manufacturing a nitride semiconductor device according to claim 12 .

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