JP7598749B2 - Semiconductor Device - Google Patents

Description

This disclosure relates to a semiconductor device.

In recent years, semiconductor devices including thin film transistors (TFTs) have been used in electronic devices in a variety of fields. For example, oxide semiconductor materials can be used for the semiconductor film of a thin film transistor (see, for example, Patent Document 1).

In the thin-film transistor using the oxide semiconductor material described in Patent Document 1, a top-gate self-aligned structure is adopted in order to manufacture a thin-film transistor with small parasitic capacitance with a relatively small number of steps. In the manufacturing method of the semiconductor device described in Patent Document 1, the gate electrode and the gate insulating layer are patterned by dry etching. At this time, the region of the oxide semiconductor layer located under the gate insulating layer that is exposed from the gate insulating layer is made low-resistance by a process such as dry etching. In this way, the low-resistance oxide semiconductor layer is connected to the source electrode and the drain electrode.

JP 2019-192852 A

However, in the method of manufacturing a semiconductor device described in Patent Document 1, the low resistance region can be formed up to the region below the gate electrode. In addition, it is not easy to control the range in which the low resistance region is formed. For this reason, in the semiconductor device described in Patent Document 1, variations in characteristics can occur due to individual differences in the range in which the low resistance region is formed below the gate electrode.

This disclosure has been made to solve the above problems, and aims to provide a semiconductor device that can reduce the variation in characteristics.

In order to achieve the above object, a semiconductor device according to one aspect of the present disclosure includes a substrate, a bottom electrode disposed above the substrate, a bottom insulating layer disposed above the bottom electrode, a shield electrode disposed above the bottom insulating layer, a shield insulating layer disposed above the shield electrode, an oxide semiconductor layer disposed above the shield insulating layer and having a channel region, a gate insulating layer disposed above the oxide semiconductor layer, and a gate electrode disposed above the gate insulating layer, and the shield electrode is disposed in a position facing the gate electrode and the oxide semiconductor layer.

This disclosure provides a semiconductor device that can reduce the variation in characteristics.

FIG. 1 is a schematic cross-sectional view showing a configuration of a main part of a thin film transistor according to a first embodiment. FIG. 2 is a top view diagrammatically illustrating the configuration of the thin film transistor according to the first embodiment. FIG. 3A is a cross-sectional view parallel to the channel length direction showing a first step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3B is a cross-sectional view parallel to the channel length direction showing a second step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3C is a cross-sectional view parallel to the channel length direction showing a third step of the method for manufacturing the thin-film transistor according to the first embodiment. FIG. 3D is a cross-sectional view parallel to the channel length direction showing a fourth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3E is a cross-sectional view parallel to the channel length direction showing a sixth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3F is a cross-sectional view parallel to the channel length direction showing a seventh step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3G is a cross-sectional view parallel to the channel length direction showing an eighth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 3H is a cross-sectional view parallel to the channel length direction showing a ninth step of the method for manufacturing the thin-film transistor according to the first embodiment. FIG. 3I is a cross-sectional view parallel to the channel length direction showing a tenth step of the method for manufacturing the thin-film transistor according to the first embodiment. FIG. 3J is a cross-sectional view parallel to the channel length direction showing an eleventh step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4A is a cross-sectional view parallel to the channel width direction showing a first step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4B is a cross-sectional view parallel to the channel width direction showing a second step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4C is a cross-sectional view parallel to the channel width direction showing a third step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4D is a cross-sectional view parallel to the channel width direction showing a fourth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4E is a cross-sectional view parallel to the channel width direction showing a fifth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4F is a cross-sectional view parallel to the channel width direction showing a sixth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4G is a cross-sectional view parallel to the channel width direction showing a seventh step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4H is a cross-sectional view parallel to the channel width direction showing an eighth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4I is a cross-sectional view parallel to the channel width direction showing a ninth step of the method for manufacturing the thin-film transistor according to the first embodiment. FIG. 4J is a cross-sectional view parallel to the channel width direction showing a tenth step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 4K is a cross-sectional view parallel to the channel width direction showing an eleventh step of the method for manufacturing the thin film transistor according to the first embodiment. FIG. 5 is a schematic cross-sectional view showing the configuration of a main part of a thin film transistor of a comparative example. FIG. 6 is a graph showing a simulation result of the relationship between the gate voltage and the drain current of the thin film transistor of the comparative example. FIG. 7 is a graph showing a simulation result of the relationship between the gate voltage and the drain current of the thin film transistor according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing a configuration of a main part of a thin film transistor according to the second embodiment. FIG. 9 is a block diagram showing a functional configuration of a display device to which the thin film transistors according to the embodiments are applied. FIG. 10 is a block diagram showing a functional configuration of an imaging device to which the thin film transistors according to the embodiments are applied. FIG. 11 is a block diagram showing a functional configuration of an electronic device to which the thin film transistors according to the embodiments are applied.

The following describes embodiments of the present disclosure with reference to the drawings. Note that each embodiment described below is a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component placement and connection, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in an independent claim that represents the highest concept in the present disclosure are described as optional components.

In addition, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scale and the like are not necessarily the same in each figure. In addition, the same reference numerals are used in each figure for substantially the same configuration, and duplicate explanations are omitted or simplified.

In addition, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in an absolute spatial sense, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to cases where two components are arranged with a gap between them and another component exists between the two components, but also to cases where two components are arranged in contact with each other.

(Embodiment 1)
A semiconductor device according to a first embodiment will be described. In this embodiment, a thin film transistor, which is an example of a semiconductor device, and a manufacturing method thereof will be described.

[1-1. Configuration]
First, the configuration of a thin film transistor according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic cross-sectional view showing the configuration of a main part of a thin film transistor 10 according to the present embodiment. The thin film transistor 10 according to the present embodiment is manufactured using a manufacturing method for a thin film transistor according to the present embodiment, which will be described later. The thin film transistor 10 is a top-gate type thin film transistor, and is used as a driving element for a display device, an imaging device, etc. The thin film transistor 10 is a specific example of a semiconductor device according to the present disclosure.

As shown in FIG. 1, the thin-film transistor 10 includes a bottom electrode 61, a bottom insulating layer 62, a shield electrode 12, a shield insulating layer 13, an oxide semiconductor layer 15, a gate insulating layer 17, and a gate electrode 18. In this embodiment, the thin-film transistor 10 further includes a substrate 11, interlayer insulating films 19 and 21, a source electrode 22, and a drain electrode 23.

The substrate 11 is a plate-like member that serves as a base for the thin-film transistor 10. In this embodiment, the substrate 11 is made of, for example, glass, quartz, silicon, or the like. The substrate 11 may be made of, for example, a resin material such as PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate), or PEN (polyethylene naphthalate). The substrate 11 may also be a metal plate such as stainless steel (SUS) on which an insulating material is formed.

The bottom electrode 61 is a conductive layer disposed above the substrate 11. The bottom electrode 61 is composed of, for example, a single element or alloy containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu). The bottom electrode 61 may also be a compound containing at least one of the above metals, or a laminated film containing two or more metals. The bottom electrode 61 may also be a transparent conductive film such as ITO. In this embodiment, a positive potential is applied to the bottom electrode 61. The potential applied to the bottom electrode 61 is, for example, about 10 V. In FIG. 1, a part of the electric field generated by applying a potential to the bottom electrode 61 is indicated by a block arrow.

The bottom insulating layer 62 is an insulating layer disposed above the bottom electrode 61. The bottom insulating layer 62 insulates the bottom electrode 61 from the shield electrode 12. In this embodiment, the bottom insulating layer 62 is disposed on the bottom electrode 61 and covers the entire bottom electrode 61. The configuration of the bottom insulating layer 62 is not particularly limited as long as it is an insulating layer. As the bottom insulating layer 62, for example, a single layer film made of one of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), a silicon oxynitride film (SiON), an aluminum oxide film (AlO _x ), and a hafnium oxide (HfO _x ), or a laminated film made of two or more of them can be used. In this embodiment, the bottom insulating layer 62 is a silicon nitride film (SiN _x ).

The shield electrode 12 is a conductive layer patterned into a predetermined shape and disposed above the bottom insulating layer 62. The shield electrode 12 is disposed at a position facing the gate electrode 18 and the oxide semiconductor layer 15. In other words, the shield electrode 12 is disposed at a position overlapping the gate electrode 18 and the oxide semiconductor layer 15 in a top view of the main surface of the substrate 11. The shield electrode 12 is composed of, for example, a simple substance or an alloy containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu). The shield electrode 12 may also be a compound containing at least one of the above metals, or a laminated film containing two or more metals. The shield electrode 12 may also be a transparent conductive film such as ITO. In this embodiment, the shield electrode 12 has the same potential as the source electrode 22. The shield electrode 12 may be electrically connected to the source electrode 22, or the same potential as the source electrode 22 may be applied to the shield electrode 12. In addition, the shield electrode 12 may be at the same potential as the gate electrode 18. The shield electrode 12 may be electrically connected to the gate electrode 18, or the same potential as the gate electrode 18 may be applied to the shield electrode 12.

The shield insulating layer 13 is an insulating layer disposed above the shield electrode 12. The shield insulating layer 13 is a shield electrode insulating layer that insulates the shield electrode 12 from the oxide semiconductor layer 15. In this embodiment, the shield insulating layer 13 is disposed on the shield electrode 12 and on the bottom insulating layer 62. The configuration of the shield insulating layer 13 is not particularly limited as long as it is an insulating layer. For example, an insulating film similar to the bottom insulating layer 62 can be used as the shield insulating layer 13. In this embodiment, the shield insulating layer 13 has a lower insulating layer 13a and an upper insulating layer 13b. The lower insulating layer 13a is an insulating layer disposed on the shield electrode 12 and on the bottom insulating layer 62. In this embodiment, the lower insulating layer 13a is a silicon nitride film (SiN _x ). The upper insulating layer 13b is an insulating layer disposed on the lower insulating layer 13a. In this embodiment, the upper insulating layer 13b is a silicon oxide film (SiO _x ).

The oxide semiconductor layer 15 is disposed above the shield insulating layer 13 and is a semiconductor layer having a channel region 15c and a low resistance region 15n. The oxide semiconductor layer 15 is disposed in a predetermined region on the shield insulating layer 13. The channel region 15c is formed in a position facing the shield electrode 12 and the gate electrode 18. In other words, the channel region 15c is formed in a position overlapping with the shield electrode 12 and the gate electrode 18 in a top view of the main surface of the substrate 11. The oxide semiconductor layer 15 is disposed in a position facing the bottom electrode 61. The length of the bottom electrode 61 in the channel length direction of the channel region 15c (i.e., the horizontal direction in FIG. 1) is longer than the length of the shield electrode 12 in the channel length direction. The low resistance region 15n is formed in a region outside the channel region 15c, of the region of the oxide semiconductor layer 15 facing the bottom electrode 61. The oxide semiconductor layer 15 is composed of an oxide semiconductor containing, as a main component, an oxide of at least one element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), and niobium (Nb). As the oxide semiconductor layer 15, for example, indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO: InGaZnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin oxide (ITO), indium oxide (InO), etc. can be used. In this embodiment, the oxide semiconductor layer 15 is an indium gallium zinc oxide film.

The gate insulating layer 17 is an insulating layer disposed above the oxide semiconductor layer 15. The gate insulating layer 17 is disposed directly below the gate electrode 18. The length of the channel region 15c of the oxide semiconductor layer 15 in the channel length direction of the gate insulating layer 17 is longer than the length of the gate electrode 18 in the channel length direction. For example, in a so-called self-aligned structure in which the gate insulating layer has a shape with the gate electrode, a current leak may occur between the gate electrode and the oxide semiconductor layer. In this embodiment, since the gate insulating layer 17 has the shape as described above, the current leak that may occur in the self-aligned structure can be suppressed. The configuration of the gate insulating layer 17 is not particularly limited as long as it is an insulating layer. As the gate insulating layer 17, for example, a single layer film made of one of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), a silicon oxynitride film (SiON), an aluminum oxide film (AlO _x ), and a hafnium oxide (HfO _x ), or a stacked film made of two or more of them can be used. In this embodiment, the gate insulating layer 17 is a silicon oxide film (SiO _x ).

The gate electrode 18 is a conductive layer disposed above the gate insulating layer 17. The gate electrode 18 faces the channel region of the oxide semiconductor layer 15 via the gate insulating layer 17. The gate electrode 18 controls the carrier density in the channel region by the gate voltage applied thereto, and also functions as a wiring that supplies a potential. The gate electrode 18 is composed of, for example, a simple substance containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu), or an alloy. The gate electrode 18 may also be a compound containing at least one of the above metals, or a laminated film containing two or more metals. The gate electrode 18 may also be a transparent conductive film such as ITO.

The interlayer insulating films 19 and 21 are insulating films disposed above the gate electrode 18. The interlayer insulating film 19 is disposed on the gate electrode 18 and the gate insulating layer 17. For example, an insulating film similar to the bottom insulating layer 62 described above can be used as the interlayer insulating film 19. In this embodiment, the interlayer insulating film 19 has a first insulating film 19a disposed above the gate electrode 18 and the gate insulating layer 17, and a second insulating film 19b disposed above the first insulating film 19a. For example, the first insulating film 19a is a silicon oxide film (SiO _x ), and the second insulating film 19b is an aluminum oxide film (AlO _x ). The interlayer insulating film 21 is an insulating film disposed on the interlayer insulating film 19. For example, a resin film having photosensitivity can be used as the interlayer insulating film 21. Specifically, for example, a polyimide resin film, a novolac resin, an acrylic resin, or the like can be used as the interlayer insulating film 21. In this embodiment, the interlayer insulating film 21 is a polyimide resin film.

The source electrode 22 and the drain electrode 23 are electrodes that function as the source and drain of the thin film transistor 10, and are made of, for example, the same metals and transparent conductive films as those listed as the constituent materials of the gate electrode 18. Materials with good electrical conductivity may be selected for the source electrode 22 and the drain electrode 23. The source electrode 22 and the drain electrode 23 are connected to the low resistance region 15n of the oxide semiconductor layer 15 via connection holes that penetrate the interlayer insulating films 19 and 21 and the gate insulating layer 17.

[1-2. Manufacturing method]
Next, a method for manufacturing the thin film transistor 10 according to the present embodiment will be described with reference to Fig. 2 to Fig. 4K. Fig. 2 is a top view showing a schematic configuration of the thin film transistor 10 according to the present embodiment. 2 shows a top view of the main surface of the substrate 11 of the thin film transistor 10 shown in FIG. 3A to 3J show respective steps of a method for manufacturing the thin film transistor 10 according to the present embodiment. 3A to 3J are cross-sectional views taken along line III-III in FIG. 2. FIGS. 4A to 4K are cross-sectional views taken along line III-III in FIG. 4A to 4K are cross-sectional views parallel to the channel width direction, illustrating steps of a method for manufacturing the thin-film transistor 10. The cross section taken along line IV-IV in FIG.

First, as shown in FIG. 3A and FIG. 4A, a bottom electrode 61 is formed on the entire surface of one of the main surfaces of the substrate 11 by, for example, a sputtering method, and then a bottom insulating layer 62 is formed on the entire surface above the bottom electrode 61 by, for example, a plasma CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 3B and FIG. 4B, the shield electrode 12 and the shield insulating layer 13 are formed. Specifically, a conductive film is formed on the entire surface above the bottom insulating layer 62, for example, by using a sputtering method. The conductive film is then patterned into a predetermined shape, for example, by using a photolithography method and a wet etching method, to form the shield electrode 12 of a predetermined shape. Next, the shield insulating layer 13 is formed above the shield electrode 12 and the bottom insulating layer 62. Specifically, a lower insulating layer 13a and an upper insulating layer 13b are formed above the shield electrode 12 and the bottom insulating layer 62, for example, by using a plasma CVD method.

Next, as shown in Figures 3C and 4C, an oxide semiconductor layer 15 is formed above the shield insulating layer 13. Specifically, an oxide semiconductor film is formed on the entire surface of the shield insulating layer 13 by, for example, a sputtering method, and then the oxide semiconductor film is patterned into a predetermined shape by, for example, a photolithography method and a wet etching method, thereby forming an oxide semiconductor layer 15 of a predetermined shape at a position facing the shield electrode 12.

Next, as shown in Figures 3D and 4D, a gate insulating layer 17 is formed above the shield insulating layer 13 and the oxide semiconductor layer 15 using, for example, a plasma CVD method.

Next, as shown in FIG. 4E, contact holes 12HA and 61HA are formed. The contact hole 12HA is formed in the shield insulating layer 13 and gate insulating layer 17 on the shield electrode 12, and is a hole that exposes the shield electrode 12. The contact hole 61HA is formed in the shield insulating layer 13, gate insulating layer 17, and bottom insulating layer 62 on the bottom electrode 61, and is a hole that exposes the bottom electrode 61. The contact hole 61HA is formed in an area where the shield electrode 12 is not formed. The contact holes 12HA and 61HA are formed, for example, using a photolithography method and a dry etching method. The contact holes 12HA and 61HA may be formed simultaneously or separately. In addition, the process of etching the shield insulating layer 13 and the gate insulating layer 17 and the process of etching the bottom insulating layer 62 may be performed separately.

Next, as shown in FIG. 3E and FIG. 4F, the gate electrode 18 and the contact electrodes 12CA and 61CA are formed. The contact electrode 12CA is an electrode formed in the contact hole 12HA and is connected to the shield electrode 12. The contact electrode 61CA is an electrode formed in the contact hole 61HA and is connected to the bottom electrode 61. Specifically, a conductive film is formed on the entire surface above the gate insulating layer 17 and each contact hole, for example, by using a sputtering method. Then, the conductive film is patterned into a predetermined shape, for example, by using a photolithography method and a wet etching method, to form the gate electrode 18 and the contact electrodes 12CA and 61CA of the predetermined shape.

Next, as shown in Figures 3F and 4G, an interlayer insulating film 19 is formed above the gate insulating layer 17, the gate electrode 18, and the contact electrodes 12CA and 61CA, for example, by using a plasma CVD method. Specifically, a first insulating film 19a and a second insulating film 19b are formed above the gate insulating layer 17, the gate electrode 18, and the contact electrodes 12CA and 61CA, for example, by using a plasma CVD method.

Next, as shown in Figures 3G and 4H, an interlayer insulating film 21 is formed above the interlayer insulating film 19. The interlayer insulating film 21 is formed by applying a photosensitive resin made of, for example, a polyimide material onto the interlayer insulating film 19, and then performing a heat treatment (pre-bake).

Subsequently, as shown in FIG. 3H and FIG. 4I, contact holes 22HA, 23HA, 12HB, 18HA, and 61HB are formed in the interlayer insulating film 21. The contact hole 22HA is formed above a region where one side of the low resistance region 15n is formed with respect to the channel region 15c of the oxide semiconductor layer 15. The contact hole 23HA is formed above a region where the other side of the low resistance region 15n is formed with respect to the channel region 15c of the oxide semiconductor layer 15. The contact hole 12HB is formed above the contact electrode 12CA. The contact hole 18HA is formed above the gate electrode 18. The contact hole 61HB is formed above the contact electrode 61CA. Each contact hole is formed, for example, by performing exposure and development on the interlayer insulating film 21.

Subsequently, as shown in FIG. 3I and FIG. 4J, contact holes 22HB, 23HB, 12HC, 18HB, and 61HC are formed in the interlayer insulating film 19 and the gate insulating layer 17. Contact hole 22HB is formed at the bottom of contact hole 22HA. Contact hole 23HB is formed at the bottom of contact hole 23HA. Contact hole 12HC is formed at the bottom of contact hole 12HB. Contact hole 18HB is formed at the bottom of contact hole 18HA. Contact hole 61HC is formed at the bottom of contact hole 61HB. Each contact hole is formed, for example, by using photolithography and dry etching.

Next, as shown in FIG. 3J and FIG. 4K, the source electrode 22, the drain electrode 23, and the contact electrodes 12CB, 18C, and 61CB are formed. The source electrode 22 is formed in the contact holes 22HA and 22HB, and is connected to the low resistance region 15n of the oxide semiconductor layer 15. The drain electrode 23 is formed in the contact holes 23HA and 23HB, and is connected to the low resistance region 15n of the oxide semiconductor layer 15. The contact electrode 12CB is an electrode formed in the contact holes 12HB and 12HC, and is connected to the contact electrode 12CA. The contact electrode 18C is an electrode formed in the contact holes 18HA and 18HB, and is connected to the gate electrode 18. The contact electrode 61CB is an electrode formed in the contact holes 61HB and 61HC, and is connected to the contact electrode 61CA.

In this manner, the thin-film transistor 10 shown in Figure 1 can be manufactured.

[1-3. Effects]
Next, the effects of the thin film transistor 10 according to the present embodiment will be described with reference to Figures 5 to 7, in comparison with a thin film transistor of a comparative example. Figure 5 is a schematic cross-sectional view showing the configuration of a main part of a thin film transistor 910 of the comparative example.

5 includes a substrate 11, a lower electrode 912, a lower insulating layer 913, an oxide semiconductor layer 915, a metal oxide film 916, a gate insulating layer 917, a gate electrode 18, interlayer insulating films 19 and 21, a source electrode 22, and a drain electrode 23. The thin film transistor 910 of the comparative example differs from the thin film transistor 10 of the present embodiment in that it does not include a bottom electrode 61, a bottom insulating layer 62, a shield electrode 12, and a shield insulating layer 13, and in that it includes the configuration of the oxide semiconductor layer 915 and the gate insulating layer 917, the lower electrode 912, the lower insulating layer 913, and the metal oxide film 916, but is the same in other respects. The differences between the thin film transistor 910 of the comparative example and the thin film transistor 10 of the present embodiment will be described below.

The lower electrode 912 is disposed above the substrate 11 in a position facing the oxide semiconductor layer 915. The lower electrode 912 differs from the shield electrode 12 of this embodiment in size and shape, but is otherwise identical in configuration.

The lower insulating layer 913 has a lower insulating layer 913a and an upper insulating layer 913b. The lower insulating layer 913 differs from the shield insulating layer 13 of this embodiment in cross-sectional shape, but is otherwise identical in configuration.

The oxide semiconductor layer 915 has a channel region 915c and a low-resistance region 915n. The low-resistance region 915n of the comparative example is made to have a low resistance when the gate electrode 18 and the gate insulating layer 917 are dry-etched. The low-resistance region 915n formed by dry etching or the like can extend to the region between the gate insulating layer 917 and the lower insulating layer 913 as shown in FIG. 5. In the example shown in FIG. 5, the length of the low-resistance region 915n extending from the end of the gate insulating layer 917 in the channel length direction to the region between the gate insulating layer 917 and the lower insulating layer 913 (hereinafter also referred to as the "extension length") is shown as ΔL/2. In other words, the channel length of the channel region 915c of the comparative example is shorter by ΔL than the length of the gate electrode 18 (and the gate insulating layer 917) in the channel length direction.

The gate insulating layer 917 has the same shape as the gate electrode 18 when viewed from above the substrate 11. The gate insulating layer 917 is patterned, for example, by a dry etching method or the like at the same time as the gate electrode 18. When the gate insulating layer 917 is patterned in this manner, a low-resistance region 915n of the oxide semiconductor layer 915 is formed.

The metal oxide film 916 is a layer disposed above the gate electrode 18 and the oxide semiconductor layer 915. The metal oxide film 916 is disposed on the low resistance region 915n of the oxide semiconductor layer 915, and has the function of stabilizing the electrical resistance of the low resistance region 915n.

In the comparative thin film transistor 910 having the above-mentioned configuration, as described above, the low resistance region 915n extends from the end of the gate insulating layer 917 in the channel length direction to the region between the gate insulating layer 917 and the lower insulating layer 913. The influence of such a low resistance region 915n on the characteristics of the thin film transistor 910 will be described with reference to FIG. 6. FIG. 6 is a graph showing a simulation result of the relationship between the gate voltage Vg and the drain current Id of the comparative thin film transistor 910. FIG. 6 shows the relationships when the extension length ΔL/2 of the low resistance region 915n is 0.7 μm (solid curve), 2.5 μm (dashed curve), and 3 μm (dotted curve). In this simulation, the length of the gate electrode 18 in the channel length direction is 6 μm, and the channel width of the channel region 915c is 10 μm. The oxide semiconductor layer 915 is an IGZO film having a thickness of 30 nm, the lower insulating layer 913a is an _SiNx film having a thickness of 50 nm, and the upper insulating layer 913b is an _SiOx film having a thickness of 100 nm. The gate insulating layer 917 is an _SiOx film having a thickness of 200 nm, and the metal oxide film 916 is an _AlOx film having a thickness of 10 nm. The first insulating film 19a of the interlayer insulating film 19 is an _SiOx film having a thickness of 100 nm, and the second insulating film 19b is an _AlOx film having a thickness of 50 nm. The drain voltage is 10 V.

As shown in FIG. 6, in the comparative thin-film transistor 910, the on/off characteristics of the thin-film transistor 910 vary depending on the extension length ΔL/2 of the low-resistance region 915n. Furthermore, when the extension length ΔL/2 is 3 μm, the thin-film transistor 910 cannot achieve an off state, as shown by the dotted curve in FIG. 6. This problem is particularly noticeable when the channel length is short (e.g., about 6 μm or less).

Here, the characteristics of the thin film transistor 10 according to the present embodiment will be described with reference to FIG. 7. FIG. 7 is a graph showing a simulation result of the relationship between the gate voltage Vg and the drain current Id of the thin film transistor 10 according to the present embodiment. FIG. 7 shows the respective relationships when the drain voltage Vd is 10 V (solid curve) and 0.1 V (dashed curve). In this simulation, the length of the gate electrode 18 in the channel length direction is 6 μm, and the channel width of the channel region 15c is 10 μm. The oxide semiconductor layer 15 is an IGZO film with a thickness of 30 nm, the lower insulating layer 13a is a SiN _x film with a thickness of 50 nm, and the upper insulating layer 13b is a SiO _x film with a thickness of 100 nm. The gate insulating layer 17 is a SiO _x film with a thickness of 200 nm. The first insulating film 19a of the interlayer insulating film 19 is a SiO _x film with a thickness of 100 nm, and the second insulating film 19b is an AlO _x film with a thickness of 50 nm. The drain voltage is 10 V, and 0 V is applied to the source electrode 22 and the shield electrode 12 (that is, they are maintained at the ground potential).

1, the thin-film transistor 10 according to the present embodiment includes a bottom electrode 61, a bottom insulating layer 62 disposed above the bottom electrode 61, a shield electrode 12 disposed above the bottom insulating layer 62, a shield insulating layer 13 disposed above the shield electrode 12, an oxide semiconductor layer 15 disposed above the shield insulating layer 13 and having a channel region 15c, a gate insulating layer 17 disposed above the oxide semiconductor layer 15, and a gate electrode 18 disposed above the gate insulating layer 17. The shield electrode 12 is disposed in a position facing the gate electrode 18 and the oxide semiconductor layer 15.

In the thin film transistor 10 having such a configuration, a low resistance region 15n can be formed in the oxide semiconductor layer 15 by an electric field generated by applying a predetermined voltage to the bottom electrode 61. For example, a positive potential (about 10 V) is applied to the bottom electrode. As a result, the carriers in the oxide semiconductor layer 15 are excited by the electric field generated by applying a voltage to the bottom electrode 61, and the oxide semiconductor layer 15 is made low-resistance. Here, the shield electrode 12 is disposed between the bottom electrode 61 and the oxide semiconductor layer 15 at a position facing the gate electrode 18. Therefore, the electric field formed by the bottom electrode 61 is not applied to the region of the oxide semiconductor layer 15 facing the gate electrode 18. Therefore, it is possible to suppress the low resistance region 15n from extending between the gate electrode 18 and the shield insulating layer 13. As described above, the region where the electric field is applied to the oxide semiconductor layer 15 can be controlled by the shield electrode 12, so that the range in which the low resistance region 15n is formed can be precisely controlled. Therefore, the variation in the characteristics of the thin film transistor 10 can be reduced.

The length of the shield electrode 12 in the channel length direction may be equal to or less than the length of the gate electrode 18 in the channel length direction. This allows the low-resistance region 15n to be formed in the region of the oxide semiconductor layer 15 facing the gate electrode 18, thereby ensuring a connection between the low-resistance region 15n and the channel region 15c.

The length of the shield electrode 12 in the channel length direction may be equal to the length of the gate electrode 18 in the channel length direction. Here, the state where these lengths are equal includes not only a state where these lengths are completely equal, but also a state where these lengths are substantially equal. For example, the state where these lengths are equal includes a state where the difference between these lengths is less than 10% of one length. The same applies to other descriptions of "lengths are equal" in this specification. In this way, by making the length of the shield electrode 12 in the channel length direction equal to the length of the gate electrode 18 in the channel length direction, it is possible to suppress the resistance of the region of the oxide semiconductor layer 15 facing the gate electrode 18 from being reduced, and a channel region 15c can be formed in the region of the oxide semiconductor layer 15 facing the gate electrode 18.

(Embodiment 2)
A semiconductor device according to a second embodiment will be described. In this embodiment, a thin film transistor, which is an example of a semiconductor device, will be described. The thin film transistor according to this embodiment differs from the thin film transistor 10 according to the first embodiment mainly in that it has a top-gate self-aligned structure. The thin film transistor according to this embodiment will be described below, focusing on the differences from the thin film transistor 10 according to the first embodiment.

[2-1. Configuration]
First, the configuration of the thin film transistor according to the present embodiment will be described with reference to Fig. 8. Fig. 8 is a schematic cross-sectional view showing the configuration of a main part of a thin film transistor 110 according to the present embodiment.

8, the thin-film transistor 110 includes a bottom electrode 61, a bottom insulating layer 62, a shield electrode 12, a shield insulating layer 13, an oxide semiconductor layer 15, a gate insulating layer 117, and a gate electrode 18. In this embodiment, the thin-film transistor 110 further includes a substrate 11, a metal oxide film 116, interlayer insulating films 119 and 21, a source electrode 22, and a drain electrode 23. The following describes the differences between the thin-film transistor 110 of this embodiment and the thin-film transistor 10 of embodiment 1.

As described above, the thin-film transistor 110 according to the present embodiment has a top-gate self-aligned structure. That is, the gate insulating layer 117 is patterned simultaneously with the gate electrode 18. As a result, when viewed from above the substrate 11, the gate insulating layer 117 has substantially the same shape as the gate electrode 18. Therefore, the length of the gate insulating layer 117 in the channel length direction of the channel region 15c is equal to the length of the gate electrode 18 in the channel length direction.

The metal oxide film 116 is a layer disposed above the gate electrode 18 and the oxide semiconductor layer 15. For example, an aluminum oxide film (AlO _x ) can be used as the metal oxide film 116. Note that, for example, titanium oxide (TiO _x ), tungsten oxide (WO _x ), tantalum oxide (TaO _x ), zirconium oxide (ZrO _x ), molybdenum oxide (MoO _x ), etc. may also be used as the metal oxide film 116.

The interlayer insulating film 119 is an insulating film disposed above the metal oxide film 116. For example, an insulating film similar to the bottom insulating layer 62 according to the first embodiment described above can be used as the interlayer insulating film 119. In this embodiment, the interlayer insulating film 119 has a first insulating film 119a disposed above the metal oxide film 116 and a second insulating film 119b disposed above the first insulating film 119a. The first insulating film 119a is a silicon oxide film (SiO _x ), and the second insulating film 119b is an aluminum oxide film (AlO _x ).

[2-2. Manufacturing method]
A method for manufacturing the thin film transistor 110 according to the present embodiment will be described. The method for manufacturing the thin film transistor 110 according to the present embodiment has the following features: in the step of forming the gate electrode 18, the gate insulating layer 117 is also patterned together with the gate electrode 18. The method for manufacturing the thin film transistor 10 according to the present embodiment differs from the method for manufacturing the thin film transistor 10 according to the first embodiment in that a step of forming the metal oxide film 116 is added, but the other points are the same. The differences will be described below.

First, similarly to embodiment 1, a bottom electrode 61, a bottom insulating layer 62, a shield electrode 12, a shield insulating layer 13, and an oxide semiconductor layer 15 are formed above the substrate 11.

Next, an insulating film that will be the base material for the gate insulating layer 117 is formed on the entire surface above the oxide semiconductor layer 15 and the shield insulating layer 13.

Next, a conductive film that will serve as the base material for the gate electrode 18 is formed over the entire surface above the insulating film.

Then, the conductive film and the insulating film are patterned into a predetermined shape by photolithography and dry etching to form the gate electrode 18 and the gate insulating layer 117 of a predetermined shape. More specifically, the gate electrode 18 and the gate insulating layer 117 are formed by removing a part of the conductive film and the insulating film using the oxide semiconductor layer 15 as an etching stopper. As the etching material used here, for example, chlorine (Cl ₂ ) and carbon tetrafluoride (CF ₄ ) can be used. The etching material is not limited to the above-mentioned materials. For example, the etching material does not have to be an etching material using the above-mentioned chemical reaction, and may be, for example, Ar plasma.

Next, a metal oxide film 116 is formed above the gate electrode 18, the oxide semiconductor layer 15, and the shield insulation layer 13.

Next, the interlayer insulating films 119 and 21, the source electrode 22, the drain electrode 23, and each contact electrode are formed above the metal oxide film 116, as in the first embodiment.

In this manner, the thin-film transistor 110 shown in Figure 8 can be manufactured.

[2-3. Effects]
Similar to the thin-film transistor 10 according to the first embodiment, the thin-film transistor 110 according to the present embodiment includes a bottom electrode 61, a bottom insulating layer 62 arranged above the bottom electrode 61, a shield electrode 12 arranged above the bottom insulating layer 62, a shield insulating layer 13 arranged above the shield electrode 12, an oxide semiconductor layer 15 arranged above the shield insulating layer 13 and having a channel region 15c, a gate insulating layer 117 arranged above the oxide semiconductor layer 15, and a gate electrode 18 arranged above the gate insulating layer 117. The shield electrode 12 is arranged at a position facing the gate electrode 18 and the oxide semiconductor layer 15.

As a result, similar to the thin-film transistor 10 according to embodiment 1, the variation in characteristics of the thin-film transistor 110 according to this embodiment can be reduced.

(Application Example 1)
A first application example of the thin film transistors according to the above-described embodiments will be described with reference to Fig. 9. Fig. 9 and Fig. 10 are block diagrams showing the functional configurations of a display device 2A and an imaging device 2B to which the thin film transistors according to the above-described embodiments are applied, respectively.

The display device 2A shown in FIG. 9 is a device that displays an image based on an externally input video signal or an internally generated video signal. The display device 2A is, for example, an organic EL (Electro Luminescence) display or a liquid crystal display. Functionally, the display device 2A includes, for example, a timing control unit 31, a signal processing unit 32, a drive unit 33, and a display pixel unit 34.

The timing control unit 31 has a timing generator that generates various timing signals (i.e., control signals) and is a processing circuit that controls the operation of the signal processing unit 32 and other components based on these various timing signals.

The signal processing unit 32 is, for example, a processing circuit that performs a predetermined correction on a digital video signal input from outside and outputs the resulting video signal to the driving unit 33.

The drive unit 33 includes, for example, a scanning line drive circuit, a signal line drive circuit, etc., and is a circuit that drives each pixel of the display pixel unit 34 via various control lines.

The display pixel unit 34 is a display circuit that includes a display element, such as an organic EL element or a liquid crystal display element, and a pixel circuit for driving the display element for each pixel.

Of the above circuits of the display device 2A, the thin-film transistors described above are applied to, for example, various circuits that constitute part of the drive unit 33 and the display pixel unit 34.

The imaging device 2B shown in FIG. 10 is, for example, a solid-state imaging device that acquires an image as an electrical signal, and includes, for example, a CCD (Charge-Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. Functionally, the imaging device 2B includes, for example, a timing control unit 35, a driving unit 36, an imaging pixel unit 37, and a signal processing unit 38.

The timing control unit 35 has a timing generator that generates various timing signals (i.e., control signals) and is a processing circuit that controls the drive of the drive unit 36 based on these various timing signals.

The drive unit 36 includes, for example, a row selection circuit, an AD conversion circuit, a horizontal transfer scanning circuit, etc., and is a circuit that reads out signals from each pixel of the imaging pixel unit 37 via various control lines.

The imaging pixel unit 37 is an imaging circuit that includes an imaging element (i.e., a photoelectric conversion element) such as a photodiode, and a pixel circuit for signal readout.

The signal processing unit 38 is a processing circuit that performs various signal processing on the signal obtained from the imaging pixel unit 37.

Of the above circuits of the imaging device 2B, for example, the thin-film transistors according to the above embodiments are applied to various circuits that constitute part of the drive unit 36 and the imaging pixel unit 37.

(Application Example 2)
A second application example of the thin film transistor according to each of the above embodiments will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a functional configuration of an electronic device 3 to which the thin film transistor according to each of the above embodiments is applied.

The electronic device 3 is a device that includes the display device 2A and the imaging device 2B. Examples of the electronic device 3 include a television device, a personal computer (PC), a smartphone, a tablet PC, a mobile phone, a digital still camera, and a digital video camera.

The electronic device 3 has an image device 2 including, for example, the above-mentioned display device 2A (or imaging device 2B), and an interface unit 40. The interface unit 40 is an input unit to which various signals, power, etc. are input from the outside. This interface unit 40 may include a user interface such as, for example, a touch panel, a keyboard, and operation buttons.

In this way, the thin-film transistors according to the above embodiments are also applied to electronic device 3.

Other Embodiments
Although the semiconductor device and the like according to the present disclosure have been described above based on the embodiments, the semiconductor device and the like according to the present disclosure are not limited to the above-mentioned embodiments. This disclosure also includes other embodiments realized by combining any components in each embodiment, and modified examples obtained by applying various modifications to each embodiment that a person skilled in the art can think of without departing from the spirit of this disclosure.

For example, the semiconductor device according to the present disclosure does not necessarily have to include all of the components included in the thin film transistor according to each of the above embodiments. For example, the semiconductor device according to the present disclosure does not necessarily have to include the interlayer insulating films 19, 21, and 119.

This disclosure is useful for electronic devices such as display devices and imaging devices that use thin-film transistors.

2 Image device 2A Display device 2B Imaging device 3 Electronic device 10, 110, 910 Thin film transistor 11 Substrate 12 Shield electrode 12CA, 12CB, 18C, 61CA, 61CB Contact electrode 12HA, 12HB, 12HC, 18HA, 18HB, 22HA, 22HB, 23HA, 23HB, 61HA, 61HB, 61HC Contact hole 13 Shield insulating layer 13a, 913a Lower insulating layer 13b, 913b Upper insulating layer 15, 915 Oxide semiconductor layer 15c, 915c Channel region 15n, 915n Low resistance region 17, 117, 917 Gate insulating layer 18 Gate electrode 19, 21, 119 Interlayer insulating film 19a, 119a First insulating film 19b, 119b Second insulating film 22 Source electrode 23 Drain electrode 31, 35 Timing control section 32, 38 Signal processing section 33, 36 Driving section 34 Display pixel section 37 Imaging pixel section 40 Interface section 116, 916 Metal oxide film 912 Lower electrode

Claims (7)

A substrate;
a bottom electrode disposed above the substrate;
a bottom insulating layer disposed above the bottom electrode;
a shield electrode disposed above the bottom insulating layer;
a shield insulation layer disposed above the shield electrode;
an oxide semiconductor layer disposed above the shield insulation layer and having a channel region;
a gate insulating layer disposed above the oxide semiconductor layer;
a gate electrode disposed above the gate insulating layer;
the shield electrode is disposed at a position facing the gate electrode and the oxide semiconductor layer ,
A ground potential is applied to the shield electrode.
Semiconductor device. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is disposed at a position facing the bottom electrode. The semiconductor device according to claim 1 , wherein a length of the bottom electrode in a channel length direction of the channel region is longer than a length of the shield electrode in the channel length direction. 4. The semiconductor device according to claim 1, wherein a length of said gate insulating layer in a channel length direction of said channel region is longer than a length of said gate electrode in said channel length direction. 4. The semiconductor device according to claim 1, wherein a length of said gate insulating layer in a channel length direction of said channel region is equal to a length of said gate electrode in said channel length direction. 6. The semiconductor device according to claim 1, wherein a positive potential is applied to the bottom electrode. The semiconductor device further includes a drain electrode and a source electrode connected to the oxide semiconductor layer,
7. The semiconductor device according to claim 1, wherein the shield electrode has the same potential as the source electrode.

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