JP7597644B2 - Gate Driver - Google Patents

Description

The present invention relates to a gate drive device.

In recent years, some gate drive devices such as inverters that have semiconductor switching elements in the upper and lower arms to supply power to a load have used SiCMOS transistors as the semiconductor switching elements. When using a body diode in a SiCMOS transistor, the on-voltage is high, resulting in large losses, and degradation of the body diode due to current flow can also be an issue.

By performing synchronous rectification, losses can be reduced and the stress on the elements can be reduced by shortening the time that current flows through the body diode. With synchronous rectification control, it is necessary to set a dead time DT (Dead Time) between the opposing arm being turned off and the own arm being turned on to prevent short circuits in the upper and lower arms, and it is necessary to shorten the dead time to reduce inverter losses.

One method for shortening the dead time is to measure the actual dead time and provide feedback to control it accordingly for the next operation. However, in practice, there is a concern that control variations or control failures may cause short circuits in the upper and lower arms.

However, on the other hand, a recovery current due to the body diode flows when the arm is turned on, which can cause a large current to flow even in normal conditions. To avoid this, a method is sometimes used in which a mask period is set to prevent false short circuit detection immediately after turning on the arm, and a short circuit is detected when the detection threshold is exceeded after the mask period has elapsed.

However, with this method, it is not possible to detect short circuits during the mask period, meaning that it is not possible to detect short circuits at the moment of turn-on or immediately afterwards, and there remains the issue that minute short circuit currents cannot be detected when the dead time is made too short.

WO2018/193527 publication

The present invention was made in consideration of the above circumstances, and its purpose is to provide a gate drive device that can detect a short circuit state even immediately after the gate of a gate-driven semiconductor switching element is turned on, and can also be used as a fail-safe for dead time shortening control, such as by providing feedback to a set dead time that is too short.

The gate drive device according to claim 1 is a gate drive device in a configuration in which gate drive type semiconductor switching elements are arranged in upper and lower arms to supply power to a load, and drive control is performed by providing gate drive signals to the semiconductor switching elements by control circuits provided corresponding to each of the semiconductor switching elements based on an on/off command signal, and the gate drive device comprises a differentiation circuit that detects a time change in current of the semiconductor switching elements, and a comparison circuit that outputs a detection signal when a time change in the current detected by the differentiation circuit during a return period of a recovery current is equal to or greater than a predetermined level, and the control circuit determines whether or not the upper and lower arms are in a short-circuited state based on the on/off command signal and the detection signal from the comparison circuit, and drives and controls the semiconductor switching elements by gate drive signals with a dead time adjusted and set based on the result of the determination.

By adopting the above configuration, when the control circuit turns on the semiconductor switching element corresponding to itself, the current flowing through the semiconductor switching element is differentiated by the differentiation circuit to detect the amount of change over time, and it is determined whether the amount of change over time during the return period of the recovery current is equal to or greater than a predetermined level.

At this time, if the amount of change over time is not equal to or greater than a predetermined level, a short circuit has not occurred, and the dead time is set appropriately. If the amount of change over time is equal to or greater than a predetermined level, it is determined that a short circuit has occurred, and the dead time is adjusted and set. As a result, the semiconductor switching element of the opposing arm is turned on at the timing at which the dead time is adjusted.

This makes it possible to quickly determine the short-circuit state immediately after the arm is turned on within this period without having to set a mask period immediately after the gate is turned on, and it is possible to suppress the short-circuit energy to an extent that does not damage the semiconductor switching elements. It can also be used as a fail-safe for dead-time shortening control, such as by providing feedback to a set dead-time that is too short, making it possible to shorten the dead-time as much as possible.

In addition, because the slope of the recovery current return of the semiconductor switching element is detected by a differential circuit, it is possible to eliminate the need for a mask period and prevent erroneous detection of overcurrent that occurs when only the current value of the semiconductor switching element is monitored.

Electrical configuration diagram showing the first embodiment 1 is a timing chart showing a first embodiment; FIG. 1 is an explanatory diagram showing the operation of the first embodiment; Electrical configuration diagram showing the second embodiment Timing chart showing the second embodiment Electrical configuration diagram showing a third embodiment Timing chart showing the third embodiment Electrical configuration diagram showing a fourth embodiment

First Embodiment
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG.
1 showing the electrical configuration, the upper and lower arms are composed of N-channel type SiCMOS transistors (hereinafter simply referred to as MOS transistors) 1a and 1b which are semiconductor switching elements connected in series. The MOS transistor 1a is arranged in the lower arm, and the MOS transistor 1b is arranged in the upper arm. The MOS transistors 1a and 1b have body diodes 2a and 2b, respectively. The common connection point of the MOS transistors 1a and 1b is connected to an inductor 3 which is a load.

The gate drive control of MOS transistors 1a and 1b is performed by gate drive devices 10A and 10B, respectively. Gate drive devices 10A and 10B have the same configuration, and below, the configuration of gate drive device 10A is indicated with the subscript a, and the configuration of gate drive device 10B is indicated with the subscript b. Gate drive devices 10A and 10B are given on-off command signals Sx1 and Sx2, respectively, from microcomputer 4, and output short circuit detection signals Ss1 and Ss2 to microcomputer 4. Below, the configuration of gate drive device 10A will be described as a representative.

The gate drive device 10A includes a control circuit 11a, a sense element 12a for detecting current, a current monitor 13a, a drive circuit 20a, a differentiation circuit 30a, and a comparison circuit 40a. The control circuit 11a receives an on/off command signal Sx1 with an adjusted dead time from the microcomputer 4, and outputs a drive signal to the drive circuit 20a in response to the signal to drive the MOS transistor 1a. The control circuit 11a also functions as a determination unit that, when a high-level detection signal is received from the comparison circuit 40a, determines whether or not a short circuit has occurred and outputs a short circuit detection signal Ss1 to the microcomputer 4.

The sense element 12a can be used when it is built into the MOS transistor 1a, or when it is not built into the MOS transistor 1a, it is provided as a current detection element and is configured to pass a minute current set to a predetermined ratio to the current flowing through the MOS transistor 1a and the body diode 2a. The drain and gate of the sense element 12a are commonly connected to the MOS transistor 1a, and the current flowing through the source is detected by the current monitor 13a.

The drive circuit 20a includes a P-channel MOS transistor 21a for ON drive, an N-channel MOS transistor 22a for OFF drive, and resistors 23a and 24a. The source of the MOS transistor 21a is connected to the drive power supply VCC1, the drain is connected to the gate of the MOS transistor 1a via resistor 23a, and a drive signal is provided from the control circuit 11a. The source of the MOS transistor 22a is connected to the drive power supply VEE1, and the drain is connected to the gate of the MOS transistor 1a via resistor 24a, and a drive signal is provided from the control circuit 11a.

The differentiation circuit 30a includes a differential amplifier 31a, a resistor 32a, and a capacitor 33a. The differential amplifier 31a has an inverting input terminal that receives a voltage signal corresponding to the current value of the MOS transistor 1a from the current monitor 13a via a differentiation capacitor 33a. A resistor 32a is connected between the inverting input terminal and the output terminal of the differential amplifier 31a, and a DC power supply VEE1 is connected to the non-inverting input terminal. The differential amplifier 31a is composed of a high-speed response operational amplifier so that it can perform amplification operations in response to changes in the current of the MOS transistor 1a.

The differentiation circuit 30a outputs from the output terminal a signal obtained by differentiating the current of the MOS transistor 1a, i.e., the voltage signal from the current monitor 13a that monitors the current of the MOS transistor 1a. In other words, the differentiation circuit 30a outputs a signal corresponding to the amount of change over time in the current value of the MOS transistor 1a. The amount of change over time in the current of the MOS transistor 1a detects the speed at which the current increases or decreases, i.e., the slope on the time axis.

The comparison circuit 40a includes a comparator 41a and a reference power supply 42a. The output signal from the differentiation circuit 30a is input to the inverting input terminal of the comparator 41a, and the threshold voltage Vth1 is input to the non-inverting input terminal from the reference power supply 42a. The threshold voltage Vth is a voltage indicating a predetermined negative level for detecting the presence or absence of a short circuit, and when the negative signal level input from the differentiation circuit 30a, i.e., the time change in the return of the recovery current, becomes equal to or less than the threshold voltage Vth, the comparator 41a outputs a high-level detection signal to the control circuit 11a.

Next, the operation of the above configuration will be described with reference to FIGS.
FIG. 2 is a timing chart showing the signal changes of each part, with period (A) being the period when sufficient dead time (hereinafter abbreviated as DT) is secured along the time axis, period (B) being the period when the DT is subsequently insufficient and a short circuit occurs, and period (C) being the period when the DT is adjusted after a short circuit is detected.

Figure 2 also shows the on/off command signals Sx1 and Sx2 and the gate voltages Vgs1 and Vgs2, and illustrates the operation of the gate drive device 10A that occurs when MOS transistor 1a is turned on relative to the off timing of MOS transistor 1b.

In response to an on/off command signal provided from the outside, the microcomputer 4 provides on/off command signals Sx1 and Sx2, in which the DT between the upper and lower arm MOS transistors 1a and 1b has been adjusted, to the gate drive devices 10A and 10B, respectively. At time t0, the on/off command signal Sx2 for MOS transistor 1b turns off, and then at time t1, when a predetermined DT has elapsed, the on/off command signal Sx1 for MOS transistor 1a turns on.

When a gate drive signal is applied from drive circuit 20a to the gate of MOS transistor 1a, gate voltage Vgs1 rises, and when it reaches the threshold voltage, drain current begins to flow, which is detected by current monitor 13a. Immediately after MOS transistor 1a is turned on, a recovery current is superimposed, so that after reaching a peak value, it drops during the return period. If DT is set appropriately, the return of the recovery current at this time has a slope below a certain level, i.e., the amount of change over time is below a certain level.

Figure 3 shows how the slope of the recovery current return waveform is a slope α below a certain level when DT is sufficient, and a slope β above a certain level when DT is zero. Since the slope of the recovery current return waveform is the differential value, it is possible to determine whether DT is insufficient by determining whether the differential value is above a certain level.

At this time, the change in the current of the MOS transistor 1a is detected by the differential circuit 30a. As shown in FIG. 2, the change is a large positive value during the period when the current increases immediately after the transistor is turned on, and is a negative value during the recovery current return period, and then becomes zero when the current value becomes constant.

When DT is sufficiently secured (A), the negative detection value generated by the differentiation circuit 30a during the recovery current return period does not fall below the threshold voltage Vth, so the comparison circuit 40a does not output a detection signal. After this, when the MOS transistor 1a turns off, the current value drops sharply and a large negative value is output from the differentiation circuit 30a. This causes the comparison circuit 40a to output a detection signal.

Even if the detection signal input from the comparison circuit 40a is at a high level, the control circuit 11a does not output the short circuit detection signal Ss1 unless the on/off command signal is on. As a result, the control circuit 11a does not output the short circuit detection signal Ss1 to the microcomputer 4.

Next, we will explain the case (B) where DT is set to approximately zero. This is the case where an on/off command signal Sx1 is output to MOS transistor 1a at approximately the same timing as time t2 when MOS transistor 1b is turned off.

In this case, MOS transistor 1a is turned on while MOS transistor 1b is not completely off. Therefore, a large current flows through MOS transistor 1a, and the return current of the recovery current also becomes a large negative value. As a result, the detection signal from differentiation circuit 30a reaches a level that exceeds the threshold voltage Vth in comparison circuit 40a, and a high-level detection signal is output at time t3.

On the other hand, in the control circuit 11a, since a high-level detection signal is input from the comparison circuit 40a while the on/off command signal Sx1 is in the on state, it is determined that a short circuit has occurred, and a short circuit detection signal Ss1 is generated and output to the microcomputer 4.

The microcomputer 4 adjusts and sets the DT based on the input of the short circuit detection signal Ss1, then adjusts and sets the DT of the on/off command signal Sx2 to be given to the gate drive device 10B, and then lengthens the DT of the on/off command signal Sx1 to be given to the gate drive device 10A. This makes it possible to immediately prevent a short circuit from occurring.

In this embodiment, a differentiation circuit 30a is provided that differentiates the current of the MOS transistor 1a, and a short circuit state is detected when the amount of change in current over time during the recovery current return period is a negative value that falls below the threshold voltage Vth, and the dead time is adjusted.

This makes it possible to quickly determine the short-circuit state immediately after the gates of the MOS transistors 1a and 1b are turned on within this period, without having to provide a mask period, and immediately after the arm is turned on, and it is possible to suppress the short-circuit energy to an extent that does not damage the MOS transistors 1a and 1b. It can also be used as a fail-safe for dead-time shortening control, such as by providing feedback to a set dead-time that is too short, and it is possible to shorten the dead-time as much as possible.

Furthermore, because the return slope of the recovery current of MOS transistors 1a and 1b is detected by differential circuits 30a and 30b, it is possible to eliminate the need to set a mask period and prevent erroneous detection of overcurrent that occurs when short circuit detection of MOS transistors 1a and 1b is performed by monitoring only the current value.

Second Embodiment
4 and 5 show the second embodiment, and the following describes the differences from the first embodiment. In this embodiment, the gate drivers 110A and 110B include control circuits 111a and 111b, respectively.

In FIG. 4, the microcomputer 4 outputs on/off command signals Sx1 and Sx2, with DT not adjusted, to the respective control circuits 111a and 111b. When the control circuit 111a detects a short circuit in the MOS transistor 1a that controls the gate drive, the control circuit 111a outputs the short circuit detection signal Ss1 to the control circuit 111b via the insulating element 5a. When the control circuit 111b detects a short circuit in the MOS transistor 1b that controls the gate drive, the control circuit 111b outputs the short circuit detection signal Ss2 to the control circuit 111a via the insulating element 5b.

Each of the control circuits 111a, 111b is configured to adjust and set DT based on the input short circuit detection signals Ss2, Ss1 to perform on/off drive control for the MOS transistors 1a, 1b that perform gate drive control without going through the microcontroller 4.
Next, the operation of the above configuration will be described with reference to FIG.

Figure 5 is a timing chart showing the signal changes at each part, and shows the same state as in Figure 2. In this embodiment, the microcomputer 4 does not adjust the DT between the upper and lower arm MOS transistors 1a and 1b, and the signal drives the on/off operation between the two transistors alternately at the same timing.

In the gate drive device 110A, the control circuit 111a sets a predetermined DT in response to the on/off command signal Sx1 received from the microcomputer 4, and drives the gate of the MOS transistor 1a by providing a gate drive signal from the drive circuit 20a to the gate of the MOS transistor 1a.

As described above, when the drain current of MOS transistor 1a starts to flow, this is detected by current monitor 13a. If DT is set appropriately, the recovery current of MOS transistor 1a returns with a slope below a certain level, i.e., the amount of change over time is below a certain level. If DT is sufficiently secured (A), the negative detection value generated by differentiation circuit 30a during the period when the recovery current returns does not become equal to or lower than threshold voltage Vth, so comparison circuit 40a does not output a detection signal.

Next, in the case of (B) where DT is set to almost zero, a large current flows through MOS transistor 1a, and the return current of the recovery current also becomes a large negative value. As a result, the detection signal from differentiation circuit 30a reaches a level that exceeds the threshold voltage Vth in comparison circuit 40a, and a high-level detection signal is output at time t3.

On the other hand, in the control circuit 111a, since a high-level detection signal is input from the comparison circuit 40a while the on/off command signal Sx1 is in the on state, it is determined that a short circuit has occurred, and a short circuit detection signal Ss1 is generated and output to the control circuit 111b of the upper arm gate drive device 11B.

Furthermore, the control circuit 111a adjusts and sets the DT to be longer based on the detection of a short circuit, and at the next on timing, the MOS transistor 1a is turned on at a timing at which an appropriate DT is set for the on/off command signal Sx1. This makes it possible to immediately prevent the occurrence of a short circuit.
Therefore, in the second embodiment as well, the same effects as those in the first embodiment can be obtained.

In the above embodiment, the DT adjustment setting is performed by detecting a short circuit obtained by the current of the MOS transistor 1a that the device controls. However, the DT adjustment setting may be performed at the next ON timing of the MOS transistor 1b in the control circuit 111b on the gate drive device 110B side of the opposing arm based on the short circuit detection signal Ss1 obtained at this time.

In other words, when the gate driver 110A receives a short circuit detection signal Ss2 from the gate driver 110B, the gate driver 110A may adjust the DT setting when the MOS transistor 1a is turned on based on the short circuit detection signal Ss2.

Third Embodiment
6 and 7 show the third embodiment, and the following describes the differences from the first embodiment. In this embodiment, the gate drivers 210A and 210B include control circuits 211a and 211b, respectively.

In FIG. 6, the current monitors 13a and 13b are configured to output a voltage signal corresponding to the detected current value to the differential circuits 30a and 30b, and also to the control circuits 211a and 211b. In this embodiment, in order to ensure accuracy in determining the short-circuit state of the MOS transistors 1a and 1b, the control circuits 211a and 211b also include the level of the current value as a determination element in addition to the detection results from the comparison circuits 40a and 40b.

Figure 7 shows the change in gate voltage Vgs and current value before and after ON driving for each MOS transistor 1a, 1b of the own arm and the opposing arm when DT is short and a short circuit occurs.

As shown in the figure, for example, when the MOS transistor of the own arm is on and the MOS transistor of the opposing arm is off, if the timing of both is approximately the same, that is, when DT is close to zero, the peak of the recovery current increases depending on the degree of the short circuit, so by using the current value at this time as a factor in determining whether or not there is a short circuit and combining it with the change in slope from the recovery return, more accurate short circuit detection can be performed.
In addition, by detecting the degree of short circuit, the amount of DT adjustment can be varied depending on the degree of short circuit.

Therefore, this third embodiment can achieve the same effects as the above embodiments, and can also perform more accurate short circuit detection and DT adjustment settings.

Fourth Embodiment
8 shows the fourth embodiment, and the following describes the differences from the first embodiment. In this embodiment, current monitor sense elements 12a and 12b are not provided, and the currents of the MOS transistors 1a and 1b are directly detected by current monitors 14a and 14b.
Therefore, the fourth embodiment can also provide the same effects as the first embodiment.

Other Embodiments
The present invention is not limited to the above-described embodiment, but can be applied to various embodiments without departing from the spirit of the present invention, and can be modified or expanded as follows, for example.

In the above embodiment, a SiCMOS transistor is used as the gate-driven semiconductor switching element, but the MOS transistor may be made of ordinary silicon, or an IGBT (Insulated Gate Bipolar Transistor) may also be used.

Although the present disclosure has been described with reference to the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

In the drawing, 1a and 1b are MOS transistors (semiconductor switching elements), 2a and 2b are body diodes, 3 is an inductor (load), 4 is a microcomputer (general control unit), 10A, 10B, 110A, 110B, 210A, and 210B are gate drive devices, 11a, 11b, 111a, 111b, 211a, and 211b are control circuits, 12a and 12b are sense elements, 13a, 13b, 14a, and 14b are current monitors, 20a and 20b are drive circuits, 30a and 30b are differential circuits, 31a and 31b are differential amplifiers, 33a and 33b are capacitors, and 40a and 40b are comparison circuits.

Claims (5)

A gate drive device in which gate drive type semiconductor switching elements are arranged in upper and lower arms to supply power to a load, and drive control is performed by applying a gate drive signal to the semiconductor switching elements by control circuits (11a, 11b, 111a, 111b, 211a, 211b) provided corresponding to each of the semiconductor switching elements based on an on/off command signal,
A differential circuit (30a, 30b) for detecting a time change in current of the semiconductor switching element;
a comparison circuit (40a, 40b) that outputs a detection signal when a time change amount during a recovery period of the recovery current among the time changes of the current detected by the differentiation circuit is equal to or greater than a predetermined level,
The control circuit determines whether or not the upper and lower arms are in a short-circuited state based on the on/off command signal and the detection signal from the comparison circuit, and drives and controls the semiconductor switching elements with a gate drive signal that adjusts and sets a dead time based on the result of the determination. The control circuit outputs the result of the determination as to whether or not the short circuit state exists to a general control unit (4) that controls the semiconductor switching elements of the upper and lower arms in a general manner, and inputs the on/off command signal in which the dead time is adjusted by the general control unit to drive and control the semiconductor switching elements. The gate drive device described in claim 1. The control circuit receives the on/off command signal, the dead time of which is not adjusted, from a central control unit (4) that centrally controls the semiconductor switching elements of the upper and lower arms, and the control circuits of the upper and lower arms share the result of the determination of whether or not the short circuit state exists, and adjusts and sets the dead time to generate a gate drive signal. The gate drive device described in claim 1. 4. The gate drive device according to claim 1, wherein the control circuit determines whether or not the short circuit state occurs based on a current value of the semiconductor switching element in addition to the on/off command signal and the detection signal from the comparison circuit. The gate drive device according to any one of claims 1 to 3, wherein the semiconductor switching element includes a sense element, and the current of the semiconductor switching element is detected by the current of the sense element.

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