JP7588047B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device, and in particular to a semiconductor device equipped with a through silicon via (TSV).

Various semiconductor devices and manufacturing methods have been proposed that have a structure in which electrodes are provided through through holes that penetrate a semiconductor substrate such as a silicon substrate.

JP 2005-294320 A JP 2010-114201 A JP 2008-53430 A

As a result of extensive research by the inventors into semiconductor devices with TSVs and methods for manufacturing the same, it was discovered that defects such as pinholes can occur in the plating seed layer formed in the through-holes in the silicon substrate, and these defects can cause erosion of the electrode layer formed on the surface of the silicon substrate, which can result in reduced reliability of the semiconductor device.

The main objective of the present invention is to provide a highly reliable semiconductor device having a through electrode provided in a substrate.

The semiconductor device according to the first aspect of the present invention comprises a semiconductor substrate having one main surface and another main surface opposite to the one main surface, a first conductive layer provided on the other main surface, a second conductive layer provided on the semiconductor substrate within a through hole that penetrates the semiconductor substrate in the thickness direction from the one main surface to the other main surface and exposes the first conductive layer, a third conductive layer provided on the first conductive layer within the through hole, and a fourth conductive layer formed at an end of the through hole between the second conductive layer and the third conductive layer.

A semiconductor device according to a second aspect of the present invention comprises a semiconductor substrate having one main surface and another main surface opposite to the one main surface, a first conductive layer provided on the other main surface, a second conductive layer provided on the first conductive layer, a third conductive layer provided on the semiconductor substrate within a through hole that penetrates the semiconductor substrate in a thickness direction from the one main surface to the other main surface to expose the first conductive layer, a fourth conductive layer provided on the first conductive layer within the through hole, and a fifth conductive layer formed integrally with the third conductive layer between the third conductive layer and the fourth conductive layer.

The present invention provides a highly reliable semiconductor device.

FIG. 1A is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention. FIG. 1-2 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention. 1-3 are schematic vertical sectional views for explaining a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention. 1 to 4 are schematic vertical sectional views for explaining a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention. 1 to 5 are schematic vertical sectional views for explaining a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention. FIG. 2 is a partially enlarged schematic vertical sectional view of part A in FIG. 1-3(F). FIG. 3 is a partially enlarged schematic vertical sectional view of the portion B in FIG. 1-3(G). FIG. 4 is a partially enlarged schematic vertical sectional view of part C in FIG. FIG. 5 is a partially enlarged schematic vertical sectional view of the portion D in FIG. 1-4(H). FIG. 6A is a schematic vertical sectional view for explaining a manufacturing method of a semiconductor device according to the second preferred embodiment of the present invention. FIG. 6B is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to the second preferred embodiment of the present invention. FIG. 6C is a schematic vertical sectional view for explaining a manufacturing method of a semiconductor device according to the second preferred embodiment of the present invention. FIG. 6-4 is a schematic vertical sectional view for explaining a manufacturing method of a semiconductor device according to the second preferred embodiment of the present invention. FIG. 7 is a partially enlarged schematic vertical sectional view of a portion E in FIG. 6-1(C). FIG. 8 is a partially enlarged schematic vertical sectional view of the portion F in FIG. 6-2(D). FIG. 9 is a partially enlarged schematic vertical sectional view of the portion G in FIG. 6-2(E). FIG. 10 is a partially enlarged schematic vertical sectional view of the portion H in FIG. 6-3(F). FIG. 11 is a partially enlarged schematic vertical sectional view of part I in FIG. 6-3(G). FIG. 12 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device for comparison. 13 is a partially enlarged schematic vertical sectional view of a portion J in FIG. 12. FIG. FIG. 14 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device for comparison. FIG. 15 is a partially enlarged schematic vertical sectional view of a portion K in FIG.

The following describes a preferred embodiment of the present invention with reference to the drawings.

(First embodiment)
1-5(J), a semiconductor device 1 according to a first preferred embodiment of the present invention includes a semiconductor silicon substrate 10, a silicon oxide film 12, a TiN film 14, an Al film 16, a through hole 20, a CVD oxide film 22, a seed metal layer 24, a Cu plating layer 26, a Cu plating layer 30, and a solder resist 32.

The silicon oxide film 12 is provided on the main surface 11 of the silicon substrate 10. The TiN film 14 is provided on the silicon oxide film 12. The Al film 16 is provided on the TiN film 14. The through hole 20 penetrates the silicon substrate 10 from the main surface 13 opposite to the main surface 11 of the silicon substrate 10 to the main surface 11, and further penetrates the silicon oxide film 12 and the TiN film 14, exposing the Al film 16 at the bottom. The CVD oxide film 22 is provided on the side surface 21 of the through hole 20 and on the main surface 13 of the silicon substrate 10. The seed metal layer 24 is provided on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the Al film 16 exposed at the bottom of the through hole 20. The Cu plating layer 26 is provided on the seed metal layer 24 in the through hole 20, on the seed metal layer 24 on the main surface 13, and on the seed metal layer 24 provided at the bottom of the through hole 20. The Cu plating layer 30 is provided on the Cu plating layer 26 in the through hole 20, on the Cu plating layer 26 on the main surface 13, and on the Cu plating layer 26 provided at the bottom of the through hole 20. The solder resist 32 is provided on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the opening 31 of the Cu plating layer 30 in the through hole 20. Circuit elements (not shown), such as semiconductor elements such as MOS transistors, are formed on the main surface 11 of the silicon substrate 10 and are covered by the silicon oxide film 12. The Al film 16 is used as a device pad for connecting the semiconductor device 1.

Next, a method for manufacturing the semiconductor device 1 according to the first preferred embodiment of the present invention will be described with reference to Figures 1-1 to 1-5 and Figures 2 to 5.

Circuit elements (not shown), such as semiconductor elements such as MOS transistors, are formed on the main surface 11 of the silicon substrate 10.

Referring to FIG. 1-1(A), next, a silicon oxide film 12 is formed on the main surface 11 of the silicon substrate 10, a TiN film 14 is formed on the silicon oxide film 12, and an Al film 16 is formed on the TiN film 14. The TiN film 14 is provided to prevent Al migration.

Referring to FIG. 1-1(B), next, a resist 18 is formed on the main surface 13 opposite the main surface 11 of the silicon substrate 10, and an opening 19 is selectively formed in the resist 18. Thereafter, the silicon substrate 10 is etched using the resist 18 as a mask to form a through hole 20 that penetrates the silicon substrate 10 from the main surface 13 to the main surface 11 of the silicon substrate 10.

Referring to FIG. 1-1(C), next, the silicon oxide film 12 and the TiN film 14 are further etched to expose the Al film 16 at the bottom of the through hole 20.

Referring to FIG. 1-2(D), next, a CVD oxide film 22 is formed on the side surface 21 and bottom of the through hole 20 and on the main surface 13 of the silicon substrate 10.

Referring to FIG. 1-2(E), the CVD oxide film 22 is then etched back to expose the Al film 16 at the bottom of the through hole 20.

Referring to FIG. 1-3(F), next, a seed metal layer 24 is formed by sputtering on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the Al film 16 exposed at the bottom of the through hole 20. The seed metal layer 24 is formed by first sputtering Ti and then sputtering Cu.

Referring to FIG. 1-3(G), next, a Cu plating layer 26 is formed by full-surface Cu plating on the seed metal layer 24 in the through hole 20, on the seed metal layer 24 on the main surface 13, and on the seed metal layer 24 provided at the bottom of the through hole 20. The Cu plating layer 26 is formed by electroless plating or electrolytic plating using the seed metal layer 24.

Referring to FIG. 1-4(H), next, a dry film 28 is formed, and an opening 29 is selectively formed in the dry film 28. The opening 29 is formed to expose the through hole 20 and the Cu plating layer 26 around the through hole 20.

Referring to FIG. 1-4(I), next, using the dry film 28 as a mask, a Cu plating layer 30 is formed on the Cu plating layer 26 in the through hole 20, on the Cu plating layer 26 in the opening 29 of the dry film 28 on the main surface 13, and on the Cu plating layer 26 provided at the bottom of the through hole 20. The Cu plating layer 30 is formed by electrolytic plating using the seed metal layer 24 and the Cu plating layer 26.

Referring to FIG. 1-5(J), next, the dry film 28 is removed, and then the Cu plating layer 26 and the seed metal layer 24 that are not covered by the Cu plating layer 30 are removed. Then, a solder resist 32 is formed on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the opening 31 of the Cu plating layer 30 in the through hole 20.

It is difficult to uniformly form the seed metal layer 24 in the through hole 20 by sputtering, and as shown in FIG. 2, an unsputtered portion 241 may occur at the bottom corner of the through hole 20. In this embodiment, the Cu plating layer 26 is formed on the seed metal layer 24 by full Cu plating, so that the unsputtered portion 241 can be covered by full Cu plating as shown in FIG. 3. Since the Cu plating grows isotropically, the unsputtered portion 241 is filled by the full Cu plating as shown in FIG. 4. Therefore, as shown in FIG. 5, the developer 34 (sodium carbonate mixed solution) of the dry film 28 can be prevented from penetrating the Al film 16 through the unsputtered portion 241 and corroding the Al film 16. The thickness of the Cu plating layer 26 for filling is preferably 1.0 to 1.5 μm.

In contrast, as shown in FIG. 12, if a dry film 28 is formed on the seed metal layer 24 without forming a Cu plating layer 26 on the seed metal layer 24 by Cu plating over the entire surface, and an opening 29 is selectively formed in the dry film 28, as shown in FIG. 13, the developer 34 of the dry film 28 penetrates the Al film 16 through the unsputtered portion 241, erodes the Al film 16, and forms an Al cavity 161. Then, as shown in FIG. 14, a Cu plating layer 30 is formed on the seed metal layer 24 using the dry film 28 as a mask, and then a solder resist 32 is formed. When reflow heat during solder ball formation in the subsequent process, mounting reflow heat during mounting of the semiconductor device 1, external stress, thermal stress, etc. are applied, cracks 221 are generated in the CVD oxide film 22 starting from the Al cavity 161 as shown in FIG. 15, which results in an increased possibility of leakage failure and reduced reliability.

Second Embodiment
Referring to FIG. 6-4(I), a semiconductor device 2 according to a second preferred embodiment of the present invention includes a semiconductor silicon substrate 10, a silicon oxide film 12, a TiN film 14, an Al film 16, a through hole 20, a CVD oxide film 22, a seed metal layer 24, a Cu plating layer 30, and a solder resist 32.

In the first embodiment, the Cu plating layer 26 is formed on the seed metal layer 24 by Cu plating over the entire surface, and the unsputtered portion 241 of the seed metal layer 24 is covered to prevent the developer 34 (sodium carbonate mixed solution) of the dry film 28 from penetrating the Al film 16 through the unsputtered portion 241 and eroding the Al film 16. In contrast, in the present embodiment, the Cu plating layer 26 is not formed on the seed metal layer 24 by Cu plating over the entire surface. In the first embodiment, the silicon oxide film 12 and the TiN film 14 are etched to expose the Al film 16 at the bottom of the through hole 20 (see FIG. 1-1(C)). In the present embodiment, however, only the silicon oxide film 12 is removed, and the TiN film 14 is not removed. Therefore, the through hole 20 penetrates the silicon substrate 10 from the main surface 13 opposite to the main surface 11 of the silicon substrate 10 to the main surface 11, and further penetrates the silicon oxide film 12, exposing the TiN film 14 at the bottom. The CVD oxide film 22 is provided on the side surface 21 of the through hole 20 and on the main surface 13 of the silicon substrate 10. The seed metal layer 24 is provided on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the TiN film 14 exposed at the bottom of the through hole 20. The Cu plating layer 30 is provided on the seed metal layer 24 in the through hole 20, on the seed metal layer 24 on the main surface 13, and on the seed metal layer 24 provided at the bottom of the through hole 20. The solder resist 32 is provided on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the opening 31 of the Cu plating layer 30 in the through hole 20. The silicon oxide film 12 is provided on the main surface 11 of the silicon substrate 10, the TiN film 14 is provided on the silicon oxide film 12, and the Al film 16 is provided on the TiN film 14. Circuit elements (not shown), such as semiconductor elements such as MOS transistors, are formed on the main surface 11 of the silicon substrate 10 and are covered with the silicon oxide film 12.

Next, a method for manufacturing a semiconductor device 2 according to a second preferred embodiment of the present invention will be described with reference to Figures 6-1 to 6-4 and Figures 7 to 11.

Circuit elements (not shown), such as semiconductor elements such as MOS transistors, are formed on the main surface 11 of the silicon substrate 10.

Referring to FIG. 6-1(A), next, a silicon oxide film 12 is formed on the main surface 11 of the silicon substrate 10, a TiN film 14 is formed on the silicon oxide film 12, and an Al film 16 is formed on the TiN film 14. The TiN film 14 is provided to prevent Al migration.

Referring to FIG. 6-1(B), next, a resist 18 is formed on the main surface 13 opposite the main surface 11 of the silicon substrate 10, and an opening 19 is selectively formed in the resist 18. Thereafter, the silicon substrate 10 is etched using the resist 18 as a mask to form a through hole 20 that penetrates the silicon substrate 10 from the main surface 13 to the main surface 11 of the silicon substrate 10.

Referring to FIG. 6-1(C) and FIG. 7, next, the silicon oxide film 12 is further etched to expose the TiN film 14 at the bottom of the through hole 20.

Referring to FIG. 6-2(D) and FIG. 8, next, a CVD oxide film 22 is formed on the side surface 21 and bottom of the through hole 20 and on the main surface 13 of the silicon substrate 10.

Referring to FIG. 6-2(E) and FIG. 9, the CVD oxide film 22 is then etched back to expose the TiN film 14 at the bottom of the through hole 20.

Referring to FIG. 6-3(F) and FIG. 10, next, a seed metal layer 24 is formed by sputtering on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the TiN film 14 exposed at the bottom of the through hole 20. The seed metal layer 24 is formed by first sputtering Ti and then sputtering Cu.

Referring to FIG. 6-3(G), next, a dry film 28 is formed, and an opening 29 is selectively formed in the dry film 28. The opening 29 is formed to expose the through hole 20 and to expose the seed metal layer 24 around the through hole 20.

Referring to FIG. 6-4(H), next, using the dry film 28 as a mask, a Cu plating layer 30 is formed on the seed metal layer 24 in the through hole 20, on the seed metal layer 24 in the opening 29 of the dry film 28 on the main surface 13, and on the seed metal layer 24 provided at the bottom of the through hole 20. The Cu plating layer 30 is formed by electrolytic plating using the seed metal layer 24.

Referring to FIG. 6-5(I), next, the dry film 28 is removed, and then the seed metal layer 24 that is not covered by the Cu plating layer 30 is removed. Then, a solder resist 32 is formed on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the opening 31 of the Cu plating layer 30 in the through hole 20.

It is difficult to uniformly form the seed metal layer 24 in the through hole 20 by sputtering, and as shown in FIG. 11, unsputtered portions 242 may occur at the corners of the bottom of the through hole 20. In this embodiment, the TiN film 14 is left without being removed, so even if unsputtered portions 242 occur, the TiN film 14 acts as a barrier to prevent the developer 34 (sodium carbonate mixed solution) of the dry film 28 from penetrating the Al film 16 through the unsputtered portions 242 and corroding the Al film 16.

Even if the TiN film 14 is left without being removed as in this embodiment, the silicon oxide film 12 is etched. However, due to variations in the etching characteristics in the plane when the TiN film 14 is left at the bottom of the through hole 20, the TiN film 14 may be partially removed, and the developer 34 of the dry film 28 may erode the Al film 16 from the unsputtered portion 242 and the portion from which the TiN film 14 has been partially removed. Therefore, it is more preferable to form a Cu plating layer 26 on the seed metal layer 24 by Cu plating over the entire surface as in the first embodiment.

Although various exemplary embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Therefore, the scope of the present invention is limited only by the following claims.

REFERENCE SIGNS LIST 10 Semiconductor silicon substrate 12 Silicon oxide film 14 TiN film 16 Al film 20 Through hole 22 CVD oxide film 24 Seed metal layer 26 Cu plating layer 28 Dry film 30 Cu plating layer 32 Solder resist

Claims (3)

A semiconductor substrate having one main surface and another main surface opposite to the one main surface;
a first conductive layer provided on the other principal surface side;
an insulating layer provided on a side surface of a through hole that penetrates the semiconductor substrate in a thickness direction from the one main surface to the other main surface and exposes the first conductive layer;
a second plating layer provided on the semiconductor substrate including within the through hole;
a seed metal layer provided on the first conductive layer and on a side surface of the insulating layer within the through hole;
a first plating layer formed in the through hole between the second plating layer and the seed metal layer;
Equipped with
The first conductive layer has a recess in the vicinity of a portion where the first conductive layer, the seed metal layer, and the insulating layer are in contact with each other. the seed metal layer comprises the same material as the second plating layer ;
The semiconductor device according to claim 1. A semiconductor substrate having one main surface and another main surface opposite to the one main surface;
a first conductive layer provided on the other principal surface side;
a second conductive layer provided on the first conductive layer;
an insulating layer provided on a side surface of a through hole that penetrates the semiconductor substrate in a thickness direction from the one main surface to the other main surface and further penetrates the second conductive layer to expose the first conductive layer;
a first plating layer provided on the semiconductor substrate including the inside of the through hole;
a first seed metal layer provided in the through hole on the first conductive layer and on a side surface of the insulating layer;
a second seed metal layer formed on the first seed metal layer between the first plating layer and the first seed metal layer;
Equipped with
the first conductive layer has a recess in the vicinity of a portion where the first conductive layer, the first seed metal layer, and the insulating layer contact each other ;
The semiconductor device further comprises a second plating layer provided within the through hole on the first seed metal layer, the second seed metal layer, and the first plating layer .