JP7582547B1 - ELECTRONIC INFORMATION STORAGE MEDIUM, IC CHIP, IC CARD, DIVIDED DATA PROCESSING METHOD, AND PROGRAM - Google Patents

Abstract

An electronic information storage medium, an IC chip, an IC card, a divided data processing method, and a program are provided that are capable of dealing more efficiently when a data update notification is received multiple times from an external device during chaining.
[Solution] When an IC chip 1 receives a data update from an external device 2 between the time when the first divided data is received by chaining and the time when the last divided data is received, the IC chip 1 increments a counter value, compares the counter value with a threshold value, and depending on the comparison result, selects either a first process of erasing the divided data stored in memory and resuming reception from the first divided data, or a second process of resuming reception from the intermediate divided data following the stored divided data without erasing the divided data stored in memory, and executes the selected process.
[Selected figure] Figure 6

Description

The present invention relates to the technical field of IC (Integrated Circuit) cards that can process data transmitted from an external device by chaining.

A data transmission protocol called chaining is known in the past, in which when transmitting data longer than the length of data that can be transmitted at one time between an IC card and an external device, the transmission data is divided into multiple blocks (i.e., divided data) and transmitted. In data transmission protocols using block formats defined in the international standards ISO/IEC 7816-3 and ISO/IEC 14443, a response from the IC card to the transmitted block is required, which causes problems in that communication time is required more than necessary and the transaction itself between the IC card and the external device also takes time. Patent Document 1 discloses a technology that can shorten communication time in a data transmission protocol control method for controlling data transmission between a contactless IC card and a reader/writer, in which when multiple divided blocks are transmitted consecutively from the transmitting side to the receiving side, the number of blocks to be transmitted consecutively is included in the first block to be transmitted.

Patent No. 5106456

However, the data transmission protocol for chaining defined by the international standard does not specifically define a protocol for when part of the transmission data transmitted by chaining is updated during chaining. If the external device does not notify the IC card of data updates during chaining, the IC card will receive a large amount of divided data before the update, which will require more communication time than necessary, or unnecessary divided data will be written to the memory in the IC card, which will put pressure on the memory capacity, and the durability of the IC chip will decrease due to multiple unnecessary writings. Therefore, when part of the transmission data is updated during chaining, it is desirable for the external device to notify the IC card of the data update, but the IC card that has received the data update notification from the external device will have a problem with how to handle the received divided data. Furthermore, the transmission data transmitted from the external device may be frequently updated during chaining. In other words, the divided data included in the transmission data may be updated multiple times. In this case, the response when the IC card receives multiple notifications of data updates from the external device during chaining becomes even more problematic.

The present invention has been made in consideration of the above problems, and one example of the objective of the present invention is to provide an electronic information storage medium, an IC chip, an IC card, a divided data processing method, and a program that can respond more efficiently when multiple notifications of data updates are received from an external device during chaining.

In order to solve the above problem, the invention described in claim 1 is an electronic information storage medium capable of sequentially receiving from an external device a predetermined command including split data obtained by splitting transmission data, and sequentially storing the split data in a memory, the electronic information storage medium comprising: a counter for counting the number of times a data update is notified from the external device; an incrementing means for incrementing the value of the counter when a data update is notified from the external device between the reception of the first split data of the transmission data and the reception of the last split data; a comparison means for comparing the value of the counter with a preset threshold; and a processing means for selecting, depending on the result of the comparison between the value of the counter and the threshold, one of a first process for erasing the split data stored in the memory and resuming reception from the first split data, and a second process for resuming reception from the intermediate split data following the stored split data without erasing the split data stored in the memory, and executing the selected process.

The invention described in claim 2 is characterized in that, in the electronic information storage medium described in claim 1, when the comparison result indicates that the counter value has reached the threshold value, the processing means selects the first process and executes the first process, while when the comparison result indicates that the counter value has not reached the threshold value, the processing means selects the second process and executes the second process.

The invention described in claim 3 is characterized in that, in the electronic information storage medium described in claim 1, when the comparison result indicates that the counter value exceeds the threshold, the processing means selects the first process and executes the first process, while when the comparison result indicates that the counter value does not exceed the threshold, the processing means selects the second process and executes the second process.

The invention described in claim 4 is characterized in that, in the electronic information storage medium described in claim 1, it further comprises a specifying means for specifying the type of the specified command when a data update is notified from the external device between the reception of the first divided data of the transmission data and the reception of the last divided data, and the processing means selects either the first process or the second process according to the result of comparing the value of the counter with the threshold value and the type of the specified command, and executes the selected process.

The invention described in claim 5 is characterized in that, in the electronic information storage medium described in claim 4, if the type of the specified command is not a type of command that handles secure data and the comparison result indicates that the value of the counter has reached the threshold, the processing means selects the first process and executes the first process, while if the comparison result indicates that the type of the specified command is not a type of command that handles secure data and the value of the counter has not reached the threshold, the processing means selects the second process and executes the second process.

The invention described in claim 6 is characterized in that, in the electronic information storage medium described in claim 4, if the type of the specified command is not a type of command that handles secure data and the comparison result indicates that the value of the counter exceeds the threshold, the processing means selects the first process and executes the first process, while if the comparison result indicates that the type of the specified command is not a type of command that handles secure data and the value of the counter does not exceed the threshold, the processing means selects the second process and executes the second process.

The invention described in claim 7 is an IC chip capable of sequentially receiving from an external device a predetermined command including split data obtained by splitting transmission data, and sequentially storing the split data in a memory, the IC chip comprising: a counter for counting the number of times a data update is notified from the external device; an incrementing means for incrementing the value of the counter when a data update is notified from the external device between the reception of the first split data of the transmission data and the reception of the last split data; a comparison means for comparing the value of the counter with a preset threshold; and a processing means for selecting, depending on the result of the comparison between the value of the counter and the threshold, one of a first process for erasing the split data stored in the memory and resuming reception from the first split data, and a second process for resuming reception from the intermediate split data following the stored split data without erasing the split data stored in the memory, and executing the selected process.

The invention described in claim 8 is an IC card capable of sequentially receiving from an external device a predetermined command including split data obtained by splitting transmission data, and sequentially storing the split data in a memory, the IC card comprising: a counter for counting the number of times a data update is notified from the external device; increment means for incrementing the value of the counter when a data update is notified from the external device between the reception of the first split data of the transmission data and the reception of the last split data; comparison means for comparing the value of the counter with a preset threshold; and processing means for selecting, depending on the result of the comparison between the value of the counter and the threshold, one of a first process for erasing the split data stored in the memory and resuming reception from the first split data, and a second process for resuming reception from the intermediate split data following the stored split data without erasing the split data stored in the memory, and executing the selected process.

The invention described in claim 9 is an electronic information storage medium capable of sequentially receiving from an external device a predetermined command including split data obtained by splitting transmission data, and sequentially storing the split data in a memory, and a split data processing method executed by the electronic information storage medium having a counter for counting the number of times a data update is notified from the external device, characterized in that it includes the steps of: incrementing the value of the counter when a data update is notified from the external device between the reception of the first split data of the transmission data and the reception of the last split data; comparing the value of the counter with a preset threshold; and selecting, depending on the result of the comparison between the value of the counter and the threshold, one of a first process of erasing the split data stored in the memory and resuming reception from the first split data, and a second process of resuming reception from the intermediate split data following the stored split data without erasing the split data stored in the memory, and executing the selected process.

The invention described in claim 10 is a computer capable of sequentially receiving, from an external device, a predetermined command including split data into which transmission data is split, and sequentially storing the split data in a memory, the computer having a counter for counting the number of times data update is notified from the external device, and is characterized in that, when a data update is notified from the external device between the reception of the first split data of the transmission data and the reception of the last split data, the computer is made to execute the steps of incrementing the value of the counter, comparing the value of the counter with a preset threshold, and selecting, depending on the result of the comparison between the value of the counter and the threshold, one of a first process of erasing the split data stored in the memory and resuming reception from the first split data, and a second process of resuming reception from the intermediate split data following the stored split data without erasing the split data stored in the memory, and executing the selected process.

The present invention makes it possible to more efficiently respond when multiple data update notifications are received from an external device during chaining.

FIG. 2 is a diagram illustrating an example of a hardware configuration of an IC chip 1. FIG. 4 is a diagram illustrating an example of a configuration of transmission data. 1 is a diagram showing a data format of a block transmitted and received in contact communication between an IC chip 1 and an external device 2. FIG. This is a diagram showing the contents of bits 6 to 1 in the PCB of the R-block. 11 is a sequence diagram showing an example of communication between an external device 2 and an IC chip 1 when data is updated multiple times during chaining. FIG. 10 is a flowchart showing an example of a divided data process executed by a CPU 15 of the IC chip 1 .

The following describes in detail an embodiment of the present invention with reference to the drawings.

[1. Configuration and Function of IC Chip 1]
First, the configuration and functions of an IC chip 1 according to this embodiment will be described with reference to Fig. 1. The IC chip 1 is an example of an electronic information storage medium capable of sequentially receiving predetermined commands including divided data obtained by dividing transmission data by chaining from an external device 2 and sequentially storing the divided data in a memory. The IC chip 1 is mounted on, for example, an IC card such as a credit card, a cash card, or a My Number card, or a mobile device such as a smartphone. In the case of a mobile device such as a smartphone, the IC chip 1 may be mounted on a small IC card that is detachable from the mobile device, or may be mounted on an embedded board as an eUICC (Embedded Universal Integrated Circuit Card) so that it cannot be easily removed or replaced from the mobile device.

1 is a diagram showing an example of the hardware configuration of an IC chip 1. As shown in FIG. 1, the IC chip 1 includes an I/O circuit 11, a RAM (Random Access Memory) 12, a NVM (Nonvolatile Memory) 13, a ROM (Read Only Memory) 14, a CPU (Central Processing Unit) 15 (an example of a computer), and a coprocessor 16 that performs cryptographic operations. The I/O circuit 11 serves as an interface with an external device 2. Note that communication between the IC chip 1 and the external device 2 may be contact communication or non-contact communication. In the case of non-contact communication, the IC chip 1 communicates with the external device 2 via an antenna (not shown) mounted on an IC card or a mobile device. Note that an example of the external device 2 is a transaction device equipped with a reader/writer. At least one of the RAM 12 and the NVM 13 is an example of a memory in which the divided data is stored. A predetermined area in the RAM 12 is used as a counter for counting the number of times that a data update, which will be described later, has been notified. Such a counter may be provided in a predetermined area in the NVM 13. For example, a flash memory is used for the NVM 13. Note that the NVM 13 may be an "Electrically Erasable Programmable Read-Only Memory." The NVM 13 or the ROM 14 stores an OS (operating system) and one or more applications (including the program of the present invention), etc.

The IC chip 1 communicates with the external device 2 via the I/O circuit 11, for example, in accordance with a half-duplex block transmission protocol. For example, ISO/IEC 7816-3 specifies the T=1 protocol (start-stop half-duplex block transmission protocol) as a half-duplex block transmission protocol. In communication in accordance with the half-duplex block transmission protocol, an I (Information)-block, an R (Receive Ready)-block, and an S (Supervisory)-block are used. The I-block is used to transmit data used by the application in the application layer. The data used in the application layer corresponds to the transmission data described above.

Here, the transmission data is divided into multiple pieces of divided data, and each piece of divided data is included in a specific command APDU (Application Protocol Data Unit) and transmitted. The command APDU is composed of a header section consisting of CLA (instruction class), INS (instruction code), P1 and P2 (instruction parameters), and a body section containing the above-mentioned divided data. For example, if the transmission data exceeds the maximum length that can be transmitted at one time (i.e., in one command APDU), the divided data will be transmitted sequentially from the external device 2 in multiple command APDUs by chaining. Figure 2 is a diagram showing an example of the configuration of transmission data. In the example of Figure 2, the transmission data td is composed of five or more pieces of divided data dd1 to ddn (n is a natural number of 5 or more). Also, in the example of Figure 2, the data length (number of bytes) of each piece of divided data dd1 to ddn is the same as each other, and is the maximum length that can be transmitted at one time. The data is transmitted to the IC chip 1 sequentially, starting with the first piece of divided data dd1.

When bit 5 of the CLA in the command APDU is set to "0", the command APDU indicates the end of chaining (or no chaining). On the other hand, when bit 5 of the CLA in the command APDU is set to "1", the command APDU indicates that the chaining is in progress. The I-block is also used by the external device 2 to notify the IC chip 1 of data updates during chaining. Here, data updates refer to updates of divided data that have not yet been transmitted to the IC chip 1 from among the transmission data. When the divided data included in the transmission data are updated multiple times, the external device 2 notifies the IC chip 1 of the data updates continuously or at intervals multiple times during chaining. Of the divided data dd1 to ddn shown in FIG. 2, for example, the divided data dd1 and the divided data dd3 are updated before transmission (for example, a specific bit or multiple bits in the divided data are changed). It is also possible that any of the divided data is updated during chaining.

The R-block is used to transmit an acknowledgment (ack) or various errors (redundancy code error, character parity error, or other error). The S-block is used to exchange control information between the external device 2 and the IC chip 1. FIG. 3 is a diagram showing the data format of blocks transmitted and received in contact communication between the IC chip 1 and the external device 2. As shown in FIG. 3, one block is composed of a prologue field, an information field, and an epilogue field. An error detection code (LRC or CRC) is stored in the epilogue field. A command APDU is stored in the information field (INF) of the I-block. Alternatively, a status word SW (e.g., 2 bytes) indicating a data update during chaining is stored in the information field (INF) of the I-block in TLV format. The T (tag) in such a TLV identifies that the V (value) is the status word SW. This allows the external device 2 to notify the IC chip 1 of a data update during chaining. The R-block does not have an information field.

The first field of each block consists of NAD (Node address byte), PCB (Protocol control byte), and LEN (Length byte). NAD indicates the source and destination of the block. The first two bits (bits 8 to 7) of the PCB indicate whether the block is an I-block, R-block, or S-block, and the remaining six bits (bits 6 to 1) indicate more detailed information. In addition, a specific bit in the PCB of an I-block can indicate whether it is the end of a chain or in the middle of a chain. Figure 4 shows the contents of bits 6 to 1 in the PCB of an R-block. In Figure 4, N(R) indicates the sequence number of the I-block that is expected to be sent after the R-block. As shown in Figure 4, bits 6 to 1 of the PCB indicate whether the R-block is an acknowledgment (ack), a block error (redundancy code error / character parity error), or other error.

Although not shown, blocks transmitted and received in non-contact communication between the IC chip 1 and external device 2 also consist of a first field, an information field, and a last field as specified in ISO/IEC 14443, and the first field consists of a PCB, a CID (Card Identifier), and an NAD. In this case, like blocks transmitted and received in contact communication, the PCB indicates whether the block is an I-block, R-block, or S-block using the first two bits (bits 8 to 7), and indicates more detailed information using the remaining six bits (bits 6 to 1).

The CPU 15 (an example of a computer) functions as the increment means, comparison means, identification means, processing means, and the like of the present invention by executing the OS and applications (including the program of the present invention) stored in the NVM 13. Specifically, when a data update is notified by the external device 2 via an I-block between the reception of the first divided data and the reception of the last divided data of the transmission data (i.e., multiple divided data) transmitted from the external device 2 via an I-block, the CPU 15 increments (e.g., adds 1) the value of a counter in the RAM 12, etc. In other words, the counter value increases each time an I-block indicating a data update is received. The CPU 15 compares the counter value with a preset threshold value (upper limit of the number of updates). Here, the threshold value is set to 2 or more.

Then, depending on the result of the comparison between the counter value and a threshold value (e.g., 2), the CPU 15 selects one of the following two processes: a first process of erasing the divided data stored in the memory (RAM 12 or NVM 13) and resuming reception from the first divided data, and a second process of resuming reception from the intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executes the selected process. For example, if the comparison result indicates that the counter value has reached the threshold value, the CPU 15 selects the first process and executes the first process, while if the comparison result indicates that the counter value has not reached the threshold value, the CPU 15 selects the second process and executes the second process. Alternatively, if the comparison result indicates that the counter value has exceeded the threshold value, the CPU 15 may select the first process and execute the first process, while if the comparison result indicates that the counter value has not exceeded the threshold value, the CPU 15 may select the second process and execute the second process.

Here, in the first process, the CPU 15 may transmit to the external device 2 an R-block for retransmitting the first divided data. In this case, the CPU 15 may set a value (e.g., 0011) that means "retransmit from the first divided data" to the lowest 4 bits (bit 4 to bit 1) of bits 6 to 1 in the PCB of the R-block. Chaining may be stopped by the R-block (e.g., other error). Meanwhile, in the second process, the CPU 15 may transmit to the external device 2 an R-block (e.g., other error) for transmitting the intermediate divided data following the stored divided data, without erasing the divided data already stored in the memory (i.e., it can be used as is). In this case, the CPU 15 may cause the external device 2 to retransmit the I-block with the sequence number specified in bit 5 (N(R)) in the PCB of the R-block.

In addition, when the CPU 15 is notified of a data update by the I-block from the external device 2 during the period from when the first divided data of the transmission data transmitted by the I-block from the external device 2 is received to when the last divided data is received, the CPU 15 may identify (for example, by referring to the INS) the type of the command APDU transmitted by the immediately preceding I-block. In this case, the CPU 15 selects either one of a first process of erasing the divided data stored in the memory and resuming reception from the first divided data, or a second process of resuming reception from the intermediate divided data following the stored divided data (i.e., the updated divided data) without erasing the divided data stored in the memory, depending on the result of comparing the counter value with the threshold value and the type of the command APDU, and executes the selected process. Here, the type of the command APDU may be predetermined depending on whether it is a command that handles secure data (for example, key data). For example, the type of the VERIFY command and PUT KEY command, which handle secure data, is predefined as "A," while the type of the WRITE BINARY command and WRITE RECORD command, which do not handle secure data, is predefined as "B."

For example, if the command type is "A" (i.e., the command type is a type of command that handles secure data), regardless of the result of comparing the counter value with the threshold, all divided data stored in memory are erased and reception is resumed from the first divided data. For example, the CPU 15 may send an R-block to the external device 2 to cause retransmission from the first divided data. In this case, as above, a value meaning "retransmission from the first divided data" may be set in the lowest 4 bits of bit 6 to bit 1 in the PCB of the R-block. Note that chaining may be stopped by the R-block (e.g., other error). This causes chaining to be stopped according to the type of command APDU.

On the other hand, if the command type is "B" (i.e., the command type is not a type of command that handles secure data) and the comparison result indicates that the counter value has not reached the threshold value (or if the comparison result indicates that the counter value has not exceeded the threshold value), the divided data stored in memory is not erased, and reception is resumed from the intermediate divided data following the stored divided data. On the other hand, if the command type is "B" and the comparison result indicates that the counter value has reached the threshold value (or if the comparison result indicates that the counter value has exceeded the threshold value), the divided data stored in memory is erased, and reception is resumed from the first divided data.

Note that, for example, when chaining is performed in an environment where security can be ensured (for example, a manufacturing factory for IC chip 1), even if the command type is "A" (i.e., the command type is a type of command that handles secure data), if the comparison result indicates that the counter value has not reached the threshold value (or if the comparison result indicates that the counter value has not exceeded the threshold value), the divided data stored in the memory may not be erased, and reception may be resumed from the intermediate divided data following the stored divided data. In this case, even if a data update is notified from the external device 2 during the period from when the first divided data of the transmission data transmitted from the external device 2 is received to when the last divided data is received, the type of the transmitted command APDU (i.e., whether or not it is a command that handles secure data) may not be identified as described above.

2. Operation of IC chip 1
Next, the operation of the IC chip 1 will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a sequence diagram showing an example of communication between the external device 2 and the IC chip 1 when data updates occur multiple times during chaining. Fig. 6 is a flow chart showing an example of divided data processing executed by the CPU 15 of the IC chip 1.

After an initialization sequence is performed between the external device 2 and the IC chip 1, in FIG. 5, the external device 2 transmits the first (first) I-block to the IC chip 1 by chaining (step S1). This I-block includes a command APDU having divided data (first divided data) obtained by dividing the transmission data. Note that in the initialization sequence, the counter is initialized (i.e., the counter value is reset to 0). When the IC chip 1 receives the first I-block from the external device 2, it obtains the divided data (first divided data) from the command APDU included in the I-block and writes (stores) it in the RAM 12 (or NVM 13) (step S2), and transmits an R-block (ack) to the external device 2 (step S3).

Next, when the external device 2 receives the R-block (ack) from the IC chip 1, it transmits the second I-block to the IC chip 1 (step S4). When the IC chip 1 receives the second I-block from the external device 2, it obtains the divided data (the second divided data) from the command APDU included in the I-block, writes (stores) it in the RAM 12 (or NVM 13) (step S5), and transmits the R-block (ack) to the external device 2 (step S6). Note that in step S5, the divided data is stored immediately after the divided data (the first divided data) stored in step S2.

If a data update (i.e., an update of a divided data that has not yet been transmitted) occurs (for the first time) in the external device 2 between the reception of the first divided data from the external device 2 in step S1 and the reception of the last divided data, the external device 2 transmits an I-block (hereinafter referred to as a "data update notification I-block") including a status word SW indicating the data update to the IC chip 1 (step S7). When the IC chip 1 receives the data update notification I-block from the external device 2, the process shown in FIG. 6 is started.

When the process shown in FIG. 6 starts, the IC chip 1 identifies the type of the command APDU most recently received by the I-block (step S101). Next, the IC chip 1 determines whether the type identified in step S101 is the type of a command that handles secure data (step S102). If it is determined that the type is the type of a command that handles secure data (step S102: YES), the process proceeds to step S106. On the other hand, if it is determined that the type is not the type of a command that handles secure data (step S102: NO), the process proceeds to step S103.

In step S103, the IC chip 1 increments the counter value (e.g., adds 1). Next, the IC chip 1 compares the counter value with a threshold value (e.g., 2) and determines whether the counter value has reached the threshold value (i.e., whether the comparison result in step S103 indicates that the counter value has reached the threshold value) (step S104). It may also be determined whether the counter value has exceeded the threshold value. If it is determined that the counter value has not reached the threshold value (step S104: NO), the process proceeds to step S105. On the other hand, if it is determined that the counter value has reached the threshold value (step S104: YES), the process proceeds to step S106.

In step S105, the IC chip 1 selects the second process described above and transmits to the external device 2 an R-block (e.g., other error) to be transmitted from the intermediate divided data following the divided data that has already been stored (written) (step S8 shown in FIG. 5). For example, if the IC chip 1 receives an I-block for notifying data update due to the occurrence of a data update immediately after receiving an I-block with sequence number "0", it transmits to the external device 2 an R-block (specified by bit 5 in the PCB) to be transmitted from the next I-block with sequence number "1".

Next, when the external device 2 receives an R-block (e.g., other error) from the IC chip 1, it resumes transmission from the intermediate divided data (updated divided data) following the divided data already transmitted among the multiple divided data constituting the updated transmission data. For example, as shown in FIG. 5, the mth (m is a natural number of 3 or more) I-block is transmitted from the external device 2 to the IC chip 1 (step S9). When the IC chip 1 receives the mth I-block from the external device 2, it obtains the divided data from the command APDU included in the I-block, writes (stores) it in the RAM 12 (or NVM 13) (step S10), and transmits an R-block (ack) to the external device 2 (step S11). That is, after resuming transmission of the divided data, the IC chip 1 sequentially receives the command APDU transmitted by the I-block from the external device 2, obtains the divided data from the command APDU, and sequentially writes it to the RAM 12 (or NVM 13).

After the division data transmission is resumed, if a data update occurs (for the second time) in another division data to be transmitted before the last division data is received, the external device 2 transmits an I-block for data update notification, including a status word SW indicating the data update, to the IC chip 1 (step S12). When the IC chip 1 receives the I-block for data update notification from the external device 2, the process shown in FIG. 6 is started, and the process is performed in the same manner as described above. Then, in step S106, the IC chip 1 selects the first process described above and transmits an R-block to the external device 2 for retransmission from the first division data. As a result, when the external device 2 receives the R-block from the IC chip 1, it resumes transmission from the I-block including the first division data among the multiple division data constituting the updated transmission data. In other words, the chaining is restarted from the beginning with the updated division data. Alternatively, when the external device 2 receives the R-block from the IC chip 1, the chaining is temporarily stopped, and after the contents of the transmission data are confirmed, the chaining is restarted from the beginning with the updated division data.

When the I-block containing the last command APDU of the chain is received, the IC chip 1 executes processing according to the command APDU using the transmission data consisting of all the stored divided data (for example, a comparison process using the transmission data, or a write process of the transmission data). Note that, for example, when Figures 5 and 6 are performed in an environment where security can be ensured, the processes of steps S101 and S102 shown in Figure 6 may be skipped, and the processes of steps S103 to S106 may be executed.

As described above, according to the above embodiment, when the IC chip 1 receives a data update notification from the external device 2 between the reception of the first divided data and the reception of the last divided data by chaining, the IC chip 1 increments the counter value, compares the counter value with a threshold value, and selects one of the following processes according to the comparison result: a first process of erasing the divided data stored in the memory and restarting reception from the first divided data, and a second process of restarting reception from the intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executes the selected process. Therefore, when the IC chip 1 receives a data update notification from the external device 2 multiple times during chaining, it can respond more efficiently. For example, if data updates occur multiple times (e.g., frequently) during chaining, the chaining is temporarily stopped, and after the contents of the transmission data are confirmed, a new chaining is performed, and the IC chip 1 receives the transmission data all at once, thereby preventing unnecessary data from being written and reducing the durability of the IC chip 1.

1 IC chip 2 External device 11 I/O circuit 12 RAM
13 NVM
14 ROM
15 CPU
16 Coprocessor

Claims (10)

An electronic information storage medium capable of sequentially receiving predetermined commands including divided data obtained by dividing transmission data from an external device and sequentially storing the divided data in a memory,
a counter for counting the number of times that the external device notifies the user of a data update;
an incrementing means for incrementing a value of the counter when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
a comparison means for comparing the value of the counter with a preset threshold value;
a processing means for selecting, according to a comparison result between the value of the counter and the threshold value, either one of a first process of erasing the divided data stored in the memory and restarting reception from the first divided data, or a second process of restarting reception from an intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executing the selected process;
An electronic information storage medium comprising: The electronic information storage medium according to claim 1, characterized in that, if the comparison result indicates that the counter value has reached the threshold, the processing means selects the first process and executes the first process, whereas, if the comparison result indicates that the counter value has not reached the threshold, the processing means selects the second process and executes the second process. The electronic information storage medium according to claim 1, characterized in that, if the comparison result indicates that the counter value exceeds the threshold, the processing means selects the first process and executes the first process, while, if the comparison result indicates that the counter value does not exceed the threshold, the processing means selects the second process and executes the second process. a specifying unit that specifies a type of the predetermined command when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
The electronic information storage medium according to claim 1, characterized in that the processing means selects either the first process or the second process depending on the result of comparing the counter value with the threshold value and the type of the specified command, and executes the selected process. The electronic information storage medium according to claim 4, characterized in that if the type of the specified command is not a type of command that handles secure data and the comparison result indicates that the value of the counter has reached the threshold, the processing means selects the first process and executes the first process, while if the comparison result indicates that the type of the specified command is not a type of command that handles secure data and the value of the counter has not reached the threshold, the processing means selects the second process and executes the second process. The electronic information storage medium according to claim 4, characterized in that, if the type of the specified command is not a type of command that handles secure data and the comparison result indicates that the value of the counter exceeds the threshold, the processing means selects the first process and executes the first process, while, if the comparison result indicates that the type of the specified command is not a type of command that handles secure data and the value of the counter does not exceed the threshold, the processing means selects the second process and executes the second process. An IC chip capable of sequentially receiving predetermined commands including divided data obtained by dividing transmission data from an external device and sequentially storing the divided data in a memory,
a counter for counting the number of times that the external device notifies the user of a data update;
an incrementing means for incrementing a value of the counter when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
a comparison means for comparing the value of the counter with a preset threshold value;
a processing means for selecting, according to a comparison result between the value of the counter and the threshold value, either one of a first process of erasing the divided data stored in the memory and resuming reception from the first divided data, or a second process of resuming reception from an intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executing the selected process;
An IC chip comprising: An IC card capable of sequentially receiving predetermined commands including divided data obtained by dividing transmission data from an external device and sequentially storing the divided data in a memory,
a counter for counting the number of times that the external device notifies the user of a data update;
an incrementing means for incrementing a value of the counter when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
a comparison means for comparing the value of the counter with a preset threshold value;
a processing means for selecting, according to a comparison result between the value of the counter and the threshold value, either one of a first process of erasing the divided data stored in the memory and resuming reception from the first divided data, or a second process of resuming reception from an intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executing the selected process;
An IC card comprising: A divided data processing method executed by an electronic information storage medium capable of sequentially receiving, from an external device, predetermined commands including divided data obtained by dividing transmission data, and sequentially storing the divided data in a memory, the electronic information storage medium including a counter for counting the number of times data update has been notified from the external device, comprising:
incrementing a value of the counter when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
comparing the value of the counter with a preset threshold;
a step of selecting, depending on a result of comparing the value of the counter with the threshold value, one of a first process of erasing the divided data stored in the memory and resuming reception from the first divided data, and a second process of resuming reception from an intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executing the selected process;
13. A method for processing divided data, comprising: A computer capable of sequentially receiving, from an external device, predetermined commands including divided data obtained by dividing transmission data, and sequentially storing the divided data in a memory, the computer including a counter for counting the number of times data update is notified from the external device,
incrementing a value of the counter when a data update is notified from the external device during a period from when a first divided data of the transmission data is received to when a last divided data of the transmission data is received;
comparing the value of the counter with a preset threshold;
a step of selecting, depending on a result of comparing the value of the counter with the threshold value, one of a first process of erasing the divided data stored in the memory and resuming reception from the first divided data, and a second process of resuming reception from an intermediate divided data following the stored divided data without erasing the divided data stored in the memory, and executing the selected process;
A program characterized by executing the above.

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