JP7571294B2 - Analog equalizer correction method, control chip, receiver, and storage medium - Google Patents

Description

This application is filed based on a Chinese patent application having application number "202011289876.4" and filed on November 17, 2020, and claims priority to that Chinese patent application, the entire text of which is incorporated herein by reference.

The present invention relates to digital signal communication, for example, to a correction method for an analog equalizer, a control chip, a receiver, and a storage medium.

A continuous time linear equalizer (CTLE) is an analog filter on the signal receiving side, and is also called an analog equalizer. When a high-speed digital signal is transmitted through a lossy channel, the CTLE can be used to amplify the high-frequency components of the signal to compensate for the loss of the high-frequency channel and improve the performance of the receiver and the quality of the received signal. As the signal transmission rate increases, the attenuation of the signal due to a channel such as a long backplane becomes more severe, and the inter-symbol interference becomes more severe, so the equalization process for the signal becomes more complicated, and over- or under-compensation causes signal distortion, which is detrimental to subsequent detection and processing. Therefore, it is required that the CTLE is adjusted and corrected on the receiving side to appropriately compensate for the loss of the high-frequency channel and to enable the receiving circuit to achieve optimal performance.

The principle of compensation is mainly to increase the high-frequency signal amplitude in the high-speed serial signal by adjusting the high-frequency gain of the CTLE, and the compensation is completed when the amplitude of the high-frequency signal is equal to the amplitude of the low-frequency signal. According to this method, a rectifier circuit needs to be designed.
There are some methods to compensate for CTLE using analog circuits, but they require complex high-pass or low-pass filter designs, and the compensation process is sensitive to channel quality and data rate.
It is possible to make a correction for the CTLE by collecting bit error rates, and when the error rate becomes a minimum, the correction can be considered to be complete. However, according to this method, it is necessary to know the transmission data in advance in order to collect bit error rates.
A variable step Least Mean Square (LMS) algorithm or a zero forcing Least Mean Square Error algorithm may be used to correct for CTLE, but the correction process is computationally complex.

According to an embodiment of the present application, there is provided a method for correcting an analog equalizer, the method including the following steps:

The height of the forward eye pattern of the output signal of an analog front end (AFE) circuit is monitored, and the analog front end circuit includes at least one stage of an analog equalizer.

If the monitored forward eye pattern height is less than the eye pattern height threshold, a correction command is generated.

The analog equalizer in the analog front-end circuit is corrected according to the correction command until the height of the monitored forward eye pattern reaches the eye pattern height threshold.

According to an embodiment of the present application, there is further provided a control chip. The control chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the program is executed by the processor, the above-mentioned analog equalizer correction method is realized.

According to an embodiment of the present application, a receiver is further provided. The receiver includes an analog front-end circuit, a monitoring circuit, and the above-mentioned control chip.

The output side of the analog front-end circuit is connected to the input side of the monitoring circuit.

The output side of the monitoring circuit is connected to the input side of the control chip.

The control chip is configured to correct the analog equalizer in the analog front-end circuit according to the monitoring results of the monitoring circuit.

According to an embodiment of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores a computer program that, when executed by a processor, realizes the above-described analog equalizer correction method.

4 is a flowchart of a method for correcting an analog equalizer provided by an embodiment. 4 is a flowchart of a correction method for an analog equalizer provided by another embodiment; FIG. 2 is a schematic diagram of a correction device for an analog equalizer provided by an embodiment; FIG. 2 is a hardware configuration schematic diagram of a control chip provided according to an embodiment. FIG. 2 is a schematic diagram of a receiver provided according to an embodiment; FIG. 2 is a schematic diagram of the working principle of a receiver provided by an embodiment;

The present application will be described below in combination with drawings and examples. It will be understood that the specific examples described herein are only for the purpose of interpreting the present application, and are not limitations on the present application. It should be noted that, unless inconsistent, the examples and features of the examples in the present application may be arbitrarily combined with each other. For the sake of convenience, the drawings show only the parts related to the present application, rather than the entire structure.

Figure 1 is a flowchart of an analog equalizer correction method provided by one embodiment. This method can be applied to a receiver control chip. As shown in Figure 1, the method provided by this embodiment includes steps 110 to 130.

In step 110, the height of the forward eye pattern of the output signal of the analog front-end circuit is monitored, the analog front-end circuit including at least one stage of an analog equalizer.

In this embodiment, a high-speed serial data signal is transmitted from a transmitter to a receiver, and after channel attenuation, the inter-symbol interference becomes very serious. The inter-symbol interference can be reduced by compensating for the channel attenuation using an analog front-end circuit in the receiver. The analog front-end circuit includes a digital circuit device and an analog circuit device, and may also include at least one stage of a CTLE. The CTLE can be used to amplify high-frequency components to compensate for the loss of the high-frequency channel, and improve the performance of the receiver and the quality of the received signal.

An eye pattern is a diagram in which a series of digital signals are superimposed on an oscilloscope, and is used to estimate the quality of a received digital signal by analyzing the characteristics of the digital signal and the effects of inter-symbol crosstalk and noise. The height of the forward eye pattern represents the degree of opening of the "eye" of the eye pattern, and is used to reflect the strength of inter-symbol crosstalk. The higher the height of the forward eye pattern and the more regular the eye pattern, the smaller the inter-symbol crosstalk,
In the opposite case, the inter-code crosstalk becomes large. In this embodiment, the compensation ability of the CTLE is adjusted based on the height of the forward eye pattern, thereby reducing the inter-code crosstalk and improving the performance of the receiver. The control chip monitors the height of the forward eye pattern of the output signal of the analog front-end circuit in real time to determine whether or not the CTLE needs to be corrected, and the policy of correcting the CTLE, such as whether or not to turn on the compensation function of the CTLE of each stage, and whether or not the high-frequency gain or low-frequency gain needs to be adjusted.

In step 120, if the monitored forward eye pattern height is lower than the eye pattern height threshold, a correction command is generated.

In this embodiment, the circuit equalization effect of the CTLE is evaluated by setting an eye height threshold. If the forward eye height is lower than the eye height threshold, it indicates that the inter-symbol crosstalk is relatively large, and the current analog front-end circuit cannot effectively compensate for the loss of the high frequency channel. In this case, it is necessary to compensate for the CTLE.
When the forward eye height reaches the eye height threshold, the inter-symbol crosstalk is relatively small and can meet the demand, so there is no need to further correct the CTLE. The correction command can be used to control and adjust the compensation ability of the CTLE. When the forward eye height is smaller than the eye height threshold, the number of CTLE stages whose compensation function is turned on can be changed, and the high frequency gain or low frequency gain of the CTLE can be adjusted to increase the forward eye height so that the demand is met.

In one embodiment, the eye pattern height threshold may be a fixed value, or may be an adjustable dynamic value that can be set or adjusted according to the type of signal transmission channel, the length of the backplane, the degree of channel attenuation, the number of CTLE stages, etc. For example, if the degree of channel attenuation is large, the quality of the received signal is poor, so by appropriately lowering the eye pattern height threshold, a post-equalization signal that satisfies actual needs can be obtained. On the other hand, if the degree of channel attenuation is small, by appropriately raising the eye pattern height threshold, a post-equalization signal of higher quality can be obtained. In addition, the more stages of the CTLE, the stronger the compensation ability of the analog front-end circuit is, so by appropriately raising the eye pattern height threshold, a post-equalization signal of higher quality can be obtained.

In step 130, the analog equalizer in the analog front-end circuit is corrected according to the correction command until the monitored forward eye pattern height reaches the eye pattern height threshold.

In this embodiment, the correction of the CTLE includes controlling the on/off of the compensation function of the CTLE of each stage and/or adjusting the gain of the CTLE of each stage, and the correction process may be performed hierarchically. For example, first, with the compensation function of the CTLE of each stage turned off, it is determined whether the height of the forward eye pattern currently being monitored is smaller than the eye pattern height threshold, and if YES, the compensation function of the CTLE of one stage can be turned on.
With the compensation function of the first stage CTLE turned on, the high frequency gain of the CTLE is gradually increased, and if the height of the forward eye pattern monitored after increasing to the upper limit is still lower than the eye pattern height threshold, the compensation function of the second stage CTLE is turned on, and then the high frequency gain of the CTLE is gradually increased until the height of the forward eye pattern reaches the eye pattern height threshold. In this way, by similar processing, the compensation functions of all the CTLEs in the AFE circuit can be turned on at most. Also, if the height of the forward eye pattern cannot reach the eye pattern height threshold by only increasing the high frequency gain, it is also possible to further increase the compensation ability of the entire CTLE by reducing the low frequency gain in addition to this, thereby achieving optimal performance of the receiver.

The method of this embodiment does not require a preset code pattern, statistical calculation of bit error rates, or complex mathematical algorithms, can be applied to any channel attenuation scenario, has a simple circuit configuration, and is easy to implement. The height of the forward eye pattern is used as the correction standard, and correction is made to the analog equalizer so that the height of the forward eye pattern of the signal is sufficiently high, thereby realizing adaptive correction of the analog equalizer to improve the quality of the eye pattern and the quality of the output signal of the analog front-end circuit.

In one embodiment, the correction command includes a compensation function ON command,
The compensation function on command is utilized to instruct turning on the compensation function of the analog equalizer in the analog front-end circuit.

In this embodiment, the compensation function ON command is used to instruct the compensation function of any stage of CTLE in the AFE circuit to be turned on, and the more stages of CTLE whose compensation function is turned on, the higher the compensation ability of the AFE circuit for high frequency attenuation. For example, if an analog front-end circuit includes three stages of CTLE, which are CTLE 1, CTLE 2, and CTLE 3, in the initial stage of the correction process, only the compensation function of CTLE 1 can be turned on.
In this state, if a forward eye map height that satisfies the requirements cannot be obtained by adjusting the gain, the correction function on command is updated to instruct turning on the correction functions of CTLE 1 and CTLE 2.
Similarly, if the forward eye map height cannot be obtained by adjusting the gain in this state, the compensation function ON command is updated to instruct turning on the compensation functions of CTLE 1, CTLE 2, and CTLE 3. The compensation function ON command can be expressed as CTLE_BOOST_EN<x:0>, where x represents the number of bits of the control code. For example, the number of CTLE stages for which the compensation function is turned on can be indicated using a 2-bit control code, and the maximum number of stages is 4. By turning on the compensation function of the CTLE one stage at a time, it is possible to avoid an excessive adjustment width in one time and to realize high-frequency attenuation compensation that meets actual demand with a minimum CTLE.

In one embodiment, the correction instructions include gain adjustment instructions;
The gain adjustment command includes increasing a high frequency gain of an analog equalizer in the analog front-end circuit by a first step size;
and decreasing the low frequency gain of an analog equalizer in the analog front-end circuitry by a second step size.

In this embodiment, the gain adjustment command is used to instruct the CTLE compensation function to be gradually adjusted. For example, in the initial stage of the compensation process, the high frequency gain is preferentially increased with a first step size, and when the forward eye height cannot be obtained by increasing the high frequency gain alone to meet the requirement, the gain adjustment command can be updated to further instruct the low frequency gain to be decreased with a second step size. For example, if the gain adjustment command is LFG<y1:0>, it indicates that the low frequency gain of the CTLE is decreased, and y1 indicates the number of bits of the control code.
When the gain adjustment command is HFG<y1:0>, it indicates that the high frequency gain of the CTLE is to be increased, and y2 indicates the number of bits of the control code. As the LFG and HFG control codes increase, the low frequency gain and the high frequency gain increase, respectively.

The correction command can simultaneously include a compensation function on command and a gain adjustment command.

In one embodiment, the high frequency gain may be preferentially increased in the correction process to obtain a higher total gain, improve the signal-to-noise ratio of the received signal, and facilitate subsequent processing of the received signal. In some embodiments, the correction process may increase the high frequency gain while simultaneously decreasing the low frequency gain, or preferentially decrease the low frequency gain and further increase the high frequency gain if the demand cannot be met, thereby achieving correction of the CTLE but at the expense of some reduction in the total gain of the signal.

In one embodiment, the first step size and the second step size may be fixed or dynamic, and may be set or adjusted according to the type of signal transmission channel, the length of the backplane, the attenuation of the channel, the number of stages of the CTLE, the difference between the forward eye pattern height and the eye pattern height threshold, etc. Taking the first step size as an example, the first step size may be a preset value or may be determined according to the upper limit value of the high frequency gain, for example, if the high frequency gain range is [0, A], the first step size may be [0, A]/B, where B is a positive integer.
In addition, in the early stage of the correction process, the difference between the monitored forward eye pattern height and the eye pattern height threshold is relatively large, so the first step size can be set to a relatively large value. As the correction process progresses, the difference between the monitored forward eye pattern height and the eye pattern height threshold gradually decreases, so that the first step size can be gradually decreased in a linear or nonlinear manner to avoid an excessive adjustment width.

In one embodiment, step 110 includes the following steps:

In step 1110, the output signal is sampled by a first decision circuit and a clock data recovery (CDR) circuit to obtain a first data signal, an edge signal, and a two-phase clock corresponding to the first data signal and the edge signal.

In step 1120, a second decision circuit samples the output signal according to a sampling clock to obtain a second data signal.

In step 1130, the second data signal is compared to the first data signal to determine a relationship between the monitored forward eye pattern height and an eye pattern height threshold.

In this embodiment, the first decision circuit is configured to sample the output signal of the AFE circuit to obtain a first data signal and an edge signal. The receiver may have two first decision circuits configured to output the first data signal and the edge signal, respectively. By inputting the first data signal and the edge signal to the CDR circuit, a two-phase clock is recovered and used as the sampling clock for the first decision circuit. In a high-speed serial communication situation, only serial data is transmitted on the channel, and no clock signal is transmitted, and accurate and reliable received data can be obtained by performing clock recovery on the received serial data by the CDR circuit. Here, the clock corresponding to the first data signal and the clock corresponding to the edge signal are clocks of opposite phases.

The second decision circuit samples the output signal according to a sampling clock to obtain a second data signal. Whether each bit of the second data signal is 0 or 1 indicates whether the height of the forward eye pattern corresponding to that bit is lower than the decision threshold. Here, the decision threshold is the eye pattern height threshold, and the eye pattern height threshold can be set using a threshold voltage circuit. By comparing the first data signal with the second data signal, the degree of inter-symbol crosstalk can be analyzed to determine whether the monitored forward eye pattern height reaches the eye pattern height threshold, and further a correction policy for the CTLE can be determined.

In one embodiment, the sampling clock corresponding to the second data signal and the clock corresponding to the first data signal are synchronized and have aligned edges.

In this embodiment, the sampling clock of the second decision circuit and the sampling clock of the first decision circuit for obtaining the first data signal are synchronized and have aligned edges, so that it is guaranteed that the second data signal output from the second decision circuit and the first data signal output from the first decision circuit are data of the same beat.

In one embodiment, step 1103 includes:

if a clock lock signal is detected, reading the first data signal and the second data signal of the same length;
performing an exclusive-or operation on bits in the first data signal that are one with the values of corresponding bits in the second data signal, and accumulating the results of the exclusive-or operations on each bit;
determining that the monitored forward eye height has reached an eye height threshold if the cumulative result is zero;
If the cumulative result is not zero, determining that the monitored forward eye height is below an eye height threshold or that the forward eye of the output signal is closed.

In this embodiment, the decision threshold of the second decision circuit, i.e., the eye height threshold, is VTH1, and when the clock lock signal is detected (i.e., CDR_LOCK=1), the first data signal and the second data signal of the same length are read, and the bit whose value is 1 in the first data signal is exclusive-ORed with the corresponding bit in the second data signal, and the result of the exclusive-OR is accumulated, and the accumulation result indicates the match between the first data signal and the second data signal. If the accumulation result is 0, an indication signal Eyeopen=1 can be output, which indicates that the eye pattern of the output signal is open and the forward eye pattern height is equal to or greater than VTH1, and no correction is required for CTLE, to indicate that the first data signal and the second data signal are completely matched.
If the cumulative result is not 0, an indication signal Eyeopen=0 can be output to indicate that the first data signal and the second data signal do not perfectly match, that the forward eye pattern height is lower than VTH1 or the eye pattern is closed and needs to be corrected against CTLE.

In one embodiment, step 120 includes the following steps:

In step 1210, if the monitored forward eye pattern height is lower than the eye pattern height threshold, the on/off state of the compensation function of each analog equalizer in the analog front-end circuit and the gain adjustment policy for the analog equalizer are determined based on the first data signal, the second data signal, and the clock lock signal.

In step 1220, correction instructions are generated based on the on/off state and the gain adjustment policy.

In this embodiment, when the clock lock signal is detected (i.e., CDR_LOCK=1), different on/off states and/or gain adjustment policies of the CTLE can be determined based on the first data signal and the second data signal, and different correction commands can be generated. For example, when the clock lock signal is detected (i.e., CDR_LOCK=1), ESDATA and DATA of the same length are read, and if the cumulative result is 0, no correction is required for the CTLE.
If the accumulation result is not 0, then a correction needs to be made to the CTLE, since the larger the accumulation result is, the less the number of bits that the first data signal and the second data signal do not match, in this case, the more CTLEs the compensation function needs to be turned on, or the width (i.e., step size) of the gain adjustment needs to be increased.

In one embodiment, the method further includes the following steps:

In step 140, a relationship between the amplitude of the output signal and the amplitude threshold is determined based on the second data signal.

In step 150, it is determined whether the low-frequency gain of the analog equalizer in the analog front-end circuit has decreased to a lower limit value based on the relationship between the amplitude of the output signal and the amplitude threshold value.

In this embodiment, the amplitude of the output signal is further monitored to ensure that the low frequency gain of the analog equalizer is not too small and to avoid the amplitude of the received signal being too small, which could affect subsequent processing.

In one embodiment, if the amplitude of the output signal needs to be monitored, one or more second decision circuits may be provided. The first decision circuit can sample the first data signal based on an eye height threshold (VTH1) throughout the entire correction process. Whether each bit of the first data signal is 0 or 1 indicates whether the forward eye height corresponding to that bit is lower than the eye height threshold. Based on this, the control chip can determine the relationship between the monitored forward eye height and the eye height threshold, and thereby determine whether correction is required for the CTLE. Meanwhile, the second decision circuit is mainly used to sample the second data signal based on an amplitude threshold (VTH2) in the correction process of reducing the low-frequency gain. In this case, whether each bit of the second data signal is 0 or 1 indicates whether the amplitude of that bit is equal to or greater than the amplitude threshold. Based on this, the control chip can determine the relationship between the amplitude of the output signal and the amplitude threshold, and further determine whether the low-frequency gain has been reduced to a lower limit. If yes, the correction is terminated; if not, the low frequency gain can be continued to be decreased to increase the forward eye height. If only one second decision circuit is provided, the second decision circuit may be used alternately to obtain the first data signal and the second data signal. If two second decision circuits are provided, one of them can be used to obtain the first data signal based on the eye height threshold, and the other can be used to obtain the second data signal based on the amplitude threshold.

In one embodiment, step 140 includes:

reading a second data signal of a set length if a clock lock signal is detected;
Counting the number of bits in the second data signal that have a value of 1 or accumulating the value of each bit in the second data signal;
determining that the amplitude of the output signal has reached an amplitude threshold value when the number of bits having a value of 1 is equal to or greater than a set value, or when the cumulative result is equal to or greater than a set value;
If the number of bits having a value of 1 or the result of the accumulation is less than a set value, determining that the amplitude of the output signal is less than an amplitude threshold value.

In this embodiment, the decision threshold of the second decision circuit, i.e., the amplitude threshold, is VTH2, and when the clock lock signal is detected (i.e., CDR_LOCK=1), the second data signal of the set length is read, and the number of bits whose value is 1 in the second data signal is counted, or the values of each part in the second data signal are accumulated, and the number of bits obtained or the accumulated result reflects the magnitude of the amplitude of the output signal. If the number of bits obtained or the accumulated result is equal to or greater than a set value (e.g., 1), the output indication signal Vamp_valid=1 is output, indicating that the output signal amplitude is equal to or greater than VTH2 and the low-frequency gain may be further reduced.
If the number of bits obtained or the cumulative result is smaller than a set value, the output instruction signal Vamp_valid=0 is output, which indicates that the output signal amplitude is smaller than VTH2 and the low-frequency gain has already decreased to the lower limit.

In one embodiment, step 130 includes the following steps:

In step 1310, the compensation function of the analog equalizer in the analog front-end circuit is turned on in accordance with the correction command.

In step 1320, based on the starting condition, the high frequency gain of the analog equalizer in the analog front-end circuit is increased by a first step size until the monitored forward eye height reaches an eye height threshold.

In step 1330, if the monitored forward eye pattern height still does not reach the eye pattern height threshold after the high frequency gain of the analog equalizer is increased to the upper limit value, the compensation function of at least one stage of the analog equalizer that is not in the on state is turned on and the high frequency gain is repeatedly increased until the monitored forward eye pattern height reaches the eye pattern height threshold, or the low frequency gain of the analog equalizer in the analog front-end circuit is decreased by a second step size.

In this embodiment, the correction of the CTLE is performed hierarchically by turning on the correction function of the CTLE in each stage one by one.
Gradually increasing the high frequency gain of the CTLE preferentially;
When the high frequency gain is increased to the upper limit, if the monitored forward eye height still does not reach the eye height threshold, turn on the compensation function of more stages of CTLE or gradually reduce the low frequency gain of CTLE. Take an example where an AFE circuit includes three stages of CTLE. The forward eye height of the output signal of the AFE circuit is monitored in real time. First, if the monitored forward eye height is lower than the eye height threshold, generate a correction command CTLE_BOOST_EN<2:0>=000, that is, turn off the correction functions of all three stages of CTLE, and the CTLE corresponds to a buffer.

Then, it monitors whether the current forward eye pattern height has reached the eye pattern height threshold (whether Eyeopen = 1), and if YES, it maintains the CTLE configuration and terminates the adaptive correction process; if not, it turns on the compensation function of CTLE 1 and sets the low-frequency gain of the three-stage CTLE to its maximum value and the high-frequency gain to its minimum value of 0.

Next, monitor whether the current forward eye height reaches the eye height threshold (Eyeopen=1 or not), if yes, keep the CTLE configuration and end the adaptive correction process, otherwise increase the high frequency gain by 1 until Eyeopen=1 when the high frequency gain has not reached the upper limit value;
If Eyeopen=0 even when the high frequency gain reaches the upper limit, the compensation functions of CTLE 1 and CTLE 2 are turned on, and the low frequency gains of the three CTLE stages are set to their maximum values and the high frequency gains to their minimum values of 0.

Then, once again, monitor whether the current forward eye pattern height has reached the eye pattern height threshold (whether Eyeopen = 1), and if YES, maintain the CTLE configuration and terminate the adaptive correction process, otherwise, if the high frequency gain has not reached its upper limit, increase the high frequency gain by 1 until Eyeopen = 1, and if Eyeopen = 0 even after the high frequency gain has reached its upper limit, turn on the compensation functions of CTLE 1, CTLE 2, and CTLE 3, and set the low frequency gain of the three stages of CTLE to its maximum value and the high frequency gain to its minimum value of 0.

Finally, with the compensation functions of the CTLEs of each stage all turned on, monitor whether the current forward eye pattern height reaches the eye pattern height threshold (whether Eyeopen = 1 or not), and if YES, maintain the CTLE configuration and terminate the adaptive correction process, otherwise increase the high frequency gain by 1 until Eyeopen = 1 when the high frequency gain has not reached the upper limit value. If Eyeopen = 0 even if the high frequency gain has reached the upper limit value, the low frequency gain can also be decreased.

In one embodiment, step 130 includes the following steps:

In step 1340, if the amplitude of the output signal is greater than or equal to the amplitude threshold and the low-frequency gain of the analog equalizer is greater than or equal to the lower limit, the low-frequency gain of the analog equalizer in the analog front-end circuit is decreased by a second step size until the monitored forward eye pattern height reaches the eye pattern height threshold.

In this embodiment, the forward eye height can also be increased by decreasing the low-frequency gain. For example, when the compensation functions of CTLE 1, CTLE 2, and CTLE 3 are all on and the high-frequency gain has already reached the upper limit, but the forward eye height still does not reach the eye height threshold, it can be determined whether the low-frequency gain is higher than the lower limit and is not 0. If YES, decrease the low-frequency gain by 1 until Eyeopen=1; if not, stop the correction process, and finally, the forward eye height does not reach the eye height threshold and Eyeopen=0.

In one embodiment, the starting state includes the low frequency gain of the analog equalizer being set to a maximum value and the high frequency gain of the analog equalizer being set to a minimum value.

In this embodiment, the high frequency gain is gradually increased from a minimum value and the low frequency gain is gradually decreased from a maximum value based on the starting state, thereby avoiding excessive adjustment ranges so as to optimize the performance of the receiver.

Figure 2 is a flowchart of a method for correcting an analog equalizer provided by another embodiment. In this embodiment, a hierarchical correction process is described using an example in which the compensation function of the CTLE is turned on step by step and the high frequency gain is preferentially increased. For technical details not described in detail in this embodiment, refer to any of the above embodiments.

As shown in FIG. 2, the method includes the following steps:

a. The output signal is sampled by a first decision circuit (denoted as SLICER) and a CDR circuit to obtain a first data signal (denoted as DATA), an edge signal (denoted as EDGE), and two-phase clocks (denoted as CLK0 and CLK180, respectively) corresponding to the first data signal and the edge signal. Here, CLK0 and CLK180 are clocks of opposite phases.

b. A second decision circuit (denoted as ESSLICER) samples the output signal according to a sampling clock (denoted as ECLK0) to obtain a second data signal (denoted as ESDATA), where ECLK0 is synchronous with CLK0 and has aligned edges.

c. The first data signal is compared with the second data signal to determine the relationship between the height of the forward eye pattern being monitored and the eye pattern height threshold. Note that the relationship between the height of the forward eye pattern being monitored and the eye pattern height threshold can be determined using the exclusive OR and cumulative sum calculations of the first data signal and the second data signal in the above-mentioned embodiment.

d. Determine whether the monitored forward eye height is less than the eye height threshold, and if so, execute e;
If not, the analog equalizer correction is complete.

e. Generate a correction command, and in accordance with the correction command, turn on the compensation function of the analog equalizer in the analog front-end circuit to enter a start state. Here, it may be instructed to turn on the compensation function of one or more stages of CTLE, or it may be instructed not to turn on the compensation function of any stage of CTLE.

f. Determine whether the monitored forward eye height reaches an eye height threshold, and if so, the analog equalizer correction is complete;
If not, execute g.

g. Increase the high frequency gain of an analog equalizer in the analog front-end circuit by a first step size.

h. Determine whether the monitored forward eye height reaches an eye height threshold, and if so, the analog equalizer correction is complete;
If not, execute i.

i. Determine whether the high frequency gain of the analog equalizer has increased to the upper limit value. If yes, execute j. If not, go back and execute g.

j. Determine whether the compensation functions of the analog equalizers in the analog front-end circuit are all turned on. If YES, execute l;
If not, execute k.

k. Turn on the compensation function of at least one stage of the analog equalizer that is not in the on state and enter the start state.

m. Determine whether the monitored forward eye height reaches an eye height threshold, and if so, the analog equalizer correction is complete;
If not, do n.

n. Determine whether the amplitude of the output signal is greater than the amplitude threshold and the low frequency gain of the analog equalizer is greater than 0, if yes, return and execute l;
If not, the analog equalizer correction is complete.

Note that before decreasing the low-frequency gain, it is determined whether the amplitude of the output signal is higher than the amplitude threshold and whether the low-frequency gain is greater than 0 (i.e., LFG in the gain adjustment command is greater than 0), so that it is possible to determine whether the low-frequency gain can be further decreased to avoid the total gain of the received signal becoming too small, which would result in a decrease in the quality of the received signal. The relationship between the amplitude of the output signal and the amplitude threshold can be determined using a statistical or cumulative calculation of the second data signal in the above-described embodiment.

According to the method of the present embodiment, a first data signal and an edge signal are obtained based on the height threshold of the eye pattern using a first decision circuit, and then clock recovery is performed to obtain accurate and reliable received data;
Then, a second data signal is obtained using a second decision circuit, and based on the second data signal, it can be determined whether the forward eye pattern height of the output signal reaches the eye pattern height threshold based on the difference in numerical value between the data path (i.e., the first data signal) of the first decision circuit after CDR clock lock and the normal data path (i.e., the second data signal), and based on the second data signal, it can be determined whether the amplitude of the output signal reaches the amplitude threshold, so that an effective correction decision can be made.
By turning on the compensation function of the CTLE step by step, the high frequency gain is gradually increased or the low frequency gain is decreased, thereby realizing fine adaptive correction, which is highly efficient, has a wide range of application, does not require complex algorithms, and has a simple control logic.

According to an embodiment of the present application, an analog equalizer correction device is further provided. FIG. 3 is a schematic diagram of a correction device for an analog equalizer provided by an embodiment. As shown in FIG. 3, the analog equalizer correction device includes a monitoring module 210, a control module 220, and a transmission module correction module 230.

The monitoring module 210 is configured to monitor the height of the forward eye pattern of the output signal of an analog front-end circuit that includes at least one stage of an analog equalizer.

The control module 220 is configured to generate a correction command when the monitored forward eye pattern height is less than the eye pattern height threshold.

The correction module 230 is configured to correct the analog equalizer in the analog front-end circuit according to the correction command until the height of the monitored forward eye pattern reaches the eye pattern height threshold.

According to the analog equalizer correction device of this embodiment, the height of the forward eye pattern is used as the correction standard, and the analog equalizer is corrected so that the height of the forward eye pattern of the signal becomes sufficiently high, thereby improving the quality of the eye pattern and the quality of the output signal of the analog front-end circuit, realizing adaptive correction of the analog equalizer, which can be applied to all channel attenuation situations, has a simple circuit configuration, and is easy to implement.

In one embodiment, the correction command includes a compensation function on command.

The compensation function on command is used to instruct the analog equalizer in the analog front-end circuit to turn on the compensation function.

In one embodiment, the correction instructions include gain adjustment instructions;
the gain adjustment command comprises increasing a high frequency gain of an analog equalizer in the analog front-end circuit by a first step size;
and decreasing a low frequency gain of an analog equalizer in the analog front-end circuit by a second step size.

In one embodiment, the monitoring module:

A first decision unit configured to sample the output signal using a first decision circuit and a clock data recovery circuit to obtain a first data signal, an edge signal, and a two-phase clock corresponding to the first data signal and the edge signal;

A second decision unit configured to sample the output signal according to a sampling clock by a second decision circuit to obtain a second data signal;

A first monitoring unit configured to compare the second data signal with the first data signal to determine a relationship between a monitored forward eye pattern height and the eye pattern height threshold.

In one embodiment, the first monitoring unit specifically includes:

If a clock lock signal is detected, a first data signal and a second data signal of the same length are read,

Perform an exclusive OR operation between bits in the first data signal that have a value of 1 and the value of the corresponding bit in the second data signal, and accumulate the results of the exclusive OR of each bit,

If the cumulative result is 0, it is determined that the height of the forward eye pattern being monitored has reached the eye pattern height threshold,

If the cumulative result is not zero, it is configured to determine that the height of the monitored forward eye pattern is lower than the eye pattern height threshold or that the forward eye pattern of the output signal is closed.

In one embodiment, the sampling clock corresponding to the second data signal and the clock corresponding to the first data signal are synchronized and have aligned edges.

In one embodiment, the control module 220:

When the height of the monitored forward eye pattern is lower than the eye pattern height threshold, determine the on/off state of the compensation function of each of the analog equalizers in the analog front-end circuit and the gain adjustment policy for the analog equalizer based on the first data signal, the second data signal, and the clock lock signal,

The correction command is configured to be generated based on the on/off state and the gain adjustment policy.

In one embodiment, the monitoring module 210:

Based on the second data signal, determine the relationship between the amplitude of the output signal and an amplitude threshold value,

Further includes a second monitoring unit configured to determine whether the low-frequency gain of an analog equalizer in the analog front-end circuit has decreased to a lower limit value based on the relationship between the amplitude of the output signal and an amplitude threshold value.

In one embodiment, the second monitoring unit specifically includes:

If a clock lock signal is detected, a second data signal of a set length is read,

Count the number of bits in the second data signal that have a value of 1, or accumulate the values of each bit in the second data signal,

If the number of bits whose value is 1 is equal to or greater than a set value, or if the cumulative result is equal to or greater than a set value, it is determined that the amplitude of the output signal has reached the amplitude threshold value,

If the number of bits whose value is 1 or the cumulative result is smaller than a set value, the amplitude of the output signal is determined to be lower than the amplitude threshold.

In one embodiment, the correction module 230:

In accordance with the correction command, the compensation function of the analog equalizer in the analog front-end circuit is turned on,

Based on a starting condition, increase the high frequency gain of an analog equalizer in the analog front-end circuit by a first step size until the monitored forward eye height reaches the eye height threshold,

If the height of the forward eye pattern monitored after the high frequency gain of the analog equalizer has increased to an upper limit value has not yet reached the eye pattern height threshold, the compensation function of at least one stage of the analog equalizer that is not in an on state is turned on and the high frequency gain is repeatedly increased until the height of the forward eye pattern monitored reaches the eye pattern height threshold, or the low frequency gain of the analog equalizer in the analog front-end circuit is decreased by a second step size.

In one embodiment, the correction module 230:

When the amplitude of the output signal is greater than or equal to the amplitude threshold and the low frequency gain of the analog equalizer is greater than or equal to the lower limit, the low frequency gain of the analog equalizer in the analog front-end circuit is configured to be reduced by a second step size until the height of the monitored forward eye pattern reaches the eye pattern height threshold.

In one embodiment, the starting state includes a low frequency gain of the analog equalizer set to a maximum value and a high frequency gain of the analog equalizer set to a minimum value.

The analog equalizer correction device proposed in this embodiment belongs to the same inventive concept as the correction method proposed in the above embodiments, so that any of the above embodiments may be referred to for technical details not described in detail in this embodiment, and this embodiment has the same beneficial effects as when implementing the analog equalizer correction method.

According to an embodiment of the present application, a control chip is further provided. FIG. 4 is a schematic diagram of the hardware configuration of a control chip provided by an embodiment. As shown in FIG. 4, the control chip provided by the present application includes a memory 32, a processor 31, and a computer program stored in the memory and executable on the processor, and when the program is executed by the processor 31, it performs the above-mentioned correction method.

The control chip may further include a memory 32;
The processor 31 in the control chip can be one or more. FIG. 4 shows one processor 31 as an example.
The memory 32 is configured to store one or more programs;
When the one or more programs are executed by the one or more processors 31, the one or more processors 31 realize the analog equalizer correction method described in the embodiments of the present application.

The control chip further includes a communication device 33, an input device 34, and an output device 35.

The processor 31, memory 32, communication device 33, input device 34 and output device 35 in the control chip can be connected by a bus or other method, and FIG. 4 shows an example in which they are connected by a bus.

The input device 34 can be used to receive input numeric and text information and generate key press signal inputs related to user settings and function control of the control chip. The output device 35 can include a display device such as a display.

The communication device 33 may include a receiver and a transmitter. The communication device 33 is configured to transmit and receive information under the control of the processor 31.

The memory 32 can be configured to store software programs, computer executable programs and modules as a computer readable storage medium, such as program instructions/modules corresponding to the analog equalizer correction method described in the embodiments of the present application (e.g., the monitoring module 210, the control module 220, and the transmission module correction module 230 in the analog equalizer correction device). The memory 32 can include a program storage area and a data storage area, and the program storage area can store an operating system, an application program required for at least one function;
The data storage area can store data created by use of the control chip, etc. Furthermore, the memory 32 can include high-speed random access memory, or can include non-volatile memory, such as at least one magnetic disk memory device, flash memory device, or other non-volatile solid-state memory device. In some examples, the memory 32 can also include memory located remotely to the processor 31, and these remote memories can be connected to the control chip via a network. Examples of the above networks include, but are not limited to, the Internet, a company intranet, a local area network, a mobile communication network, and combinations thereof.

According to an embodiment of the present application, a receiver is further provided. Figure 5 is a schematic diagram of a receiver provided according to an embodiment. As shown in Figure 5, the system includes an analog front-end circuit, a monitoring circuit, and the control chip described in the above embodiment;
an output side of the analog front-end circuit is connected to an input side of the monitoring circuit;
the output of the monitoring circuit is connected to the input of the control chip;
The control chip is configured to make a correction to an analog equalizer in the analog front-end circuit according to a monitoring result of the monitoring circuit.

In the receiver of this embodiment, the height of the forward eye pattern is used as the correction standard, and the analog equalizer is corrected so that the height of the forward eye pattern of the signal is sufficiently high, thereby improving the quality of the eye pattern and the quality of the output signal of the analog front-end circuit, realizing adaptive correction of the analog equalizer, which can be applied to all channel attenuation situations, has a simple circuit configuration, and is easy to implement.

In one embodiment, the monitoring circuit includes a first decision circuit, a clock data recovery circuit, and a second decision circuit.

In this embodiment, a first decision circuit and a clock data recovery circuit sample the output signal to obtain a first data signal, an edge signal, and a two-phase clock corresponding to the first data signal and the edge signal;
sampling the output signal according to a sampling clock by a second decision circuit to obtain a second data signal;
The second data signal is compared to the first data signal to determine a relationship between a monitored forward eye height and the eye height threshold.

Figure 6 is a schematic diagram of the operation principle of a receiver provided by one embodiment. As shown in Figure 6, a signal received by the receiver passes through an on-die termination resistor (ODT) for weakening signal reflection, three stages of CTLE, two SLICER circuits, a CDR circuit, an ESSLICER circuit, a VTH circuit, a data demultiplexer (DMUX) circuit, and a control chip in sequence, and the AFE circuit includes an on-die ODT and a CTLE. The high-speed serial data signal transmitted by the transmitter (Transmit, TX) passes through channel attenuation and interference and arrives at the input side of the receiver (Reception, RX), where the eye pattern is closed or may not be able to open to a preset degree. By adjusting the compensation function on/off state and/or gain of the three-stage CTLE, the eye pattern of the output signal of the AFE circuit can be opened to a preset degree, thereby realizing accurate transmission of data.

The correction command generated by the control chip includes a compensation function on command, for example, CTLE_BOOST_EN<2:0> for controlling the on/off state of the compensation function of the three stages of CTLE.
The correction command may further include gain adjustment commands, for example, LFG<4:0> for controlling the overall low-frequency gain of the three-stage CTLE, and HFG<4:0> for controlling the overall high-frequency gain of the three-stage CTLE, and the larger the control code of the LFG or HFG command, the larger the adjustment range of the low-frequency gain or high-frequency gain will be accordingly.

In FIG. 6, the output signal of the AFE circuit is input to two SLICER circuits, which sample the signal to obtain a first data signal and an edge signal.
The two-phase clocks CLK0 and CLK180 output from the CDR are used to determine the sampling of the two SLICER circuits, respectively.
The first data signal and the edge signal are input to the CDR circuit to perform clock recovery. The VTH circuit can be used to set the decision thresholds (VTH1 and/or VTH2) of the ESSLICER circuit.
The sampling clock ECLK0 of the ESSLICER is synchronous with and edge-aligned with the sampling clock CLK0 of the SLICER used to sample and obtain the first data signal. The control chip performs correction to the CTLE based on the first data signal, the second data signal, and the clock lock signal, and when the correction is completed, the recovered correct data can be output to the Physical Coding Sublayer (PCS) via DMUX.

In this embodiment, there are no limitations on the number of CTLE stages, the number of control code bits in the correction command, or the number of ESSLICERs and VTHs. The decision thresholds corresponding to the first and second decision circuits may be fixed values or dynamic values.

The receiver proposed in this embodiment belongs to the same inventive concept as the correction method proposed in the above embodiments, so that any of the above embodiments may be referred to for technical details not described in detail in this embodiment, and this embodiment has the same beneficial effects as when implementing a correction method for an analog equalizer.

According to an embodiment of the present application, a storage medium is further provided, the storage medium storing a computer program, which, when executed by a processor, realizes the analog equalizer correction method according to any one of the embodiments of the present application. The method includes: monitoring a forward eye pattern height of an output signal of an analog front-end circuit including at least one stage of an analog equalizer;
generating a correction command when the monitored forward eye height is less than an eye height threshold;
and correcting an analog equalizer in the analog front-end circuit according to the correction command until a monitored forward eye height reaches the eye height threshold.

The computer storage medium of the embodiments of the present application may be any combination of one or more computer readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of computer readable storage media include an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory, a read only memory (ROM), an erasable programmable read only memory (EPROM), a flash memory, an optical fiber, a portable CD-ROM, an optical memory device, a magnetic memory device, or any suitable combination of the above. A computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

The program code contained in the computer readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the above.

One or more programming languages or combinations thereof may be used to create computer program code for carrying out the operations of the present application, including object-oriented programming languages such as Java, Smalltalk, C++, and traditional procedural programming languages such as "C" or similar programming languages. The program code may run entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. When a remote computer is involved, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider).

The above are merely illustrative examples of the present application and are not intended to limit the scope of protection of the present application.

Those skilled in the art will appreciate that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a mobile web browser, or a mobile station mounted on a vehicle.

In general, various embodiments of the present application may be implemented in hardware or special purpose circuits, software, logic, or any combination thereof. For example, but not limited to, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software executable by a controller, microprocessor, or other computing device.

Embodiments of the present application may be implemented, for example, by a data processor of a mobile device executing computer program instructions, either in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or target code written in any combination of one or more programming languages.

The above provides a detailed description of the exemplary embodiments of the present application as illustrative and non-limiting examples. However, when considered in conjunction with the accompanying drawings and claims, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art without departing from the scope of the present application. Therefore, the appropriate scope of the present application is determined based on the claims.

Claims (15)

A method for correcting an analog equalizer, comprising: monitoring an eye pattern height of an output signal of an analog front-end circuit including at least one stage of an analog equalizer;
generating a correction command if the monitored eye height is less than an eye height threshold;
correcting an analog equalizer in the analog front-end circuit according to the correction command until a monitored eye height reaches the eye height threshold;
Including,
correcting an analog equalizer in the analog front-end circuit according to the correction command until a monitored eye height reaches the eye height threshold;
decreasing a low frequency gain of an analog equalizer in the analog front end circuit by a second step size until a monitored eye height reaches the eye height threshold when the amplitude of the output signal is greater than or equal to an amplitude threshold and a low frequency gain of an analog equalizer is greater than or equal to a lower limit.
A correction method for an analog equalizer, comprising: The correction command includes a compensation function ON command,
The method of claim 1 , wherein the compensation function on command is utilized to instruct turning on a compensation function of an analog equalizer in the analog front-end circuit. the correction command includes a gain adjustment command;
The gain adjustment command is
increasing a high frequency gain of an analog equalizer in the analog front end circuit by a first step size;
and decreasing a low frequency gain of an analog equalizer in the analog front-end circuit by a second step size. Monitoring the height of the eye pattern of the output signal of the analog front-end circuit is
sampling the output signal by a first decision circuit and a clock data recovery circuit to obtain a first data signal, an edge signal, and a two-phase clock corresponding to the first data signal and the edge signal;
sampling the output signal according to a sampling clock by a second decision circuit to obtain a second data signal;
and comparing the second data signal with the first data signal to determine a relationship between a monitored eye height and the eye height threshold. Comparing the second data signal to the first data signal to determine a relationship between a monitored eye height and the eye height threshold includes:
if a clock lock signal is detected, reading a second data signal and the first data signal of the same length;
performing an exclusive-or operation on bits in the first data signal that are one with the values of corresponding bits in the second data signal, and accumulating the results of the exclusive-or operations on each bit;
if the cumulative result is zero, determining that the height of the monitored eye pattern has reached the eye pattern height threshold;
and if the result of the accumulation is not zero, determining that the monitored eye height is below the eye height threshold or that the eye of the output signal is closed. 6. The method according to claim 4 or 5, wherein a sampling clock corresponding to the second data signal and a clock corresponding to the first data signal are synchronous and edge-aligned. generating a correction command when the monitored eye height is less than an eye height threshold;
When the monitored eye pattern height is lower than an eye pattern height threshold, determining an on/off state of a compensation function of each of the analog equalizers in the analog front-end circuit and a gain adjustment policy for the analog equalizers based on the first data signal, the second data signal, and a clock lock signal;
The method of claim 4 , further comprising: generating the correction instructions based on the on/off state and the gain adjustment policy. determining a relationship between an amplitude of the output signal and an amplitude threshold based on the second data signal;
8. The method of claim 4, further comprising: determining whether a low-frequency gain of an analog equalizer in the analog front-end circuit has decreased to a lower limit value based on a relationship between the amplitude of the output signal and an amplitude threshold value. Determining a relationship between an amplitude of the output signal and an amplitude threshold based on the second data signal includes:
reading a second data signal of a set length if a clock lock signal is detected;
Counting the number of bits in the second data signal that have a value of 1 or accumulating the value of each bit in the second data signal;
determining that the amplitude of the output signal has reached the amplitude threshold value when the number of bits having a value of 1 is equal to or greater than a set value, or when the cumulative result is equal to or greater than a set value;
and determining that the amplitude of the output signal is below the amplitude threshold if the number of bits with a value of 1 or the result of the accumulation is less than a set value. correcting an analog equalizer in the analog front-end circuit according to the correction command until a monitored eye height reaches the eye height threshold;
turning on a compensation function of an analog equalizer in the analog front-end circuit according to the correction command;
increasing a high frequency gain of an analog equalizer in the analog front-end circuit by a first step size until a monitored eye height reaches the eye height threshold based on a starting condition;
10. The method according to claim 1, further comprising: if the monitored eye height still does not reach the eye height threshold after the high frequency gain of the analog equalizer is increased to an upper limit value, repeatedly performing an operation of increasing the high frequency gain by turning on a compensation function of at least one stage of the analog equalizer that is not in an on state until the monitored eye height reaches the eye height threshold, or reducing the low frequency gain of the analog equalizer in the analog front-end circuit by a second step size. The method of claim 10 , wherein the starting condition includes a low frequency gain of an analog equalizer set to a maximum value and a high frequency gain of an analog equalizer set to a minimum value. A control chip including a memory, a processor, and a computer program stored in the memory and executable on the processor,
A control chip that, when the program is executed by the processor, realizes the analog equalizer correction method according to any one of claims 1 to 11 . A receiver including an analog front-end circuit, a monitoring circuit, and a control chip according to claim 12 ,
an output side of the analog front-end circuit is connected to an input side of the monitoring circuit;
the output of the monitoring circuit is connected to the input of the control chip;
The control chip is configured to correct an analog equalizer in the analog front-end circuit according to a monitoring result of the monitoring circuit. the monitoring circuit includes a first decision circuit, a clock data recovery circuit, and a second decision circuit;
the first decision circuit is configured to sample the output signal of the analog front-end circuit according to the two-phase clock supplied from the clock data recovery circuit to obtain a first data signal and an edge signal;
14. The receiver of claim 13 , wherein the second decision circuit is configured to sample the output signal according to a sampling clock to obtain a second data signal. A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the analog equalizer correction method according to any one of claims 1 to 11 .