JP7569258B2 - Thin film capacitor and its manufacturing method - Google Patents

Description

The present invention relates to a thin-film capacitor and a manufacturing method thereof, and in particular to a thin-film capacitor having a redistribution layer that connects a capacitor layer and a terminal electrode, and a manufacturing method thereof.

Circuit boards on which ICs are mounted usually have decoupling capacitors to stabilize the potential of the power supply supplied to the IC. Multilayer ceramic chip capacitors are generally used as decoupling capacitors, and the necessary decoupling capacitance is ensured by mounting a large number of multilayer ceramic chip capacitors on the surface of the circuit board.

However, in recent years, there is sometimes a shortage of space on a circuit board to mount a large number of multilayer ceramic chip capacitors. For this reason, thin film capacitors that can be embedded in a circuit board are sometimes used instead of multilayer ceramic chip capacitors (see Patent Document 1).

The thin-film capacitor described in Patent Document 1 has a rewiring layer that connects the capacitor layer and the terminal electrode.

JP 2018-137310 A

However, depending on the positional relationship between the outer edge of the capacitor layer, the outer edge of the insulating resin layer on which the redistribution layer is formed, and the outer edge of the terminal electrode, internal cracks may occur due to stress applied during singulation.

Therefore, the present invention aims to provide a thin-film capacitor with a structure that is less susceptible to cracks during individualization, and a method for manufacturing the same.

The thin film capacitor according to the present invention comprises a support material, a capacitor layer provided on the support material and consisting of a plurality of electrode layers and a plurality of dielectric layers alternately stacked, a first redistribution layer provided on a first insulating resin layer covering the capacitor layer, a second redistribution layer provided on a second insulating resin layer covering the first redistribution layer, and a terminal electrode connected to the second redistribution layer, characterized in that the peripheral edge of the first insulating resin layer is located outside the peripheral edge of the capacitor layer, and the peripheral edge of the terminal electrode is located outside the peripheral edge of the first insulating resin layer.

According to the present invention, when the support material is pushed through by a blade to separate the material, the fulcrum positions at which stress is concentrated are dispersed, making it less likely that cracks will occur during the process.

The thin-film capacitor according to the present invention may further include a passivation layer made of an inorganic insulating material provided between the capacitor layer and the first insulating resin layer. This makes it less likely that cracks will occur in the passivation layer during singulation.

In the present invention, the terminal electrode may be inclined near the outer peripheral edge so that the distance from the substrate becomes shorter as it approaches the outer peripheral edge. This causes stress to concentrate on the outer peripheral edge of the terminal electrode during singulation. As a result, cracks are more likely to occur in the second insulating resin layer at this position, and the inside of the element located away from the outer peripheral edge of the terminal electrode is protected.

In the present invention, the distance from the outer edge of the first insulating resin layer to the outer edge of the terminal electrode may be 10 μm or more. This further distributes the fulcrum positions at which stress is concentrated, making it less likely that cracks will occur during singulation.

In the present invention, the outer peripheral edge of the first insulating resin layer may be covered by a dummy pattern of the first rewiring layer. This prevents the characteristics from changing even if stress is applied to the dummy pattern.

In this way, the present invention makes it possible to provide a thin-film capacitor with a structure that is less susceptible to cracks during individualization, and a method for manufacturing the same.

FIG. 1 is a schematic plan view of a thin film capacitor 1 according to an embodiment of the present invention. 2(a) is a schematic cross-sectional view taken along line AA shown in FIG. 1, and FIG. 2(b) is a schematic cross-sectional view taken along line BB shown in FIG. FIG. 3 is a schematic cross-sectional view taken along line CC shown in FIG. FIG. 4 is a schematic cross-sectional view for explaining a method for dividing the thin film capacitor 1 into individual pieces. FIG. 5 is a schematic plan view of a thin film capacitor 1A according to a first modified example. FIG. 6 is a schematic plan view of a thin film capacitor 1B according to a second modified example.

A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Figure 1 is a schematic plan view of a thin-film capacitor 1 according to one embodiment of the present invention. Also, Figure 2(a) is a schematic cross-sectional view taken along line A-A in Figure 1, Figure 2(b) is a schematic cross-sectional view taken along line B-B in Figure 1, and Figure 3 is a schematic cross-sectional view taken along line C-C in Figure 1.

As shown in Figures 1 to 3, the thin film capacitor 1 according to this embodiment includes a support material 10, a capacitor layer 20 provided on the surface of the support material 10, a passivation layer 30 covering the capacitor layer 20, insulating resin layers 31 and 32 covering the passivation layer 30, rewiring layers 41 and 42 provided on the surfaces of the insulating resin layers 31 and 32, respectively, and terminal electrodes 51 and 52 connected to the rewiring layer 42.

The support material 10 is made of a high melting point metal such as nickel (Ni) and functions as a support for ensuring the mechanical strength of the thin film capacitor 1 according to this embodiment, and also functions as part of the electrode layer of the capacitor. However, it is not essential for the present invention that the support material 10 be part of the electrode layer. It is also not essential that the support material 10 be made of a conductive material; for example, it may be a film made of an insulating material.

The capacitor layer 20 has a structure in which electrode layers 21, 22 made of nickel (Ni) or the like are alternately stacked with dielectric layers 23 interposed therebetween. In the example shown in FIG. 2, the capacitor layer 20 is composed of three electrode layers 21, three electrode layers 22, and six dielectric layers 23, but the number of layers of these electrode layers 21, 22, and dielectric layers 23 is not particularly limited.

The dielectric layer 23 is made of, for example, a perovskite-based dielectric material. Perovskite-based dielectric materials include (ferro)dielectric materials having a perovskite structure such as BaTiO ₃ (barium titanate), (Ba _1-x Sr _x )TiO ₃ (barium strontium titanate), (Ba _1-x Ca _x )TiO ₃ , PbTiO ₃ , and Pb(Zr _x Ti _1-x )O ₃ , as well as composite perovskite relaxor-type ferroelectric materials such as Pb(Mg _1/3 Nb _2/3 )O ₃ , bismuth layered compounds such as Bi ₄ Ti ₃ O ₁₂ and SrBi ₂ Ta ₂ O ₉ , (Sr _1-x Ba _x )Nb ₂ O ₆ , and PbNb ₂ O 3 . Examples of the ferroelectric materials include tungsten bronze type ferroelectric materials represented by _.6 . Here, in the perovskite structure, the perovskite relaxor type ferroelectric material, the bismuth layered compound, and the tungsten bronze type ferroelectric material, the A site and the B site ratio are usually an integer ratio, but may be intentionally deviated from the integer ratio in order to improve the characteristics. In addition, in order to control the characteristics of the dielectric layer 23, the dielectric layer 23 may contain an additive substance as a subcomponent as appropriate. The dielectric layer 23 is sintered, and its relative dielectric constant (ε _r ) is, for example, 100 or more. In addition, the higher the relative dielectric constant of the dielectric layer 23, the more preferable it is, and the upper limit value is not particularly limited. The thickness of each dielectric layer 23 is, for example, about 10 nm to 1000 nm.

The passivation layer 30 is made of an inorganic insulating material such as silicon oxide (SiO ₂ ) and covers the entire surface of the capacitor layer 20 except for the connection portion to the rewiring layer 41. The passivation layer 30 is relatively brittle and is therefore prone to cracks due to stress.

The insulating resin layer 31 is made of an organic insulating material and covers the capacitor layer 20 via the passivation layer 30. As shown in FIG. 1 and FIG. 3, the outer edge of the insulating resin layer 31 is located outside the outer edge of the capacitor layer 20 (the edge side of the chip constituting the thin film capacitor). As a result, the insulating resin layer 31 has a portion that overlaps with the capacitor layer 20 in a planar view and a portion that does not overlap with the capacitor layer 20. Here, the outer edge of the capacitor layer 20 refers to the outer edge of the portion that functions as a capacitor. In other words, if some layers of the electrode layers 21, 22 close to the support material 10 are not connected to the terminal electrodes 51, 52 and do not function as a capacitor, the portion consisting of these electrode layers 21, 22 and the dielectric layer 23 located between them does not constitute the capacitor layer 20, and the portion consisting of the electrode layers 21, 22 connected to the terminal electrodes 51, 52 and the dielectric layer 23 located between them constitutes the capacitor layer 20. The reason why the electrode layers 21, 22 located in the lower layers are not connected to the terminal electrodes 51, 52 is because the film quality of the dielectric layer 23 located in the lower layer is unstable. Therefore, the capacitor layer 20 is composed of the upper electrode layers 21 and 22 and the dielectric layer 23 located between them.

On the surface of the insulating resin layer 31, a redistribution layer 41 made of a metal such as Cu is provided. The redistribution layer 41 has a portion connected to the electrode layer 21 through a via hole provided in the capacitor layer 20, and a portion connected to the electrode layer 22 through a via hole provided in the capacitor layer 20. FIG. 2(a) shows the redistribution layer 41 connected to the electrode layer 22, and FIG. 2(b) shows the redistribution layer 41 connected to the electrode layer 21. As shown in FIG. 3, the peripheral portion of the redistribution layer 41 forms a dummy pattern 41D, and is separated in-plane from the portion connected to the electrode layers 21 and 22. As a result, the peripheral edge of the insulating resin layer 31 is covered by the dummy pattern 41D of the redistribution layer 41.

The rewiring layer 41 is covered with an insulating resin layer 32. The insulating resin layer 32 is made of the same organic insulating material as the insulating resin layer 31. In this embodiment, the outer peripheral edge of the insulating resin layer 32 is aligned in plan with the side surface 12 of the support material 10.

A redistribution layer 42 made of a metal such as Cu is provided on the surface of the insulating resin layer 32. The redistribution layer 42 has a portion that is connected to the electrode layer 21 via the redistribution layer 41, and a portion that is connected to the electrode layer 22 via the redistribution layer 41. FIG. 2(a) shows the redistribution layer 42 connected to the electrode layer 22, and FIG. 2(b) shows the redistribution layer 42 connected to the electrode layer 21.

The rewiring layer 42 is covered with terminal electrodes 51 and 52 made of a metal such as Cu. The terminal electrode 51 is connected to the electrode layer 21 via the rewiring layers 42 and 41, and the terminal electrode 52 is connected to the electrode layer 22 via the rewiring layers 42 and 41. When the dummy pattern 41D is in contact with the support material 10 made of a conductive material and the support material 10 functions as a part of the electrode layer, the dummy pattern 41D and the terminal electrode 51 or 52 are electrically connected. As shown in Figures 1 and 3, the outer peripheral edges of the terminal electrodes 51 and 52 are located outside the outer peripheral edge of the insulating resin layer 31. As a result, the terminal electrodes 51 and 52 have parts that overlap with the insulating resin layer 31 and parts that do not overlap with the insulating resin layer 31 in a plan view.

The above is the structure of the thin film capacitor 1 according to this embodiment. Next, we will explain the manufacturing method of the thin film capacitor 1 according to this embodiment.

First, an assembly substrate made of nickel (Ni) or the like is prepared. The assembly substrate is a substrate for obtaining a large number of thin-film capacitors 1, and corresponds to the support material 10 before cutting. Next, the dielectric layer 23 and the electrode layers 21, 22 are alternately laminated on the surface of the assembly substrate using a method such as sputtering, and then via holes for connection are formed, and the electrode layers 21, 22 and the dielectric layer 23 in the peripheral region are removed to form the capacitor layer 20. Next, the dielectric layer 23 is sintered by firing.

Next, a passivation layer 30 is formed on the entire surface of the capacitor layer 20 using a method such as sputtering. Next, the passivation layer 30 in the portion corresponding to the via hole is removed by patterning, and then an insulating resin layer 31 is formed on the entire surface. Next, a via hole is provided in the insulating resin layer 31, and the insulating resin layer 31 in the peripheral region is removed. At this time, patterning is performed so that the peripheral edge of the insulating resin layer 31 is positioned outside the peripheral edge of the capacitor layer 20.

Next, a rewiring layer 41 is formed on the surface of the insulating resin layer 31. As a result, a part of the rewiring layer 41 is connected to the electrode layer 21 through the via hole, and the remaining part of the rewiring layer 41 is connected to the electrode layer 22 through the via hole. Next, an insulating resin layer 32 is formed to cover the rewiring layer 41, and then a via hole that exposes the rewiring layer 41 is formed in the insulating resin layer 32. Next, a rewiring layer 42 is formed on the surface of the insulating resin layer 32. As a result, a part of the rewiring layer 42 is connected to the electrode layer 21 through the rewiring layer 41, and the remaining part of the rewiring layer 42 is connected to the electrode layer 22 through the rewiring layer 41.

Next, the terminal electrodes 51 and 52 are formed on the surface of the rewiring layer 42 using electrolytic plating or the like. At this time, the position of the plating resist is adjusted so that the outer peripheral edges of the terminal electrodes 51 and 52 are positioned outside the outer peripheral edge of the insulating resin layer 31. Then, as shown in FIG. 4, the assembly substrate 10a and the insulating resin layer 32 are pressed through with a blade 60 to separate them into a plurality of thin-film capacitors 1. At this time, stress is applied to each part of the thin-film capacitor 1 by the pressure of the blade 60. The stress applied at this time is particularly concentrated at position P1 of the outer peripheral edge of the capacitor layer 20, position P2 of the outer peripheral edge of the insulating resin layer 31, and position P3 of the outer peripheral edges of the terminal electrodes 51 and 52. This is because positions P1 to P3 become fulcrums when the thin-film capacitor 1 tries to deform due to the pressure of the blade 60. In particular, since the terminal electrodes 51 and 52 have a relatively high rigidity, the most stress is concentrated at position P3.

However, in this embodiment, since the positions P1 to P3 are distributed and the position P3 where the stress is most concentrated is far away from the capacitor layer 20, the capacitor layer 20 itself is not subjected to strong stress. Moreover, as shown in FIG. 4, the terminal electrode 51 (52) is inclined near the outer peripheral edge and its height position becomes lower as it approaches the outer peripheral edge, so that stress is concentrated on the terminal electrode edge portion at position P3 during singulation. As a result, cracks are likely to occur in the insulating resin layer 32 at position P3, so the inside of the element located at a position away from the outer peripheral edge of the terminal electrode 51 (52) is protected. Therefore, cracks are unlikely to occur in the passivation layer 30 during singulation, and even if cracks occur, they occur outside the capacitor layer 20, so there is no impact on various characteristics such as insulation resistance.

To fully obtain this effect, it is desirable for the distance between positions P1 and P2, and the distance between positions P2 and P3 to be greater; in particular, reliability can be significantly improved by ensuring that the distance between positions P2 and P3 is 10 μm or greater. On the other hand, as these distances increase, the effective area of the capacitor layer 20 relative to the chip size decreases, so it is preferable for the distance between positions P1 and P2 to be in the range of 5 to 30 μm, and for the distance between positions P2 and P3 to be in the range of 5 to 50 μm.

Figure 5 is a schematic plan view of a thin-film capacitor 1A according to a first modified example. As shown in Figure 5, the thin-film capacitor 1A according to the first modified example differs from the thin-film capacitor 1 according to the above embodiment in that it has four terminal electrodes 51 to 54. Thus, in the present invention, the number of terminal electrodes is not particularly limited.

Figure 6 is a schematic plan view of a thin film capacitor 1B according to a second modified example. As shown in Figure 6, the thin film capacitor 1B according to the second modified example differs from the thin film capacitor 1 according to the above embodiment in that the terminal electrodes 51, 52 are arranged in the short side direction. In this way, by arranging the terminal electrodes 51, 52 in the short side direction, it is possible to reduce the ESL.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these are also included within the scope of the present invention.

Reference Signs List 1, 1A, 1B Thin film capacitor 10 Support material 10a Substrate assembly 12 Side surface of support material 20 Capacitor layers 21, 22 Electrode layer 23 Dielectric layer 30 Passivation layers 31, 32 Insulating resin layers 41, 42 Rewiring layer 41D Dummy patterns 51 to 54 Terminal electrodes 60 Blades P1 to P3 Position of outer periphery edge

Claims (5)

A support material;
a capacitor layer provided on the support material and including a plurality of electrode layers and a plurality of dielectric layers alternately stacked;
a first rewiring layer provided on a first insulating resin layer covering the capacitor layer;
a second rewiring layer provided on a second insulating resin layer covering the first rewiring layer;
a terminal electrode connected to the second redistribution layer;
an outer peripheral edge of the first insulating resin layer is located outside an outer peripheral edge of the capacitor layer;
an outer peripheral edge of the terminal electrode is located outside an outer peripheral edge of the first insulating resin layer ;
a thin-film capacitor characterized in that the height position of the terminal electrode based on the support material is inclined near the outer peripheral edge so that the height at a portion overlapping with the capacitor layer, outside the outer peripheral edge of the capacitor layer, and the height at a portion overlapping with the first insulating resin layer, outside the outer peripheral edge of the first insulating resin layer, is lower than the height at a portion overlapping with the capacitor layer, outside the outer peripheral edge of the capacitor layer, and the height at a portion overlapping with the second insulating resin layer, outside the outer peripheral edge of the first insulating resin layer, is lower than the height at a portion overlapping with the first insulating resin layer, outside the outer peripheral edge of the capacitor layer. The thin-film capacitor according to claim 1, further comprising a passivation layer made of an inorganic insulating material provided between the capacitor layer and the first insulating resin layer. 3. The thin film capacitor according to claim 1, wherein the distance from an outer peripheral edge of the first insulating resin layer to an outer peripheral edge of the terminal electrode is 10 [mu]m or more. 4. The thin film capacitor according to claim 1, wherein an outer peripheral edge of the first insulating resin layer is covered with a dummy pattern of a first rewiring layer. 5. A method for producing a thin film capacitor according to claim 1 , wherein the supporting material is cut with a blade to separate the thin film capacitor.

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