JP7566554B2 - Signal generating device and signal reading system - Google Patents

Description

The present invention relates to a signal generating device that generates a code identification signal capable of identifying a code sequence corresponding to a logic signal based on a two-wire differential voltage logic signal transmitted over a communication path, and a signal reading system equipped with such a signal generating device.

For example, the following Patent Document 1 discloses an invention for a vehicle data collection device (hereinafter simply referred to as the "collection device") configured to collect and record various CAN frames (control data) transmitted via a serial bus (in-vehicle LAN) for CAN communication. This collection device is configured to be connectable to a diagnostic connector (connector for connecting diagnostic equipment: hereinafter simply referred to as the "connector") provided on the serial bus to allow connection of external equipment for purposes such as fault diagnosis and maintenance. This collection device also employs a configuration in which, when connected to the above connector, it operates using power supplied via the connector, and automatically starts/stops collection of CAN frames from the serial bus in conjunction with the operation of the ignition switch.

However, there was a demand for a device that could read CAN frames from a serial bus with a configuration different from that of the above-mentioned collection device (a configuration that does not use the connector provided on the serial bus), so the applicant proposed the signal generation device and signal reading system disclosed in the following Patent Document 2.

This signal generating device includes a detection unit that detects a differential signal indicating a change in the potential difference between each of the coated conductor wires that changes according to a logic pattern, which is an arrangement pattern of high potential periods and low potential periods in a logic signal of a two-wire differential voltage method transmitted via a communication path (a pair of coated conductor wires that constitute a serial bus for CAN communication), and a signal generating unit, and generates a code identification signal that can identify the code sequence corresponding to the logic signal.

In this case, the detection unit includes a transformer having a primary winding and a secondary winding, and a resistor connected between each terminal of the secondary winding, and inputs each signal detected by a pair of electrodes, which are respectively brought into contact with the coating of the pair of coated conductors, to each terminal of the primary winding via a coupling capacitance between the pair of coated conductors and the pair of electrodes, and detects the above-mentioned differential signal based on an output signal output from each terminal of the secondary winding. The signal generation unit generates, as a code identification signal, a signal that indicates the start of a low voltage period when the voltage at the rising edge of the differential signal is equal to or greater than a first reference value and the start of a high voltage period when the voltage at the falling edge of the differential signal is equal to or less than a second reference value.

In this signal generating device, in a configuration that does not take into account the wiring capacitance of the shielded cable connecting the pair of electrodes and the detection unit (a configuration in which the capacitance value of this wiring capacitance is negligibly small), the voltage of the coated conductor wire is differentiated by the coupling capacitance and transmitted to the electrode, so that the differential signal Sd output from the detection unit rises from zero volts to the maximum positive voltage in a short time at the timing (rising edge of logic signal Sa) when the logic signal Sa, represented by the differential voltage (Va-Vb) of the voltages Va and Vb of the pair of coated conductor wires, transitions from a low voltage state (recessive state indicating the symbol Cs "1") to a high voltage state (dominant state indicating the symbol Cs "0"), then gradually decreases and returns to zero volts, and then falls from zero volts to the maximum negative voltage in a short time at the timing (falling edge of logic signal Sa) when the logic signal Sa transitions from a high voltage state to a low voltage state, then gradually increases and returns to zero volts, as shown in FIG. 16 (differential waveform).

The signal generating unit disposed downstream of the detection unit is, for example, a comparator with hysteresis that operates with two positive and negative operating voltages (for example, ±5V) (a comparator in which the output voltage is resistively divided with zero volts as a reference and applied to the non-inverting input terminal, and the differential signal Sd is input to the inverting input terminal). With this configuration, the signal generating unit converts the differential signal Sd from the detection unit into a sign identification signal Sf as a binary signal based on the positive threshold Vr1 as a first reference value obtained by resistively dividing the positive output voltage (voltage close to the positive operating voltage) and the negative threshold Vr2 (|Vr2| = |Vr1|) as a second reference value obtained by resistively dividing the negative output voltage (voltage close to the negative operating voltage), as shown in FIG. 16. In this case, as shown in FIG. 16, the high voltage period of the code identification signal Sf corresponds to the period (recessive) when the code of the logic signal Sa is "1," and the low voltage period corresponds to the period (dominant) when the code of the logic signal Sa is "0."

JP 2008-70133 A (pages 4-11, Figures 1-17) JP 2019-146141 A (pages 14-16, Figures 1-3)

However, in a serial bus for CAN communication, collisions between signals output from multiple electronic control units (ECUs) connected to the serial bus occur regularly. For this reason, the signal waveform of logic signal Sa is not an ideal waveform that is constant at a voltage (low voltage or high voltage) corresponding to the code "1" or "0" during each period of code Cs "1" or "0" as shown in Figure 16 above, but rather has a waveform that rises and falls in a pulse-like or step-like manner, especially during the high voltage period, as shown in Figure 17. For this reason, in a configuration in which the detection unit generates a difference signal Sd of a signal waveform corresponding to the differential waveform of the logic signal Sa, and the signal generation unit, which is composed of a comparator with hysteresis, compares this difference signal Sd with a positive threshold Vr1 and a negative threshold Vr2 to generate a code identification signal Sf, as shown in FIG. 17, even at times other than the timing when the code Cs switches between "1" and "0", the difference signal Sd exceeds the positive threshold Vr1 (for example, at times t2, t4, and t6 in the figure) or falls below the negative threshold Vr2 (for example, at times t1, t3, and t5 in the figure) at times when the rate of change is large when the voltage of the logic signal Sa rises or falls in a pulse-like or step-like manner. Therefore, this signal generation device has a problem to be improved in that, as shown in FIG. 17, a state in which the voltage becomes temporarily high during a low voltage period corresponding to the code "0" occurs (i.e., an incorrect code identification signal Sf is generated).

The present invention was made in consideration of the above-mentioned problems that need to be improved, and its main objective is to provide a signal generating device and a signal reading system that can generate a code identification signal that can accurately identify the code indicated by a logic signal while adopting a configuration in which it is connected to a communication path such as a serial bus for CAN communication via a coupling capacitance.

To achieve the above object, the signal generating device of the present invention is a signal generating device that generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through a communication path formed by a coated conductor wire, and includes a signal restoration unit that generates a restored signal having a signal waveform equivalent to the signal waveform of the logic signal by integrating a signal waveform corresponding to the differential waveform of the logic signal detected from the coated conductor wire, and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage and binarizing it.

In addition, in the signal generating device of the present invention, the signal restoration unit includes a transformer having a primary winding and a secondary winding and a resistor connected between each terminal of the secondary winding, and generates the restoration signal by inputting a signal detected by an electrode that is brought into contact with a coating portion of the coated conductor to the primary winding via a coupling capacitance between the coated conductor and the electrode, and integrating a signal waveform that corresponds to a differential waveform of the logic signal output from the secondary winding. Here, the following configurations can be adopted for this signal generating device. For example, when a communication path is composed of a pair of covered conductor wires, a signal generating device that generates a code identifying signal capable of identifying a code corresponding to a logic signal based on a logic signal of a two-wire differential voltage method transmitted through a communication path composed of a pair of covered conductor wires includes a transformer having a primary winding and a secondary winding, and a resistor connected between each terminal of the secondary winding, and is configured to include a detection unit that inputs each signal detected by the pair of electrodes via a coupling capacitance between a pair of electrodes that are respectively brought into contact with the coating portions of the pair of covered conductor wires and the pair of covered conductor wires to each terminal of the primary winding, and outputs a detection signal of a signal waveform equivalent to the differential waveform of the logic signal based on an output signal output from each terminal of the secondary winding, an integration unit that integrates the detection signal to output a restored signal of a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identifying signal by comparing the restored signal with a threshold voltage to binarize it. In addition, when the communication path is composed of a single coated conductor wire, a signal generating device that generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through the communication path composed of a single coated conductor wire includes a transformer having a primary winding and a secondary winding and a resistor connected between each terminal of the secondary winding, and includes a detection unit that inputs a signal detected by an electrode that is brought into contact with the coating of the coated conductor wire through a coupling capacitance between the electrode and the coated conductor wire to the primary winding and outputs a detection signal of a signal waveform equivalent to the differential waveform of the logic signal based on an output signal output from the secondary winding, an integration unit that integrates the detection signal to output a restored signal of a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage and binarizing it.

In addition, in the signal generating device of the present invention, the signal restoration unit includes a resistive element that receives a signal detected by an electrode through capacitive coupling via a coupling capacitance between an electrode that is brought into contact with the coating of the coated conductor and the coated conductor, and generates the restored signal by integrating a signal waveform that corresponds to a differential waveform of the logic signal generated in the resistive element. Here, the following configurations can be adopted for this signal generating device. For example, in a case where a communication path is constituted by a pair of covered conductor wires, a signal generating device is provided that generates a code identifying signal capable of identifying a code corresponding to a logic signal based on a logic signal of a two-wire differential voltage method transmitted through a communication path constituted by the pair of covered conductor wires, the signal generating device being provided with: a first resistor element connected to one of a pair of electrodes that are brought into contact with the coatings of the pair of covered conductor wires, and generating a first voltage signal having a signal waveform corresponding to a differential waveform of a voltage signal transmitted to one of the covered conductor wires that is capacitively coupled to the one of the pair of covered conductor wires; a second resistor element connected to the other of the pair of electrodes, and generating a second voltage signal having a signal waveform corresponding to the differential waveform of a voltage signal transmitted to the other of the covered conductor wires that is capacitively coupled to the other of the pair of covered conductor wires; and a detection unit including a differential amplifier unit that outputs a detection signal having a signal waveform corresponding to the differential waveform of the logic signal based on a differential voltage between the first voltage signal and the second voltage signal; an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal; and a signal generating unit that generates the code identifying signal by comparing the restored signal with a threshold voltage to binarize it. In addition, when the communication path is composed of a single coated conductor wire, a signal generating device that generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through the communication path composed of a single coated conductor wire is provided with a detection unit that includes a resistive element that is connected to an electrode that is brought into contact with the coating of the coated conductor wire and that generates a voltage signal having a signal waveform equivalent to the differential waveform of the logic signal transmitted to the coated conductor wire that is capacitively coupled to the electrode, and an amplifier that amplifies the voltage signal and outputs it as a detection signal, an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage and binarizing it.

In addition, in the signal generating device of the present invention, the signal restoration unit includes a transformer having a primary winding and a secondary winding and resistors connected between each terminal of the secondary winding, and generates the restored signal by inputting a signal output from a current detection probe attached to the coated conductor to the primary winding and integrating a signal waveform corresponding to a differential waveform of the logic signal output from the secondary winding. Here, the following configurations can be adopted for this signal generating device. For example, in a case where a communication path is constituted by a pair of covered conductor wires, a signal generating device is provided that generates a code identifying signal capable of identifying a code corresponding to a logic signal based on a logic signal of a two-wire differential voltage system transmitted via a communication path constituted by a pair of covered conductor wires, the signal generating device being provided with a transformer having a primary winding and a secondary winding and a resistor connected between each terminal of the secondary winding, and is provided with a detection unit that inputs a current signal output from a first current detection probe attached to one of the pair of covered conductor wires and a current signal output from a second current detection probe attached to the other of the pair of covered conductor wires to each terminal of the primary winding and outputs a detection signal having a signal waveform equivalent to the differential waveform of the logic signal based on an output signal output from each terminal of the secondary winding, an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identifying signal by comparing the restored signal with a threshold voltage to binarize it. In addition, when the communication path is composed of a single coated conductor wire, a signal generating device that generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through the communication path composed of a single coated conductor wire includes a transformer having a primary winding and a secondary winding and a resistor connected between each terminal of the secondary winding, and includes a detection unit that inputs a current signal output from a current detection probe attached to the coated conductor wire to the primary winding and outputs a detection signal having a signal waveform equivalent to the differential waveform of the logic signal based on the output signal output from the secondary winding, an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage and binarizing it.

In addition, in the signal generating device of the present invention, the signal restoration unit includes a resistive element that receives a signal output from a current detection probe attached to the coated conductor, and generates the restored signal by integrating a signal waveform corresponding to a differential waveform of the logic signal generated in the resistive element. Here, the following configurations can be adopted for this signal generating device. For example, in a case where a communication path is constituted by a pair of covered conductor wires, a signal generating device is provided that generates a code identification signal capable of identifying a code corresponding to a logic signal based on a logic signal of a two-wire differential voltage method transmitted through a communication path constituted by the pair of covered conductor wires, the signal generating device being provided with: a first resistance element connected to a first current detection probe attached to one of the pair of covered conductor wires and generating a first voltage signal having a signal waveform corresponding to a differential waveform of the voltage signal transmitted to the one covered conductor wire; a second resistance element connected to a second current detection probe attached to the other covered conductor wire of the pair of covered conductor wires and generating a second voltage signal having a signal waveform corresponding to the differential waveform of the voltage signal transmitted to the other covered conductor wire; and a detection unit including a differential amplifier unit that outputs a detection signal having a signal waveform corresponding to the differential waveform of the logic signal based on a differential voltage between the first voltage signal and the second voltage signal; an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal; and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage to binarize it. In addition, when the communication path is composed of a single coated conductor wire, a signal generating device generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through the communication path composed of a single coated conductor wire, and is configured to include a detection unit that is connected to a current detection probe attached to the coated conductor wire and includes a resistance element that generates a voltage signal having a signal waveform equivalent to the differential waveform of the voltage signal transmitted to the coated conductor wire, and an amplifier that amplifies the generated voltage signal and outputs it as a detection signal, an integration unit that integrates the detection signal to output a restored signal having a signal waveform equivalent to the signal waveform of the logic signal, and a signal generating unit that generates the code identification signal by comparing the restored signal with a threshold voltage and binarizing it.

The signal generating device of the present invention is any of the signal generating devices described above, and further includes a waveform shaping unit disposed between the signal restoration unit and the signal generating unit, which shapes the restored signal into a single-ended signal with a peak-to-peak voltage equivalent to the peak-to-peak voltage of the restored signal and with a voltage during a low voltage period set to a target constant voltage, and outputs the signal.

The signal generating device of the present invention is any of the above signal generating devices, and further includes a waveform shaping unit disposed between the signal restoration unit and the signal generating unit, which shapes the restored signal into a single-ended signal with a peak-to-peak voltage equivalent to the peak-to-peak voltage of the restored signal and with a voltage during a high voltage period set to a target constant voltage, and outputs the signal.

The signal reading system of the present invention includes a signal generating device as described above, and a signal converting device that converts the code identification signal generated by the signal generating device into a signal of a communication method that conforms to the communication method of the logic signal and outputs the converted signal.

In the above-mentioned signal generating device and in a signal reading system equipped with any of these signal generating devices, the signal restoration unit integrates a signal waveform equivalent to the differential waveform of the logic signal transmitted through a communication path formed of a coated conductor wire, and generates a restored signal having a signal waveform equivalent to the signal waveform of the logic signal.

Therefore, with these signal generating devices and signal reading systems, even when a pulse-like or step-like voltage change occurs in the signal waveform of the logic signal, the restored signal can be correctly binarized at a single threshold voltage in the signal generating section without being affected by this voltage change, and a correct code identification signal can be generated.

According to the signal generating device and the signal reading system including this signal generating device, the waveform shaping unit adjusts the voltage level of the low-voltage side (the voltage during the low-voltage period) to the target constant voltage (i.e., shapes it into a single-ended signal) while maintaining the amplitude (peak-to-peak voltage) of the restored signal output from the signal restoration unit, and outputs it to the signal generating unit as a new restored signal. Therefore, by defining a voltage slightly higher than the target constant voltage as the threshold voltage in the signal generating unit, even when the voltage level of the low-voltage side of the restored signal output from the signal restoration unit is fluctuating, the new restored signal shaped into a single-ended signal can be reliably binarized at the threshold voltage to generate a code identification signal.

According to the signal generating device and the signal reading system including this signal generating device, the waveform shaping unit adjusts the voltage level of the high-voltage side (the voltage during the high-voltage period) to the target constant voltage (i.e., shapes it into a single-ended signal) while maintaining the amplitude (peak-to-peak voltage) of the restored signal output from the signal restoration unit, and outputs it to the signal generating unit as a new restored signal. Therefore, by defining a voltage slightly lower than the target constant voltage as the threshold voltage in the signal generating unit, even when the voltage level of the high-voltage side of the restored signal output from the signal restoration unit is fluctuating, the new restored signal shaped into a single-ended signal can be reliably binarized at the threshold voltage to generate a code identification signal.

FIG. 1 is a diagram showing a configuration of a signal reading system 1A. FIG. 2 is a diagram showing a configuration of a signal generating device 2A. 4 is a waveform diagram of the code Cs, the logic signal Sa, the current signal I1, the detection signal Sd, the restoration signal Sre, and the code identification signal Sf. FIG. 2 is a diagram showing a configuration of a signal generating device 2B. 5 is a diagram showing another configuration of the differential amplifier unit 23 in FIG. 4. FIG. 2 is a diagram showing the configuration of a signal reading system 1B. FIG. 2 is a diagram showing the configuration of a signal generating device 2C. FIG. 2 is a diagram showing the configuration of a signal generating device 2D. 1 is a diagram for explaining the structure of a signal reading system 1C in which a signal generating device 2A (2B) is connected to coated conductor wires La, Lb via current detection probes PLc, PLd. FIG. 13 is a configuration diagram for explaining the structure of a signal reading system 1D in which a signal generating device 2C (2D) is connected to a coated conductor wire Lw via a current detection probe PLc. FIG. 13 is a configuration diagram showing another configuration (a configuration having a waveform shaping unit 7) of the signal generating devices 2A, 2B, 2C, and 2D. 12 is a circuit diagram of a signal generating unit 6 and a waveform shaping unit 7 in FIG. 11. 12 is another circuit diagram of the signal generating unit 6 and the waveform shaping unit 7 in FIG. 11 . FIG. 2 is a diagram showing another configuration of the signal generating device 2A. FIG. 13 is a diagram showing another configuration of the signal generating device 2B. 1 is a waveform diagram of a code Cs, a logic signal Sa, a difference signal Sd, and a code identification signal Sf for explaining the background art. 11 is another waveform diagram of the code Cs, the logic signal Sa, the difference signal Sd, and the code identifying signal Sf for explaining the problem in the background art. FIG.

Below, an embodiment of a signal generating device and a signal reading system will be described with reference to the attached drawings.

As shown in FIG. 1, a signal reading system 1A, which is an example of a "signal reading system," has a signal generating device 2A, which is an example of a "signal generating device," and is configured to detect a two-wire differential voltage logic signal (logic signal Sa defined by the difference between the voltages Va and Vb transmitted to the coated conductors La and Lb) transmitted via a communication path SB consisting of a pair of coated conductors La and Lb, generate (read) a code identifying signal Sf capable of identifying a code Cs (a code of "1" or "0" represented by the voltage of the logic signal Sa; see FIG. 3) corresponding to the logic signal Sa, convert this code identifying signal Sf into a transmission signal So conforming to the same communication protocol as the logic signal Sa of the communication path SB, and output (transmit) it to various CAN communication-compatible devices.

The signal generating device 2A and signal reading system 1A can target, as this logic signal Sa, various "two-wire differential voltage type logic signals" that comply with various communication protocols such as "CAN (registered trademark) protocol," "CAN FD," and "FlexRay (registered trademark)," as well as various "two-wire differential voltage type logic signals" that comply with various communication protocols that enable small-amplitude, low-power consumption communication using "LVDS." In this case, in the "serial bus for CAN communication" of the "CAN protocol" and "CAN FD," the "high-side signal line (CANH)/low-side signal line (CANL)" corresponds to the "pair of covered conductors for transmitting logic signals," in the "serial bus for FlexRay communication," the "positive-side signal line (BP)/negative-side signal line (BM)" corresponds to the "pair of covered conductors for transmitting logic signals," and in the "serial bus for LVDS communication," the "positive logic side signal line/negative logic side signal line" corresponds to the "pair of covered conductors for transmitting logic signals." In the following, as an example, an application to a CAN bus (serial bus for CAN communication, hereinafter also referred to as the CAN bus SB) as a communication path SB arranged in an automobile will be described.

As shown in FIG. 1, the signal reading system 1A is configured to include a signal generating device 2A and a signal converting device 3 (an example of a "signal converting device"). The principle of transmitting the logic signal Sa via the CAN bus SB is well known and will not be described in detail, but in this example, the coated conductor wire La is the signal line corresponding to "CANH" and the coated conductor wire Lb is the signal line corresponding to "CANL". With this configuration, the logic signal Sa defined by the difference (Va-Vb) between the voltages Va and Vb corresponds to a recessive period indicating the code Cs "1" during a low voltage period, and corresponds to a dominant period indicating the code Cs "0" during a high voltage period, as shown in FIG. 3.

As an example, as shown in FIG. 2, the signal generating device 2A includes a detection unit 4A, an integration unit 5, and a signal generating unit 6, and is connected to a pair of coated conductor wires La, Lb via a pair of probes PLa, PLb to generate and output a code identification signal Sf.

The pair of probes PLa, PLb are configured identically as metal non-contact probes using shielded cables (coaxial cables, for example). Specifically, the probe PLa is configured such that the free end side (free end) of the probe PLa, which is removably connected to the corresponding coated conductor La, is provided with an electrode portion 11a that is connected (capacitively coupled) to the core wire (not shown) of the coated conductor La, and the base end side (base end) is provided with a connector (not shown) that is connected (fixedly or removably connected) to the corresponding input terminal portion 14 of the input terminal portions 14, 15 (described later) of the signal generating device 2A. In addition, the probe PLb is configured such that, on the free end side (free end portion) that is removably connected to the corresponding coated conductor wire Lb, an electrode portion 11b is provided that is connected (capacitively coupled) to the core wire (not shown) of the coated conductor wire Lb, and, on the base end side (base end portion), a connection connector (not shown) is provided that is connected (fixedly or removably connected) to the corresponding input terminal portion 15 of the input terminal portions 14, 15 of the signal generating device 2A.

As shown in Figures 1 and 2, when the electrode unit 11a is connected to the coated conductor La, it contacts (butts) the insulating coating part (hereinafter also simply referred to as the "coating part") of the coated conductor La, and has an electrode 12a that capacitively couples with the core wire (the conductor itself (metal part)) of the coated conductor La, and a shield 13a that covers the contact part of the electrode 12a in the coating part of the coated conductor La, including the electrode 12a, to prevent capacitive coupling with other metal parts of the electrode 12a (metal parts other than the core wire of the coated conductor La). The electrode 12a is also connected to one terminal TP1 of the primary winding 21a of the transformer 21 of the detection unit 4A, which will be described later, via the core wire of the shielded cable constituting the probe PLa and one terminal of the input terminal unit 14. In addition, the shield 13a is connected to the first reference potential portion (first ground G1) of the primary side (primary winding 21a side of the transformer 21) of the signal generating device 2A via the shield of this shielded cable and another terminal of the input terminal section 14.

As shown in Figs. 1 and 2, the electrode 11b, when connected to the coated conductor Lb, is in contact with (butt against) the insulating coating (hereinafter also simply referred to as the "coating") of the coated conductor Lb, and is capacitively coupled with the core (conductor itself (metal part)) of the coated conductor Lb, and is provided with a shield 13b that covers the contact portion of the electrode 12b in the coating of the coated conductor Lb, including the electrode 12b, to prevent capacitive coupling with other metal parts of the electrode 12b (metal parts other than the core of the coated conductor Lb). The electrode 12b is connected to the other terminal TP2 of the primary winding 21a of the transformer 21 of the detection unit 4A via the core of the shielded cable constituting the probe PLb and one terminal of the input terminal unit 15. The shield 13b is connected to the first ground G1 via the shield of the shielded cable and the other terminal of the input terminal unit 15.

With this configuration, a current path (also referred to as the primary side current path) is formed that runs from the core of the coated conductor wire La to the core of the coated conductor wire Lb via the coupling capacitance between this core and electrode 12a, electrode 12a, the core of the shielded cable that constitutes probe PLa, one terminal of input terminal unit 14, primary winding 21a, one terminal of input terminal unit 15, the core of the shielded cable that constitutes probe PLb, electrode 12b, and the coupling capacitance between the core of the coated conductor wire Lb and electrode 12b. In addition, since this primary current path is configured with capacitance components (coupling capacitances) connected in series, a current signal I1 having a signal waveform obtained by differentiating the signal waveform of the logic signal Sa defined by the difference (Va-Vb) between the voltages Va and Vb of the coated conductors La and Lb (i.e., a signal waveform that is maintained at zero during a period in which the signal waveform of the logic signal Sa does not change, temporarily increases in a spike-like manner on the positive side in synchronization with the rising portion of the signal waveform of the logic signal Sa, then exponentially decreases and returns to zero, while temporarily increases in a spike-like manner on the negative side in synchronization with the falling portion of the signal waveform of the logic signal Sa, then exponentially decreases and returns to zero) flows in the phase state shown in FIG. 3.

The detection unit 4A, together with the integrator 5, constitutes the signal restoration unit 8. In this case, the signal restoration unit 8 integrates a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductors La and Lb to generate a restoration signal Sre having a signal waveform equivalent to that of the logic signal Sa. As shown in FIG. 2, the detection unit 4A includes a transformer 21, a resistor 22, a differential amplifier 23, and a capacitor 24. The transformer 21 includes a primary winding 21a and a secondary winding 21b, and is configured as an insulating transformer for electrically insulating the circuit on the primary winding 21a side from the circuit on the secondary winding 21b side. In addition, the transformer 21 converts the above-mentioned current signal I1 (primary side current signal) flowing through the primary winding 21a into a secondary side current signal I2 at a predetermined transformation ratio (fixed), and supplies it to a current path (also called a secondary side current path) including the secondary winding 21b.

Furthermore, the terminal TP1 of the primary winding 21a is connected to the core wire (and thus the electrode 12a) of the shielded cable constituting the probe PLa via one terminal of the input terminal section 14 as described above, and the terminal TP2 is connected to the core wire (and thus the electrode 12b) of the shielded cable constituting the probe PLb via one terminal of the input terminal section 15 as described above. With this configuration, the signals detected by the electrodes 12a and 12b through the coupling capacitance between the core wires of the coated conductors La and Lb are input to the terminals TP1 and TP2 of the primary winding 21a, and the current signal I1 flows in the above-mentioned primary side current path including the primary winding 21a. The secondary winding 21b is configured with a center tap. This center tap is connected to the second reference potential portion (second ground G2) of the secondary side (secondary winding 21b side of the transformer 21) in the signal generating device 2A. The capacitor 24 is connected between the first ground G1 and the second ground G2, isolating the two grounds G1 and G2 in terms of DC but connecting them in terms of AC.

The resistor 22 is connected between the terminals TP3 and TP4 of the secondary winding 21b. With this configuration, the resistor 22 forms the above-mentioned secondary current path in the secondary winding 21b of the transformer 21, and converts the secondary current signal I2 flowing through this secondary current path into a voltage signal. In this case, since the center tap of the secondary winding 21b is connected to the second ground G2, this voltage signal is separated into a first voltage signal Vc1 (for example, a signal with half the amplitude and the same phase as the above-mentioned voltage signal converted by the resistor 22) generated at the terminal TP3 (output from the terminal TP3) with the second ground G2 as the reference, and a second voltage signal Vc2 (for example, a signal with half the amplitude and the opposite phase to the above-mentioned voltage signal converted by the resistor 22) generated at the terminal TP4 (output from the terminal TP4) with the second ground G2 as the reference, and output to the differential amplifier 23 in the subsequent stage.

As an example, the differential amplifier 23 includes an operational amplifier 23a and four resistors 23b to 23e. Of the resistors 23b and 23c (with the same resistance value) serving as input resistors of the operational amplifier 23a, the resistor 23b has one end connected to the inverting input terminal of the operational amplifier 23a and the other end connected to terminal TP3. The resistor 23c has one end connected to the non-inverting input terminal of the operational amplifier 23a and the other end connected to terminal TP4. The resistor 23d is connected between the output terminal and the inverting input terminal of the operational amplifier 23a. The resistor 23e is set to the same resistance value as the resistor 23d, and has one end connected to the non-inverting input terminal and the other end connected to the second ground G2. With this configuration, the differential amplifier 23 inverts and amplifies the differential voltage (Vc1-Vc2) between the first voltage signal Vc1 generated at the terminal TP3 and the second voltage signal Vc2 generated at the terminal TP4 with a gain obtained by dividing the resistance value of the resistor 23d by the resistance value of the resistor 23b, and outputs the result as the detection signal Sd. Although not shown, the operational amplifier 23a operates, as an example, at the same operating voltages Vcc and Vee (positive and negative voltages such as ±5V) as the operational amplifier 5a (described later) constituting the integrator 5 and the comparator 6a (described later) constituting the signal generator 6.

As described above, the current signal I1 input to the detection unit 4A is a differential signal of the logic signal Sa, and therefore the secondary side current signal I2 generated due to this current signal I1, each voltage signal Vc1, Vc2, their differential voltage (Vc1-Vc2), and the detection signal Sd obtained by amplifying this differential voltage (Vc1-Vc2) are also signals indicating the differential signal of the logic signal Sa (signals having a signal waveform equivalent to the differential waveform of the logic signal Sa).

The integrator 5 is, for example, a known integrator circuit made up of an operational amplifier 5a, a resistor 5b, and a capacitor 5c as shown in FIG. 2. The integrator 5 integrates the detection signal Sd, which indicates the differential signal of the logic signal Sa, to generate and output a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa. In addition, the integrator circuit that can constitute the integrator 5 is not limited to this integrator circuit, and can also be constituted by a known low-pass filter (RC filter) made up of a resistor and a capacitor, as described later.

In this case, the phase of the secondary side current signal I2 relative to the phase of the current signal I1 (i.e., the phase of the logic signal Sa), the phase of each voltage signal Vc1, Vc2 (their differential voltage (Vc1-Vc2)), and the phase of the detection signal Sd change depending on the polarity of the secondary winding 21b relative to the primary winding 21a of the transformer 21, the configuration of the differential amplifier 23 (whether it is inverting amplification or non-inverting amplification), and the configuration of the integrator 5 (whether the integrated signal is output with the same polarity as the integrated signal or with the opposite polarity). Therefore, the phase of the restored signal Sre relative to the phase of the logic signal Sa can also be in phase or opposite, depending on the configurations of the transformer 21, the differential amplifier 23, and the integrator 5 described above. In this example, for ease of understanding, the detection signal Sd is output in the phase state shown in FIG. 3 relative to the phase of the logic signal Sa, and the integrator 5 configured as shown in FIG. 2 integrates this detection signal Sd to generate and output the restored signal Sre in the phase state shown in FIG. 3 (the same phase as the logic signal Sa).

The signal generating unit 6 is, for example, configured with a comparator 6a as shown in FIG. 2, and generates and outputs the code identification signal Sf in a state in which it is in phase with the logic signal Sa as shown in FIG. 3 (a state in which it is a low voltage during a period when the logic signal Sa is at a low voltage, and a high voltage during a period when the logic signal Sa is at a high voltage) by comparing the restored signal Sre with a threshold voltage Vth and binarizing it, as shown in FIG. 3. In addition, as for the restored signal Sre, since the voltage level on the low voltage side is more stable than the voltage level on the high voltage side as shown in FIG. 3, the threshold voltage Vth is set to a voltage slightly higher than the voltage level on the low voltage side.

The signal conversion device 3 converts the code identification signal Sf output from the signal generation device 2A into a transmission signal So that complies with the communication protocol of the various CAN communication-compatible devices connected to the signal reading system 1A (i.e., the same communication protocol as the logic signal Sa of the communication path SB. In this example, the communication protocol of the CAN bus SB), and outputs (transmits) the signal to the various CAN communication-compatible devices. For example, the signal conversion device 3 can be composed of various CAN transceivers.

Next, an example of using the signal reading system 1A and the operation of the signal reading system 1A at that time will be described with reference to the drawings.

First, as shown in Figures 1 and 2, the electrodes 11a and 11b are attached to the corresponding coated conductor wires La and Lb so that the electrodes 12a and 12b come into contact (abut) with the coated portions of the coated conductor wires La and Lb in the CAN bus SB, and the CAN communication-compatible device that is to output the transmission signal So is connected to the signal conversion device 3.

In this case, the signal reading system 1A of this example can read the logic signal Sa from the CAN bus SB simply by attaching the electrodes 11a, 11b without processing the coated conductors La, Lb themselves (stripping off the insulating coating), so it can be used even when a diagnostic connector is not provided on the CAN bus SB. Even if a diagnostic connector is provided, the connection location to the CAN bus SB (the respective mounting locations of the electrodes 11a, 11b) is not limited to the location of the diagnostic connector, and it is possible to connect (attach the electrodes 11a, 11b) to any location in the longitudinal direction of the coated conductors La, Lb.

In this state, in the signal generating device 2A, a current signal I1 having a signal waveform obtained by differentiating the signal waveform of the logic signal Sa defined by the difference (Va-Vb) between the voltages Va and Vb of the coated conductor wires La and Lb flows through the primary current path including the primary winding 21a of the transformer 21 constituting the detection unit 4A. The detection unit 4A converts this current signal I1 into a detection signal Sd, which is a signal indicating the differentiated signal of the logic signal Sa (a signal having a signal waveform equivalent to the differentiated waveform of the logic signal Sa), and outputs it.

The integrator 5 integrates the detection signal Sd to generate and output a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa. The signal generator 6 compares the restored signal Sre with a threshold voltage Vth to digitize it, thereby generating and outputting a code identification signal Sf.

Next, the signal conversion device 3 converts this code identification signal Sf into a transmission signal So and outputs (transmits) it to the connected CAN communication-compatible device.

In this manner, in the signal generating device 2A and the signal reading system 1A, in a configuration in which the coated conductor wires La, Lb are connected via non-contact metal probes PLa, PLb (connected by capacitive coupling), the detection unit 4A detects a current signal I1 (current signal I1, which is a differentiated signal of logic signal Sa) having a signal waveform obtained by differentiating the signal waveform of logic signal Sa transmitted to the CAN bus SB consisting of the coated conductor wires La, Lb, and converts this current signal I1 into a detection signal Sd, which is a differentiated signal of logic signal Sa, and outputs it. The integrating unit 5 integrates the detection signal Sd to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa.

In a configuration such as the signal generating device 2A and the signal reading system 1A that detects a signal (hereinafter, for the sake of explanation, also referred to as a differentiated signal. In this example, the current signal I1) having a signal waveform obtained by differentiating the signal waveform of the logic signal Sa, as shown in FIG. 3, the signal waveform of the logic signal Sa has a situation in which the voltage of the logic signal Sa rises or falls in a pulse-like or step-like manner due to collision of signals at a timing other than the timing of switching of the code Cs (the timing of switching from code "1" to code "0" and from code "0" to code "1". In the following, for the sake of distinction, this timing is also referred to as a specific timing). In this case, as shown in FIG. 3, a spike-like signal is generated at this timing (a timing other than the specific timing) in the current signal I1 obtained by differentiating the signal waveform of the logic signal Sa, and in the detection signal Sd, which is a signal obtained by converting the current signal I1 into a voltage signal. The peak value of this spike-like signal is large when the amount of change in the voltage of the logic signal Sa per unit time is large, even when the amount of change is small.

For this reason, in a configuration in which a signal (differential signal Sd) equivalent to this detection signal Sd is directly compared with thresholds (positive threshold Vr1 and negative threshold Vr2) to generate a code identification signal Sf, as in the signal generation device proposed by the applicant of the present application described in the background art (the signal generation device described with reference to the above Patent Document 2), the above-mentioned problem of generating an incorrect code identification signal occurs. In contrast, according to the signal generation device 2A and the signal reading system 1A, the integrating unit 5 integrates the detection signal Sd to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa, and outputs the restored signal Sre to the signal generation unit 6. Therefore, even when a pulse-like or step-like voltage change occurs in the signal waveform of the logic signal Sa, the restored signal Sre can be correctly binarized by the signal generation unit 6 with one threshold voltage Vth without being affected by the voltage change, and a correct code identification signal Sf can be generated.

The configuration of the detector 4A is not limited to the above configuration, and various configurations can be adopted. For example, although not shown, a configuration can be adopted in which a transformer having a secondary winding without a center tap is used instead of the above transformer 21 (a transformer having a center tap on the secondary winding 21b), and a non-differential amplifier is used instead of the differential amplifier 23, as disclosed in FIG. 4 of the above Patent Document 2.

In addition, in the above-mentioned detection unit 4A, one terminal TP1 of the primary winding 21a of the transformer 21 is connected to the electrode 12a that is capacitively coupled to the coated conductor La via the probe PLa, and the other terminal TP2 of the primary winding 21a is connected to the electrode 12b that is capacitively coupled to the coated conductor Lb via the probe PLb, thereby forming a primary side current path (a current path formed by connecting capacitive components (coupling capacitance) in series) from the coated conductor La to the coated conductor Lb via the primary winding 21a, and a configuration is adopted in which a current signal I1 having a signal waveform obtained by differentiating the signal waveform of the logic signal Sa is detected, but the configuration for detecting a signal having a signal waveform obtained by differentiating the signal waveform of the logic signal Sa is not limited to this configuration.

For example, as shown in FIG. 5 of the above-mentioned Patent Document 2, the core of the shielded cable constituting the probe PLa is connected to the first ground G1 via a resistor on the primary side (the primary winding side of the transformer) of the signal generating device, and the core of the shielded cable constituting the probe PLb is connected to the first ground G1 via another resistor (same resistance value as the first resistor). This forms two current paths: one current path (hereinafter, for the sake of explanation, also referred to as the first current path) from the coated conductor La to the first ground G1 via the coupling capacitance, the core of the shielded cable constituting the probe PLa, and the one resistor; and another current path (hereinafter, for the sake of explanation, also referred to as the second current path) from the coated conductor Lb to the first ground G1 via the coupling capacitance, the core of the shielded cable constituting the probe PLb, and another resistor.

In the detection unit having this configuration, a current signal (hereinafter, for the sake of explanation, also referred to as the first current signal) having a signal waveform obtained by differentiating the signal waveform of the voltage Va of the coated conductor La flows through the first current path, and one resistor converts this first current signal into a voltage signal (hereinafter, for the sake of explanation, also referred to as the first voltage signal) and outputs it. In addition, a current signal (hereinafter, for the sake of explanation, also referred to as the second current signal) having a signal waveform obtained by differentiating the signal waveform of the voltage Vb of the coated conductor Lb flows through the second current path, and another resistor converts this second current signal into a voltage signal (hereinafter, for the sake of explanation, also referred to as the second voltage signal) and outputs it. In addition, in this detection unit, a differential amplifier (differential amplifier including a transformer) having an extremely high input impedance inputs the first voltage signal and the second voltage signal and amplifies the difference voltage between them to generate a detection signal Sd.

Therefore, the signal generating device and signal reading system using the detection unit 4A configured to detect a current signal having a signal waveform obtained by individually differentiating the signal waveforms of the voltages Va and Vb of the coated conductors La and Lb can also achieve the same effects as the signal generating device 2A and signal reading system 1A described above.

Although the detection unit has been described as having a configuration including a transformer (isolation transformer), it is also possible to employ a detection unit 4B that does not use a transformer, as in the signal generating device 2B shown in FIG. 4. The signal generating device 2B will be described below. Note that the same components as those in the signal generating device 2A are given the same reference numerals, and duplicated descriptions will be omitted.

As an example, as shown in FIG. 4, this signal generating device 2B includes a detection unit 4B, an integration unit 5, and a signal generating unit 6, and is connected to a pair of coated conductor wires La, Lb via a pair of probes PLa, PLb to generate and output a code identification signal Sf.

The detection unit 4B, together with the integrator 5, constitutes the signal restoration unit 8. In this case, the signal restoration unit 8 generates a restoration signal Sre having a signal waveform equivalent to the signal waveform of the logic signal Sa by integrating a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductors La and Lb. The detection unit 4B includes two resistors 25 and 26 and a differential amplifier 23. The resistor 25 as the first resistive element has one end connected to the electrode 12a via the input terminal unit 14 and the core wire of the shielded cable constituting the probe PLa, and the other end connected to the first ground G1 (in this example, since there is no distinction between the first ground G1 and the second ground G2, hereinafter, also referred to as ground G). The resistor 26 as the second resistive element has a resistance value defined to be the same as that of the resistor 25, and one end connected to the electrode 12b via the input terminal unit 15 and the core wire of the shielded cable constituting the probe PLb, and the other end connected to ground G. With this configuration, two current paths are formed in the detection unit 4B: a first current path that runs from the coated conductor wire La to ground G via the coupling capacitance, electrode 12a, the core wire of the shielded cable that constitutes the probe PLa, and resistor 25; and a second current path that runs from the coated conductor wire Lb to ground G via the coupling capacitance, electrode 12b, the core wire of the shielded cable that constitutes the probe PLb, and resistor 26.

In addition, a first current signal I1a having a signal waveform obtained by differentiating the signal waveform of the voltage Va of the coated conductor wire La flows through the first current path, and a resistor 25 converts this first current signal I1a into a first voltage signal Vc1 and outputs it. In addition, a second current signal I1b having a signal waveform obtained by differentiating the signal waveform of the voltage Vb of the coated conductor wire Lb flows through the second current path, and a resistor 26 converts this second current signal I1b into a second voltage signal Vc2 and outputs it. Since the voltage Va of the coated conductor wire La and the voltage Vb of the coated conductor wire Lb are voltage signals whose phases are inverted, the first voltage signal Vc1 and the second voltage signal Vc2 are also voltage signals whose phases are inverted.

In addition to the configuration of the detection unit 4A of the signal generating device 2A (configuration of FIG. 2), the differential amplifier 23 includes two operational amplifiers 23f, 23g and three resistors 23h, 23i, and 23j. In this case, the non-inverting input terminal of the operational amplifier 23f is connected to one end of the resistor 25, the resistor 23h is connected between the output terminal and the inverting input terminal, and the output terminal is connected to the resistor 23b. In addition, the non-inverting input terminal of the operational amplifier 23g is connected to one end of the resistor 26, the resistor 23i (having the same resistance value as the resistor 23h) is connected between the output terminal and the inverting input terminal, and the output terminal is connected to the resistor 23c. The inverting input terminals of the operational amplifiers 23f and 23g are connected to each other via one resistor 23j. The differential amplifier 23 in this example is configured as an instrumentation amplifier with the above configuration, inputs the first voltage signal Vc1 and the second voltage signal Vc2 with high input impedance, and amplifies the difference (Vc1-Vc2) to output it as the detection signal Sd (a signal with a waveform equivalent to the differentiated waveform of the logic signal Sa).

Therefore, in the signal generating device 2B equipped with a detection unit 4B having such a configuration without a transformer, and in the signal reading system 1A equipped with this signal generating device 2B, similar to the above-mentioned signal generating device 2A and the signal reading system 1A equipped with this signal generating device 2A, the integrating unit 5 integrates the detection signal Sd to generate a restored signal Sre having a signal waveform equivalent to the signal waveform of the logic signal Sa, and outputs the restored signal Sre to the signal generating unit 6, so that it is possible to achieve the same effect as the above-mentioned signal generating device 2A and the signal reading system 1A equipped with this signal generating device 2A.

In the above-mentioned detection unit 4B, the differential amplifier 23 is configured as an instrumentation amplifier, but this is not limited to this configuration. For example, instead of the configuration in which the inverting input terminals of the operational amplifiers 23f and 23g are directly connected to each other via one resistor 23j (the configuration in FIG. 4), a configuration in which each inverting input terminal of the operational amplifiers 23f and 23g is connected to ground G via individual resistors 23k and 23m, as shown in FIG. 5, can be adopted. Furthermore, although not shown, a configuration in which a capacitor is individually connected in series to each resistor 23k and 23m and each inverting input terminal of the operational amplifiers 23f and 23g is connected to ground G via an RC series circuit can be adopted. Even when these configurations are adopted, the same effects as those of the signal generating device 2B equipped with the detection unit 4B configured as shown in FIG. 4 and the signal reading system 1A equipped with this signal generating device 2B can be achieved.

We have described each of the signal generating devices 2A and 2B that read the two-wire differential voltage logic signal Sa transmitted to the CAN bus SB consisting of two coated conductors La and Lb, and the signal reading system 1A that includes any of these devices. However, the signal generating device that reads the logic signal transmitted through a communication path consisting of one coated conductor and generates the code identification signal Sf, and the signal reading system that includes this signal generating device can also adopt a configuration in which the device is connected to one coated conductor via a metal non-contact probe (a configuration in which the device is connected by capacitive coupling), the detection unit detects a signal having a signal waveform obtained by differentiating the signal waveform of the logic signal transmitted to the coated conductor, and the integration unit integrates this signal (or an amplified signal of this signal) to generate a restored signal having a signal waveform equivalent to the signal waveform of the logic signal. Below, the signal generating device and the signal reading system will be described with reference to Figures 6, 7, and 8. Note that the same components as any one of the signal generating devices 2A and 2B described above, and the signal reading system 1A including this device, are designated by the same reference numerals, and redundant explanations will be omitted.

As shown in FIG. 6, signal reading system 1B, which is an example of a "signal reading system," has one of signal generating devices 2C and 2D, which are examples of "signal generating devices," and is configured to detect a single-wire voltage drive type (single-wire type) logic signal (logic signal Sa defined by the voltage Vw transmitted to the coated conductor wire Lw) transmitted through a communication path SB consisting of a single coated conductor wire Lw, generate (read) a code identification signal Sf capable of identifying a code Cs corresponding to the logic signal Sa, convert this code identification signal Sf into a transmission signal So that complies with the same communication protocol as the logic signal Sa of the communication path SB, and output (transmit) it to various CAN communication-compatible devices. The signal generating devices 2C and 2D can handle various "single-wire voltage-driven logic signals" that comply with various communication protocols such as the "CAN protocol," "CAN FD," and "FlexRay (registered trademark)," as well as various "single-wire voltage-driven logic signals" that comply with various communication protocols that enable small-amplitude, low-power consumption communication using "LVDS."

First, as shown in FIG. 6, a signal reading system 1B including a signal generating device 2C and a signal converting device 3 will be described. Note that the same components as those in the signal reading system 1A are designated by the same reference numerals and will not be described again.

As an example, as shown in FIG. 7, the signal generating device 2C includes a detection unit 4C, an integration unit 5, and a signal generating unit 6, and is connected to the coated conductor wire Lw via one probe PL to generate and output a code identification signal Sf. Since the probe PL has the same configuration as the probes PLa and PLb described above, the same components as those of the probe PLa are assigned the same reference numerals and redundant explanations are omitted, assuming that the probe PL is the same as the probe PLa.

The detection unit 4C, in combination with the integration unit 5, constitutes the signal restoration unit 8. In this case, the signal restoration unit 8 integrates a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductor wire Lw to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa. The detection unit 4C includes a transformer 31, a resistor 32 as a resistive element, a non-differential amplifier 33 as an amplifier, and a capacitor 34.

The transformer 31 is configured as an insulating transformer having a primary winding 31a and a secondary winding 31b to electrically insulate the circuit on the primary winding 31a side from the circuit on the secondary winding 31b side. Specifically, one terminal TP1 of the primary winding 31a is connected to the core wire (and thus the electrode 12a) of the shielded cable constituting the probe PLa via one terminal of the input terminal section 14, and the other terminal TP2 of the primary winding 31a is connected to the first reference potential portion (first ground G1) on the primary side (the primary winding 31a side of the transformer 31) of the signal generating device 2C. The other terminal of the input terminal section 14 is also connected to the first ground G1. This configuration forms a single current path (primary side current path) that runs from the core of the coated conductor Lw through the coupling capacitance between this core and the electrode 12a, the electrode 12a, the core of the shielded cable that constitutes the probe PLa, one terminal of the input terminal section 14, and the primary winding 31a to the first ground G1.

Furthermore, one terminal TP3 of the secondary winding 31b is connected to one end of the resistor 32, and the other terminal TP4 of the secondary winding 31b is connected to the second reference potential portion (second ground G2) of the secondary side (secondary winding 31b side of the transformer 31) of the signal generating device 2C. The other end of the resistor 32 is connected to the second ground G2. With this configuration, another current path (secondary side current path) is formed from the secondary winding 31b through one terminal TP3 of the secondary winding 31b and the resistor 32 to the other terminal TP4 (second ground G2) of the secondary winding 31b. The capacitor 34 is connected between the first ground G1 and the second ground G2, and separates the two grounds G1 and G2 in terms of DC while connecting them in terms of AC.

In addition, a current signal I1 having a signal waveform obtained by differentiating the signal waveform of the voltage Vw of the coated conductor Lw flows in the phase state shown in FIG. 3 in the primary current path including the primary winding 31a. The transformer 31 converts this current signal I1 (primary current signal) flowing in the primary winding 31a into a secondary current signal I2 at a predefined current transformation ratio (fixed) and supplies it to the secondary current path formed by the secondary winding 31b and resistor 32. The resistor 32 converts this secondary current signal I2 into a voltage signal Vc1 and outputs it. In addition, as an example, the polarity of the secondary winding 31b with respect to the primary winding 31a is specified so that the voltage signal Vc1 is output in the same phase state as the current signal I1 shown in FIG. 3.

The non-differential amplifier 33 includes, as an example, a non-inverting amplifier circuit composed of one operational amplifier 33a and two resistors 33b and 33c, and an inverting amplifier circuit 33d that inverts the output signal of the non-inverting amplifier circuit and outputs it as a detection signal Sd. In this case, in the non-inverting amplifier circuit, the non-inverting input terminal of the operational amplifier 33a is connected to one end of the resistor 32, the resistor 33b is connected between the output terminal and the inverting input terminal of the operational amplifier 33a, and the inverting input terminal of the operational amplifier 33a is connected to the second ground G2 via the resistor 33c. With the above configuration, the non-differential amplifier 33 in this example is configured as an inverting amplifier as a whole, and inputs the voltage signal Vc1 with high impedance, inverts the phase and amplifies it, and outputs it as the detection signal Sd (a signal with a signal waveform equivalent to the differential waveform of the voltage Vw (the differential waveform of the logic signal Sa)) in the phase state shown in FIG. 3. Note that the non-differential amplifier 33 can also be configured as an inverting amplifier by omitting the inverting amplifier circuit 33d, for example.

Therefore, in this signal generating device 2C and in the signal reading system 1B including this signal generating device 2C, the integrating unit 5 integrates the detection signal Sd to generate a restored signal Sre having a signal waveform equivalent to the signal waveform of the voltage Vw (the signal waveform of the logic signal Sa) and outputs the restored signal Sre to the signal generating unit 6, so that the same effect as the above-mentioned signal generating device 2B and the signal reading system 1A including this signal generating device 2B can be achieved.

Next, as shown in FIG. 6, a signal reading system 1B including a signal generating device 2D and a signal converting device 3 will be described. Note that the same components as those of the signal generating device 2C and the signal reading system 1B including the signal generating device 2C will be assigned the same reference numerals and redundant description will be omitted.

As an example, as shown in FIG. 8, the signal generating device 2D includes a detection unit 4D, an integration unit 5, and a signal generating unit 6, and is connected to the coated conductor wire Lw via one probe PL to generate and output a code identification signal Sf. Since the probe PL has the same configuration as the probes PLa and PLb described above, it is assumed to be the same as the probe PLa as an example, and the same components as the probe PLa are given the same reference numerals and redundant explanations are omitted. In addition, some components of the detection unit 4D are the same as those of the detection unit 4C, and therefore the same components are given the same reference numerals and redundant explanations are omitted.

The detection unit 4D, together with the integrator 5, constitutes the signal restoration unit 8. In this case, the signal restoration unit 8 integrates a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductor Lw to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa. The detection unit 4D includes a resistor 32 and a non-differential amplifier 33 as an amplifier. In this detection unit 4D, one end of the resistor 32 is connected to the core wire of the shielded cable constituting the probe PLa via one terminal of the input terminal unit 14, and the other end is connected to ground G. In addition, one end of the resistor 32 is connected to the non-inverting input terminal of the operational amplifier 33a constituting the non-differential amplifier unit 33. In addition, the other terminal of the input terminal unit 14 is also connected to ground G.

In addition, in this detection unit 4D, one current path is formed from the coated conductor wire Lw through the coupling capacitance, the electrode 12a, the core wire of the shielded cable constituting the probe PL, and the resistor 32 to the ground G. In this current path, a current signal I1 having a signal waveform obtained by differentiating the signal waveform of the voltage Vw of the coated conductor wire Lw flows in the phase state shown in FIG. 3, and the resistor 32 converts this current signal I1 into a voltage signal Vc1 and outputs it.

The non-differential amplifier 33, for example, is configured in the same manner as the non-differential amplifier 33 of the detection unit 4C described above, and includes a non-inverting amplifier circuit composed of one operational amplifier 33a and two resistors 33b and 33c, and an inverting amplifier circuit 33d. The first voltage signal Vc1 is input at high impedance, and the first voltage signal Vc1 is inverted and amplified, and output as a detection signal Sd (a signal having a waveform equivalent to the differentiated waveform of the logic signal Sa) in the phase state shown in FIG. 3. The non-differential amplifier 33 can also be configured as an inverting amplifier, for example, by omitting the inverting amplifier circuit 33d.

Therefore, in this signal generating device 2D and in the signal reading system 1B equipped with this signal generating device 2D, the integrating unit 5 integrates the detection signal Sd to generate a restored signal Sre having a signal waveform equivalent to the signal waveform of the voltage Vw (the signal waveform of the logic signal Sa) and outputs the restored signal Sre to the signal generating unit 6, so that the same effect as the above-mentioned signal generating device 2B and the signal reading system 1A equipped with this signal generating device 2B can be achieved.

In addition, in each of the signal reading systems 1A and 1B, the above-mentioned probes PLa and PLb, which have electrode portions 11a and 11b that are capacitively coupled with the metal portions (core wires) of the coated conductor wires La and Lb and function as voltage detection probes, are connected to the signal generating devices 2A, 2B, 2C, and 2D, but the present invention is not limited to this configuration.

For example, instead of the probes PLa and PLb, as shown in FIG. 9, a first current detection probe PLc and a second current detection probe PLd (hereinafter also referred to as current detection probes PLc and PLd. A clamp-type current detection probe that can be attached to the coated conductor wires La and Lb without cutting the coated conductor wires La and Lb is preferable) can be connected to the signal generating device 2A (2B), or as shown in FIG. 10, one of the current detection probes PLc and PLd (current detection probe PLc is used as an example in FIG. 10) can be connected to the signal generating device 2C (2D) to generate the code identification signal Sf. Note that the signal generating devices 2A (2B, 2C, and 2D) have already been described, so their description will be omitted.

As an example, the current detection probes PLc, PLd are identically configured, and include a current sensor unit having a magnetic core 61 that is configured to be separable and into which a corresponding one of the coated conductors La, Lb can be inserted (capable of clamping the coated conductor), and a coil 62 formed by winding a wire around the magnetic core 61. The current detection probes PLc and PLd detect the current flowing through the corresponding coated conductor wire (the current Ia flowing through the coated conductor wire La and the coated conductor wire Lw, and the current Ib flowing through the coated conductor wire Lb) when the corresponding coated conductor wire (the coated conductor wire La in the current detection probe PLc and the coated conductor wire Lb in the current detection probe PLd) is clamped by each current sensor unit, and output a current signal Ii (current signal Iia for voltages Va and Vw, and current signal Iib for voltage Vb) having a signal waveform equivalent to the differential waveform of the signal transmitted to the corresponding coated conductor wire to the signal generating device 2A (2B, 2C, 2D) via a shielded cable (coaxial cable, as an example).

In these current detection probes PLc, PLd, each magnetic core 61 is attached by partially untwisting the coated conductors La, Lb that make up the CAN bus SB (the coated conductors La, Lb are twisted together under normal conditions), and clamping them to the untwisted coated conductors La, Lb. However, since the range that can be unwound is narrow, it is necessary to use a core material for the magnetic core 61 that has a small cross section (cross section in a plane perpendicular to the circumferential direction) and therefore a small outer diameter. This also requires that the number of turns in the coil 62 be reduced.

Therefore, in the signal generating device 2A using the current detection probes PLc and PLd of this configuration, although not shown, the current signals Iia and Iib from the current detection probes PLc and PLd are input to the terminals TP1 and TP2 of the primary winding 21a, so that a current signal having a signal waveform equivalent to the above-mentioned current signal I1 (a signal waveform obtained by differentiating the signal waveform of the logic signal Sa) flows in the above-mentioned primary current path including the primary winding 21a. Also, in the signal generating device 2C using the current detection probe PLc, although not shown, the current signal Iia from the current detection probe PLc is input to the terminal TP1 of the primary winding 21a, so that a current signal having a signal waveform equivalent to the above-mentioned current signal I1 (a signal waveform obtained by differentiating the signal waveform of the logic signal Sa) flows in the above-mentioned primary current path including the primary winding 21a.

In addition, in the signal generating device 2B using the current detection probes PLc and PLd, although not shown, the current signal Iia (signal waveform equivalent to the first current signal I1a described above) from the current detection probe PLc flows in a first current path including resistor 25 (i.e., the current path on the current detection probe PLc side), and the current signal Iib (signal waveform equivalent to the second current signal I1b described above) from the current detection probe PLd flows in a second current path including resistor 26 (i.e., the current path on the current detection probe PLd side). In addition, in the signal generating device 2D using the current detection probe PLc, although not shown, the current signal Iia (signal waveform equivalent to the current signal I1 described above) from the current detection probe PLc flows in a current path including resistor 32.

As a result, in the signal generating device 2A (2B, 2C, 2D), even in a configuration in which the current detection probes PLc, PLd are connected, the detection unit 4A (4B, 4C, 4D) outputs the above-mentioned detection signal Sd, the integration unit 5 integrates this detection signal Sd, and generates and outputs a restored signal Sre having a signal waveform equivalent to the signal waveform of the logic signal Sa, and the signal generating unit 6 compares this restored signal Sre with the threshold voltage Vth to digitize it, thereby generating and outputting the code identification signal Sf (see Figure 3).

As described above, the signal generating unit 6 employs a configuration in which the restored signal Sre is binarized to generate the code identification signal Sf at a threshold voltage Vth defined based on the more stable voltage level of the low-voltage side and high-voltage side voltage levels of the restored signal Sre (in the above example, the low-voltage side voltage level). However, noise of a lower frequency than the frequency of the logic signal Sa (for example, noise of a frequency equivalent to the commercial frequency) may be superimposed on the restored signal Sre. In this case, the voltage level that was considered stable also fluctuates due to the influence of this noise, and the signal generating unit 6 may not be able to accurately binarize the restored signal Sre based on a constant threshold voltage Vth.

Even in such a case, in order for the signal generating unit 6 to accurately digitize the restored signal Sre based on a constant threshold voltage Vth, it is possible to adopt a configuration in which various waveform shaping units (hereinafter referred to as waveform shaping units 7) disclosed by the applicant in the above-mentioned Patent Document 2 are disposed (interposed) between the integrating unit 5 and the signal generating unit 6 as shown in FIG. 11. This configuration can be adopted in any of the above-mentioned signal generating devices 2A, 2B, 2C, and 2D.

The following is a specific explanation of an example that uses the waveform shaping unit with the simplest configuration among those disclosed in the above-mentioned Patent Document 2 (a waveform shaping unit composed of a capacitor, a resistor, and a diode).

First, in a configuration in which the threshold voltage Vth in the signal generating unit 6 is defined based on the voltage level of the low-voltage side of the restored signal Sre, it is necessary to make the voltage level of the low-voltage side of the restored signal Sre constant (stabilize it at a predetermined constant voltage (hereinafter also referred to as the target constant voltage Vtg)). In this case, as shown in FIG. 12, the waveform shaping unit 7 is configured to include a capacitor 7c connected between an input terminal 7a to which the restored signal Sre is input and an output terminal 7b to which the stabilized new restored signal Sre1 is output, a resistor 7d having one end connected to the output terminal 7b and the other end to which the target constant voltage Vtg is applied, and a diode 7e having a cathode terminal connected to the output terminal 7b and an anode terminal to which the target constant voltage Vtg is applied. If the forward voltage drop of the diode 7e can be ignored, the waveform shaping unit 7 with this configuration maintains the amplitude (peak-to-peak voltage) of the input restoration signal Sre, adjusts the voltage level on the low voltage side (the voltage during the low voltage period) to the target constant voltage Vtg (i.e., shapes it into a single-ended signal), and outputs it as the restoration signal Sre1.

Therefore, in the signal generating section 6 downstream of the waveform shaping section 7, by defining a voltage slightly higher than the target constant voltage Vtg as the threshold voltage Vth, it is possible to reliably binarize the restored signal Sre at the threshold voltage Vth to generate the code identification signal Sf even when the voltage level on the low voltage side of the restored signal Sre is fluctuating.

Next, for example, a case will be described in which the restored signal Sre is output in the signal generating devices 2A, 2B, 2C, and 2D with a phase inverted from the phase state shown in FIG. 3. In this case, the threshold voltage Vth in the signal generating unit 6 is defined based on the voltage level of the high voltage side of the restored signal Sre. In this configuration, it is necessary to keep the voltage level of the high voltage side of the restored signal Sre constant (stabilize it at the target constant voltage Vtg). In this case, as shown in FIG. 13, the waveform shaping unit 7 has the same configuration as shown in FIG. 12 for the capacitor 7c and resistor 7d. On the other hand, the diode 7e is configured differently from the configuration shown in FIG. 12, with the anode terminal connected to the output terminal 7b and the target constant voltage Vtg applied to the cathode terminal. The waveform shaping unit 7 with this configuration maintains the amplitude of the input restored signal Sre, adjusts the voltage level of the high voltage side to the target constant voltage Vtg, and outputs it as the restored signal Sre1.

Therefore, in the signal generating section 6 downstream of the waveform shaping section 7, by defining a voltage slightly lower than the target constant voltage Vtg as the threshold voltage Vth, it is possible to reliably binarize the restored signal Sre at the threshold voltage Vth and generate the code identification signal Sf even when the voltage level on the high voltage side of the restored signal Sre is fluctuating.

As described above, the waveform shaping unit 7 has the function of aligning the voltage level of the desired voltage side of the low-voltage side and high-voltage side of the restored signal Sre (the potential of the voltage side compared with the threshold voltage Vth in the signal generating unit 6) to a constant target constant voltage Vtg, in other words, the function of fixing it to the target constant voltage Vtg, so it can also be called a "reference potential fixing circuit." Furthermore, according to the signal generating devices 2A, 2B, 2C, 2D and the signal reading systems 1A, 1B, 1C, 1D equipped with this waveform shaping unit 7, the restored signal Sre can be reliably binarized at the threshold voltage Vth in the signal generating unit 6 as described above to generate the code identification signal Sf.

The configuration of the signal restoration unit 8 is not limited to the above configuration, and various configurations can be adopted. For example, in the above signal generating devices 2A to 2D, an example in which the integrating unit 5 is arranged after the detecting units 4A to 4D has been described, but the arrangement position of the integrating unit 5 is not limited to this. For example, in the signal generating devices 2A and 2B, the integrating unit 5 can be arranged at any position between the electrode unit 11a (or the current detection probe PLc (coil 62)) and the signal generating unit 6, and at any position between the electrode unit 11b (or the current detection probe PLd (coil 62)) and the signal generating unit 6. In addition, in the signal generating devices 2C and 2D, the integrating unit 5 can be arranged at any position between the electrode unit 11a (or the current detection probe PLc (coil 62)) and the signal generating unit 6. In addition, as for the configuration of the integrating unit 5, as described above, it can be configured with a known low-pass filter (RC filter) composed of a resistor and a capacitor. In the following description, the same reference numerals are used for the same configuration as the signal generating devices 2A and 2B, and duplicated explanations are omitted. Additionally, duplicate explanations of operations that are the same as those of signal generating devices 2C and 2D will be omitted.

Specifically, for example, in the signal generating device 2A, as shown in FIG. 14, a low-pass filter type integrating section 5A1 composed of a resistor RI1 and a capacitor CI1 is arranged between the terminal TP3 of the secondary winding 21b of the transformer 21 and the other end of the resistor 23b, and a low-pass filter type integrating section 5A2 (hereinafter, when the integrating sections 5A1 and 5A2 are not distinguished from each other, they are also referred to as "integrating section 5A") composed of a resistor RI2 and a capacitor CI2 and having the same configuration as the integrating section 5A1 is arranged between the terminal TP4 of the secondary winding 21b of the transformer 21 and the other end of the resistor 23c. Even in this configuration, the signal restoring section 8 integrates a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductors La and Lb to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa, and outputs the restored signal Sre to the signal generating section 6. Specifically, in the signal restoration unit 8, the integrator 5A1 integrates the first voltage signal Vc1 generated at the terminal TP3 with respect to the second ground G2 as a reference to output an integrated signal, and the integrator 5A2 integrates the second voltage signal Vc2 generated at the terminal TP4 with respect to the second ground G2 as a reference to output an integrated signal, and the differential amplifier 23 inverts and amplifies the difference voltage between the integrated signal output from the integrator 5A1 and the integrated signal output from the integrator 5A2 with a gain obtained by dividing the resistance value of resistor 23d by the resistance value of resistor 23b, to generate the restoration signal Sre shown in FIG. 3 and output it to the signal generator 6.

In addition, with respect to the signal generating device 2A, it is also possible to adopt a configuration in which the integrating units 5A1 and 5A2 are not provided, that is, in a configuration in which the terminal TP3 of the secondary winding 21b of the transformer 21 is connected to the other end of the resistor 23b and the terminal TP4 of the secondary winding 21b is connected to the other end of the resistor 23c, and capacitors CI3 and CI4 having the same capacitance are connected in parallel to the resistors 23d and 23e, respectively, as shown by the dashed lines in the figure. In the signal restoration unit 8 of this configuration, the differential amplifier 23 inverts and amplifies the differential voltage between the first voltage signal Vc1 and the second voltage signal Vc2 with a gain obtained by dividing the resistance value of the resistor 23d by the resistance value of the resistor 23b, and integrates it to generate the restoration signal Sre shown in FIG. 3 and output it to the signal generating unit 6. Also, although not shown, a configuration can be adopted in which the integrator 5 (or integrator 5A) is disposed between the electrode 11a (or current detection probe PLc (coil 62)) and terminal TP1 of the primary winding 21a in the transformer 21, and between the electrode 11b (or current detection probe PLd (coil 62)) and terminal TP2 of the primary winding 21a.

Also, as shown in FIG. 15, for the signal generating device 2B, an integrator 5 (or integrator 5A) can be arranged between one end of resistor 25 and the non-inverting input terminal of operational amplifier 23f, and between one end of resistor 26 and the non-inverting input terminal of operational amplifier 23g. Although not shown, an integrator 5 (or integrator 5A) can be arranged between the output terminal of operational amplifier 23f and the other end of resistor 23b, and between the output terminal of operational amplifier 23g and the other end of resistor 23c, without arranging integrator 5 (or integrator 5A) at these positions. Furthermore, although not shown, an integrator 5 (or integrator 5A) can be arranged in parallel with resistors 23d and 23e, without arranging integrator 5 (or integrator 5A) at these positions. Also, although not shown, a configuration can be adopted in which an integrator 5 (or integrator 5A) is disposed between the electrode 11a (or current detection probe PLc (coil 62)) and one end of the resistor 25, and between the electrode 11b (or current detection probe PLd (coil 62)) and one end of the resistor 26. In the signal restoration unit 8 of such a configuration, the signal restoration unit 8 generates the restoration signal Sre shown in FIG. 3 and outputs it to the signal generation unit 6 in the same manner as the signal restoration unit 8 of the signal generation device 2A described above.

Similarly, the signal generating device 2C may be configured to have an integrating unit 5 (or integrating unit 5A) between the terminal TP3 of the secondary winding 21b of the transformer 21 and the non-inverting input terminal of the operational amplifier 33a, a capacitor CI3 connected in parallel to the resistor 33b, or an integrating unit 5 (or integrating unit 5A) between the electrode unit 11a (or the current detection probe PLc (coil 62)) and the terminal TP1 of the primary winding 21a of the transformer 21. In these configurations, the signal restoration unit 8 also integrates a signal waveform equivalent to the differential waveform of the logic signal Sa detected from the coated conductor wire Lw to generate a restored signal Sre having a signal waveform equivalent to that of the logic signal Sa, and outputs the signal to the signal generating unit 6.

Also, with respect to the signal generating device 2D, a configuration in which the integrating unit 5 (or the integrating unit 5A) is disposed between one end of the resistor 32 and the non-inverting input terminal of the operational amplifier 33a, a configuration in which the capacitor CI3 is connected in parallel to the resistor 33b, and a configuration in which the integrating unit 5 (or the integrating unit 5A) is disposed between the electrode unit 11a (or the current detection probe PLc (coil 62)) and one end of the resistor 32 can be adopted. Even in these configurations, the signal restoration unit 8 integrates a signal waveform equivalent to the differential waveform of the logic signal Sa detected from the coated conductor wire Lw, thereby generating a restored signal Sre having a signal waveform equivalent to the signal waveform of the logic signal Sa, and outputs the restored signal Sre to the signal generating unit 6.

According to the signal generating devices 2A, 2B, 2C, 2D having the above-mentioned integrating units 5, 5A, and the signal reading systems 1A, 1B having these signal generating devices 2A, 2B, 2C, 2D, the signal restoration unit 8 is configured to generate a restored signal Sre having a signal waveform equivalent to the signal waveform of the logic signal Sa by integrating a signal waveform corresponding to the differential waveform of the logic signal Sa detected from the coated conductor wires La, Lb (or coated conductor wire Lw). Therefore, even when a pulse-like or step-like voltage change occurs in the signal waveform of the logic signal Sa, the signal generating unit 6 can correctly binarize the restored signal Sre at one threshold voltage Vth and generate a correct code identification signal Sf without being affected by this voltage change.

According to the present invention, the newly restored signal shaped into a single-ended signal can be reliably binarized using a threshold voltage to generate a code identification signal. As a result, the present invention can be widely applied to a signal generation device that generates such a code identification signal, and to a signal reading system equipped with this signal generation device.

1A, 1B, 1C, 1D Signal reading system 2A, 2B, 2C, 2D Signal generating device 3 Signal conversion device 4A, 4B, 4C, 4D Detection unit 5, 5A Integration unit 6 Signal generating unit 7 Waveform shaping unit 8 Signal restoration unit 12a, 12b Electrode 21 Transformer 21a Primary winding 21b Secondary winding 22 Resistor La, Lb Covered conductor Sa Logic signal SB CAN bus (communication path)
Sd: detection signal Sf: code identification signal Sre: restoration signal TP3, TP4: each terminal of the secondary winding Vth: threshold voltage

Claims (8)

A signal generating device that generates a code identification signal capable of identifying a code corresponding to a logic signal based on the logic signal transmitted through a communication path formed of a coated conductor wire,
a signal restoration unit that generates a restored signal having a signal waveform equivalent to the signal waveform of the logic signal by integrating a signal waveform corresponding to a differential waveform of the logic signal detected from the coated conductor;
a signal generating unit that generates the code identifying signal by comparing the restored signal with a threshold voltage and binarizing the restored signal, The signal generating device according to claim 1, wherein the signal restoration unit includes a transformer having a primary winding and a secondary winding, and a resistor connected between each terminal of the secondary winding, and inputs a signal detected by an electrode that is brought into contact with a coating portion of the coated conductor to the primary winding via a coupling capacitance between the coated conductor and the electrode, and generates the restored signal by integrating a signal waveform that corresponds to a differential waveform of the logic signal output from the secondary winding. The signal generating device according to claim 1, wherein the signal restoration unit includes a resistive element that receives a signal detected by the electrode through capacitive coupling via a coupling capacitance between the electrode that is in contact with the coating of the coated conductor and the coated conductor, and generates the restored signal by integrating a signal waveform that corresponds to a differential waveform of the logic signal generated in the resistive element. The signal generating device according to claim 1, wherein the signal restoration unit includes a transformer having a primary winding and a secondary winding, and a resistor connected between each terminal of the secondary winding, and generates the restored signal by inputting a signal output from a current detection probe attached to the coated conductor to the primary winding and integrating a signal waveform corresponding to a differential waveform of the logic signal output from the secondary winding. The signal generating device according to claim 1, wherein the signal restoration unit includes a resistive element that receives a signal output from a current detection probe attached to the coated conductor wire, and generates the restored signal by integrating a signal waveform that corresponds to a differential waveform of the logic signal generated in the resistive element. A signal generating device according to any one of claims 1 to 5, further comprising a waveform shaping unit disposed between the signal restoration unit and the signal generating unit, which shapes the restored signal into a single-ended signal having a peak-to-peak voltage equivalent to the peak-to-peak voltage of the restored signal and a voltage during a low voltage period set to a target constant voltage, and outputs the signal. A signal generating device according to any one of claims 1 to 5, further comprising a waveform shaping unit disposed between the signal restoration unit and the signal generating unit, which shapes the restored signal into a single-ended signal having a peak-to-peak voltage equivalent to the peak-to-peak voltage of the restored signal and a voltage during a high voltage period set to a target constant voltage, and outputs the signal. A signal generating device according to any one of claims 1 to 7,
a signal conversion device that converts the code identifying signal generated by the signal generation device into a signal of a communication method conforming to the communication method of the logic signal and outputs the signal.

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