JP7558029B2 - Buffer Circuit - Google Patents

Description

This invention relates to a buffer circuit that outputs a voltage to an external device.

Conventionally, there are cases where a buffer circuit outputs a voltage to an external device (IC: Integrated Circuit). For example, as shown in FIG. 6, there are cases where an IC does not have a built-in A/D (Analog/Digital) converter, and the voltage of an analog circuit inside the IC is output to an external A/D converter (external device) 102 via a buffer circuit 101.

In such cases, the buffer circuit may need to limit the voltage it outputs, depending on the external device to which it outputs the voltage. In other words, depending on the conditions of use, the power supply voltage on the buffer circuit side may be higher than the power supply voltage on the external device side. In this case, it is necessary to limit the output voltage from the buffer circuit to less than or equal to the power supply voltage on the external device side.

In FIG. 6, the output voltage from the buffer circuit 101 is A/D converted by the external A/D converter 102. The buffer circuit 101 is connected to a power supply 103, and the buffer circuit 101 operates on the power supply voltage from the power supply 103. The external A/D converter 102 is connected to a power supply 104, and the external A/D converter 102 operates on the power supply voltage from the power supply 104. Protective diodes D1' to D4' are connected between the external A/D converter 102 and the buffer circuit 101. In FIG. 6, VREG1 indicates the power supply voltage on the buffer circuit 101 side, VREG2 indicates the power supply voltage on the external A/D converter 102 side, and VO1 indicates the output voltage from the buffer circuit 101. In FIG. 6, it is assumed that VREG1>VREG2.

In this case, the output voltage from the buffer circuit 101 must be limited to be equal to or lower than the power supply voltage on the external A/D converter 102 side (VO1≦VREG2). On the other hand, if the output voltage from the buffer circuit 101 exceeds the power supply voltage on the external A/D converter 102 side (VO1>VREG2), as shown by the arrows in Figure 6, excessive current will flow through the protective diodes D1' to D4', which may lead to failure.

In response to this, a semiconductor integrated circuit is known that uses a source follower circuit to limit the output voltage of an operational amplifier (see, for example, Patent Document 1). In this semiconductor integrated circuit, in order to limit the output voltage of a high-voltage driven circuit without limiting the voltage fed back to the differential amplifier circuit, high-voltage and low-voltage output stages are mounted and configured to switch the output stage according to the operating phase. The operating phases include a first phase in which the input is sampled and fed back, and a second phase in which the input is amplified and output. This makes it possible to avoid failures even when the output of a high-voltage driven circuit is connected to an external circuit driven by a low voltage. Note that a high-voltage output is essential in the first phase, because if a low voltage is output, the desired output cannot be obtained.

JP 2019-22083 A

On the other hand, in a buffer circuit, it is necessary to be able to reliably limit the output voltage not only during normal operation, but also when the buffer circuit is not operating normally, such as when the power supply is turned on. However, in the semiconductor integrated circuit disclosed in Patent Document 1, a high voltage is output in the first phase. Therefore, if the configuration of this semiconductor integrated circuit is applied to a buffer circuit, there is a possibility that the output voltage cannot be reliably limited when the buffer circuit is not operating normally, such as when the power supply is turned on.

This invention was made to solve the above problems, and aims to provide a buffer circuit that can limit the output voltage to a level equal to or lower than the power supply voltage of the external device to which it is output, even when the buffer circuit is not operating normally.

The buffer circuit according to the present invention is characterized in comprising an input stage that amplifies the difference between a voltage input to an inverting input terminal and a voltage input to a non-inverting input terminal, and an output stage that operates on a power supply voltage from a power supply connected to an external A/D converter, amplifies the voltage amplified by the input stage, and outputs it to the external A/D converter .

With the above configuration, this invention makes it possible to limit the output voltage to a level equal to or lower than the power supply voltage of the external device to which it is output, even when the buffer circuit is not operating normally.

FIG. 1 is a diagram showing a configuration example of a buffer circuit according to a first embodiment; FIG. 1 is a diagram showing a configuration example of a current source circuit included in a buffer circuit according to a first embodiment; FIG. 1 is a diagram showing another example of the configuration of a current source circuit included in a buffer circuit according to a first embodiment; 4 is a diagram showing an example of a relationship between an internal voltage and an output voltage of the buffer circuit according to the first embodiment; FIG. 11 is a diagram illustrating another configuration example of the buffer circuit according to the first embodiment. 1A and 1B are diagrams illustrating an excess current that occurs in a conventional buffer circuit when an output voltage is higher than a power supply voltage on an external device side.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
Embodiment 1.
FIG. 1 is a diagram showing an example of the configuration of a buffer circuit 1 according to a first embodiment.
1 shows a case where an external A/D converter 2 is connected as an external device to a buffer circuit 1. The external A/D converter 2 converts an analog voltage input to an input terminal into a digital voltage.

The external A/D converter 2 is connected to a power supply 4. The negative terminal of the power supply 4 is grounded. The external A/D converter 2 operates on the power supply voltage from the power supply 4. In FIG. 1, VREG2 indicates the power supply voltage from the power supply 4.

In addition, protective diodes D1 to D4, for example, are connected between the external A/D converter 2 and the buffer circuit 1 as electrostatic protection elements. These electrostatic protection elements are formed in the part of the IC that is connected to the outside (part called I/O, etc.), and serve as a current path to prevent damage to the inside of the IC when an excessive voltage higher than the IC's own power supply is applied due to static electricity, etc. Here, protective diodes D1 and D2 are assumed to be electrostatic protection elements built into the IC in which the buffer circuit 1 is built. In addition, protective diodes D3 and D4 are assumed to be electrostatic protection elements built into the external A/D converter 2.

The cathode of the protective diode D1 is connected to the positive terminal of the power supply 4. The cathode of the protective diode D2 is connected to the anode of the protective diode D1, and the anode is connected to the negative terminal of the power supply 4. The cathode of the protective diode D3 is connected to the positive terminal of the power supply 4. The cathode of the protective diode D4 is connected to the anode of the protective diode D1, the anode of the protective diode D3, and the input end of the external A/D converter 2, and the anode is connected to the negative terminal of the power supply 4.

Buffer circuit 1 is an analog buffer circuit built into an analog circuit IC. As shown in FIG. 1, buffer circuit 1 includes an operational amplifier OP1, a transistor Tr1, and a current source circuit Ic1. Transistor Tr1 and current source circuit Ic1 form a source follower circuit. Power supplies 3 and 4 are also connected to buffer circuit 1. The negative terminal of power supply 3 is grounded. The operational amplifier OP1 (input stage) of buffer circuit 1 operates on the power supply voltage from power supply 3. On the other hand, the source follower circuit (output stage) of buffer circuit 1 operates on the power supply voltage from power supply 4. In FIG. 1, VREG1 indicates the power supply voltage from power supply 3.

In FIG. 1, the measurement point indicates a location in another analog circuit in the IC incorporating the buffer circuit 1 where an analog voltage is to be output to the outside, and the voltage at that location (internal voltage) is indicated as VO1.

The operational amplifier OP1 amplifies the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal, and outputs the amplified voltage from the output terminal. The internal voltage (VO1) is input to the non-inverting input terminal of this operational amplifier OP1, and the inverting input terminal is connected to the source terminal of the transistor Tr1.

The gate terminal of the transistor Tr1 is connected to the output terminal of the operational amplifier OP1, the drain terminal is connected to the positive terminal of the power supply 4, and the source terminal is connected to the input terminal of the current source circuit Ic1 and the output terminal of the buffer circuit 1.

The output terminal of the buffer circuit 1 is connected to the input terminal of the external A/D converter 2 via protective diodes D1 to D4. In FIG. 1, VO2 indicates the output voltage from the buffer circuit 1.

The output terminal of the current source circuit Ic1 is grounded. The current source circuit Ic1 is configured, for example, as an Nch-type current mirror circuit using CMOS (Complementary Metal Oxide Semiconductor) transistors. FIG. 2 shows a connection example in which the current source circuit Ic1 is configured as an Nch-type current mirror circuit using CMOS transistors.

The current source circuit Ic1 shown in FIG. 2 includes a current source circuit Ic2 and transistors Tr2 and Tr3.
The current source circuit Ic2 outputs a bias current. The input terminal of the current source circuit Ic2 is connected to the positive terminal of the power source 3.
The transistor Tr2 has a gate terminal connected to the output terminal of the current source circuit Ic2, a drain terminal connected to the output terminal of the current source circuit Ic2, and a source terminal grounded.
The transistor Tr3 has a gate terminal connected to the gate terminal of the transistor Tr2, a drain terminal connected to the source terminal of the transistor Tr1, and a source terminal grounded.

The transistor Tr1 and current source circuit Ic1 shown in FIG. 2 form an Nch type source follower circuit.

Note that FIG. 2 shows a case where the current source circuit Ic1 is configured as an Nch-type current mirror circuit using CMOS transistors. However, the configuration of the current source circuit Ic1 is not limited to this, and the current source circuit Ic1 may be configured as, for example, a current mirror circuit using NPN transistors.

Note that in Figures 1 and 2, the source follower circuit is shown to be configured with a transistor Tr1 and a current source circuit Ic1. However, this is not limiting, and the source follower circuit may be configured to operate using the power supply voltage on the external A/D converter 2 side, amplify the voltage amplified by the operational amplifier OP1, and output it to the external A/D converter 2. For example, as shown in Figure 3, the source follower circuit may be configured with a transistor Tr1 and a resistor R1. In this case, one end of the resistor R1 is connected to the source terminal of the transistor Tr1, and the other end is grounded.

In the above, the operational amplifier OP1 constitutes an input stage of the buffer circuit 1 that amplifies the difference between the voltage input to the inverting input terminal and the voltage input to the non-inverting input terminal. Also, the source follower circuit constitutes an output stage of the buffer circuit 1 that operates using the power supply voltage of the external device (external A/D converter 2) and amplifies the voltage amplified by the input stage and outputs it to the external device.

Next, the effects of the buffer circuit 1 according to the first embodiment shown in FIGS. 1 to 3 will be described.
In the buffer circuit 1 according to the first embodiment, the power supply voltage on the output stage side connected to the external device (external A/D converter 2) is set as the limiting voltage (power supply voltage on the external device side), thereby limiting the output voltage. Specifically, in the buffer circuit 1 according to the first embodiment shown in FIGS. 1 to 3, an operational amplifier OP1 and a source follower circuit are combined to configure a voltage follower circuit, and the drain terminal of the source follower circuit is connected to the power supply 4 of the external A/D converter 2. As a result, in the buffer circuit 1 according to the first embodiment shown in FIGS. 1 to 3, the power supply voltage on the external A/D converter 2 side is used as the power supply voltage on the source follower circuit side, so that the upper limit of the output voltage (VO2) is limited to the power supply voltage (VREG2) on the external A/D converter 2 side.

FIG. 4 shows an example of the relationship between the internal voltage (VO1) of the buffer circuit 1 and the output voltage (VO2) of the buffer circuit 1. In FIG.
4, in a region where the internal voltage (VO1) of the buffer circuit 1 is equal to or lower than the output voltage (VREG2), the buffer circuit 1 operates as a voltage follower circuit and outputs the internal voltage (VO1) as is as the output voltage (VO2). On the other hand, in a region where the internal voltage (VO1) of the buffer circuit 1 is higher than the output voltage (VREG2), the output voltage (VO2) is limited to the power supply voltage (VREG2) of the external device.

Moreover, in the buffer circuit 1 according to the first embodiment shown in FIGS. 1 to 3, the output voltage can be reliably limited not only during normal operation but also when the buffer circuit 1 is not operating normally, such as at power-on.
That is, since power supply 3 and power supply 4 are separate power supplies, it is assumed that the start-up timings may differ when the power supplies are started up. On the other hand, in the buffer circuit 1 according to the first embodiment shown in Figures 1 to 3, even if power supply 3 starts up before power supply 4 starts up, the output stage of the buffer circuit 1 operates on the power supply voltage of power supply 4, so that the output voltage will not be higher than the power supply voltage (VREG2) of power supply 4. Therefore, no excessive current will flow through the protective diodes D1 to D4 attached to the external A/D converter 2.

In the above, the input stage of the buffer circuit 1 is configured with an operational amplifier OP1, and the output stage of the buffer circuit 1 is configured with a source follower circuit. However, this is not limited, and the buffer circuit 1 may be configured to have an input stage that amplifies the difference between the voltage input to the inverting input terminal and the voltage input to the non-inverting input terminal, and an output stage that operates with the power supply voltage of the external device and amplifies the voltage amplified by the input stage and outputs it to the external device. For example, as shown in FIG. 5, the input stage and output stage of the buffer circuit 1 may be configured with an operational amplifier OP2 whose output side is configured with a source ground circuit 11. In this case, the power supply 4 of the external device is used as the power supply for the source ground circuit 11.

The buffer circuit 1 shown in FIG. 5 is composed of transistors Tr4 to Tr10, a resistor R2, and a capacitor C1. The transistors Tr4 to Tr8 form the input side of the operational amplifier OP2. The transistors Tr9 and Tr10, the resistor R2, and the capacitor C1 form the output side (source-grounded circuit 11) of the operational amplifier OP2.

A bias voltage is applied to the gate terminal of transistor Tr4, and the source terminal is connected to the positive terminal of power supply 3. In FIG. 5, VBias1 indicates the bias voltage applied to the gate terminal of transistor Tr4.

The transistor Tr5 has a gate terminal connected to the output terminal of the buffer circuit 1 and a source terminal connected to the drain terminal of the transistor Tr4. The gate terminal of the transistor Tr5 corresponds to the inverting input terminal of the operational amplifier OP2.
The transistor Tr6 has a gate terminal to which the internal voltage (VO1) is input, and a source terminal connected to the drain terminal of the transistor Tr4 The gate terminal of the transistor Tr6 corresponds to the non-inverting input terminal of the operational amplifier OP2.

The transistor Tr7 has a gate terminal connected to the drain terminal of the transistor Tr5, a drain terminal connected to the drain terminal of the transistor Tr5, and a source terminal grounded.
The transistor Tr8 has a gate terminal connected to the gate terminal of the transistor Tr7, a drain terminal connected to the drain terminal of the transistor Tr6, and a source terminal grounded.

One end of the resistor R2 is connected to the drain terminal of the transistor Tr6.
One end of the capacitor C1 is connected to the other end of the resistor R2.

The transistor Tr9 has a gate terminal connected to the drain terminal of the transistor Tr6, a drain terminal connected to the other end of the capacitor C1 and the output terminal of the buffer circuit 1, and a source terminal grounded.
The transistor Tr10 has a gate terminal to which a bias voltage is applied, a source terminal connected to the positive terminal of the power supply 4, and a drain terminal connected to the output terminal of the buffer circuit 1. In Fig. 5, VBias2 indicates the bias voltage applied to the gate terminal of the transistor Tr10.

The output terminal of the buffer circuit 1 is connected to the input terminal of the external A/D converter 2 via protective diodes D1 to D4.

The buffer circuit 1 configured as shown in FIG. 5 also provides the same effects as the buffer circuit 1 configured as shown in FIGS. 1 to 3.

In the above, an external A/D converter 2 is connected to the buffer circuit 1 as an external device. However, the external device is not limited to this, and the external device may be any device that outputs a voltage from the buffer circuit 1.

As described above, according to this embodiment 1, the buffer circuit 1 includes an input stage that amplifies the difference between the voltage input to the inverting input terminal and the voltage input to the non-inverting input terminal, and an output stage that operates using the power supply voltage of the external device and amplifies the voltage amplified by the input stage and outputs it to the external device. As a result, the buffer circuit 1 according to embodiment 1 can limit the output voltage to less than the power supply voltage of the external device to which it is output, even when the buffer circuit 1 is not operating normally.

In addition, any of the components of the embodiments of the present invention may be modified or omitted within the scope of the invention.

1 Buffer circuit 2 External A/D converter 3 Power supply 4 Power supply 11 Source ground circuit D1 to D4 Protection diodes OP1, OP2 Operational amplifiers Tr1 to Tr10 Transistors Ic1, Ic2 Current source circuit R1, R2 Resistor C1 Capacitor

Claims (5)

an input stage that amplifies a difference between a voltage input to an inverting input terminal and a voltage input to a non-inverting input terminal;
an output stage that operates using a power supply voltage from a power supply connected to an external A/D converter , and amplifies the voltage amplified by the input stage and outputs the amplified voltage to the external A/D converter . The input stage and the output stage include:
An operational amplifier,
2. The buffer circuit according to claim 1, further comprising a source follower circuit connected to an output terminal of the operational amplifier and operated by a power supply voltage from a power supply connected to the external A/D converter . The source follower circuit comprises:
a transistor having a gate terminal connected to the output terminal of the operational amplifier, a source terminal connected to the inverting input terminal of the operational amplifier, and a drain terminal to which a power supply voltage from a power supply connected to the external A/D converter is applied;
3. The buffer circuit according to claim 2, further comprising: a current source circuit having an input terminal connected to the source terminal of the transistor and an output terminal grounded. The source follower circuit comprises:
a transistor having a gate terminal connected to the output terminal of the operational amplifier, a source terminal connected to the inverting input terminal of the operational amplifier, and a drain terminal to which a power supply voltage from a power supply connected to the external A/D converter is applied;
3. The buffer circuit according to claim 2, further comprising a resistor having one end connected to the source terminal of the transistor and the other end grounded. The input stage and the output stage include:
2. The buffer circuit according to claim 1, further comprising an operational amplifier including a common-source circuit that operates on a power supply voltage from a power supply connected to the external A/D converter .

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