JP7548116B2 - Gate drive circuit and method for controlling the gate drive circuit - Google Patents

Description

The present invention relates to a gate drive circuit for driving series-connected semiconductor devices.

A pulse power supply such as that described in Patent Document 1 connects multiple semiconductor devices in series to achieve high voltage resistance. Figure 16 shows the circuit configuration diagram of Patent Document 1 (left: gate amplifier circuit, right: overall configuration diagram). As shown in Figure 16, Patent Document 1 uses optical fiber to insulate the semiconductor element on the high voltage side from the control circuit on the low voltage side, and drives the semiconductor device by driving the gate amplifier.

Japanese Patent Application Publication No. 03-237811

In this case, since a negative voltage cannot be applied when the gate is off, there is a risk of false firing when the gate voltage threshold is low, as in the case of SiC MOSFETs, which can cause short circuits and uneven voltage distribution, which can lead to damage to the device.

In addition, since the gate amplifier must be connected in parallel with the semiconductor device to be driven, the elements that make up the gate amplifier, such as the transistor (reference number 33 in Patent Document 1), must have the same withstand voltage as the semiconductor device to be driven, resulting in problems of high cost and large size.

Given the above, the challenge is to apply a negative bias to a gate drive circuit while maintaining insulation between the high-voltage circuit and the low-voltage circuit, and to achieve a low-cost and compact design.

The present invention was devised in view of the above-mentioned problems of the related art, and one aspect of the present invention is a gate drive circuit for n semiconductor devices connected in series, comprising a transmission section for transmitting gate signals and power, a transformer section having a first transformer with a primary winding connected to the transmission section, and a drive circuit section having a first stage drive circuit to an nth stage drive circuit for controlling the n semiconductor devices, respectively, and each of the first stage drive circuit to the nth stage drive circuit has a plurality of switch devices and first and second power supply capacitors between the secondary winding and tertiary winding of the first transformer and the semiconductor device to be driven, and when the gate command of the semiconductor device to be driven is high, the plurality of switch devices are controlled to connect the first power supply capacitor in parallel to the semiconductor device to be driven, and when the gate command of the semiconductor device to be driven is low, the plurality of switch devices are controlled to connect the second power supply capacitor in inverse parallel to the semiconductor device to be driven.

In one embodiment, the transmission unit includes a transmission circuit having an input capacitor, a first full-bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full-bridge circuit and the primary winding of the first transformer, and the first-stage drive circuit to the n-th-stage drive circuit each include a first diode having an anode connected to one end of the secondary winding of the first transformer, a second diode having an anode connected to the other end of the secondary winding of the first transformer, a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode, and a third diode having an anode connected to the cathode of the third diode. a first terminal of said resistor connected to said cathode of said fourth diode and a midpoint of said tertiary winding of said first transformer; a fifth diode having an anode connected to one end of said tertiary winding of said first transformer; a sixth diode having an anode connected to the cathode of said fourth diode and the cathode of said fifth diode and a cathode connected to a junction of said first and second power supply capacitors; a first resistor having one end connected to the junction of said fourth, fifth and sixth diodes and the other end connected to the midpoint of said tertiary winding of said first transformer; a first switch device connected to the junction point of the first, second and third diodes, having a second terminal connected to the junction point of the third diode and the first power supply capacitor, and having a third terminal connected to a first terminal of the semiconductor device to be driven; a second switch device having a first terminal connected to the junction point of the first, second and third diodes, having a second terminal connected to the first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer; and a third switch device having a second terminal connected to the junction point of the first, second and third diodes, and having a third terminal connected to the midpoint of the tertiary winding of the first transformer. a fourth switch device having a first terminal connected to the junction of the fourth, fifth, and sixth diodes, a second terminal connected to the cathode of the sixth diode, and a third terminal connected to the first terminal of the third switch device; and a fifth switch device having a first terminal connected to the junction of the fourth, fifth, and sixth diodes, a second terminal connected to the first terminal of the third switch device, and a third terminal connected to the midpoint of the tertiary winding of the first transformer, and the third terminal of the semiconductor device to be driven is connected to the junction of the first and second power supply capacitors and the midpoint of the secondary winding of the first transformer.

In another aspect, the transformer unit includes the first transformer and the second transformer, the transmission unit includes an ON-side transmission circuit having an input capacitor, a first full bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full bridge circuit and the primary winding of the first transformer, and an OFF-side transmission circuit having a second full bridge circuit connected to the input capacitor and a second DC blocking capacitor connected between the second full bridge circuit and the primary winding of the second transformer, and the drive circuit unit includes the first stage drive circuit to the nth stage drive circuit and the first stage OFF-side drive circuit to the nth stage OFF-side drive circuit, and the first stage drive circuit to the nth stage drive circuit each include a first diode having an anode connected to one end of the secondary winding of the first transformer, a second diode having an anode connected to the other end of the secondary winding of the first transformer, and the a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode, first and second power supply capacitors connected in series between the cathode of the third diode and a midpoint of the tertiary winding of the first transformer, a fourth diode having an anode connected to one end of the tertiary winding of the first transformer, a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer, a sixth diode having an anode connected to the cathode of the fourth diode and the cathode of the fifth diode and a cathode connected to a junction point of the first and second power supply capacitors, a first resistor having one end connected to the junction point of the fourth, fifth and sixth diodes and the other end connected to the midpoint of the tertiary winding of the first transformer, a second resistor having one end connected to the junction point of the first, second and third diodes, and a first terminal connected to the other end of the second resistor and a second terminal connected to the junction point of the third diode and the first power supply capacitor. a first switch device connected to the other end of the second resistor, a second terminal connected to the first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer; a third switch device having a second terminal connected to the other end of the second resistor and a third terminal connected to the midpoint of the tertiary winding of the first transformer; a seventh diode having an anode connected to the first terminal of the third switch device and a cathode connected to the cathode of the sixth diode; and a fifth switch device having a first terminal connected to a junction point of the fourth, fifth, and sixth diodes and a third terminal connected to the midpoint of the tertiary winding of the first transformer, Each of the first stage OFF side drive circuit to the nth stage OFF side drive circuit includes an eighth diode having an anode connected to one end of the secondary winding of the second transformer and a cathode connected to the connection point between the third diode and the first power supply capacitor, a ninth diode having an anode connected to the other end of the secondary winding of the second transformer and a cathode connected to the connection point between the third diode and the first power supply capacitor, a tenth diode having an anode connected to one end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device, and an eleventh diode having an anode connected to the other end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device, and characterized in that the midpoint of the secondary winding of the second transformer is connected to the midpoint of the secondary winding of the first transformer, and the midpoint of the tertiary winding of the second transformer is connected to the midpoint of the tertiary winding of the first transformer.

In one embodiment, a third resistor is connected between the second terminal of the fifth switch device and the first terminal of the third switch device.

In one aspect, a first voltage adjustment mechanism is provided between the first switch device and the first power supply capacitor, and a second voltage adjustment mechanism is provided between the second switch device and the second power supply capacitor.

In one aspect, the first and second voltage adjustment mechanisms include a semiconductor element having a second terminal connected to the first power supply capacitor or the second power supply capacitor and a third terminal connected to the first switch device or the second switch device, a reference voltage having one end connected to the connection point between the first and second power supply capacitors, a sixth resistor connected to one end of the reference voltage, a seventh resistor connected between the other end of the sixth resistor and the first switch device or the second switch device, and an amplifier circuit having an input terminal that is the connection point between the other end of the reference voltage and the sixth and seventh resistors and an output terminal connected to the first terminal of the semiconductor element.

In one aspect, the first and second full bridge circuits include first and second semiconductor switches connected in series across the input capacitor, and third and fourth semiconductor switches connected in series across the input capacitor, and the connection point of the third and fourth semiconductor switches is connected to one end of the primary winding of the first transformer or one end of the primary winding of the second transformer via the first DC cut capacitor or the second DC cut capacitor, and the connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer, and the control circuit turns the first and fourth semiconductor switches ON and turns the second and third semiconductor switches OFF when the voltages of the first and second DC cut capacitors are positive, and turns the first and fourth semiconductor switches OFF and the second and third semiconductor switches ON when the voltages of the first and second DC cut capacitors are negative.

In one aspect, the voltages of the first and second DC blocking capacitors are low-pass filtered or moving average processed values.

In one aspect, the timing for sampling the voltages of the first and second DC blocking capacitors is set to the timing of the peak of the carrier, and the timing for switching the first to fourth semiconductor switches is set to the timing of the zero crossing of the carrier.

In another embodiment, the first and second full bridge circuits include first and second semiconductor switches connected in series between both ends of the input capacitor, and third and fourth semiconductor switches connected in series between both ends of the input capacitor, and a connection point between the third and fourth semiconductor switches is connected to one end of the primary winding of the first transformer or one end of the primary winding of the second transformer via the first DC blocking capacitor or the second DC blocking capacitor, and the connection point between the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer, and the control circuit includes a voltage-controlled oscillator that controls an oscillation frequency by an input voltage, and a phase of the output of the voltage-controlled oscillator when the gate command is off. The device is equipped with a sample-and-hold circuit that samples and holds information and outputs it as sample phase information, a phase determination unit that outputs 2π as a phase command value when the sample phase information is π or more and less than 2π, and outputs 0 as the phase command value when the sample phase information is 0 or more and less than π, and a PI controller that performs PI control based on the phase command value and the sample phase information and outputs a voltage that is the result of the PI control to the voltage-controlled oscillator, and is characterized in that when the output of the voltage-controlled oscillator is positive, the first and fourth semiconductor switches are turned ON and the second and third semiconductor switches are turned OFF, and when the output of the voltage-controlled oscillator is negative, the first and fourth semiconductor switches are turned OFF and the second and third semiconductor switches are turned ON.

In one aspect, the control circuit includes a capacitor voltage feedback unit that performs PI control based on the difference between the voltage command value and the voltage detection value of the first DC blocking capacitor or the second DC blocking capacitor, and the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor voltage feedback unit.

In another aspect, the control circuit includes a capacitor current feedback unit that performs PI control based on the difference between the current command value and the current detection value of the first DC cutting capacitor or the second DC cutting capacitor, and the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor current feedback unit.

In one embodiment, the voltage-controlled oscillator includes an eighth resistor having one end connected to the input terminal, a ninth resistor having one end connected to the input terminal, a first comparator having one input terminal connected to the other end of the eighth resistor and the other input terminal connected to the other end of the ninth resistor, a capacitor connected between one input terminal and an output terminal of the first comparator, a tenth resistor having one end connected to one input terminal of the first comparator, a semiconductor switch having a second terminal connected to the other end of the tenth resistor and a third terminal grounded, and a second input terminal of the first comparator. The semiconductor device is characterized by comprising an 11th resistor connected between the terminal and the third terminal of the semiconductor switch, a second comparator having one input terminal connected to the output of the first comparator, a 12th resistor having one end connected to the other input terminal of the second comparator and the other end grounded, a 13th resistor connected between the output terminal of the second comparator and the other input terminal, a 14th resistor connected between the first terminal of the semiconductor device and the output terminal of the second comparator, and a duty ratio correction unit that corrects the duty ratio according to the output of the second comparator.

The present invention makes it possible to apply a negative bias to a gate drive circuit while maintaining insulation between the high-voltage circuit and the low-voltage circuit, and to achieve a low-cost and compact design.

FIG. 2 is a circuit diagram showing the configuration of a gate drive circuit according to the first embodiment. FIG. 4 is a diagram showing an operation example of the first embodiment. FIG. 11 is a circuit diagram showing a gate drive circuit according to a second embodiment. FIG. 11 is a diagram showing an operation example of the second embodiment. FIG. 11 is a circuit diagram showing a gate drive circuit according to a third embodiment. FIG. 2 is a diagram showing a configuration example of a regulator. FIG. 13 is a diagram showing the influence of a DC blocking capacitor voltage Vc on the operation. FIG. 13 is a block diagram of a control circuit according to a fourth embodiment. FIG. 13 is a block diagram of a control circuit according to a fifth embodiment. FIG. 13 is a block diagram of a control circuit according to a sixth embodiment. FIG. 23 is a block diagram of a control circuit according to a seventh embodiment. FIG. 2 shows an example of the configuration of a VCO. FIG. 4 is a diagram showing an example of characteristics of a VCO. FIG. 23 is a block diagram of a control circuit according to an eighth embodiment. FIG. 13 is a block diagram of a control circuit according to a ninth embodiment. FIG. 1 is a circuit configuration diagram of Patent Document 1.

Below, embodiments 1 to 9 of the gate drive circuit of the present invention will be described in detail with reference to Figures 1 to 15.

[Embodiment 1]
Fig. 1 shows an example of the circuit configuration of the gate drive circuit in the first embodiment. Fig. 1 shows a configuration in which n semiconductor devices 1 to n to be driven are connected in series, where n is any natural number (1, 2, 3, ... n). The gate drive circuit includes a transmission section that transmits gate signals and power, a transformer section having a first transformer Tr1, and a drive circuit section having a first stage drive circuit 11 to nth stage drive circuit 1n that respectively control the n semiconductor devices. The first stage drive circuit 11 to nth stage drive circuit 1n have the same configuration.

The transmission section of the first embodiment includes a transmission circuit 10. In the transmission circuit 10, first and second semiconductor switches S1 and S2 are connected in series across the input capacitor Vin. Third and fourth semiconductor switches S3 and S4 are connected in series across the input capacitor Vin. The first to fourth semiconductor switches S1 to S4 form a first full bridge circuit. One end of the first DC blocking capacitor C1 is connected to the connection point of the third and fourth semiconductor switches S3 and S4, and one end of the primary winding of the first transformer Tr1 is connected to the other end of the first DC blocking capacitor C1. The connection point of the first and second semiconductor switches S1 and S2 is connected to the other end of the primary winding of the first transformer Tr1. A switching pattern of the first to fourth semiconductor switches S1 to S4 is generated based on the gate command of the semiconductor devices 1 to n to be driven.

In the first stage drive circuit 11, the anode of the first diode D1 is connected to one end of the secondary winding of the first transformer Tr1. The anode of the second diode D2 is connected to the other end of the secondary winding of the first transformer Tr1. The anode of the third diode D3 is connected to the cathode of the first diode D1 and the cathode of the second diode D2. The first and second power supply capacitors C11 and C21 are connected in series between the cathode of the third diode D3 and the midpoint of the tertiary winding of the first transformer Tr1.

The anode of the fourth diode D4 is connected to one end of the tertiary winding of the first transformer Tr1. The anode of the fifth diode D5 is connected to the other end of the tertiary winding of the first transformer Tr1. The cathode of the fourth diode D4 and the cathode of the fifth diode D5 are connected to the anode of the sixth diode D6. The cathode of the sixth diode D6 is connected to the connection point of the first and second power supply capacitors C11 and C21. The first resistor R1 has one end connected to the connection point of the fourth, fifth, and sixth diodes D4, D5, and D6, and the other end connected to the midpoint of the tertiary winding of the first transformer Tr.

The first switch device FET1 has a first terminal (gate terminal) connected to the connection point of the first, second, and third diodes D1, D2, and D3, a second terminal (drain terminal) connected to the connection point of the third diode D3 and the first power supply capacitor C11, and a third terminal (source terminal) connected to the first terminal (gate terminal) of the semiconductor device 1 to be driven.

The second switch device FET2 has a first terminal (gate terminal) connected to the connection point of the first, second, and third diodes D1, D2, and D3, a second terminal (drain terminal) connected to the first terminal (gate terminal) of the semiconductor device 1 to be driven, and a third terminal (source terminal) connected to the midpoint of the tertiary winding of the first transformer Tr.

The third switch device FET3 has a second terminal (drain terminal) connected to the connection point of the first, second, and third diodes D1, D2, and D3, and a third terminal (source terminal) connected to the midpoint of the tertiary winding of the first transformer Tr.

The fourth switch device FET4 has a first terminal (gate terminal) connected to the connection point of the fourth, fifth, and sixth diodes D4, D5, and D6, a second terminal (drain terminal) connected to the cathode of the sixth diode D6, and a third terminal (source terminal) connected to the first terminal (gate terminal) of the third switch device FET3.

The fifth switch device FET5 has a first terminal (gate terminal) connected to the connection point of the fourth, fifth, and sixth diodes D4, D5, and D6, a second terminal (drain terminal) connected to the first terminal (gate terminal) of the third switch device FET3, and a third terminal (source terminal) connected to the midpoint of the tertiary winding of the first transformer Tr. The third terminal (source terminal) of the semiconductor device to be driven is connected to the midpoint of the first and second power supply capacitors C11 and C21 and the secondary winding of the first transformer Tr1.

The second stage drive circuit 12 to the nth stage drive circuit 1n are similar to the first stage drive circuit 11.

The transmission circuit 10 transmits gate commands and power from the first stage drive circuit 11 to the nth stage drive circuit 1n, and charges the power supply capacitors C1n and C2n of the nth stage drive circuit 1n from the power supply capacitors C11 and C21 of the first stage drive circuit 11, while at the same time controlling the conduction state of the semiconductor devices 1 to n to be driven.

The charging voltage of the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n can be set to any value by changing the turn ratio of the primary winding, secondary winding, and tertiary winding of the first transformer Tr. In addition, by using the first transformer Tr, it is possible to electrically insulate the high voltage side from the low voltage side.

In addition, the voltage applied to the gate is generally a few tenths of the withstand voltage between the drain and source. Since the voltages applied to the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n are set by the voltage applied to the gate, the withstand voltages of the first to fifth switch devices FET1 to FET5 that constitute them can be set accordingly low, which allows for lower costs and smaller size compared to Patent Document 1.

The first to nth stage drive circuits 11 to 1n operate to energize the semiconductor devices 1 to n to be driven while the transmission circuit 10 is operating, and operate to turn off the semiconductor devices 1 to n to be driven when the operation of the transmission circuit 10 stops. An operation chart is shown in Figure 2. The following explanation focuses on the ON/OFF operation of the semiconductor device 1 to be driven.

When the gate command of the semiconductor device 1 to be driven becomes high, the transmission circuit 10 starts operating and transmits power to the first stage drive circuit 11. Then, the first switch device FET1 and the fifth switch device FET5 become conductive, the first power supply capacitor C11 is connected in parallel to the semiconductor device 1 to be driven, and the semiconductor device 1 to be driven becomes conductive.

When the gate command for the semiconductor device 1 to be driven goes low, the transmission circuit 10 stops operating and stops transmitting power to the first stage drive circuit 11. Then, the second, third and fourth switch devices FET2, FET3 and FET4 become conductive, the second power supply capacitor C21 is connected in inverse parallel to the semiconductor device 1 to be driven, and a voltage equal to the charging voltage of the second power supply capacitor C21 is applied as a negative voltage, turning off the semiconductor device 1 to be driven. The second to nth stage drive circuits 12 to 1n also operate in a similar manner, making it possible to control the ON and OFF of the semiconductor devices 2 to n to be driven.

This allows for bipolar output while maintaining insulation between the high-voltage and low-voltage circuits, and allows for the application of a negative bias, while also realizing an inexpensive, compact gate drive circuit.

[Embodiment 2]
Fig. 3 shows an example of the circuit configuration of the gate drive circuit in the present embodiment 2. Fig. 3 shows a configuration in which n semiconductor devices 1 to n to be driven are connected in series, where n is an arbitrary natural number (1, 2, 3, ..., n).

In Figure 3, A1, B1, C1, D1, ..., An, Bn, Cn, and Dn each represent the destination of the wiring, and A1 is connected to A1, B1 is connected to B1, and so on.

The transformer section of the second embodiment includes a first transformer Tr1 and a second transformer Tr2. The transmission circuit section includes an ON-side transmission circuit 10a and an OFF-side transmission circuit 10b. The drive circuit section includes a first-stage ON-side drive circuit (first-stage drive circuit) 11a to an n-th stage ON-side drive circuit (n-th stage drive circuit) 1na, and a first-stage OFF-side drive circuit 11b to an n-th stage OFF-side drive circuit 1nb.

The first stage ON side drive circuit 11a and the second stage to nth stage ON side drive circuits 12a to 1na have the same configuration, and the first stage OFF side drive circuit 11b and the second stage to nth stage OFF side drive circuits 12b to 1nb have the same configuration. The second embodiment is characterized in that it transmits ON and OFF commands separately for the semiconductor devices 1 to n to be driven. This makes it possible to control the ON and OFF of the semiconductor devices 1 to n to be driven without relying on the characteristics of the constituent elements, making it possible to operate faster than the first embodiment.

As shown in FIG. 3, the ON-side transmission circuit 10a is similar to the transmission circuit 10 of the first embodiment. It generates switching patterns for the first to fourth semiconductor switches S1 to S4 based on the gate ON command of the semiconductor devices 1 to n to be driven.

In the OFF-side transmission circuit 10b, the first and second semiconductor switches S1c and S2c are connected in series across the input capacitor Vin. In addition, the third and fourth semiconductor switches S3c and S4c are connected in series across the input capacitor Vin. One end of the second DC blocking capacitor C2 is connected to the connection point of the third and fourth semiconductor switches S3c and S4c. One end of the primary winding of the second transformer Tr2 is connected to the other end of the second DC blocking capacitor C2. The connection point of the first and second semiconductor switches S1c and S2c is connected to the other end of the primary winding of the second transformer Tr2.

The switching patterns of the first to fourth semiconductor switches S1c to S4c are generated based on the gate OFF command of the semiconductor devices 1 to n to be driven.

Next, the first stage ON side drive circuit 11a will be described with respect to only the differences from the first stage drive circuit 11 of the first embodiment. A second resistor R2 is connected between the connection point of the first, second, and third diodes D1, D2, and D3 and the first terminals (gate terminals) of the first and second switch devices FET1 and FET2. A seventh diode D7 is provided instead of the fourth switch device FET4. The anode of the seventh diode D7 is connected to the first terminal (gate terminal) of the third switch device FET3, and the cathode of the seventh diode D7 is connected to the cathode of the sixth diode D6. A third resistor R3 is connected between the first terminal (gate terminal) of the third switch device FET3 and the second terminal (drain terminal) of the fifth switch device FET5. The third resistor R3 may be omitted. When the third resistor R3 is omitted, the circuit operates as a short circuit.

In the first stage OFF drive circuit 11b, the anode of the eighth diode D8 is connected to one end of the secondary winding of the second transformer Tr2. The anode of the ninth diode D9 is connected to the other end of the secondary winding of the second transformer Tr2. The cathode of the eighth diode D8 and the cathode of the ninth diode D9 are connected, and the connection point is D1. D1 is connected to the connection point of the third diode D3 and the first power supply capacitor C11. In addition, the midpoint of the secondary winding of the second transformer Tr2 is C1. C1 is connected to the midpoint of the secondary winding of the first transformer Tr1.

The anode of the tenth diode D10 is connected to one end of the tertiary winding of the second transformer Tr2. The anode of the eleventh diode D11 is connected to the other end of the tertiary winding of the second transformer Tr2. The cathode of the tenth diode D10 and the cathode of the eleventh diode D11 are connected, and the connection point is A1. A1 is connected to the first terminal (gate terminal) of the third switch device FET3. In addition, the midpoint of the tertiary winding of the second transformer Tr2 is B1. B1 is connected to the midpoint of the tertiary winding of the first transformer Tr1.

The ON-side transmission circuit 10a transmits a gate ON command and power from the first-stage ON-side drive circuit 11a to the n-th stage ON-side drive circuit 1na, and charges the first power supply capacitor C1n and second power supply capacitor C2n of the n-th stage ON-side drive circuit 1na from the first power supply capacitor C11 and second power supply capacitor C21 of the first-stage ON-side drive circuit 11a, while simultaneously controlling the semiconductor devices 1 to n to be driven to a conductive state.

The OFF-side transmission circuit 10b transmits a gate OFF command and power from the first-stage OFF-side drive circuit 11b to the n-th stage OFF-side drive circuit 1nb, and charges the first power supply capacitor C1n and second power supply capacitor C2n of the n-th stage ON-side drive circuit 1na from the first power supply capacitor C11 and second power supply capacitor C21 of the first-stage ON-side drive circuit 11a, while simultaneously controlling the semiconductor devices 1 to n to be driven to a non-conductive state.

The charging voltages of the first power supply capacitor C11 to the first power supply capacitor C1n and the second power supply capacitor C21 to the second power supply capacitor C2n can be set to any value by changing the turn ratio of the primary winding, secondary winding, and tertiary winding of the first and second transformers Tr1 and Tr2. In addition, the high-voltage side and the low-voltage side can be electrically insulated by using the first and second transformers Tr1 and Tr2.

In addition, the voltage applied to the gate is generally a few tenths of the withstand voltage between the drain and source. Since the voltage applied to the first power supply capacitors C11 to C1n and the second power supply capacitors C21 to C2n is set by the voltage applied to the gate, the withstand voltages of the first to third and fifth switch devices FET1 to FET3 and FET5 that constitute them can be set low accordingly, which allows for lower costs and smaller size compared to Patent Document 1.

The first to nth stage ON-side drive circuits 11a to 1na operate to energize the semiconductor devices 1 to n to be driven while the ON-side transmission circuit 10a is operating and the OFF-side transmission circuit 10b is stopped.

On the other hand, the first to nth stage OFF-side drive circuits 11b to 1nb operate to turn off the semiconductor devices 1 to n to be driven while the ON-side transmission circuit 10a stops operating and the OFF-side transmission circuit 10b is operating.

The operation chart is shown in Figure 4. The following explanation focuses on the ON/OFF operation of the semiconductor device 1 to be driven. When the gate command of the semiconductor device 1 to be driven goes high, the ON-side transmission circuit 10a starts operating and transmits power to the first-stage ON-side drive circuit 11a. Then, the first switch device FET1 and the fifth switch device FET5 become conductive, the first power supply capacitor C11 is connected in parallel to the semiconductor device 1 to be driven, and the semiconductor device 1 to be driven becomes conductive.

When the gate command for the semiconductor device 1 to be driven goes low, the ON-side transmission circuit 10a stops operating and the OFF-side transmission circuit 10b starts operating. Then, the second and third switch devices FET2 and FET3 become conductive, and the second power supply capacitor C21 is connected in inverse parallel to the semiconductor device 1 to be driven, and a voltage equal to the charging voltage of the second power supply capacitor C21 is applied as a negative voltage, turning off the semiconductor device 1 to be driven. The second to nth stages also operate in a similar manner, making it possible to control the ON and OFF of the semiconductor devices 2 to n to be driven.

This allows for bipolar output while maintaining insulation between the high-voltage and low-voltage circuits, and allows for the application of a negative bias, while also realizing an inexpensive, compact gate drive circuit.

[Embodiment 3]
5 shows an example of the circuit configuration of the gate drive circuit in the present embodiment 3. The present embodiment 3 is characterized in that voltage adjustment mechanisms (hereinafter referred to as regulators) 31, 32 are provided between the first and second power supply capacitors C11, C21 and the first and second switch devices FET1, FET2.

As shown in FIG. 5, a third power supply capacitor C31 is connected in parallel to the first power supply capacitor C11. A first regulator 31 is connected between the first power supply capacitor C11 and the second terminal (drain terminal) of the first switch device FET1. A fourth power supply capacitor C41 is connected in parallel to the second power supply capacitor C21. A second regulator 32 is connected between the second power supply capacitor C21 and the third terminal (source terminal) of the second switch device FET2.

In this third embodiment, the third resistor R3 of the second embodiment is omitted. A fourth resistor R4 is connected between the connection point of the tenth, eleventh, and seventh diodes D10, D11, and D7 and the first terminal (gate terminal) of the third switch device FET3 and the second terminal (drain terminal) of the fifth switch device FET5. A fifth resistor R5 is connected between the connection point of the fourth, fifth, and sixth diodes D4, D5, D6, and the first resistor R1 and the first terminal (gate terminal) of the fifth switch device FET5.

The terminal 1 of the first regulator 31 is connected to the first power supply capacitor C11. The terminal 2 of the first regulator 31 is connected to the connection point of the first and second power supply capacitors C11 and C21. The terminal 3 of the first regulator 31 is connected to the second terminal (drain terminal) of the first switch device FET1. The terminal 1 of the second regulator 32 is connected to the second power supply capacitor C21. The terminal 2 of the second regulator 32 is connected to the connection point of the first and second power supply capacitors C11 and C21. The terminal 3 of the second regulator 32 is connected to the third terminal (source terminal) of the second switch device FET2.

Figure 6 shows an example of the configuration of the first and second regulators 31 and 32. The first and second regulators 31 and 32 each include a semiconductor element 41, a reference voltage 42, an amplifier circuit 43, a sixth resistor R6, and a seventh resistor R7.

The second terminal (drain terminal) of the semiconductor element 41 is connected to the first power supply capacitor C11 or the second power supply capacitor C21, and the third terminal (source terminal) is connected to the first switch device FET1 or the second switch device FET2.

One end of the reference voltage 42 is connected to the connection point of the first and second power supply capacitors C11 and C21. The sixth resistor R6 is connected to one end of the reference voltage 42. The seventh resistor R7 is connected between the other end of the sixth resistor R6 and the first switch device FET1 or the second switch device FET2.

The amplifier circuit 43 has an input terminal connected to the other end of the reference voltage 42 and the connection point between the sixth and seventh resistors R6 and R7, and an output terminal connected to the first terminal (gate terminal) of the semiconductor element 41.

The example in Figure 6 is a three-terminal linear regulator, but a switching regulator or the like may be used instead. The positive bias voltage is controlled by the first regulator 31, and the negative bias voltage is controlled by the second regulator 32. This makes it possible to supply a stable voltage to the semiconductor devices 1 to n to be driven, without depending on the characteristics of the element or voltage drops due to wiring impedance.

By stabilizing the voltage applied between the gate and source, it is possible to prevent an increase in loss due to a decrease in the gate-source voltage. Other operations are the same as in embodiment 2, and it is also possible to expand to n stages.

[Embodiment 4]
In the transmission circuit 10 of the first embodiment, the first full bridge circuit is driven to transmit power to be transmitted to the gates of the semiconductor devices 1 to n to be driven and gate signals of the semiconductor devices. In order to prevent DC bias magnetism in the first transformer Tr1, a first DC blocking capacitor C1 is connected between the output of the first full bridge circuit and the first transformer Tr1, but a DC voltage is charged in the first DC blocking capacitor C1 due to the dead time of the first full bridge circuit and variations in voltage drop of the semiconductor switches.

As shown in FIG. 7, the voltage applied to the first transformer Tr1 is the voltage output by the first full bridge circuit minus the voltage Vc of the first DC blocking capacitor C1. If the voltage Vc charged in the first DC blocking capacitor C1 is large, a sufficient voltage is not applied to the first transformer Tr1, and a sufficient voltage is not output to the secondary side of the first transformer Tr1, which delays the turn-on of the first and fifth switch devices FET1 and FET5, causing a decrease in the rise speed of the gate voltage.

In this fourth embodiment, we will explain a gate drive circuit that can operate at high speed regardless of the operating state by controlling the voltage charged to the first DC blocking capacitor C1 through the devised switching pattern of the first full bridge circuit.

Figure 8 shows an example of the configuration of the control circuit in this embodiment 4. The DC blocking capacitor voltage Vc is detected. The comparator 33a judges whether the DC blocking capacitor voltage Vc is greater than 0 (whether the DC blocking capacitor voltage Vc is positive or not). If the DC blocking capacitor voltage Vc is positive, the command generator 34a generates a command to turn the first and fourth semiconductor switches S1 and S4 ON and turn the second and third semiconductor switches S2 and S3 OFF.

The comparator 33b determines whether the DC blocking capacitor voltage Vc is less than 0 (whether the DC blocking capacitor voltage Vc is negative). If the DC blocking capacitor voltage Vc is negative, the command generator 34b generates a command to turn the second and third semiconductor switches S2 and S3 ON and turn the first and fourth semiconductor switches S1 and S4 OFF.

The gate circuit 35 outputs gate signals to the semiconductor switches S1 to S4 according to the commands generated by the command generators 34a and 34b.

The feature of this embodiment 4 is that it detects the DC blocking capacitor voltage Vc and selects the gate signal of the full bridge circuit based on the polarity of the voltage.

When the value of the DC blocking capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on and the second and third semiconductor switches S2 and S3 are turned off. When the value of the DC blocking capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off and the second and third semiconductor switches S2 and S3 are turned on. This makes it possible to always keep the DC blocking capacitor voltage Vc at 0.

Note that, although the configuration in which the present embodiment 4 is applied to the first embodiment has been described, the present embodiment 4 can also be applied to the ON-side transmission circuit 10a and the OFF-side transmission circuit 10b in the second and third embodiments.

As a result, the required voltage can be applied to the transformer without being affected by dead time or semiconductor switch variations, making it possible to improve the turn-on speed of the semiconductor device being driven. This makes it possible to realize a gate drive circuit capable of high-speed operation.

[Embodiment 5]
9 shows an example of the configuration of a control circuit in the fifth embodiment. As shown in FIG. 9, the fifth embodiment adds an averaging processor 36 to the fourth embodiment.

The fifth embodiment is characterized in that the DC blocking capacitor voltage Vc is detected, and the average processing unit 36 filters the DC blocking capacitor voltage Vc using a low-pass filter or performs moving average processing to calculate the average value, and selects the gate signal of the full bridge circuit based on the polarity of the voltage after the processing.

By adding the processing of the average processing unit 36 to the fourth embodiment, it is possible to prevent erroneous judgments due to noise, etc. The other operations are the same as those of the fourth embodiment, and when the value of the DC blocking capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on and the second and third semiconductor switches S2 and S3 are turned off. When the value of the DC blocking capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off and the second and third semiconductor switches S2 and S3 are turned on. This makes it possible to always keep the DC blocking capacitor voltage Vc at 0.

As a result, the necessary voltage can be applied to the pulse transformer without being affected by dead time or element variations, making it possible to improve the turn-on speed of the semiconductor device being driven.

[Embodiment 6]
10 shows an example of the configuration of a control circuit in the sixth embodiment. In the sixth embodiment, a peak detection circuit 37, a first hold circuit 38, a comparator 39, and a second hold circuit 40 are added to the fourth embodiment.

The peak detection circuit 37 in FIG. 10 has the role of detecting the peak of the carrier, and outputs a signal when it detects the peak of the carrier. The first hold circuit 38 updates the output value according to the output of the peak detection circuit 37.

The carrier and its center point (0) are input to the comparator 39, and if the carrier is lower than 0, it outputs high, and if it is higher than 0, it outputs low. The second hold circuit 40 updates the output value at the falling edge or rising edge of the output of the comparator 39.

Therefore, the value of the DC blocking capacitor voltage Vc is sampled at the peak of the carrier, and the switching timing of the first to fourth semiconductor switches S1 to S4 is the zero crossing of the carrier.

By providing the circuit described above, the timing of sampling the DC blocking capacitor voltage Vc and the timing of switching the first to fourth semiconductor switches S1 to S4 are reliably shifted, preventing erroneous judgments due to noise caused by switching.

Other operations are the same as in embodiment 4. When the value of the DC blocking capacitor voltage Vc is positive, the first and fourth semiconductor switches S1 and S4 are turned on and the second and third semiconductor switches S2 and S3 are turned off. When the value of the DC blocking capacitor voltage Vc is negative, the first and fourth semiconductor switches S1 and S4 are turned off and the second and third semiconductor switches S2 and S3 are turned on.

This makes it possible to always keep the DC blocking capacitor voltage Vc at zero. Therefore, the necessary voltage can be applied to the transformer without being affected by dead time or semiconductor element variations, making it possible to improve the turn-on speed of the semiconductor device being driven.

Although the configuration in which embodiment 6 is applied to embodiment 4 has been described, embodiment 6 may also be applied to embodiment 5.

[Embodiment 7]
In Fig. 1, the first full bridge circuit is driven to transmit power and a gate signal to the gate of the semiconductor device to be driven. A first DC blocking capacitor C1 is connected between the first full bridge circuit and the first transformer Tr1 in order to prevent DC bias magnetism of the first transformer Tr1. In the fourth to sixth embodiments, the voltage is fed back so that the time average of the DC blocking capacitor voltage Vc becomes zero regardless of the operating state, and the switching pattern of the first full bridge circuit is controlled to ensure the voltage applied to the first transformer Tr1, thereby realizing stable operation of the gate drive circuit.

However, in the above method, the rate of change of the DC blocking capacitor voltage Vc depends on the magnitude of the excitation inductance of the first transformer Tr1. Therefore, if the excitation inductance of the first transformer Tr1 is large, the current flowing becomes small and the rate of change of the DC blocking capacitor voltage Vc becomes slow.

The switching pattern changes when the polarity of the DC blocking capacitor voltage Vc changes, resulting in a lower switching frequency. When the switching frequency is lowered, the excitation current increases and the residual magnetic flux of the first transformer Tr1 increases, so the time that the output voltage is held becomes longer. This leads to the problem that the gate drive circuit cannot reproduce short pulse widths (i.e., the gate drive circuit cannot operate at high speed).

In this embodiment 7, the switching frequency is increased and the residual magnetic flux of the transformer is controlled to be low without being affected by the circuit parameters, thereby achieving high-speed operation of the gate drive circuit.

The configuration diagram of the control circuit in this embodiment 7 is shown in FIG. 11. The voltage-controlled oscillator (hereinafter referred to as VCO) 44 controls the oscillation frequency by the input voltage. The edge detection unit 45 detects the edge of the off timing of the gate command. The sample-and-hold circuit 46 samples the phase information θ of the output of the VCO 44 when the gate command is off, and outputs it as sampled phase information θ.

The phase determination unit 47 outputs 2π if the sample phase information θ output from the sample hold circuit 46 is π≦θ<2π, and outputs 0 if 0≦θ<π. The output of the phase determination unit 47 is the phase command value. The subtractor 48 calculates the difference between the phase command value and the sample phase information θ. The PI control unit 49 performs PI control based on the phase command value and the sample phase information. Specifically, it performs PI control based on the difference calculated by the subtractor 48, and outputs the resulting voltage to the VCO 44. The output of the VCO 44 is output to the comparators 33a and 33b and the sample hold circuit 46. The comparators 33a and 33b and subsequent steps are the same as in the fourth embodiment.

In the seventh embodiment, the phase information θ of the frequency output by the VCO 44 is sampled and fed back at the off timing of the gate command of the semiconductor device to be driven, thereby controlling the output frequency of the VCO 44 so that the phase information θ becomes 2π or 0. As a result, the output frequency of the VCO 44 is determined by the voltage input to the VCO 44, so the switching frequency can be determined without being affected by circuit parameters such as the excitation inductance, and further, the residual magnetic flux of the first transformer Tr1 is reduced to achieve high-speed operation.

A typical configuration example of the VCO 44 is shown in FIG. 12. As shown in FIG. 12, one end of an eighth resistor R8 is connected to the input terminal Input. In addition, one end of a ninth resistor R9 is connected to the input terminal Input. The other end of the eighth resistor R8 is connected to one input terminal of the first comparator 50. The other end of the ninth resistor R9 is connected to the other input terminal of the first comparator 50. A capacitor 51 is connected between one input terminal and the output terminal of the first comparator 50.

One end of a tenth resistor R10 is connected to one input terminal of the first comparator 50. The other end of the tenth resistor R10 is connected to the second terminal (drain terminal) of the semiconductor switch 52. The third terminal (source terminal) of the semiconductor switch 52 is grounded. An eleventh resistor R11 is connected between the other input terminal of the first comparator 50 and the third terminal (source terminal) of the semiconductor switch 52.

The output terminal of the first comparator 50 is connected to one input terminal of the second comparator 53. One end of the twelfth resistor R12 is connected to the other input terminal of the second comparator 53. The other end of the twelfth resistor R12 is grounded. A thirteenth resistor R13 is connected between the other input terminal of the second comparator 53 and the output terminal of the second comparator 53. A fourteenth resistor R14 is connected between the first terminal (gate terminal) of the semiconductor switch 52 and the output terminal of the second comparator 53. The output of the second comparator 53 is input to the duty ratio correction unit 54. The duty ratio correction unit 54 corrects the duty ratio according to the output of the second comparator 53. The output of the duty ratio correction unit 54 becomes the output of the VCO 44.

Figure 12 is merely a representative example of the VCO 44, and any other device having similar functions can be used instead. Figure 13 shows an example of the characteristics of the VCO 44 assumed in this embodiment 7. As shown in Figure 13, as the input voltage to the VCO 44 increases, the frequency f increases. Note that the output of the VCO 44 is a square wave with a duty of 50%.

The phase determination unit 47 generates a phase command value based on the magnitude of the sampled phase information θ. If the sampled phase information θ is less than π, it outputs 0 as the phase command value, and if the sampled phase information θ is equal to or greater than π, it outputs 2π as the phase command value. The difference between the phase command value (output of the phase determination unit 47) and the sampled phase information θ (phase detection value) is input to the PI controller 49, whose output is input to the VCO 44. The VCO 44 can control the phase information θ to be 0 or 2π at the timing when the gate command is turned off by outputting a frequency based on the input.

This allows the switching frequency to be adjusted to match the gate pulse width of the semiconductor device being driven, and the DC blocking capacitor voltage Vc can be controlled to be 0 when the gate command is turned off, so the residual magnetic flux of the first transformer Tr1 can be suppressed to almost zero, achieving high-speed operation of the gate drive circuit.

As described above, according to the seventh embodiment, by controlling the driving frequency of the gate driving circuit in accordance with the gate command, it is possible to realize a gate driving circuit that can withstand high voltages and operate at high speeds without being affected by circuit constants, etc.

Note that although the seventh embodiment has been described as being applied to the gate drive circuit of the first embodiment, it can also be applied to the gate drive circuits of the second and third embodiments.

[Embodiment 8]
14 shows a configuration diagram of a control circuit according to the eighth embodiment. As in the seventh embodiment, the phase information θ of the frequency output by the VCO 44 is sampled at the off timing of the gate command of the semiconductor device to be driven and fed back, thereby controlling the output frequency of the VCO 44 so that the phase information θ becomes 2π or 0. This reduces the residual magnetic flux of the first transformer Tr1 (second transformer Tr2) and achieves high-speed operation.

The eighth embodiment is characterized by the addition of a capacitor voltage feedback unit 55 to the configuration of the seventh embodiment. The capacitor voltage feedback unit 55 calculates the difference between the voltage command value of the first DC cutting capacitor (the second DC cutting capacitor C2 in the case of the OFF-side transmission circuit 10b) and the voltage detection value in a subtraction unit 56. The PI controller 57 performs PI control based on this difference. The subtractor 48 subtracts the sample phase information θ from the value obtained by adding the phase command value and the output of the PI controller 57. The other configurations are the same as those of the seventh embodiment.

The capacitor voltage feedback unit 55 corrects the input voltage of the VCO 44 so that the DC blocking capacitor voltage vc becomes 0 by inputting 0 as the voltage command value. This makes it possible to correct the dead time for preventing short circuits in the semiconductor switches of the first and second full bridge circuits and the DC components generated due to variations in the semiconductor switches of the first and second full bridge circuits, and to control the frequency so that the DC components become 0. Note that when calculating different physical quantities such as voltage values and phases, unit conversion is performed during the calculation to ensure consistency.

This allows the switching frequency to be adjusted to match the gate pulse width of the semiconductor device being driven without being affected by dead time or semiconductor switch variations, enabling high-speed operation of the gate drive circuit.

Note that, although the eighth embodiment has been described as an example applied to the gate drive circuit of the first embodiment, it can also be applied to the gate drive circuits of the second and third embodiments.

[Embodiment 9]
15 shows a configuration diagram of a control circuit according to the ninth embodiment. As in the seventh embodiment, the phase information θ of the frequency output by the VCO 44 is sampled at the off timing of the gate command of the semiconductor device to be driven and fed back, thereby controlling the output frequency of the VCO 44 so that the phase information θ becomes 2π or 0. This reduces the residual magnetic flux of the first transformer Tr1 (second transformer Tr2) and achieves high-speed operation.

The feature of the ninth embodiment is that a capacitor current feedback unit 58 is added to the configuration of the seventh embodiment. The capacitor current feedback unit 58 calculates the difference between the current command value of the first DC cutting capacitor C1 (the second DC cutting capacitor C2 in the case of the OFF-side transmission circuit 10b) and the current detection value ic in a subtraction unit 59. The PI controller 57 performs PI control based on this difference. The subtractor 48 subtracts the sample phase information θ from the value obtained by adding the phase command value and the output of the PI controller 57. The other configurations are the same as those of the seventh embodiment.

The capacitor current feedback unit 58 corrects the input voltage of the VCO 44 so that the current of the first DC blocking capacitor C1 becomes zero by inputting 0 as the current command value. This makes it possible to correct the dead time for preventing short circuits in the semiconductor switches of the first and second full bridge circuits and the DC components generated due to variations in the semiconductor switches of the first and second full bridge circuits, and to control the frequency so that the DC components become zero.

In the case of embodiment 8, there is a possibility that a surge voltage may be detected during switching, but the effect of this can be mitigated by detecting the current. Note that when calculating different physical quantities such as current values and phases, unit conversion is performed during the calculation to ensure consistency.

This allows the switching frequency to be adjusted to match the gate pulse width of the semiconductor device being driven without being affected by dead time or semiconductor switch variations, enabling high-speed operation of the gate drive circuit.

Note that, although the present embodiment 9 has been described as an example applied to the gate drive circuit of embodiment 1, it can also be applied to the gate drive circuits of embodiments 2 and 3.

Although the present invention has been described in detail above only with respect to the specific examples, it will be clear to those skilled in the art that various modifications and alterations are possible within the scope of the technical concept of the present invention, and it goes without saying that such modifications and alterations fall within the scope of the claims.

1...semiconductor device to be driven 10, 10a, 10b...transmission circuit, ON-side transmission circuit, OFF-side transmission circuit 11 to 1n...1st stage drive circuit to nth stage drive circuit 11a to 1na...1st stage to nth stage ON-side drive circuit (1st stage to nth stage drive circuit)
11b to 1nb... 1st to nth stage OFF side drive circuits Tr1, Tr2... 1st transformer, 2nd transformer D1 to D7... 1st to 7th diodes FET1 to FET5... 1st to 5th switch devices C11, C21... 1st power supply capacitor, 2nd power supply capacitor S1 to S4... 1st to 4th semiconductor switches C1, C2... 1st and 2nd DC blocking capacitors Vin... Input capacitor 31, 32... Regulator (voltage adjustment mechanism)
33a, 33b, 39... Comparators 34a, 34b... Command generation unit 35... Gate circuit 36... Averaging processing unit 37... Peak detection circuit 38, 40... First and second hold circuits 44... Voltage controlled oscillator 45... Edge detection unit 46... Sample and hold circuit 47... Phase determination unit 48... Subtractor 49... PI control unit 50... First comparator 51... Capacitor 52... Semiconductor switch 53... Second comparator 54... Duty ratio correction unit 55... Capacitor voltage feedback unit 56... Subtractor 57... PI controller 58... Capacitor current feedback unit 59... Subtractor

Claims (14)

A gate drive circuit for n series-connected semiconductor devices, comprising:
a transmission unit that transmits a gate signal and power;
a transformer unit including a first transformer having a primary winding connected to the transmission unit;
a drive circuit unit having a first stage drive circuit to an nth stage drive circuit that respectively control the n semiconductor devices;
Each of the first stage drive circuit to the nth stage drive circuit has a plurality of switch devices and first and second power supply capacitors between a secondary winding and a tertiary winding of the first transformer and the semiconductor device to be driven, and when a gate command for the semiconductor device to be driven is high, the plurality of switch devices are controlled to connect the first power supply capacitor in parallel to the semiconductor device to be driven, and when a gate command for the semiconductor device to be driven is low, the plurality of switch devices are controlled to connect the second power supply capacitor in inverse parallel to the semiconductor device to be driven ,
the transmission unit includes a transmission circuit having an input capacitor, a first full-bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full-bridge circuit and a primary winding of the first transformer,
The first stage drive circuit to the nth stage drive circuit each include
a first diode having an anode connected to one end of a secondary winding of the first transformer;
a second diode having an anode connected to the other end of the secondary winding of the first transformer;
a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode;
first and second power supply capacitors connected in series between the cathode of the third diode and a midpoint of the tertiary winding of the first transformer;
a fourth diode having an anode connected to one end of the tertiary winding of the first transformer;
a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer;
a sixth diode having an anode connected to the cathode of the fourth diode and the cathode of the fifth diode and a cathode connected to the connection point of the first and second power supply capacitors;
a first resistor having one end connected to a connection point of the fourth, fifth, and sixth diodes and the other end connected to a midpoint of the tertiary winding of the first transformer;
a first switch device having a first terminal connected to a junction point between the first, second and third diodes, a second terminal connected to a junction point between the third diode and the first power supply capacitor, and a third terminal connected to a first terminal of the semiconductor device to be driven;
a second switch device having a first terminal connected to a connection point of the first, second, and third diodes, a second terminal connected to a first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a third switch device having a second terminal connected to a junction of the first, second and third diodes and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a fourth switch device having a first terminal connected to the junction of the fourth, fifth and sixth diodes, a second terminal connected to the cathode of the sixth diode, and a third terminal connected to the first terminal of the third switch device;
a fifth switch device having a first terminal connected to a junction point of the fourth, fifth and sixth diodes, a second terminal connected to a first terminal of the third switch device, and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a third terminal of the semiconductor device to be driven is connected to a connection point of the first and second power supply capacitors and a midpoint of a secondary winding of the first transformer. A gate drive circuit for n series-connected semiconductor devices, comprising:
a transmission unit that transmits a gate signal and power;
a transformer unit including a first transformer having a primary winding connected to the transmission unit;
a drive circuit unit having a first stage drive circuit to an nth stage drive circuit that respectively control the n semiconductor devices;
Each of the first stage drive circuit to the nth stage drive circuit has a plurality of switch devices and first and second power supply capacitors between a secondary winding and a tertiary winding of the first transformer and the semiconductor device to be driven, and when a gate command for the semiconductor device to be driven is high, the plurality of switch devices are controlled to connect the first power supply capacitor in parallel to the semiconductor device to be driven, and when a gate command for the semiconductor device to be driven is low, the plurality of switch devices are controlled to connect the second power supply capacitor in inverse parallel to the semiconductor device to be driven ,
the transformer unit includes the first transformer and a second transformer,
The transmission unit is
an ON-side transmission circuit including an input capacitor, a first full-bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full-bridge circuit and a primary winding of the first transformer;
an OFF-side transmission circuit including a second full-bridge circuit connected to the input capacitor, and a second DC blocking capacitor connected between the second full-bridge circuit and a primary winding of the second transformer;
the drive circuit section includes the first stage drive circuit to the nth stage drive circuit and a first stage OFF-side drive circuit to an nth stage OFF-side drive circuit,
The first stage drive circuit to the nth stage drive circuit each include
a first diode having an anode connected to one end of a secondary winding of the first transformer;
a second diode having an anode connected to the other end of the secondary winding of the first transformer;
a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode;
first and second power supply capacitors connected in series between the cathode of the third diode and a midpoint of the tertiary winding of the first transformer;
a fourth diode having an anode connected to one end of the tertiary winding of the first transformer;
a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer;
a sixth diode having an anode connected to the cathode of the fourth diode and the cathode of the fifth diode and a cathode connected to the connection point of the first and second power supply capacitors;
a first resistor having one end connected to a connection point of the fourth, fifth, and sixth diodes and the other end connected to a midpoint of the tertiary winding of the first transformer;
a second resistor having one end connected to a connection point of the first, second, and third diodes;
a first switch device having a first terminal connected to the other end of the second resistor, a second terminal connected to a connection point between the third diode and the first power supply capacitor, and a third terminal connected to a first terminal of the semiconductor device to be driven;
a second switch device having a first terminal connected to the other end of the second resistor, a second terminal connected to a first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a third switch device having a second terminal connected to the other end of the second resistor and a third terminal connected to a midpoint of the tertiary winding of the first transformer;
a seventh diode having an anode connected to the first terminal of the third switch device and a cathode connected to the cathode of the sixth diode;
a fifth switch device having a first terminal connected to a junction point of the fourth, fifth, and sixth diodes and a third terminal connected to a midpoint of the tertiary winding of the first transformer;
a third terminal of the semiconductor device to be driven is connected to a connection point of the first and second power supply capacitors and a midpoint of a secondary winding of the first transformer;
The first stage OFF-side driving circuit to the nth stage OFF-side driving circuit each include
an eighth diode having an anode connected to one end of the secondary winding of the second transformer and a cathode connected to a connection point between the third diode and the first power supply capacitor;
a ninth diode having an anode connected to the other end of the secondary winding of the second transformer and a cathode connected to a connection point between the third diode and the first power supply capacitor;
a tenth diode having an anode connected to one end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device;
an eleventh diode having an anode connected to the other end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device;
a midpoint of a secondary winding of the second transformer is connected to a midpoint of a secondary winding of the first transformer, and a midpoint of a tertiary winding of the second transformer is connected to a midpoint of a tertiary winding of the first transformer. 3. The gate drive circuit of claim 2, further comprising a third resistor connected between the second terminal of the fifth switch device and the first terminal of the third switch device. a first voltage regulation mechanism between the first switch device and the first source capacitor;
4. The gate drive circuit according to claim 1, further comprising a second voltage adjustment mechanism provided between the second switch device and the second power supply capacitor. The first and second voltage adjustment mechanisms include
a semiconductor device having a second terminal connected to the first power supply capacitor or the second power supply capacitor and a third terminal connected to the first switch device or the second switch device;
a reference voltage having one end connected to the junction of the first and second power supply capacitors;
A sixth resistor connected to one end of the reference voltage;
a seventh resistor connected between the other end of the sixth resistor and the first switch device or the second switch device;
an amplifier circuit having an input terminal connected to the other end of the reference voltage and the connection point between the sixth and seventh resistors and an output terminal connected to the first terminal of the semiconductor element;
5. The gate drive circuit according to claim 4, further comprising: the first and second full bridge circuits include first and second semiconductor switches connected in series across the input capacitor, and third and fourth semiconductor switches connected in series across the input capacitor, a connection point of the third and fourth semiconductor switches is connected to one end of a primary winding of the first transformer or one end of a primary winding of the second transformer via the first DC blocking capacitor or the second DC blocking capacitor, and a connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer,
The control circuit includes:
When the voltages of the first and second DC blocking capacitors are positive, the first and fourth semiconductor switches are turned ON and the second and third semiconductor switches are turned OFF;
A gate drive circuit as described in any one of claims 1 to 5, characterized in that when the voltages of the first and second DC blocking capacitors are negative, the first and fourth semiconductor switches are turned OFF and the second and third semiconductor switches are turned ON. 7. The gate drive circuit according to claim 6 , wherein the voltages of the first and second DC blocking capacitors are values that have been subjected to low-pass filtering or moving average processing. The timing of sampling the voltages of the first and second DC blocking capacitors is the timing of the peak of a carrier.
8. The gate drive circuit according to claim 6 , wherein the switching timing of the first to fourth semiconductor switches is set to the zero cross timing of the carrier. the first and second full bridge circuits include first and second semiconductor switches connected in series across the input capacitor, and third and fourth semiconductor switches connected in series across the input capacitor, a connection point of the third and fourth semiconductor switches is connected to one end of a primary winding of the first transformer or one end of a primary winding of the second transformer via the first DC blocking capacitor or the second DC blocking capacitor, and a connection point of the first and second semiconductor switches is connected to the other end of the primary winding of the first transformer or the other end of the primary winding of the second transformer,
The control circuit includes:
a voltage controlled oscillator that controls an oscillation frequency according to an input voltage;
a sample-and-hold circuit that samples and holds phase information of the output of the voltage-controlled oscillator when the gate command is off, and outputs the sampled phase information;
a phase determination unit that outputs 2π as a phase command value when the sample phase information is equal to or greater than π and less than 2π, and outputs 0 as the phase command value when the sample phase information is equal to or greater than 0 and less than π;
a PI controller that performs PI control based on the phase command value and the sampled phase information and outputs a voltage resulting from the PI control to the voltage controlled oscillator;
Equipped with
When the output of the voltage controlled oscillator is positive, the first and fourth semiconductor switches are turned ON and the second and third semiconductor switches are turned OFF;
A gate drive circuit as described in any one of claims 1 to 5, characterized in that when the output of the voltage-controlled oscillator is negative, the first and fourth semiconductor switches are turned OFF and the second and third semiconductor switches are turned ON. The control circuit includes:
a capacitor voltage feedback unit that performs PI control based on a difference between a voltage command value and a voltage detection value of the first DC blocking capacitor or the second DC blocking capacitor,
10. The gate drive circuit according to claim 9, wherein the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor voltage feedback unit. The control circuit includes:
a capacitor current feedback unit that performs PI control based on a difference between a current command value and a current detection value of the first DC blocking capacitor or the second DC blocking capacitor,
10. The gate drive circuit according to claim 9, wherein the PI controller performs PI control based on a value obtained by subtracting the sample phase information from a value obtained by adding the phase command value and the output of the capacitor current feedback unit. The voltage controlled oscillator comprises:
an eighth resistor having one end connected to the input terminal;
a ninth resistor having one end connected to the input terminal;
a first comparator having one input terminal connected to the other end of the eighth resistor and having the other input terminal connected to the other end of the ninth resistor;
a capacitor connected between one input terminal and an output terminal of the first comparator;
a tenth resistor having one end connected to one input terminal of the first comparator;
a semiconductor switch having a second terminal connected to the other end of the tenth resistor and a third terminal grounded;
an eleventh resistor connected between the other input terminal of the first comparator and a third terminal of the semiconductor switch;
a second comparator having one input terminal connected to the output of the first comparator;
a twelfth resistor, one end of which is connected to the other input terminal of the second comparator and the other end of which is grounded;
a thirteenth resistor connected between the output terminal and the other input terminal of the second comparator;
a fourteenth resistor connected between the first terminal of the semiconductor device and the output terminal of the second comparator;
12. The gate drive circuit according to claim 10, further comprising: a duty ratio correction section that corrects a duty ratio in accordance with an output of the second comparator. a transmission section that transmits a gate signal and power, a transformer section having a first transformer with a primary winding connected to the transmission section, and a drive circuit section having first stage drive circuit to nth stage drive circuit that control n semiconductor devices, respectively, wherein the first stage drive circuit to nth stage drive circuit each include a plurality of switch devices and first and second power supply capacitors between a secondary winding and a tertiary winding of the first transformer and the semiconductor device to be driven,
the transmission unit includes a transmission circuit having an input capacitor, a first full-bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full-bridge circuit and a primary winding of the first transformer,
The first stage drive circuit to the nth stage drive circuit each include
a first diode having an anode connected to one end of a secondary winding of the first transformer;
a second diode having an anode connected to the other end of the secondary winding of the first transformer;
a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode;
first and second power supply capacitors connected in series between the cathode of the third diode and a midpoint of the tertiary winding of the first transformer;
a fourth diode having an anode connected to one end of the tertiary winding of the first transformer;
a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer;
a sixth diode having an anode connected to the cathode of the fourth diode and the cathode of the fifth diode and a cathode connected to the connection point of the first and second power supply capacitors;
a first resistor having one end connected to a connection point of the fourth, fifth, and sixth diodes and the other end connected to a midpoint of the tertiary winding of the first transformer;
a first switch device having a first terminal connected to a junction point between the first, second and third diodes, a second terminal connected to a junction point between the third diode and the first power supply capacitor, and a third terminal connected to a first terminal of the semiconductor device to be driven;
a second switch device having a first terminal connected to a connection point of the first, second, and third diodes, a second terminal connected to a first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a third switch device having a second terminal connected to a junction of the first, second and third diodes and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a fourth switch device having a first terminal connected to the junction of the fourth, fifth and sixth diodes, a second terminal connected to the cathode of the sixth diode, and a third terminal connected to the first terminal of the third switch device;
a fifth switch device having a first terminal connected to a junction point of the fourth, fifth and sixth diodes, a second terminal connected to a first terminal of the third switch device, and a third terminal connected to a midpoint of the tertiary winding of the first transformer;
a third terminal of the semiconductor device to be driven is connected to a connection point of the first and second power supply capacitors and a midpoint of a secondary winding of the first transformer ,
a first stage drive circuit that controls the first to n-th stage drive circuits to connect the first power supply capacitor in parallel to the semiconductor device to be driven when a gate command for the semiconductor device to be driven is high, and to connect the second power supply capacitor in inverse parallel to the semiconductor device to be driven when a gate command for the semiconductor device to be driven is low. a transmission section that transmits a gate signal and power, a transformer section having a first transformer with a primary winding connected to the transmission section, and a drive circuit section having first stage drive circuit to nth stage drive circuit that control n semiconductor devices, respectively, wherein the first stage drive circuit to nth stage drive circuit each include a plurality of switch devices and first and second power supply capacitors between a secondary winding and a tertiary winding of the first transformer and the semiconductor device to be driven,
the transformer unit includes the first transformer and a second transformer,
The transmission unit is
an ON-side transmission circuit including an input capacitor, a first full-bridge circuit connected to the input capacitor, and a first DC blocking capacitor connected between the first full-bridge circuit and a primary winding of the first transformer;
an OFF-side transmission circuit including a second full-bridge circuit connected to the input capacitor, and a second DC blocking capacitor connected between the second full-bridge circuit and a primary winding of the second transformer;
the drive circuit section includes the first stage drive circuit to the nth stage drive circuit and a first stage OFF-side drive circuit to an nth stage OFF-side drive circuit,
The first stage drive circuit to the nth stage drive circuit each include
a first diode having an anode connected to one end of a secondary winding of the first transformer;
a second diode having an anode connected to the other end of the secondary winding of the first transformer;
a third diode having an anode connected to the cathode of the first diode and the cathode of the second diode;
first and second power supply capacitors connected in series between the cathode of the third diode and a midpoint of the tertiary winding of the first transformer;
a fourth diode having an anode connected to one end of the tertiary winding of the first transformer;
a fifth diode having an anode connected to the other end of the tertiary winding of the first transformer;
a sixth diode having an anode connected to the cathode of the fourth diode and the cathode of the fifth diode and a cathode connected to the connection point of the first and second power supply capacitors;
a first resistor having one end connected to a connection point of the fourth, fifth, and sixth diodes and the other end connected to a midpoint of the tertiary winding of the first transformer;
a second resistor having one end connected to a connection point of the first, second, and third diodes;
a first switch device having a first terminal connected to the other end of the second resistor, a second terminal connected to a connection point between the third diode and the first power supply capacitor, and a third terminal connected to a first terminal of the semiconductor device to be driven;
a second switch device having a first terminal connected to the other end of the second resistor, a second terminal connected to a first terminal of the semiconductor device to be driven, and a third terminal connected to a midpoint of a tertiary winding of the first transformer;
a third switch device having a second terminal connected to the other end of the second resistor and a third terminal connected to a midpoint of the tertiary winding of the first transformer;
a seventh diode having an anode connected to the first terminal of the third switch device and a cathode connected to the cathode of the sixth diode;
a fifth switch device having a first terminal connected to a junction point of the fourth, fifth, and sixth diodes and a third terminal connected to a midpoint of the tertiary winding of the first transformer;
a third terminal of the semiconductor device to be driven is connected to a connection point of the first and second power supply capacitors and a midpoint of a secondary winding of the first transformer;
The first stage OFF-side driving circuit to the nth stage OFF-side driving circuit each include
an eighth diode having an anode connected to one end of the secondary winding of the second transformer and a cathode connected to a connection point between the third diode and the first power supply capacitor;
a ninth diode having an anode connected to the other end of the secondary winding of the second transformer and a cathode connected to a connection point between the third diode and the first power supply capacitor;
a tenth diode having an anode connected to one end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device;
an eleventh diode having an anode connected to the other end of the tertiary winding of the second transformer and a cathode connected to the first terminal of the third switch device;
A method for controlling a gate drive circuit, in which a midpoint of a secondary winding of the second transformer is connected to a midpoint of a secondary winding of the first transformer, and a midpoint of a tertiary winding of the second transformer is connected to a midpoint of a tertiary winding of the first transformer ,
a first stage drive circuit that controls a first power supply capacitor in parallel to the semiconductor device to be driven when a gate command for the semiconductor device to be driven is high, and a second stage drive circuit that controls a first stage drive circuit that controls a second stage drive circuit that connects the first power supply capacitor in parallel to the semiconductor device to be driven when a gate command for the semiconductor device to be driven is low.

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