JP7548072B2 - Power Conversion Equipment - Google Patents

Description

The present invention relates to a power conversion device.

Conventionally, power conversion devices equipped with a transformer having a primary winding and a secondary winding have been known (see, for example, Patent Document 1). The power conversion device described in Patent Document 1 includes a primary full-bridge circuit having a plurality of primary switching elements, a secondary full-bridge circuit having a plurality of secondary switching elements, and a control circuit that controls each switching element.

JP 2018-26961 A

Here, for example, depending on the object or situation to which the power conversion device is applied, the magnitude relationship between the input voltage input to the primary side full bridge circuit and the output voltage output from the secondary side full bridge circuit may change. In this case, if the control mode for controlling each switching element is changed depending on the magnitude relationship, the control may become complicated.

A power conversion device that achieves the above object includes a transformer having a primary winding and a secondary winding, a primary full bridge circuit that is connected to the primary winding and has a plurality of primary switching elements and a plurality of primary capacitors connected in parallel to the plurality of primary switching elements, a secondary full bridge circuit that is connected to the secondary winding and has a plurality of secondary switching elements and a plurality of secondary capacitors that are connected in parallel to the plurality of secondary switching elements and have a different capacity from the primary capacitors, and a control circuit that converts an input voltage input to the primary full bridge circuit into an output voltage output from the secondary full bridge circuit by controlling each of the switching elements, and the control circuit The circuit has a double-sided PWM control mode in which the primary side voltage input to the primary winding is switched to positive, negative, or 0, and the secondary side voltage input to the secondary winding is switched to positive, negative, or 0, as a control mode for periodically controlling each of the switching elements, and the double-sided PWM control mode includes an inversion period in which the polarity of the primary side voltage and the secondary side voltage are inverted, and the control circuit controls each of the switching elements in the double-sided PWM control mode so that the magnitude of the primary side current flowing through the primary side winding at the start timing of the inversion period is equal to or greater than a primary side threshold, and the magnitude of the secondary side current flowing through the secondary side winding at the end timing of the inversion period is equal to or greater than a secondary side threshold different from the primary side threshold.

According to this configuration, by adopting the double-sided PWM control mode as the control mode, voltage conversion can be performed regardless of the magnitude relationship between the input voltage and the output voltage. This eliminates the need to switch between different control modes depending on the magnitude relationship between the input voltage and the output voltage, reducing the complexity of control that accompanies changes in the magnitude relationship between the input voltage and the output voltage.

The primary side threshold and secondary side threshold are different in response to the difference in capacitance between the primary side capacitor and the secondary side capacitor. The control circuit controls each switching element so that the magnitude of the primary side current flowing through the primary side winding at the start timing of the inversion period is equal to or greater than the primary side threshold, and the magnitude of the secondary side current flowing through the secondary side winding at the end timing of the inversion period is equal to or greater than the secondary side threshold, thereby performing soft switching. This allows soft switching to be performed in the double-sided PWM control mode under conditions where the capacitance of the primary side capacitor and the capacitance of the secondary side capacitor are different.

In the above power conversion device, it is preferable that a capacitance of the primary side capacitor is larger than a capacitance of the secondary side capacitor, and the primary side threshold value is larger than the secondary side threshold value.
According to this configuration, the primary side threshold is larger than the secondary side threshold in correspondence with the fact that the capacitance of the primary side capacitor is larger than the capacitance of the secondary side capacitor, so that a primary side current capable of charging and discharging the primary side capacitor can be secured at the start timing of the inversion period, thereby realizing soft switching.

For the above power conversion device, when the primary side threshold is greater than the secondary side threshold, the control circuit may set the inversion period to a value corresponding to the primary side threshold by controlling the duty ratio of the primary side voltage.

According to this configuration, the duty ratio of the primary voltage is controlled to set an inversion period corresponding to the primary threshold. This allows the magnitude of the primary current at the start timing of the inversion period to be equal to or greater than the primary threshold. Therefore, the above-mentioned effects can be obtained.

In the above power conversion device, it is preferable that a capacitance of the secondary side capacitor is larger than a capacitance of the primary side capacitor, and the secondary side threshold value is larger than the primary side threshold value.
According to this configuration, the secondary side threshold is larger than the primary side threshold in correspondence with the fact that the capacitance of the secondary side capacitor is larger than the capacitance of the primary side capacitor, so that a secondary side current capable of charging and discharging the secondary side capacitor at the end timing of the inversion period can be secured, thereby realizing soft switching.

For the above power conversion device, when the secondary side threshold is greater than the primary side threshold, the control circuit may set the inversion period to a value corresponding to the secondary side threshold by controlling the duty ratio of the secondary side voltage.

According to this configuration, the duty ratio of the secondary voltage is controlled to set an inversion period corresponding to the secondary threshold. This allows the magnitude of the secondary current at the end timing of the inversion period to be equal to or greater than the secondary threshold. Therefore, the above-mentioned effects can be obtained.

In the above power conversion device, the control circuit may control the output current from the secondary full bridge circuit by controlling the inversion period within a range in which the magnitude of the primary side current at the start timing of the inversion period is equal to or greater than the primary side threshold value, and the magnitude of the secondary side current at the end timing of the inversion period is equal to or greater than the secondary side threshold value, in the double-sided PWM control mode.

This configuration allows the output current to be controlled while performing soft switching.

This invention reduces the complexity of control that accompanies changes in the magnitude relationship between the input voltage and the output voltage.

FIG. 2 is a circuit diagram showing the electrical configuration of the power conversion device and the power supply system. 1A is a graph showing a primary side voltage, and FIG. 1B is a graph showing a secondary side voltage. FIG. 4 is a diagram showing switching patterns of each switching element in a double-sided PWM control mode. 4 is a flowchart showing a double-sided PWM control mode process. 1A is a graph showing a primary voltage; FIG. 1B is a graph showing a secondary voltage; FIG. 1C is a graph showing a primary current and a secondary current; and FIG. 1A is a graph showing a primary voltage; FIG. 1B is a graph showing a secondary voltage; FIG. 1C is a graph showing a primary current and a secondary current; and FIG.

Hereinafter, an embodiment of a power conversion device and a power supply system including the power conversion device will be described.
1, the power supply system 100 includes a DC power supply 110, a load 120, and a power conversion device 10. The DC power supply 110 is a voltage source that outputs a DC voltage. The load 120 is, for example, a power storage device that can charge and discharge DC power, and one example of the load 120 is a secondary battery. The secondary battery is, for example, a lithium ion battery or a lead storage battery.

The power conversion device 10 of this embodiment is a so-called dual active bridge type DC/DC converter. The power conversion device 10 is provided between a DC power source 110 and a load 120. The power conversion device 10 can convert the power of the DC power source 110 and output it to the load 120. The power conversion device 10 can also convert the power of the load 120 and output it to the DC power source 110. In the following description, the primary side is treated as the input and the secondary side is treated as the output. In other words, the power conversion device 10 converts the DC voltage input from the DC power source 110 and outputs it to the load 120.

The power conversion device 10 includes a transformer 20 , a primary side full bridge circuit 30 , a secondary side full bridge circuit 40 , and a control circuit 50 .
The transformer 20 has a magnetic core 21, and a primary winding 22 and a secondary winding 23 wound around the core 21. That is, the transformer 20 is a so-called insulated type. The transformer 20 has a reactor L. The reactor L may be an element such as a choke coil, or may be a leakage inductance of the primary winding 22 and the secondary winding 23.

The primary-side full-bridge circuit 30 has a plurality of primary-side switching elements, namely, a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. The primary-side full-bridge circuit 30 also has a plurality of primary-side diodes D1 to D4, and a plurality of primary-side capacitors C1 to C4.

In this embodiment, n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the primary side switching elements Q1 to Q4. However, this is not limited to this, and other switching elements such as p-type MOSFETs and IGBTs (Insulated Gate Bipolar Transistors) may also be used.

The four primary side switching elements Q1 to Q4 constitute a first leg 31 and a second leg 32. The first leg 31 is a series connection in which the source of the first switching element Q1 and the drain of the second switching element Q2 are connected by a first connection line 33. The second leg 32 is a series connection in which the source of the third switching element Q3 and the drain of the fourth switching element Q4 are connected by a second connection line 34. The first leg 31 and the second leg 32 are connected to the primary side terminals 35, 36 so as to be connected in parallel with each other. In other words, it can be said that the primary side full bridge circuit 30 is connected to the primary side terminals 35, 36. At this time, the first switching element Q1 and the third switching element Q3 constitute the upper arm, and the second switching element Q2 and the fourth switching element Q4 constitute the lower arm.

The primary side diodes D1 to D4 and the primary side capacitors C1 to C4 are connected in parallel with the primary side switching elements Q1 to Q4, respectively. The primary side diodes D1 to D4 may be parasitic diodes or elements. The primary side diodes D1 to D4 are connected in reverse to the primary side switching elements Q1 to Q4. The primary side capacitors C1 to C4 may be parasitic capacitance, elements, or a combination of parasitic capacitance and elements.

The primary full bridge circuit 30 is connected to the primary winding 22 of the transformer 20. In particular, the first connection line 33 and the second connection line 34 of the primary full bridge circuit 30 are each connected to the primary winding 22. Therefore, a voltage V1 equal to the potential difference between the second connection line 34 and the first connection line 33 is applied to the primary winding 22. In the following description, the voltage V1 applied to the primary winding 22 may be referred to as the "primary voltage V1." Note that the primary voltage V1 is positive when the potential of the first connection line 33 is higher than the potential of the second connection line 34.

The DC power supply 110 is connected to the primary terminals 35 and 36. Therefore, the primary full bridge circuit 30 is connected to the DC power supply 110 via the primary terminals 35 and 36.

The primary voltage sensor 37 is a voltmeter for measuring the input voltage Vin input to the primary full bridge circuit 30. The primary voltage sensor 37 is connected to the primary terminals 35 and 36 in parallel with the primary full bridge circuit 30.

The primary side current sensor 38 is an ammeter for measuring the input current Iin from the DC power supply 110 to the primary side full bridge circuit 30. The primary side current sensor 38 can be of any type, such as a shunt resistor or a Hall element.

The secondary full bridge circuit 40 has a plurality of secondary switching elements, namely a fifth switching element Q5, a sixth switching element Q6, a seventh switching element Q7, and an eighth switching element Q8. The secondary full bridge circuit 40 also has a plurality of secondary diodes D5 to D8, and a plurality of secondary capacitors C5 to C8.

In this embodiment, n-type MOSFETs are used as the secondary side switching elements Q5 to Q8, but other switching elements such as p-type MOSFETs or IGBTs may also be used.

The four secondary side switching elements Q5 to Q8 constitute a third leg 41 and a fourth leg 42. The third leg 41 is a series connection in which the source of the fifth switching element Q5 and the drain of the sixth switching element Q6 are connected by a third connection line 43. The fourth leg 42 is a series connection in which the source of the seventh switching element Q7 and the drain of the eighth switching element Q8 are connected by a fourth connection line 44. The third leg 41 and the fourth leg 42 are connected to the secondary side terminals 45, 46 so as to be connected in parallel with each other. In other words, it can be said that the secondary side full bridge circuit 40 is connected to the secondary side terminals 45, 46. At this time, the fifth switching element Q5 and the seventh switching element Q7 constitute the upper arm, and the sixth switching element Q6 and the eighth switching element Q8 constitute the lower arm.

The secondary side diodes D5 to D8 and the secondary side capacitors C5 to C8 are connected in parallel to the secondary side switching elements Q5 to Q8, respectively. The secondary side diodes D5 to D8 may be parasitic diodes or elements. The secondary side diodes D5 to D8 are connected in reverse to the secondary side switching elements Q5 to Q8. The secondary side capacitors C5 to C8 may be parasitic capacitance, elements, or a combination of parasitic capacitance and elements. That is, the multiple capacitors C1 to C8 are connected in parallel to the multiple primary side switching elements Q1 to Q4 and the multiple secondary side switching elements Q5 to Q8, respectively.

In this embodiment, the capacitance of the primary side capacitors C1 to C4 is different from the capacitance of the secondary side capacitors C5 to C8. For example, the capacitance of the primary side capacitors C1 to C4 may be greater than the capacitance of the secondary side capacitors C5 to C8. Alternatively, the capacitance of the secondary side capacitors C5 to C8 may be greater than the capacitance of the primary side capacitors C1 to C4.

An example of a factor that causes the capacitance of the primary side capacitors C1 to C4 to differ from the capacitance of the secondary side capacitors C5 to C8 will be described. For example, if the turns ratio of the transformer 20 is other than 1, the current flowing through the primary side full bridge circuit 30 may differ from the current flowing through the secondary side full bridge circuit 40. In this case, elements with different specifications may be used for the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8 to correspond to the turns ratio. Then, the capacitance of the primary side capacitors C1 to C4 may differ from the capacitance of the secondary side capacitors C5 to C8. Note that the different specifications may be, for example, different rated currents for the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8.

The third connection line 43 and the fourth connection line 44 of the secondary full bridge circuit 40 are each connected to the secondary winding 23. Therefore, a voltage V2 equal to the potential difference between the third connection line 43 and the fourth connection line 44 is applied to the secondary winding 23. In the following description, the voltage V2 applied to the secondary winding 23 may be referred to as the "secondary voltage V2." Note that the secondary voltage V2 is positive when the potential of the third connection line 43 is higher than the potential of the fourth connection line 44.

The secondary side terminals 45, 46 are used to connect the power conversion device 10 and the load 120. When the load 120 is connected to the secondary side terminals 45, 46, the secondary side full bridge circuit 40 is connected to the load 120 via the secondary side terminals 45, 46. Note that the power conversion device 10 only needs to be connectable to the load 120. However, this is not limited, and the power conversion device 10 may also be configured to include the load 120.

The secondary voltage sensor 47 is a voltmeter for measuring the output voltage Vout output from the secondary full bridge circuit 40. The secondary voltage sensor 47 is connected to the secondary terminals 45 and 46 in parallel with the secondary full bridge circuit 40.

When the load 120 is a power storage device, when the load 120 is connected to the secondary terminals 45, 46, the secondary voltage sensor 47 detects the voltage of the load 120 as the output voltage Vout.

The secondary current sensor 48 is an ammeter for measuring the output current Iout output from the secondary full bridge circuit 40. The secondary current sensor 48 can be of any type, such as a shunt resistor or a Hall element.

The control circuit 50 is connected to both voltage sensors 37, 47 and to both current sensors 38, 48. The control circuit 50 obtains the input voltage Vin from the primary voltage sensor 37 and the output voltage Vout from the secondary voltage sensor 47. The control circuit 50 obtains the input current Iin from the primary current sensor 38 and the output current Iout from the secondary current sensor 48.

The control circuit 50 converts the input voltage Vin into an output voltage Vout by periodically controlling the multiple primary side switching elements Q1 to Q4 and the multiple secondary side switching elements Q5 to Q8. In this embodiment, the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8 are both switched and controlled at a predetermined period T.

The specific hardware configuration of the control circuit 50 is arbitrary. For example, the control circuit 50 may be configured to have a dedicated hardware circuit for performing switching control. For example, the control circuit 50 may be configured to have a memory that stores a control program and necessary information for performing switching control, and a CPU that performs switching control based on the control program.

Next, we will explain the control modes that control the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8. In the following explanation, each diode D1 to D8 may be referred to as the "nth diode Dn" and each capacitor C1 to C8 may be referred to as the "nth capacitor Cn." Note that n is a natural number from 1 to 8.

The control circuit 50 of this embodiment has a double-sided PWM control mode as a control mode for controlling the switching elements Q1 to Q8. The double-sided PWM control mode will be described.
2(a) and 2(b), the double-sided PWM control mode is a mode in which both the primary side voltage V1 and the secondary side voltage V2 are switched to positive, negative, or 0. In this case, it can be said that the primary side voltage V1 and the secondary side voltage V2 are periodically switched to positive, negative, or 0 with a predetermined duty ratio.

When the secondary voltage V2 is "0", the output current Iout is "0". Therefore, the double-sided PWM control mode can be said to be a type of control mode that has a period during which the output current Iout is "0" within one cycle.

As shown in FIG. 3, in the double-sided PWM control mode, for example, a first pattern P1, a second pattern P2, a third pattern P3, a fourth pattern P4, a fifth pattern P5, a sixth pattern P6, a seventh pattern P7, and an eighth pattern P8 are set as the switching patterns of each of the switching elements Q1 to Q8. Note that in the following description, the switching patterns of each of the switching elements Q1 to Q8 may be simply referred to as "switching patterns."

As shown in FIG. 3, the first pattern P1 is a switching pattern in which the switching elements Q1, Q4, Q6, and Q7 are in the ON state, and the switching elements Q2, Q3, Q5, and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is positive and the secondary voltage V2 is negative.

As shown in FIG. 3, the second pattern P2 is a switching pattern in which the switching elements Q1, Q4, Q6, and Q8 are in the ON state, and the switching elements Q2, Q3, Q5, and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is positive, and the secondary voltage V2 is "0".

As shown in FIG. 3, the third pattern P3 is a switching pattern in which switching elements Q1, Q4, Q5, and Q8 are in the ON state, and switching elements Q2, Q3, Q6, and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is positive, and the secondary voltage V2 is positive.

As shown in FIG. 3, the fourth pattern P4 is a switching pattern in which switching elements Q1, Q3, Q5, and Q8 are in the ON state, and switching elements Q2, Q4, Q6, and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is "0" and the secondary voltage V2 is positive.

As shown in FIG. 3, the fifth pattern P5 is a switching pattern in which switching elements Q2, Q3, Q5, and Q8 are in the ON state, and switching elements Q1, Q4, Q6, and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is negative and the secondary voltage V2 is positive.

As shown in FIG. 3, the sixth pattern P6 is a switching pattern in which the switching elements Q2, Q3, Q5, and Q7 are in the ON state, and the switching elements Q1, Q4, Q6, and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is negative, and the secondary voltage V2 is "0".

As shown in FIG. 3, the seventh pattern P7 is a switching pattern in which switching elements Q2, Q3, Q6, and Q7 are in the ON state, and switching elements Q1, Q4, Q5, and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is negative, and the secondary voltage V2 is negative.

As shown in FIG. 3, the eighth pattern P8 is a switching pattern in which the switching elements Q2, Q4, Q6, and Q7 are in the ON state, and the switching elements Q1, Q3, Q5, and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary voltage V1 is "0" and the secondary voltage V2 is negative.

In the double-sided PWM control mode, the control circuit 50 repeats a unit operation of sequentially switching the switching pattern in the order of P1→P2→P3→P4→P5→P6→P7→P8 in a cycle T. This causes the primary voltage V1 and the secondary voltage V2 to change sequentially with a predetermined phase difference, and voltage conversion (in other words, power conversion) is performed. In this case, the control circuit 50 can be said to control the primary full bridge circuit 30 and the secondary full bridge circuit 40 with a phase difference.

In particular, in the double-sided PWM control mode, by controlling each switching element Q1 to Q8, voltage conversion can be performed regardless of the magnitude relationship between the input voltage Vin and the output voltage Vout. In other words, the double-sided PWM control mode is a control mode that allows voltage increase and decrease.

Here, in the double-sided PWM control mode, patterns P1 to P4 are a half cycle (T/2), and patterns P5 to P8 are a half cycle (T/2). Patterns P1 to P4 and patterns P5 to P8 are the same except for the polarity being reversed. For this reason, patterns P1 to P4 will be described in detail below, and the specific control modes of patterns P5 to P8 will not be described.

As shown in FIG. 2, the double-sided PWM control mode includes an inversion period Φ during which the polarity of the primary side voltage V1 and the secondary side voltage V2 is inverted. In detail, the double-sided PWM control mode is composed of an inversion period Φ and a transmission period W. The transmission period W is a period other than the inversion period Φ in a half cycle. In this embodiment, the inversion period Φ is a period during which the first pattern P1 is set, and the transmission period W is a period during which the patterns P2 to P4 are set.

The transmission period W includes an input period T1 during which the primary voltage V1 is positive, and an output period T2 during which the secondary voltage V2 is positive. The input period T1 is the period during which patterns P2 and P3 are set, and the output period T2 is the period during which patterns P3 and P4 are set. In other words, the period during which the third pattern P3 is set is included in both the input period T1 and the output period T2.

In the double-sided PWM control mode, the output current Iout depends on the inversion period Φ and both periods T1 and T2. Therefore, the control circuit 50 can control the output current Iout by controlling the inversion period Φ and both periods T1 and T2. The inversion period Φ and both periods T1 and T2 depend, for example, on the phase difference between the primary full bridge circuit 30 and the secondary full bridge circuit 40 (in other words, the phase difference between the primary voltage V1 and the secondary voltage V2), the duty ratio of the primary switching elements Q1 to Q4, and the duty ratio of the secondary switching elements Q5 to Q8. Therefore, the control circuit 50 may control the inversion period Φ and both periods T1 and T2 by controlling, for example, the above parameters, thereby controlling the output current Iout. The parameters for controlling the inversion period Φ and both periods T1 and T2 are not limited to those described above, and may be, for example, the phase difference between the first leg 31 and the second leg 32, or the phase difference between the third leg 41 and the fourth leg 42.

The inversion period Φ in patterns P5 to P8 is the period in which the fifth pattern P5 is set, and the transmission period W is the period in which patterns P6 to P8 are set. Since the polarity of patterns P1 to P4 and patterns P5 to P8 are inverted, in patterns P5 to P8, the input period T1 is the period in which the primary voltage V1 is negative, and the output period T2 is the period in which the secondary voltage V2 is negative.

As shown in FIG. 1, the control circuit 50 is configured to be able to communicate with a load control device 121 that controls the load 120. When the control circuit 50 receives the required power Pr from the load control device 121, it executes a double-sided PWM control mode process so that the required power Pr can be supplied to the load 120 in the double-sided PWM control mode.

The double-sided PWM control mode process will be described with reference to FIG.
4, in step S101, the control circuit 50 sets a target current It based on the required power Pr and the detection result of the secondary voltage sensor 47. Then, in step S102, the control circuit 50 derives the target current It and the inversion period Φ and both periods T1 and T2 that satisfy the soft switching condition.

Now, the soft switching conditions will be explained using FIG. 5. FIG. 5(a) shows the waveform of the primary voltage V1, FIG. 5(b) shows the waveform of the secondary voltage V2, FIG. 5(c) shows the waveforms of the primary current IL and the secondary current IS, and FIG. 5(d) shows the waveform of the output current Iout. The primary current IL is the current flowing through the primary winding 22, and the secondary current IS is the current flowing through the secondary winding 23. In this embodiment, for convenience of explanation, it is assumed that the primary current IL and the secondary current IS are the same.

As shown in FIG. 5(c), the soft switching conditions in the double-sided PWM control mode include (A) the magnitude of the primary side current IL being equal to or greater than the primary side threshold ILmin at the start timing of the inversion period Φ. In other words, the soft switching conditions include the switching pattern switching from the eighth pattern P8 to the first pattern P1 when the magnitude of the primary side current IL is equal to or greater than the primary side threshold ILmin. The primary side threshold ILmin is set, for example, based on the capacitance of the primary side capacitors C1 to C4, and is the magnitude of the current required to charge and discharge the primary side capacitors C1 to C4 using the primary side current IL. Note that since the primary side current IL is negative at the start timing of the inversion period Φ, the condition (A) can also be said to be the primary side current IL being equal to or less than -ILmin.

The soft switching condition in the double-sided PWM control mode includes (B) the magnitude of the secondary-side current IS being equal to or greater than the secondary-side threshold ISmin at the end of the inversion period Φ. In other words, the soft switching condition includes the switching pattern switching from the first pattern P1 to the second pattern P2 when the magnitude of the secondary-side current IS is equal to or greater than the secondary-side threshold ISmin. The secondary-side threshold ISmin is set, for example, based on the capacitance of the secondary-side capacitors C5 to C8, and is the magnitude of the current required to charge and discharge the secondary-side capacitors C5 to C8 using the secondary-side current IS. Note that since the secondary-side current IS is positive at the end of the inversion period Φ, the condition (B) can also be said to be the secondary-side current IS being equal to or greater than the secondary-side threshold ISmin.

In step S102, the control circuit 50 of this embodiment derives the inversion period Φ and both periods T1 and T2 that can realize the target current It while satisfying the conditions (A) and (B). In detail, the control circuit 50 controls the output current Iout to be the target current It by deriving the inversion period Φ that corresponds to the target current It within a range that satisfies the conditions (A) and (B). In other words, it can be said that the control circuit 50 controls the output current Iout by controlling the inversion period Φ within a range that satisfies the conditions (A) and (B).

The specific manner in which the inversion period Φ and both periods T1 and T2 are derived is arbitrary. For example, they may be derived by referring to a table in which the target current It is associated with the inversion period Φ and both periods T1 and T2, or they may be derived by calculation.

As shown in FIG. 4, after executing the process of step S102, the control circuit 50 proceeds to step S103, where it determines the switching mode of each switching element Q1 to Q8 based on the inversion period Φ and both periods T1 and T2 derived in step S102. In detail, the control circuit 50 determines the phase difference between the two full bridge circuits 30, 40 and the duty ratio of both switching elements Q1 to Q4 and Q5 to Q8 so that the inversion period Φ and both periods T1 and T2 derived in step S102 are obtained. It can also be said that the control circuit 50 determines the set period of each switching pattern so that the inversion period Φ and both periods T1 and T2 derived in step S102 are obtained.

Then, in step S104, the control circuit 50 performs switching control of each of the switching elements Q1 to Q8 in the determined switching mode.
Next, the operation of this embodiment will be described with reference to FIG. 5 and FIG.

First, a case where the capacitance of the primary side capacitors C1 to C4 is greater than the capacitance of the secondary side capacitors C5 to C8 will be described using Figure 5. Figure 5 is a graph showing an example of the voltages V1, V2 and the currents IL, IS, and Iout when the capacitance of the primary side capacitors C1 to C4 is greater than the capacitance of the secondary side capacitors C5 to C8. Note that the two-dot chain line in Figure 5 shows the waveforms of the voltages V1, V2 and the currents IL, IS, and Iout when the primary side threshold ILmin is the same as the secondary side threshold ISmin for comparison.

As shown in FIG. 5, when the capacitance of the primary side capacitors C1 to C4 is greater than the capacitance of the secondary side capacitors C5 to C8, the magnitude of the primary side threshold ILmin is greater than the magnitude of the secondary side threshold ISmin. In this configuration, each switching element Q1 to Q8 is controlled so that the inversion period Φ satisfies the conditions (A) and (B). This satisfies the conditions (A) and (B). In this case, the magnitude of the primary side current IL at the start timing of the inversion period Φ is greater than the magnitude of the secondary side current IS at the end timing of the inversion period Φ.

Here, as shown by the solid line and the two-dot chain line in Figure 5, the inversion period Φ is larger than when the primary threshold ILmin is the same as the secondary threshold ISmin, and the waveform of the primary voltage V1 (more specifically, the duty ratio) changes in response to the inversion period Φ.

In other words, when the primary threshold ILmin is greater than the secondary threshold ISmin, the control circuit 50 of this embodiment controls the duty ratio of the primary voltage V1 in accordance with the difference between the two thresholds ILmin and ISmin, thereby setting the inversion period Φ corresponding to the primary threshold ILmin. In detail, the control circuit 50 controls the duty ratio of the primary voltage V1 in accordance with the difference between the two thresholds ILmin and ISmin so that the inversion period Φ satisfies the conditions (A) and (B). As described above, the duty ratio of the primary voltage V1 is a parameter controlled by the duty ratio of each switching element Q1 to Q8, the phase difference between each leg 31, 32, or the phase difference between each leg 41, 42, etc.

Next, a case where the capacitance of the secondary side capacitors C5 to C8 is greater than that of the primary side capacitors C1 to C4 will be described with reference to FIG. 6. FIG. 6 is a graph showing an example of the voltages V1, V2 and the currents IL, IS, and Iout when the capacitance of the secondary side capacitors C5 to C8 is greater than that of the primary side capacitors C1 to C4. In detail, FIG. 6(a) shows the waveform of the primary side voltage V1, FIG. 6(b) shows the waveform of the secondary side voltage V2, FIG. 6(c) shows the waveforms of the primary side current IL and the secondary side current IS, and FIG. 6(d) shows the waveform of the output current Iout. The two-dot chain lines in FIG. 6 show the waveforms of the voltages V1, V2 and the currents IL, IS, and Iout when the secondary side threshold ISmin is the same as the primary side threshold ILmin for comparison.

As shown in FIG. 6, when the capacitance of the secondary capacitors C5 to C8 is greater than the capacitance of the primary capacitors C1 to C4, the magnitude of the secondary threshold ISmin is greater than the magnitude of the primary threshold ILmin. In this configuration, each switching element Q1 to Q8 is controlled so that the inversion period Φ satisfies the conditions (A) and (B). This satisfies the conditions (A) and (B). For example, the magnitude of the secondary current IS at the end timing of the inversion period Φ is greater than the magnitude of the primary current IL at the start timing of the inversion period Φ.

Here, as shown by the solid line and the two-dot chain line in FIG. 6, the inversion period Φ is larger than when the secondary threshold ISmin is the same as the primary threshold ILmin, and the waveform of the secondary voltage V2 (more specifically, the duty ratio) changes in response to the inversion period Φ.

In other words, when the secondary threshold ISmin is greater than the primary threshold ILmin, the control circuit 50 of this embodiment controls the duty ratio of the secondary voltage V2 in response to the difference between the two thresholds ILmin and ISmin, thereby setting the inversion period Φ corresponding to the secondary threshold ISmin. In detail, the control circuit 50 controls the duty ratio of the secondary voltage V2 in response to the difference between the two thresholds ILmin and ISmin so that the inversion period Φ satisfies the conditions (A) and (B). Note that, as described above, the duty ratio of the secondary voltage V2 is a parameter controlled by the duty ratio of each switching element Q1 to Q8, the phase difference between each leg 31, 32, or the phase difference between each leg 41, 42, etc.

The present embodiment described above in detail provides the following advantages.
(1) The power conversion device 10 includes a transformer 20 having a primary winding 22 and a secondary winding 23 , a primary full-bridge circuit 30 , a secondary full-bridge circuit 40 , and a control circuit 50 .

The primary full bridge circuit 30 is connected to the primary winding 22. The primary full bridge circuit 30 includes a plurality of primary switching elements Q1 to Q4 and primary capacitors C1 to C4 connected in parallel to the primary switching elements Q1 to Q4.

The secondary full bridge circuit 40 is connected to the secondary winding 23. The secondary full bridge circuit 40 includes a plurality of secondary switching elements Q5 to Q8 and secondary capacitors C5 to C8 connected in parallel to the secondary switching elements Q5 to Q8.

The control circuit 50 has a double-sided PWM control mode as a control mode for periodically controlling each of the switching elements Q1 to Q8. The double-sided PWM control mode is a mode in which the primary voltage V1 input to the primary winding 22 switches between positive, negative, or zero, and the secondary voltage V2 input to the secondary winding 23 switches between positive, negative, or zero. The double-sided PWM control mode includes an inversion period Φ during which the polarities of the primary voltage V1 and the secondary voltage V2 are inverted.

The capacitance of the primary capacitors C1 to C4 is different from that of the secondary capacitors C5 to C8. Correspondingly, the primary threshold ILmin is different from the secondary threshold ISmin. In the double-sided PWM control mode, the control circuit 50 controls each switching element Q1 to Q8 to satisfy conditions (A) and (B). Condition (A) is that the magnitude of the primary current IL flowing through the primary winding 22 at the start timing of the inversion period Φ is equal to or greater than the primary threshold ILmin, and condition (B) is that the magnitude of the secondary current IS flowing through the secondary winding 23 at the end timing of the inversion period Φ is equal to or greater than the secondary threshold ISmin.

According to this configuration, by adopting the double-sided PWM control mode as the control mode, voltage conversion can be performed regardless of the magnitude relationship between the input voltage Vin and the output voltage Vout. This eliminates the need to switch between different control modes depending on the magnitude relationship between the input voltage Vin and the output voltage Vout, reducing the complexity of control associated with changes in the magnitude relationship between the input voltage Vin and the output voltage Vout.

The primary side threshold ILmin and secondary side threshold ISmin are different in response to the difference in capacitance between the primary side capacitors C1 to C4 and the secondary side capacitors C5 to C8. Then, by the control circuit 50 controlling each switching element Q1 to Q8 so as to satisfy conditions (A) and (B), soft switching is performed even when the capacitance between the primary side capacitors C1 to C4 and the secondary side capacitors C5 to C8 are different. This allows soft switching to be performed in the double-sided PWM control mode under conditions where the capacitance between the primary side capacitors C1 to C4 and the secondary side capacitors C5 to C8 are different.

(2) The capacitance of the primary-side capacitors C1 to C4 is greater than the capacitance of the secondary-side capacitors C5 to C8, and the primary-side threshold value ILmin is greater than the secondary-side threshold value ISmin.
According to this configuration, the primary side threshold ILmin is larger than the secondary side threshold ISmin in correspondence with the fact that the capacitance of the primary side capacitors C1 to C4 is larger than the capacitance of the secondary side capacitors C5 to C8. This makes it possible to secure the primary side current IL that can charge and discharge the primary side capacitors C1 to C4 at the start timing of the inversion period Φ, thereby realizing soft switching.

(3) When the primary side threshold ILmin is greater than the secondary side threshold ISmin, the control circuit 50 controls the duty ratio of the primary side voltage V1 to set the inversion period Φ corresponding to the primary side threshold ILmin.

According to this configuration, the duty ratio of the primary voltage V1 is controlled to set the inversion period Φ corresponding to the primary threshold ILmin. This allows the magnitude of the primary current IL at the start timing of the inversion period Φ to be equal to or greater than the primary threshold ILmin. Therefore, the effect of (2) can be obtained.

(4) The capacitances of the secondary-side capacitors C5 to C8 are greater than the capacitances of the primary-side capacitors C1 to C4. The secondary-side threshold ISmin is greater than the primary-side threshold ILmin.
According to this configuration, the secondary threshold value ISmin is set to be larger than the primary threshold value ILmin in response to the fact that the capacitances of the secondary capacitors C5 to C8 are larger than the capacitances of the primary capacitors C1 to C4. This makes it possible to ensure the secondary current IS that can charge and discharge the secondary capacitors C5 to C8 at the end timing of the inversion period Φ, thereby achieving soft switching.

(5) When the secondary threshold ISmin is greater than the primary threshold ILmin, the control circuit 50 controls the duty ratio of the secondary voltage V2 to set the inversion period Φ corresponding to the secondary threshold ISmin.

According to this configuration, the duty ratio of the secondary voltage V2 is controlled to set the inversion period Φ corresponding to the secondary threshold ISmin. This allows the magnitude of the secondary current IS at the end timing of the inversion period Φ to be equal to or greater than the secondary threshold ISmin. Therefore, the effect of (4) can be obtained.

(6) The control circuit 50 controls the inversion period Φ within a range that satisfies the conditions (A) and (B) to thereby control the output current Iout.
According to this configuration, the output current Iout can be controlled while performing soft switching, thereby making it possible to output the target current It.

The above embodiment may be modified as follows: The above embodiment and each of the following modifications may be combined with each other within a range where no technical contradiction occurs.
The power conversion device 10 may perform bidirectional voltage conversion. In this case, the voltage input to the secondary full bridge circuit 40 may be the input voltage Vin, and the voltage output from the primary full bridge circuit 30 may be the output voltage Vout. In this case, for example, patterns P1 to P8 may be used in which the primary switching elements Q1 to Q4 and the secondary switching elements Q5 to Q8 are interchanged.

○ The load 120 is not limited to a power storage device and may be any device, for example a drive device that is driven at a target voltage. In this case, the load control device 121 transmits the required current and the required voltage to the control circuit 50. The control circuit 50 may control each of the switching elements Q1 to Q8 so as to satisfy the soft switching conditions within a range in which the output voltage Vout becomes the required voltage and the output current Iout becomes the required current.

10...power conversion device, 20...transformer, 22...primary winding, 23...secondary winding, 30...primary full bridge circuit, 40...secondary full bridge circuit, 50...control circuit, V1...primary voltage, V2...secondary voltage, IL...primary current, ILmin...primary threshold, ISmin...secondary threshold, IS...secondary current, Iout...output current, Q1-Q4...primary switching elements, Q5-Q8...secondary switching elements, C1-C4...primary capacitors, C5-C8...secondary capacitors, W...transmission period, T1...input period, T2...output period, Φ...inversion period, Vin...input voltage, Vout...output voltage.

Claims (6)

a transformer having a primary winding and a secondary winding;
a primary side full bridge circuit connected to the primary winding, the primary side full bridge circuit having a plurality of primary side switching elements and a plurality of primary side capacitors connected in parallel to the plurality of primary side switching elements;
a secondary side full bridge circuit connected to the secondary winding, the secondary side full bridge circuit having a plurality of secondary side switching elements and a plurality of secondary side capacitors connected in parallel to the plurality of secondary side switching elements and having a capacitance different from that of the plurality of primary side capacitors;
a control circuit for converting an input voltage input to the primary side full bridge circuit into an output voltage output from the secondary side full bridge circuit by controlling the plurality of primary side switching elements and the plurality of secondary side switching elements ,
the control circuit includes a double-sided PWM control mode in which a primary-side voltage applied to the primary winding is switched to a positive, negative, or zero, and a secondary-side voltage applied to the secondary winding is switched to a positive, negative, or zero, as a control mode for periodically controlling the plurality of primary-side switching elements and the plurality of secondary-side switching elements;
the double-sided PWM control mode includes an inversion period in which the polarities of the primary side voltage and the secondary side voltage are inverted,
The control circuit, in the double-sided PWM control mode, controls the multiple primary-side switching elements and the multiple secondary-side switching elements so that the magnitude of the primary-side current flowing through the primary winding at the start timing of the inversion period is equal to or greater than a primary-side threshold, and the magnitude of the secondary-side current flowing through the secondary winding at the end timing of the inversion period is equal to or greater than a secondary-side threshold that is different from the primary-side threshold. The capacitance of the plurality of primary side capacitors is greater than the capacitance of the plurality of secondary side capacitors,
The power conversion device according to claim 1 , wherein the primary side threshold is greater than the secondary side threshold. The power conversion device according to claim 2, wherein the control circuit controls the duty ratio of the primary side voltage when the primary side threshold is greater than the secondary side threshold to set the inversion period to a value corresponding to the primary side threshold. The capacitance of the plurality of secondary side capacitors is greater than the capacitance of the plurality of primary side capacitors,
The power conversion device according to claim 1 , wherein the secondary side threshold is greater than the primary side threshold. The power conversion device according to claim 4, wherein when the secondary side threshold is greater than the primary side threshold, the control circuit controls the duty ratio of the secondary side voltage to set the inversion period to a value corresponding to the secondary side threshold. The power conversion device according to any one of claims 1 to 5, wherein the control circuit controls the output current from the secondary full bridge circuit by controlling the inversion period within a range in which the magnitude of the primary current at the start timing of the inversion period is equal to or greater than the primary threshold value and the magnitude of the secondary current at the end timing of the inversion period is equal to or greater than the secondary threshold value in the double-sided PWM control mode.