JP7546616B2 - Power Factor Corrected Power Supply - Google Patents

Description

This application relates to a power factor compensated power supply device.

Some conventional power factor compensation power supplies have a converter including a reactor (inductor) and a switching element, and a full-wave rectifier circuit, and by making the on-time of the switching element roughly constant during one cycle of the input AC voltage, they simultaneously realize the operation of converting AC power to DC power and the operation of power factor correction (PFC). In such power factor compensation power supplies, some aim to reduce switching loss by detecting resonance that occurs between the reactor (inductor) and the switching element, and turning on the switching element at the bottom timing when the voltage across the switching element reaches the bottom during resonance. It has also been proposed to provide a fixed-period pulse that masks the resonance signal that detects the resonance, and to turn on the switching element at the bottom timing after the fixed-period pulse becomes L (see, for example, Patent Document 1).

Patent No. 6890080

According to the technology described in Patent Document 1, the timing at which the switching element is turned on is restricted to be later than the timing at which the fixed-cycle pulse becomes L, so that the switching frequency can be made lower than the frequency determined by the fixed-cycle pulse, and it is possible to prevent switching operations from being performed at a specific frequency. On the other hand, when the switching frequency is restricted by the fixed-cycle pulse as described above, there is a problem in that the switching frequencies are concentrated in a frequency band slightly lower than the frequency determined by the fixed-cycle pulse, and there is a risk of large EMI noise (Electro-Magnetic Interference noise) being generated in the frequency band where the switching frequencies are concentrated.
The present application discloses technology for solving the above-mentioned problems, and aims to provide a power factor compensated power supply device that can prevent the concentration of switching frequencies in a specific frequency band.

The power factor compensation power supply device disclosed in the present application includes a converter having a switching element and an inductor, which converts the AC voltage supplied from an AC power source into a DC voltage and outputs it to a load, a switching control unit which controls the on/off of the switching element, and a timing adjustment unit which adjusts the switching frequency of the switching element by adjusting the on/off timing of the switching element, and when the fluctuating switching frequency approaches a predetermined avoidance frequency band, the timing adjustment unit increases the magnitude of the fluctuation in the switching frequency to lower the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or raises the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band.

The power factor compensated power supply device disclosed in this application can prevent the switching frequency from concentrating in a specific frequency band.

1 is a block diagram showing a configuration of a power factor compensated power supply device according to a first embodiment; 4A to 4C are diagrams illustrating the operation of a power supply main circuit unit and ZCD count control according to the first embodiment. 4 is a diagram illustrating an example of a relationship between a power supply voltage, a switching frequency, and an allowed count number in the first embodiment. FIG. 13 is a diagram showing another example of the relationship between the power supply voltage, the switching frequency, and the permitted count number in the first embodiment. FIG. 2 is a diagram illustrating an example of a hardware configuration for implementing each functional unit of a power supply control unit according to the first embodiment; FIG. 13 is a block diagram showing a configuration of a power factor compensated power supply device in a modified example of the first embodiment. FIG. 11 is a block diagram showing a configuration of a power factor compensated power supply device in a second embodiment. FIG. 11 is a diagram illustrating the operation of a power supply main circuit unit according to the third embodiment. FIG. 13 is a block diagram showing a power factor compensated power supply device according to a fourth embodiment. FIG. 13 is a block diagram showing a configuration of a power factor compensated power supply device in a fifth embodiment. FIG. 13 is a block diagram showing a power factor compensated power supply device according to a sixth embodiment. FIG. 23 is a block diagram showing a power factor compensated power supply device in a modified example of the sixth embodiment.

Embodiment 1.
A first embodiment will be described below with reference to Fig. 1 to Fig. 5. Fig. 1 is a block diagram showing the configuration of a power factor compensated power supply device in the first embodiment. A power factor compensated power supply device 100 converts AC power supplied from an AC power supply 91 into DC power and supplies it to a load 92, and is provided with a power supply main circuit section 110 connected between the AC power supply 91 and the load 92 and having a converter 140 therein, and a power supply control section 120 that controls the converter 140. The AC power supply 91 supplies an AC power supply voltage VAC, i.e., an AC voltage, to the power supply main circuit section 110. An AC current IAC flows from the AC power supply 91 to the power supply main circuit section 110.

The power supply main circuit section 110 is mainly composed of an input filter 111, i.e., a filter section, a full-wave rectifier circuit 112, and a converter 140. The power supply main circuit section 110 also includes an output voltage detection section 113 that detects the output voltage vo of the converter 140.

The input filter 111 suppresses the conduction of EMI noise generated by the switching operation of the switching element 142 of the converter 140 to the AC power supply 91. The input filter 111 has a choke coil (not shown), which is, for example, a hybrid choke coil, a common mode choke coil, or a normal mode choke coil, and reduces the magnitude of the conducted EMI noise flowing in from the converter 140.

The full-wave rectifier circuit 112 performs full-wave rectification on the power supply voltage vac supplied from the AC power supply 91, and outputs the resulting full-wave rectified voltage to the converter 140. The full-wave rectifier circuit 112 is configured with a diode bridge (not shown). Note that, although a full-wave rectifier circuit is used as the rectifier circuit in the first embodiment, it may be replaced with a half-wave rectifier circuit.

The converter 140 converts the full-wave rectified voltage output from the full-wave rectifier circuit 112 into DC. The converter 140 also adjusts the magnitude of the output voltage vo to a predetermined target, and outputs the adjusted output voltage vo to the load 92.

1, the converter 140 is configured, for example, by a boost chopper circuit. More specifically, the converter 140 includes an input capacitor 144 having one end connected to a high-voltage side electric circuit and the other end connected to a low-voltage side electric circuit on the output side of the full-wave rectifier circuit 112, a reactor 141 (i.e., an inductor) having one end connected to a connection point between one end of the input capacitor 144 and the high-voltage side electric circuit, a diode 143 having an anode connected to the other end of the reactor 141, an output capacitor 145 having one end connected to the cathode of the diode 143 and the other end connected to the low-voltage side electric circuit, and a switching element 142 having one end connected to a connection point between the other end of the reactor 141 and the anode of the diode 143 and the other end connected to the low-voltage side electric circuit. The other end of the input capacitor 144, the other end of the switching element 142, and the other end of the output capacitor 145 are connected to the other end of the load 92 via the low-voltage side electric circuit. The black circle (●) shown on reactor 141 indicates polarity.

The switching element 142 is a semiconductor switching element such as a FET (Field Effect Transistor) element or an IGBT (Insulated Gate Bipolar Transistor) element that is driven by a gate signal (hereinafter, PWM signal Vg) generated in the power supply control unit 120 by PWM (Pulse Width Modulation) control. When the switching element 142 is a FET, one end and the other end of the switching element 142 described above become the drain terminal and source terminal of the FET element. When the switching element 142 is an IGBT element, one end and the other end of the switching element 142 described above become the collector terminal and emitter terminal of the IGBT element.

In addition, the diode 143 in the first embodiment can be replaced with a switching element 149 (not shown) such as an FET element or an IGBT element, and a synchronous rectification method can be used in which the on/off of the switching elements 142 and 149 is operated using reverse logic.

The power supply main circuit 110 includes an output voltage detection unit 113 and a zero current detection unit 114, i.e., a minimum value detection unit. The output voltage detection unit 113 detects the magnitude of the DC output voltage vo as an output voltage detection value vosen, and is composed of, for example, two or more voltage dividing resistors connected in series. The zero current detection unit 114 detects the zero point of the current flowing through the reactor 141, and can be realized by providing an auxiliary winding for the reactor 141, as shown in FIG. 1. A potential difference corresponding to the reactor current iL flowing through the reactor 141 occurs between both ends of the auxiliary winding, and this potential difference is detected by the zero current detection unit 114. The zero current detection unit 114 outputs a zero current signal ZCD that becomes high (High, hereinafter referred to as "H") or low (Low, hereinafter referred to as "L") depending on the detected voltage. The L signal of the zero current signal ZCD corresponds to a minimum value signal.

The zero current detection unit 114 does not have to use an auxiliary winding as long as it is configured to detect the zero point of the reactor current iL. For example, a current detection resistor may be placed on the low side of the reactor 141 and the zero point of the current of the reactor 141 may be detected from the voltage generated across the current detection resistor, or a current detection resistor may be connected in series with the reactor and detected from the high potential side.

Next, the power supply control unit 120 will be described. The power supply control unit 120 includes a switching control unit 121 that controls the on/off of the switching element 142, an output voltage control unit 122, and a timing adjustment unit 123 that adjusts the switching frequency fsw of the switching element 142. The output voltage control unit 122 derives the time for which the PWM signal Vg is maintained at H, i.e., the on time ton of the switching element 142, based on the output voltage detection value vosen and the target voltage value voref. The timing adjustment unit 123 in the first embodiment determines the permitted count number Cn based on the PWM signal Vg input from the switching control unit 121. The "permitted count number" is a value that determines the timing for changing the switching element 142 from off to on. The switching control unit 121 performs "ZCD count control" (described later) based on the on-time ton derived by the output voltage control unit 122, the permitted count number Cn determined by the timing adjustment unit 123, and the zero current signal ZCD sent from the zero current detection unit 114, and generates a PWM signal Vg to drive the switching element 142. In the first embodiment, the switching control unit 121 also outputs the PWM signal Vg to the timing adjustment unit 123.

Next, the main circuit operation of the power factor compensated power supply device 100, i.e., the operation of the power supply main circuit unit 110 and the ZCD count control will be described. FIG. 2 is a diagram for explaining the operation of the power supply main circuit unit and the ZCD count control according to the first embodiment, and shows the relationship between the PWM signal Vg output by the switching control unit 121, the reactor current iL flowing through the reactor 141, the voltage Vds across the switching element 142, and the zero current signal ZCD output by the zero current detection unit 114, with the horizontal axis of each graph in the diagram representing time.

When the PWM signal Vg becomes H and the switching element 142 turns on, in the circuit shown in FIG. 1, current flows through the AC power supply 91, the switching element 142, the reactor 141, the load 92, and the AC power supply 91 in that order, and the reactor current iL increases. During the period in which the reactor current iL increases, the zero current signal ZCD becomes L.

When the PWM signal Vg becomes L and the switching element 142 turns off, current flows through the reactor 141, the load 92, the diode 143, and the reactor 141 in that order, and the reactor current iL decreases to zero. During the period in which the reactor current iL decreases to zero, the zero current signal ZCD becomes H.

When the reactor current iL decreases to zero, LC resonance occurs due to the inductance component of the reactor 141 and the parasitic capacitance of the switching element 142, and the resonant current due to this LC resonance flows through the reactor 141, and the voltage Vds across both ends oscillates. Due to this resonant current, during the period in which the resonant current flows through the reactor 141, the zero current signal ZCD becomes L at the timing when the reactor current iL becomes zero and then rises (the timing when the reactor current iL switches from negative to positive). As can be seen from FIG. 2, the timing when the reactor current iL switches from negative to positive is also the bottom timing when the voltage Vds across the switching element becomes minimal, so by setting the PWM signal Vg to H at the timing when the zero current signal ZCD switches from H to L, the switching loss generated by the switching of the switching element 142 can be reduced.

In the ZCD count control of the first embodiment, after the PWM signal Vg becomes L, the PWM signal Vg is switched to H based on the timing at which the zero current signal ZCD switches from H to L, but at that time, the timing adjustment unit 123 adjusts the on/off timing of the switching element 142. That is, after the PWM signal Vg becomes L, the switching control unit 121 counts the number of times that the zero current signal ZCD switches from H to L during the period in which the resonant current flows through the reactor 141, and sets the PWM signal Vg to H based on the timing at which the count reaches the permitted count number Cn determined by the timing adjustment unit 123. Note that a count unit that performs the count may be provided separately from the switching control unit 121. In this case, when the count number reaches the permitted count number Cn, the count unit transmits a permitted count number reaching signal to the switching control unit 121, and the switching control unit 121 sets the PWM signal Vg to H based on the timing at which the permitted count number reaching signal is received.

The power supply control unit 120 will now be described in detail. The power supply control unit 120 may be entirely composed of a general digital control circuit (including a software circuit having the same functions as a digital control circuit) that does not use an IC (Interted Circuit), or may be composed only partially of a digital control circuit. It may also be entirely composed of an analog control circuit without using a digital control circuit. In the first embodiment, a configuration in which a digital control circuit is used, for example, using a microcomputer, will be described.

The output voltage control unit 122 calculates the difference between the output voltage detection value vosen and the target voltage value voref, and calculates the on-time ton of the switching element 142 so that this difference becomes zero. The on-time ton can be calculated using any control method that controls so that the difference between the output voltage detection value vosen and the target voltage value voref becomes zero, such as classical control such as PI control (proportional integral control) and PID control (proportional differential integral control), or modern control such as H∞ (H-infinity) control. The output voltage vo can be adjusted to any target voltage value voref by calculating the on-time ton by the output voltage control unit 122.

In order to achieve PFC operation, the on-time ton calculated by the output voltage control unit 122 is set to be approximately constant during the period of the full-wave rectified voltage (half the period of the power supply voltage vac). However, PFC operation may be achieved by updating the on-time ton only once per period of the full-wave rectified voltage, or by setting the control responsiveness to be small.

The timing adjustment unit 123 detects the timing at which the PWM signal Vg sent from the switching control unit 121 switches from L to H, and calculates the switching frequency fsw of the switching element 142 by measuring the time from one switching timing to the next switching timing. Based on the calculated switching frequency fsw, the timing adjustment unit 123 determines an allowed count number Cn so that the switching frequency fsw does not fall within a specific frequency band, i.e., so that the switching element 142 does not perform switching operation in the specific frequency band, and outputs the determined count number Cn to the switching control unit 121. Note that hereinafter, the specific frequency band that is set not to operate is referred to as the "avoidance frequency band."

The avoidance frequency band is not limited to a frequency band with a certain range, and may be set to include only specific frequencies. In this case, the specific frequency is referred to as the "avoidance frequency," and the "avoidance frequency band" in the following explanation may be read as the "avoidance frequency." Furthermore, the "avoidance frequency" is conceptually included in the "avoidance frequency band."

After the switching element 142 is turned off, the switching control unit 121 counts the number of times that the zero current signal ZCD output by the zero current detection unit 114 switches from H to L during the period in which the PWM signal Vg is maintained at L, and changes the PWM signal Vg from L to H based on the timing at which the number of times reaches the permitted count number Cn determined by the timing adjustment unit 123. The timing at which the PWM signal Vg is changed from L to H may be the same as the timing at which the number of times reaches the permitted count number Cn, or may be delayed by a predetermined time. After changing the PWM signal Vg from L to H, the switching control unit 121 switches the PWM signal Vg from H to L after the on-time ton derived by the output voltage control unit 122 has elapsed. The switching control unit 121 also transmits the PWM signal Vg to the switching element 142 and the timing adjustment unit 123. The switching control unit 121 drives the switching element 142 while performing the ZCD count control as described above.

From FIG. 2, it can be seen that the timing for changing the PWM signal Vg from L to H becomes later as the permitted count number Cn increases. From this, it can be seen that the larger the permitted count number Cn, the longer the switching period of the switching element 142 becomes, and the lower the switching frequency fsw becomes. It can also be seen that the smaller the permitted count number Cn, the higher the switching frequency fsw becomes.

Next, the operation of the power factor compensation power supply device 100 will be further described with reference to FIG. 3. FIG. 3 is a diagram showing an example of the relationship between the power supply voltage, the switching frequency, and the permitted count number in the first embodiment. The horizontal axis of each graph in FIG. 3 is time, and the vertical axis represents the power supply voltage vac, the switching frequency fsw, and the permitted count number Cn, starting from the graph at the top of the figure. When the on-time ton is controlled to be approximately constant during the period of the full-wave rectified voltage (half the period of the power supply voltage vac), the switching frequency fsw varies depending on the magnitude of the power supply voltage vac. That is, the switching frequency fsw increases as the absolute value of the power supply voltage vac decreases, and the switching frequency fsw decreases as the absolute value of the power supply voltage vac increases. Note that the magnitude of the power supply voltage vac during one period is determined by the phase of the power supply voltage vac, so the switching frequency fsw varies depending on the phase of the power supply voltage vac.

In the first embodiment, when the timing adjustment unit 123 detects that the switching frequency fsw is approaching the avoidance frequency band while decreasing, the permitted count number Cn is changed to a large value. In the example shown in FIG. 3, the permitted count number Cn is changed from 2 to 3. When the permitted count number Cn increases, the decrease in the switching frequency fsw due to the increase in the power supply voltage vac is added to the decrease in the switching frequency fsw due to the increase in the permitted count number Cn, and the switching frequency fsw drops sharply. This realizes operation that avoids the avoidance frequency band. More specifically, the switching frequency fsw changes discontinuously from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band. Conversely, when the timing adjustment unit 123 detects that the switching frequency fsw is approaching the avoidance frequency band while increasing, the permitted count number is changed to a small value. In the example shown in FIG. 3, the permitted count number Cn is changed from 3 to 2. By reducing the permitted count number Cn, the switching frequency fsw is suddenly increased, and operation that avoids the avoidance frequency band is realized. More specifically, the switching frequency fsw changes discontinuously from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band.

By varying the switching frequency fsw as described above, the switching frequency fsw is prevented from entering the avoidance frequency band. In addition, the switching element 142 is prevented from performing switching operation at a frequency within the avoidance frequency band. Note that the approach of the switching frequency fsw to the avoidance frequency band can be detected based on the difference between the current switching frequency fsw and any frequency within the avoidance frequency band, such as the upper limit, lower limit, or center value. When the magnitude of this difference decreases and becomes smaller than a predetermined value, the approach of the switching frequency fsw to the avoidance frequency band is detected.

As described above, in the first embodiment, when the switching frequency fsw is rising, the switching frequency fsw is further increased, and when the switching frequency fsw is falling, the switching frequency fsw is further decreased. By performing such an operation, it is possible to realize an operation that avoids the avoidance frequency band. Furthermore, by performing the above operation, it is possible to prevent the switching frequency fsw from concentrating at one frequency. This can be confirmed from the fact that the switching frequency fsw can be distributed at 1/4 cycle of the power supply voltage vac in FIG. 3. By distributing the switching frequency fsw, it is possible to distribute the frequency of the EMI noise generated by the switching operation to multiple frequencies. By distributing the frequency of the EMI noise to multiple frequencies in this way, the maximum value of the generated EMI noise can be reduced compared to the case where the EMI noise is concentrated at one frequency due to the effect of spectrum spreading.

In addition, in the first embodiment, when the switching frequency fsw is increasing, when the avoidance frequency band is avoided, the switching frequency fsw is increased to a frequency higher than the avoidance frequency band. When the cutoff frequency of the input filter 111 is included in the avoidance frequency band, the timing adjustment unit 123 increases the switching frequency fsw to a frequency higher than the avoidance frequency band and higher than the cutoff frequency of the input filter 111. The higher the switching frequency fsw (in this case, the higher the frequency of the EMI noise generated by the switching operation), the greater the EMI noise attenuation effect of the input filter 111. Therefore, by increasing the switching frequency fsw to a higher frequency, the attenuation effect of the input filter 111 can be increased and the amount of EMI noise conducted to the AC power supply 91 can be more effectively suppressed.

When calculating the switching frequency fsw and determining the permitted count number Cn based on the timing at which the PWM signal Vg switches to H, a delay occurs between when the permitted count number Cn is changed and when the switching frequency fsw actually changes, so it is desirable to determine the timing of changing the permitted count number Cn taking this delay into account.

3, only one avoidance frequency band is provided, but multiple avoidance frequency bands may be provided. In the example shown in FIG. 4, two avoidance frequency bands, a first avoidance frequency band and a second avoidance frequency band, are provided. The first avoidance frequency band is a higher frequency band than the second avoidance frequency band. In order to avoid these two avoidance frequency bands, the permitted count number Cn is changed from 1 to 2 (when the switching frequency fsw is decreasing) or from 2 to 1 (when the switching frequency fsw is increasing) to avoid the first avoidance frequency band. In order to avoid the second avoidance frequency band, the permitted count number Cn is changed from 2 to 3 (when the switching frequency fsw is decreasing) or from 3 to 2 (when the switching frequency fsw is increasing). In the examples shown in FIG. 3 and FIG. 4, the permitted count number Cn is changed by 1 at a time, but the permitted count number Cn may be changed by 2 or more at a time.

Next, the hardware configuration for implementing each functional unit of the power factor compensation power supply device 100, particularly the power supply control unit 120, will be described. FIG. 5 is a diagram showing an example of a hardware configuration for implementing each functional unit of the power supply control unit according to the first embodiment. As described above, the power supply control unit 120 is configured by a digital control circuit using a microcomputer, and an example of a more specific hardware configuration of the microcomputer is shown in FIG. 5. That is, the power supply control unit 120 is mainly configured by a processor 71, a memory 72 as a main storage device, and an auxiliary storage device 73. The processor 71 is configured by, for example, a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), etc.

The memory 72 is composed of a volatile storage device such as a random access memory, and the auxiliary storage device 73 is composed of a non-volatile storage device such as a flash memory or a hard disk. A predetermined program executed by the processor 71 is stored in the auxiliary storage device 73, and the processor 71 reads and executes this program as appropriate to perform various arithmetic processing. At this time, the predetermined program is temporarily saved from the auxiliary storage device 73 to the memory 72, and the processor 71 reads the program from the memory 72. The various arithmetic processing of the control system according to the first embodiment is realized by the processor 71 executing the predetermined program as described above. The results of the arithmetic processing by the processor 71 are temporarily stored in the memory 72, and are then stored in the auxiliary storage device 73 according to the purpose of the executed arithmetic processing.

The power supply control unit 120 also includes a receiver 74 that receives signals or data from the power supply main circuit unit 110 and the like, and a transmitter 75 that transmits signals or data to the power supply main circuit unit 110 and the like.

As described above, the switching frequency fsw is calculated from the PWM signal Vg, and if the switching frequency fsw approaches the avoidance frequency band while increasing, the permitted count number Cn is decreased to discontinuously increase the switching frequency fsw. If the switching frequency fsw approaches the avoidance frequency band while decreasing, the permitted count number Cn is increased to discontinuously decrease the switching frequency fsw. By performing such control, it is possible to realize switching operation that avoids the avoidance frequency band. In addition, since the frequency of the switching operation is prevented from concentrating at a specific frequency, it is possible to realize dispersion of the switching frequency fsw.

In addition, in the first embodiment, the above-mentioned ZCD count control turns on the switching element at the timing when the reactor current iL becomes zero and the voltage across the switching element becomes a minimum value, thereby reducing switching losses.

Note that, for some reason, there may be cases where the change in the switching frequency fsw does not become discontinuous. In this case, the switching frequency fsw will temporarily enter the avoidance frequency band, but the fluctuation of the switching frequency fsw will be abrupt so that it passes through the avoidance frequency band in a short time, and therefore the switching frequency fsw will not concentrate in the avoidance frequency band.

According to the first embodiment, it is possible to prevent the switching frequency from concentrating in a specific frequency band. More specifically, the converter includes a switching control unit that counts the number of times that the voltage across the switching element of the converter oscillates to a minimum and turns on the switching element based on the timing at which this number reaches an allowed count number, and a timing adjustment unit that changes the allowed count number when the switching frequency approaches the avoidance frequency band to prevent the switching frequency from entering the avoidance frequency band. It is possible to set the avoidance frequency band to include a specific frequency band and determine the allowed count number accordingly, so that it is possible to prevent the switching frequency from concentrating in a specific frequency band as the switching frequency fluctuates periodically.

In addition, in embodiment 1, switching operations are prevented from occurring at switching frequencies in the avoidance frequency band, so switching operations can also be prevented from occurring at specific frequencies.

Next, a modified example of the first embodiment will be described. FIG. 6 is a block diagram showing the configuration of a power factor compensated power supply device in a modified example of the first embodiment. In FIG. 6, the same or corresponding components as those in the first embodiment are given the same reference numerals. The power factor compensated power supply device 101 differs from the power factor compensated power supply device 100 in that it is connected to the load 92 via the power converter 93. The operation of the power factor compensated power supply device 101 is similar to that of the power factor compensated power supply device 100 described above. When a power converter 93 other than the converter 140 is connected between the converter 140 and the load 92 as shown in FIG. 6, the avoidance frequency band may be set to include the operating frequency of the power converter 93. In addition, although not shown, it is also possible that another power converter 93 is connected in parallel with the power factor compensated power supply device 100. Even in such a case, the operating frequency of the power converter 93 may be set to the avoidance frequency band. By setting the avoidance frequency band in this way, it is possible to prevent the frequencies of EMI noise generated from two or more power converters (including the converter 140) from concentrating on one frequency. This reduces the capacitance required for the input filter 111, making it possible to reduce the size and cost of the input filter 111.

Although not shown in the figure, the operating frequency of the power converter 93 may be input to the timing adjustment unit 123, and the timing adjustment unit 123 may set the avoidance frequency band to include the operating frequency of the power converter 93.

The avoided frequency band may also be determined based on the standard value of the noise to be complied with, such as 150 kHz or 526 kHz. For example, noise above 526 kHz in the AM frequency band is severely restricted by the noise standard because it causes noise in AM radio. In this way, by determining a frequency band severely restricted by the noise standard as the avoided frequency band, it is possible to facilitate compliance with the noise standard and achieve a smaller, more cost-effective input filter 111. Furthermore, the smaller, more cost-effective input filter 111 leads to a smaller, more cost-effective power factor compensated power supply device as a whole.

In addition to the above, the avoidance frequency band can be set arbitrarily according to the designer's intention, so any fixed value may be defined as the avoidance frequency band.

The configuration may be modified as appropriate as long as it is possible to perform switching operations at least when the reactor current iL is zero and rising, and when the voltage Vds across the switching element 142 is at a minimum value, and if it is possible to further increase the switching frequency fsw when the switching frequency fsw is rising and approaching the avoidance frequency band, and further decrease the switching frequency fsw when the switching frequency fsw is decreasing and approaching the avoidance frequency band.

Embodiment 2.
Next, a second embodiment will be described with reference to Fig. 7. Fig. 7 is a block diagram showing the configuration of a power factor compensated power supply device in the second embodiment. In Fig. 7, the same reference numerals are used for components that are the same as or correspond to those in the first embodiment. The power supply main circuit section 1101 of the power factor compensated power supply device 102 includes a full-wave rectified voltage detection section 115, i.e., an input voltage detection section, which detects a full-wave rectified voltage vin, i.e., an input voltage, and outputs the full-wave rectified voltage detection value vinsen to a timing adjustment section 1231, and an output current detection section 116, which detects an output current io flowing through a load 92, and outputs the output current detection value iosen to the timing adjustment section 1231.

The timing adjustment unit 1231 compares a predetermined threshold th with the full-wave rectified voltage detection value vinsen to determine the permitted count number Cn. Two predetermined thresholds th are prepared: one for use when the full-wave rectified voltage vin increases and the switching frequency fsw decreases, and one for use when the full-wave rectified voltage vin decreases and the switching frequency increases. The values are set in advance so that the permitted count number can be changed at the timing to avoid the avoidance frequency band.

As shown in FIG. 3, the switching frequency fsw is determined depending on the absolute value of the power supply voltage vac, that is, the magnitude of the full-wave rectified voltage vin. Therefore, if the threshold th is set to a value corresponding to the avoidance frequency band, the relationship between the current switching frequency fsw and the avoidance frequency band can be grasped by comparing the threshold th with the full-wave rectified voltage detection value vinsen as described above. In addition, it is possible to grasp whether the switching frequency fsw is approaching the avoidance frequency band from the time change of the comparison result between the threshold th and the full-wave rectified voltage detection value vinsen. In addition, since it is possible to grasp whether the switching frequency fsw is increasing or decreasing from the time change of the full-wave rectified voltage detection value vinsen, it is possible to determine the permitted count number Cn for avoiding the avoidance frequency band. In this way, according to the second embodiment, it is possible to determine the permitted count number Cn without using the PWM signal Vg as in the first embodiment and its modified example. For this reason, the switching control unit 1211 does not need to output the PWM signal Vg to the timing adjustment unit 1231.

Note that, in a system in which the size of the load 92 varies, a configuration in which the threshold value th is corrected according to the size of the load 92 can be considered. Here, the size of the load 92 is calculated from the output voltage detection value vosen and the output current detection value iosen. In the power factor compensated power supply device 102, the output current detection value iosen and the output voltage detection value vosen are input to the timing adjustment unit 1231, which estimates the size of the load 92 from the output voltage detection value vosen and the output current detection value iosen. The timing adjustment unit 1231 corrects the threshold value th according to the estimated size of the load 92. For example, when the load 92 is small, the switching frequency fsw is more likely to increase, so the threshold value th is increased even if the avoidance frequency band is the same.

Embodiment 3.
Next, a third embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram showing the operation of the power supply main circuit section according to the third embodiment, and shows the relationship between the PWM signal Vg output by the switching control section 121, the reactor current iL flowing through the reactor 141, the voltage Vds across both ends of the switching element 142, the zero current signal ZCD output by the zero current detection section 114, and the delay time signal Td, with the horizontal axis of each graph in the diagram representing time.

In the third embodiment, a voltage detection unit (not shown) is provided that detects the voltage Vds across the switching element 142, and ZCD count control is realized by detecting the voltage Vds across the switching element 142. The voltage detection unit corresponds to a minimum value detection unit. As shown in FIG. 2, the timing at which the zero current signal ZCD falls to L coincides with the bottom timing of the voltage Vds across the switching element 142, so that ZCD count control can be realized in the same manner as in the first embodiment, even in a configuration in which a voltage detection unit across the switching element 142 is provided instead of the zero current detection unit 114. That is, according to the third embodiment, ZCD count control can be realized without using the zero current detection unit 114.

In addition, in the third embodiment, the ZCD count control is performed using the delay time signal Td. As shown in FIG. 8, the operation is the same as that of the first embodiment (FIG. 2) until the PWM signal Vg changes from H to L and the zero current signal ZCD changes from H to L. When the zero current signal ZCD switches from H to L, the delay time signal Td becomes H based on this, and the PWM signal Vg switches to H based on the delay time signal switching to L. The time during which the delay time signal Td maintains H may be set to an integer multiple of the resonance period of the LC resonance caused by the inductance component of the reactor 141 and the parasitic capacitance of the switching element 142. By maintaining the delay time signal Td at H for a time that is an integer multiple of the above-mentioned resonance period, the same operation as the ZCD count control of the first embodiment is realized. For example, FIG. 8 shows an example in which the delay time is set to 1 time the resonance period, and the same operation as when the permitted count number Cn is set to 2 in the ZCD count control of the first embodiment is realized.

Note that the configuration for performing ZCD count control using the delay time signal Td as described above replaces the permitted count number Cn with a delay time, so it does not prevent the use of the zero current detection unit 114. When performing control using the delay time signal Td, the timing adjustment unit 123 determines the length of the delay time (the length of time the delay time signal Td maintains H) instead of the permitted count number Cn, and outputs the delay time signal Td to the switching control unit 121. As a result, the delay time is input from the timing adjustment unit 123 to the switching control unit 121. The switching control unit 121 generates a PWM signal Vg based on the on-time ton sent from the output voltage control unit 122, the zero current signal ZCD from the zero current detection unit 114 or a signal from the both-end voltage detection unit of the switching element 142 (a minimum value signal that detects the bottom timing of the both-end voltage Vds), and the delay time signal Td sent from the timing adjustment unit 123, and controls the switching element 142. The switching control unit 121 does not set the PWM signal Vg to H (keeps it at L) while the delay time signal Td is H. By doing so, the same operation as the ZCD count control of the first embodiment can be realized by the delay time signal Td.

Furthermore, even if both the zero current detection unit 114 and the detection unit for the voltage across the switching element 142 are omitted, the configuration may be such that the operation of embodiment 1 is realized by calculation. The on-time ton of the switching element 142 is calculated by the output voltage control unit 122 as described above. The off-time of the switching element 142 is calculated as follows by dividing the off-time into the time until the reactor current iL reaches zero and the time when LC resonance occurs. That is, the time until the reactor current iL reaches zero can be calculated from the on-time ton, the full-wave rectified voltage detection value vinsen, the output voltage detection value vosen, and the reactance value of the reactor 141. The time when LC resonance occurs can be calculated from the resonance period calculated from the reactance value of the reactor 141 and the parasitic component of the switching element 142. From the above, the time of one switching period can be calculated, and the switching frequency fsw can be calculated from the various calculated times. Therefore, even if both the zero current detection unit 114 and the unit for detecting the voltage across the switching element 142 are omitted, the same operation as in embodiment 1 can be achieved.

Embodiment 4.
Next, a fourth embodiment will be described with reference to Fig. 9. Fig. 9 is a block diagram showing a power factor compensated power supply device according to the fourth embodiment. In Fig. 9, components that are the same as or correspond to those in the first embodiment are given the same reference numerals. A power supply main circuit section 1102 of a power factor compensated power supply device 103 includes a converter 1401 formed of a step-down chopper. That is, the converter 1401 includes an input capacitor 144 having one end connected to a high-voltage side electric circuit and the other end connected to a low-voltage side electric circuit on the output side of the full-wave rectifier circuit 112, a switching element 1421 having one end connected to a connection point between one end of the input capacitor 144 and the high-voltage side electric circuit, a reactor 1411 having one end connected to the other end of the switching element 1421, an output capacitor 145 having one end connected to the other end of the reactor 1411 and the other end connected to the low-voltage side electric circuit, and a diode 1431 having a cathode connected to the connection point between the other end of the switching element 1421 and one end of the reactor 1411 and an anode connected to the low-voltage side electric circuit. The other end of the input capacitor 144, the anode of the diode 1431, and the other end of the output capacitor 145 are connected to the other end of the load 92 via the low-voltage side electric circuit. Other configurations of the power factor compensated power supply device 103 are similar to those of the power factor compensated power supply device 100. In the power factor compensated power supply device 103, the waveforms of the various signals shown in Figures 2 and 3 have similar relationships, so that the control (ZCD control) of the above-mentioned first embodiment can be realized.

As described above, even if the configuration of converter 140 is replaced from a boost chopper to a step-down chopper, the same control as in embodiment 1 is realized. The configuration of converter 140 may be any circuit topology including a reactor and a switching element, and may be a configuration other than the boost chopper and step-down chopper described above, such as a flyback converter or a forward converter.

Embodiment 5.
Next, a fifth embodiment will be described with reference to FIG. 10. FIG. 10 is a block diagram showing the configuration of a power factor compensated power supply device according to the fifth embodiment. In FIG. 10, the same or corresponding components as those in the first embodiment are given the same reference numerals. In the second embodiment, the load 92 in the first embodiment is replaced with an LED (Light Emitting Diode) module 921. The LED module 921 may adopt a configuration in which, for example, LED chips are all connected in series, or may be connected in parallel or in series-parallel, or may be one LED. Furthermore, although an LED is connected as a load here, it may be changed to an organic electroluminescence (organic EL), a laser diode, or the like, instead of an LED.

Because it is desirable to use current control for LEDs due to their characteristics, the power factor compensated power supply device 200 includes an output current detection unit 116 that detects the output current io flowing through the LED module 921 and outputs it as an output current detection value iosen, and the configuration of the power supply control unit 220 is different from that of the first embodiment. In the power supply control unit 220, an output current control unit 222 is provided instead of the output voltage control unit 122 of the first embodiment. The output current detection value iosen detected by the output current detection unit 116 is input to the output current control unit 222. In addition, the power factor compensated power supply device 200 is provided with a dimmer 250 that outputs a dimming signal Sd, which is a command signal for the output current io to be passed through the LED. The dimming signal Sd output by the dimmer 250 is input to the output current control unit 222, and the output current control unit 222 derives the on-time ton of the switching element 142 from the dimming signal Sd and the output current detection value iosen. By configuring the power supply control unit 220 in this manner, it is possible to perform the same control as in embodiment 1 and control the current flowing through the LED module 921.

Thus, in the fifth embodiment, when an LED module 921 is provided as the load 92 of the second embodiment, the output current detection value iosen detected by the output current detection unit 116 is fed back to the output current control unit 222, and the output current io is controlled by the output current control unit 222 so that it becomes the target output current. Then, as in the first embodiment, the timing adjustment unit 123 determines the permitted count number Cn, and the switching control unit 121 controls the switching element 142. Even when the load 92 is the LED module 921, as in the first embodiment, the switching loss can be reduced by performing switching operation at the bottom timing when the reactor current iL becomes zero and rises (the timing when the reactor current iL switches from negative to positive) and when the voltage Vds across the switching element is minimum. In addition, by changing the permitted count number Cn, when the switching frequency fsw increases, the switching frequency fsw is further increased, and when the switching frequency decreases, the switching frequency is further decreased, thereby realizing switching operation that avoids the avoidance frequency band and distributed operation of the switching frequency fsw.

In the fifth embodiment, the dimming signal Sd corresponding to the output current command value is obtained from the dimmer 250. However, any modification may be made, for example, a memory unit that holds the output current command value may be provided inside the power supply control unit 220.

Embodiment 6.
Next, the sixth embodiment will be described based on FIG. 11. FIG. 11 is a block diagram showing a power factor compensated power supply device according to the sixth embodiment. In FIG. 11, the same or corresponding components as those in FIG. 10 are given the same reference numerals. The power factor compensated power supply device 201 is a device in which the load 92 in the second embodiment is replaced with an LED module 921. Therefore, the configuration of the power supply control unit is different from that in the fifth embodiment. In addition, the dimmer 2501 outputs a dimming signal Sd to the output current control unit 222 and the timing adjustment unit 223 of the power supply control unit 2201. In the power factor compensated power supply device 102 in the second embodiment, the full-wave rectified voltage detection value vinsen, the output voltage detection value vosen, and the output current detection value iosen are input to the timing adjustment unit 1231, and the permitted count number Cn is determined by comparing the full-wave rectified voltage detection value vinsen with the threshold value th. In addition, a method of correcting the threshold value th according to the size of the load 92 calculated from the output voltage detection value vosen and the output current detection value iosen has been described. In the case where the load 92 is an LED module 921 as in embodiment 6, as shown in FIG. 11, the full-wave rectified voltage detection value vinsen and the dimming signal Sd are input to the timing adjustment unit 223, and the threshold value th is corrected according to the dimming signal Sd.

This is because when the LED module 921 is used as a load, the output voltage vo does not change even if the output current io flowing through the LED module 921 is changed by the dimming function, and therefore the power consumed by the LED module 921 can be estimated if there is information on the dimming signal Sd that indicates information on the output current io.

Note that since the timing adjustment unit 223 can determine the permitted count number Cn without using the PWM signal Vg, the switching control unit 1211 does not need to output the PWM signal Vg to the timing adjustment unit 223.

Next, a modified example of the sixth embodiment will be described. FIG. 12 is a block diagram showing the configuration of a power factor compensated power supply device in a modified example of the sixth embodiment. In FIG. 12, components that are the same as or correspond to those in the sixth embodiment are given the same reference numerals. The power factor compensated power supply device 202 differs from the power factor compensated power supply device 201 in that it is connected to the load 92 via a current adjustment circuit 931. Even with this circuit configuration, the waveforms of the various signals shown in FIGS. 2 and 3 have the same relationship, so that the same effect as that described in the sixth embodiment can be achieved.

Although the present application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.
Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in the present application, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment.

100, 101, 102, 103, 200, 201, 202 Power factor compensated power supply device, 111 Input filter, 112 Full-wave rectifier circuit, 113 Output voltage detection unit, 114 Zero current detection unit, 115 Full-wave rectifier voltage detection unit, 116 Output current detection unit, 121, 1211 Switching control unit, 122 Output voltage control unit, 123, 1231, 223 Timing adjustment unit, 222 Output current control unit, 140, 1401 Converter, 141, 1411 Reactor, 142, 1421 Switching element, 250, 2501 Dimmer, 91 AC power supply, 92 Load, 93 Power converter, 931 Current adjustment circuit, iL Reactor current, io Output current, Sd Dimming signal, ton On time, vac Power supply voltage, vin Full-wave rectified voltage, vo output voltage, voref target voltage value, ZCD zero current signal

Claims (18)

a converter having a switching element and an inductor, which converts an AC voltage supplied from an AC power source into a DC voltage and outputs the DC voltage to a load;
A switching control unit that controls on/off of the switching element;
a timing adjustment unit that adjusts a switching frequency of the switching element by adjusting an on/off timing of the switching element,
the timing adjustment unit, when the fluctuating switching frequency approaches a predetermined avoidance frequency band, increases a magnitude of fluctuation of the switching frequency to reduce the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or increases the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band. The power factor compensated power supply device according to claim 1, wherein the timing adjustment unit, when the switching frequency approaches the avoidance frequency band while increasing, reduces the off-time of the switching element to further increase the switching frequency, and, when the switching frequency approaches the avoidance frequency band while decreasing, increases the off-time of the switching element to further decrease the switching frequency. a minimum value detection unit that detects when the voltage across the switching element oscillates to a minimum when the switching element is off, or when the current flowing through the inductor becomes positive from negative when the switching element is off, and outputs a minimum value signal to the switching control unit when such detection is detected;
3. The power factor compensated power supply device according to claim 1, wherein the switching control unit turns on the switching element based on the timing at which the minimum value signal is input, while following the adjustment of the on/off timing of the switching element by the timing adjustment unit. the switching control unit counts the number of times the minimum value signal is input, and turns on the switching element based on the timing at which the number of times reaches an allowed count number input from the timing adjustment unit;
4. The power factor compensated power supply device according to claim 3, wherein the timing adjustment unit changes the permitted count number when the switching frequency approaches the avoidance frequency band, and reduces the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or increases the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band. The power factor compensated power supply device according to claim 4, wherein the timing adjustment unit, when the switching frequency approaches the avoidance frequency band while increasing, decreases the permitted count number to further increase the switching frequency, and, when the switching frequency approaches the avoidance frequency band while decreasing, increases the permitted count number to further decrease the switching frequency. The power factor compensated power supply device according to claim 4 or 5, further comprising an input voltage detection unit that detects an input voltage input to the converter, and the timing adjustment unit determines the permitted count number based on the input voltage. the switching control unit turns on the switching element based on a timing when a delay time input from the timing adjustment unit has elapsed since the minimum value signal was input;
4. The power factor compensated power supply device according to claim 3, wherein the timing adjustment unit changes the delay time when the switching frequency approaches the avoidance frequency band, and reduces the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or increases the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band. The power factor compensated power supply device according to claim 7, wherein the timing adjustment unit, when the switching frequency approaches the avoidance frequency band while increasing, decreases the delay time to further increase the switching frequency, and when the switching frequency approaches the avoidance frequency band while decreasing, increases the delay time to further decrease the switching frequency. The power factor compensated power supply device according to claim 7 or 8, further comprising an input voltage detection unit that detects an input voltage input to the converter, and the timing adjustment unit determines the delay time based on the input voltage. The power factor compensated power supply device according to any one of claims 1 to 9, wherein the converter includes a step-up chopper or a step-down chopper. The power factor compensated power supply device according to any one of claims 1 to 10, wherein the converter is connected to the AC power supply via a rectifier circuit that rectifies the AC voltage. The power factor compensated power supply device according to any one of claims 1 to 11, wherein the converter is connected to the AC power supply via a filter unit that suppresses the conduction of noise from the converter to the AC power supply. The power factor compensated power supply device according to claim 12, wherein the timing adjustment unit increases the switching frequency to a frequency higher than the avoidance frequency band and higher than the cutoff frequency of the filter unit when the switching frequency increases and approaches the avoidance frequency band. The power factor compensated power supply device according to any one of claims 1 to 13, further comprising an output voltage detection unit that detects the output voltage output to the load, and an output voltage control unit that calculates the on-time of the switching element and outputs the calculated on-time to the switching control unit, and the output voltage control unit calculates the on-time so that the voltage value of the output voltage becomes a target voltage value. The power factor compensated power supply device according to any one of claims 1 to 14, wherein the avoidance frequency band is determined based on the operating frequency of a power converter connected in parallel or series with the power factor compensated power supply device between the AC power source and the load, or based on a noise standard with which the power factor compensated power supply device must comply. the load is an LED module;
14. The power factor compensated power supply device according to claim 1, further comprising an output current detection unit that detects an output current flowing to the LED module, an output current control unit that calculates an on-time of the switching element and outputs the on-time to the switching control unit, and a dimmer that outputs a dimming signal to the output current control unit, wherein the output current control unit calculates the on-time to set a current value of the output current to a target current value, and the target current value is determined based on the dimming signal. a minimum value detection unit that detects when the voltage across the switching element oscillates to a minimum when the switching element is off, or when the current flowing through the inductor becomes positive from negative when the switching element is off, and outputs a minimum value signal to the switching control unit when such detection is detected;
An input voltage detection unit that detects an input voltage input to the converter,
The dimmer outputs the dimming signal to the timing adjustment unit,
the switching control unit counts the number of times the minimum value signal is input, and turns on the switching element based on the timing at which the number of times reaches an allowed count number input from the timing adjustment unit;
17. The power factor compensated power supply device of claim 16, wherein the timing adjustment unit changes the permitted count number when the switching frequency approaches the avoidance frequency band, and reduces the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or increases the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band, and determines the permitted count number based on the input voltage and the dimming signal. a minimum value detection unit that detects when the voltage across the switching element oscillates to a minimum when the switching element is off, or when the current flowing through the inductor becomes positive from negative when the switching element is off, and outputs a minimum value signal to the switching control unit when such detection is detected;
An input voltage detection unit that detects an input voltage input to the converter,
The dimmer outputs the dimming signal to the timing adjustment unit,
the switching control unit turns on the switching element based on a timing when a delay time input from the timing adjustment unit has elapsed since the minimum value signal was input;
17. The power factor compensated power supply device of claim 16, wherein the timing adjustment unit changes the delay time when the switching frequency approaches the avoidance frequency band, and reduces the switching frequency from a frequency higher than the avoidance frequency band to a frequency lower than the avoidance frequency band, or increases the switching frequency from a frequency lower than the avoidance frequency band to a frequency higher than the avoidance frequency band, and determines the delay time based on the input voltage and the dimming signal.

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