JP7545454B2 - Display device - Google Patents

Description

The present invention relates to a structure of a display device having a transistor and a driving method thereof, and more particularly to a structure of an active matrix display device having thin film transistors and a driving method thereof, and also to an electronic device using such a display device in a display portion.

In recent years, so-called self-luminous display devices in which pixels are formed of light-emitting elements such as light-emitting diodes (LEDs) have been attracting attention. Light-emitting elements used in such self-luminous display devices include organic light-emitting diodes (OLEDs).
Diode, organic EL element, electroluminescence (Electro Lumi
Light-emitting diode (OLED) elements have been attracting attention and are being used in EL displays. Light-emitting diode (OLED) elements are self-emitting elements,
Compared to liquid crystal displays, it has the advantages of high pixel visibility, no need for a backlight, and fast response speed. The brightness of the light-emitting element is controlled by the value of the current flowing through it.

In recent years, active matrix display devices have been developed in which each pixel is provided with a light emitting element and a transistor for controlling the light emission of the light emitting element. Active matrix display devices are not only capable of high-definition, large-screen display, which is difficult with passive matrix display devices, but also realize low-power operation that exceeds that of passive matrix display devices and are highly reliable, and are expected to be put to practical use.

Methods of driving pixels in active matrix display devices can be classified according to the type of signal input to the pixel into a voltage input method and a current input method. The former voltage input method is a method in which a video signal (voltage) to be input to the pixel is input to a gate electrode of a driving element, and the driving element is used to control the brightness of the light-emitting element. The latter current input method is a method in which a set signal current is passed through the light-emitting element to control the brightness of the light-emitting element.

Here, an example of a pixel configuration in a display device to which a voltage input method is applied and a driving method thereof will be briefly described with reference to Fig. 67. Note that an EL display device will be taken as an example of a representative display device and the description will be given.

Fig. 67 is a diagram showing an example of a pixel configuration in a display device to which a voltage input method is applied (see Patent Document 1). The pixel shown in Fig. 67 has a driving transistor 6701, a switching transistor 6702, a storage capacitor 6703, a signal line 6704, a scanning line 6705, first and second power supply lines 6706 and 6707, and a light emitting element 6708.

In this specification, when a transistor is on, the gate
This refers to a state in which the source-to-source voltage exceeds its threshold voltage and current flows between the source and drain, and a transistor is off refers to a state in which the gate-to-source voltage of the transistor is below its threshold voltage and no current flows between the source and drain.

When the potential of the scanning line 6705 changes and the switching transistor 6702 is turned on, the video signal input to the signal line 6704 is input to the gate electrode of the driving transistor 6701. The gate-source voltage of the driving transistor 6701 is determined according to the potential of the input video signal, and the current flowing between the source and drain of the driving transistor 6701 is determined. This current is supplied to the light emitting element 6708, and the light emitting element 6708
will emit light.

In this way, the voltage input method is a method in which the gate and output voltages of the driving transistors are controlled by the potential of the video signal.
This is a method of setting the source voltage and the current flowing between the source and drain, and making the light-emitting element emit light with a brightness that corresponds to this current.

A polysilicon (p-Si) transistor is used as a semiconductor element for driving the light-emitting element. However, polysilicon transistors are prone to variations in electrical characteristics such as threshold voltage, on-current, and mobility due to defects in crystal grain boundaries. In the pixel shown in FIG. 67, if the characteristics of the driving transistor 6701 vary from pixel to pixel, even when the same video signal is input, the magnitude of the drain current of the driving transistor 6701 corresponding to the signal will differ, resulting in variations in the brightness of the light-emitting element 6708.

In addition, in the conventional pixel circuit (Fig. 67), the storage capacitor is connected between the gate and source of the driving transistor, but if this storage capacitor is made of a MOS transistor, when the gate-source voltage of the MOS transistor becomes almost equal to the threshold voltage of the MOS transistor, the channel region is no longer induced in the MOS transistor, and the MOS transistor no longer functions as a storage capacitor, resulting in the inability to properly store video signals.

JP 2001-147659 A

Thus, in the conventional voltage input method, variations in the electrical characteristics of the transistors result in variations in luminance.

In view of the above problems, an object of the present invention is to provide a semiconductor device, a display device, and a driving method thereof that can compensate for variations in the threshold voltage of a transistor and reduce variations in luminance.

Note that the present invention is not limited to semiconductor devices and display devices having light-emitting elements, and an object of the present invention is to suppress variations in drain current caused by variations in threshold voltage of transistors. Therefore, the destination of the drain current of the driving transistor is not limited to the light-emitting element. Hereinafter, the destination of the drain current is collectively referred to as a load.

The present invention is a semiconductor device having a pixel, the pixel including at least a signal line to which a video signal is applied, a capacitance line, a first transistor having a first electrode electrically connected to the signal line and a second electrode electrically connected to a load, a second transistor having a function as a switch for selecting whether or not to electrically connect a second electrode and a gate electrode of the first transistor, and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the capacitance line, and an amount of current flowing to the load is determined by a potential obtained by adding or subtracting an absolute value of a threshold voltage of the first transistor to or from a video signal voltage applied to the first electrode of the storage capacitor and the gate electrode of the first transistor, and a potential of the first electrode of the first transistor.

The present invention relates to a semiconductor device having a pixel, and the pixel includes at least a signal line, a capacitance line, and a first electrode electrically connected to the signal line and a second electrode electrically connected to a load.
a second transistor having a function as a switch for selecting whether or not to electrically connect a second electrode and a gate electrode of the first transistor, and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitance line, wherein a voltage based on a video signal voltage applied to a signal line and a threshold voltage of the first transistor is stored in the storage capacitor, and a current set in the first transistor according to the voltage is supplied to a load.

The present invention relates to a semiconductor device having a pixel, the pixel including a signal line, a capacitance line, a power supply line,
a third transistor having a function as a switch electrically connecting a first electrode of the first transistor to a power supply line; a fourth transistor having a function as a switch for selecting whether or not to electrically connect a second electrode of the first transistor to a gate electrode; a fifth transistor having a function as a switch electrically connecting a second electrode of the first transistor to a load; and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitance line, wherein a voltage based on a video signal voltage applied to a signal line and a threshold voltage of the first transistor is stored in the storage capacitor, and a current set in the first transistor according to the voltage is supplied to the load from the power supply line.

The present invention relates to a semiconductor device having a pixel, the pixel including a signal line, a capacitance line, a power supply line,
a third transistor having a function as a switch for electrically connecting a first electrode of the first transistor to a power supply line; a fourth transistor having a function as a switch for selecting whether or not to electrically connect a second electrode of the first transistor to a gate electrode; and a storage capacitor having a first electrode electrically connected to a gate electrode of the first transistor and a second electrode electrically connected to a capacitance line, wherein a voltage based on a video signal voltage applied to a signal line and a threshold voltage of the first transistor is stored in the storage capacitor, and a current set in the first transistor according to the voltage is supplied to the load from the power supply line.

In the semiconductor device of the present invention, the pixel may further include a sixth transistor, and an initial potential may be applied to the second electrode of the first transistor through the sixth transistor.

Note that in the semiconductor device of the present invention, the second electrode of the first transistor may be electrically connected to a wiring included in a pixel through a sixth transistor.

In the semiconductor device of the present invention, the pixel may further include an initialization line electrically connected to the second electrode of the first transistor through a sixth transistor.

In the semiconductor device of the present invention, other wirings included in the pixel may be used as the capacitance line.

In the semiconductor device of the present invention, it is preferable that the value of W/L of the first transistor be the largest among the values of the ratio W/L of the channel length L to the channel width W of each transistor included in the pixel.

In the semiconductor device of the present invention, the second transistor and the third transistor are
They may be of different conductivity types.

In the semiconductor device of the present invention, the pixel may further include a plurality of scanning lines, and gate electrodes of at least two transistors included in the pixel may be electrically connected to the same scanning line.

Note that the semiconductor device of the present invention may further include a plurality of scan lines, and gate electrodes of the plurality of transistors included in the pixel may be electrically connected to different scan lines.

In the semiconductor device of the present invention, the fourth transistor may be an N-channel transistor.

The present invention relates to a semiconductor device including a signal line, a capacitance line, a power supply line, a first transistor having a first electrode electrically connected to the signal line and a second electrode electrically connected to a load, and a second transistor having a second electrode electrically connected to the load.
a pixel including a second transistor having a function as a switch for selecting whether or not to electrically connect a first electrode and a gate electrode of the first transistor, and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitance line, wherein a current is caused to flow through a load to store a predetermined initial voltage in the storage capacitor, the second transistor is turned on, and a voltage based on a video signal voltage supplied from a signal line and a threshold voltage of the first transistor is stored in the storage capacitor, the voltage based on the voltage is applied to the gate electrode of the first transistor, and a current is supplied to the load from a power supply line via the first transistor.

The present invention relates to a semiconductor device including a signal line, a capacitance line, a power supply line, a first transistor having a first electrode electrically connected to the signal line and a second electrode electrically connected to a load, and a second transistor having a second electrode electrically connected to the load.
a pixel including a second transistor having a function as a switch for selecting whether to electrically connect the first electrode and the gate electrode of the first transistor, a third transistor having a function as a switch for applying an initial potential to the second electrode of the first transistor, and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitance line, wherein the third transistor is turned on to apply an initial potential to the second electrode of the first transistor, and then the second transistor is turned on to cause the storage capacitor to hold a video signal voltage supplied from a signal line and a voltage based on a threshold voltage of the first transistor, and the voltage based on the voltage is applied to the gate electrode of the first transistor,
A method for driving a semiconductor device is characterized in that a current is supplied to a load from a power supply line via a first transistor.

Note that in the driving method of the present invention, an initialization line electrically connected to the second electrode of the first transistor through a third transistor may be further provided, and an initial potential may be supplied from the initialization line.

In addition, in the driving method of the present invention, the voltage applied to the power supply line may be different between a period in which the storage capacitor stores the video signal voltage supplied from the signal line and the voltage based on the threshold voltage of the first transistor and a period other than the period.

Furthermore, in the above configuration, the load may be a light-emitting element.

Due to the structure of a transistor, it is difficult to distinguish between the source and the drain. Furthermore, depending on the operation of the circuit, the high and low potentials may be reversed.
The source and drain are not particularly specified, and are described as the first electrode and the second electrode. For example, when the first electrode is the source, the second electrode refers to the drain, and conversely, when the first electrode is the drain, the second electrode refers to the source.

In this document (specification, claims, drawings, etc.), one pixel refers to one color element. Therefore, in the case of a color display device consisting of R (red), G (green), and B (blue) color elements, the minimum unit of an image is composed of three pixels, an R pixel, a G pixel, and a B pixel. The color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white (W) may be added to RGBW. In addition, one or more colors, such as yellow, cyan, and magenta, may be added to RGB. In addition, for example, a similar color may be added to at least one of the RGB colors. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have different wavelengths. By using such color elements, it is possible to display more realistically and reduce power consumption. It is also possible to control the brightness of one color element using multiple areas. In this case, one color element is considered to be one pixel, and each area that controls the brightness is considered to be a sub-pixel. Therefore, for example, when the area gradation method is used, there are multiple regions for controlling brightness for one color element, and the gradation is expressed by the entirety of the regions, and each region for controlling brightness is a sub-pixel. Therefore, in this case, one color element is composed of multiple sub-pixels. In addition, in this case, the size of the region contributing to the display may differ depending on the sub-pixel. In addition, in the multiple regions for controlling brightness for one color element, that is, in the multiple sub-pixels constituting one color element, the signal supplied to each may be slightly different to widen the viewing angle.

In this document (specification, claims, drawings, etc.), pixels may be arranged (distributed) in a matrix. Here, pixels arranged (distributed) in a matrix may be arranged in a straight line in the vertical or horizontal direction, or in a jagged line. Therefore, for example, when a three-color color element (
For example, when performing full-color display using RGB, the dots may be arranged in stripes or in a so-called delta arrangement of three color elements. It also includes a Bayer arrangement. The size of the display area may differ for each dot of a color element. This can reduce power consumption or extend the life of the display element.

In this document (specification, claims, drawings, etc.), the light-emitting element refers to an element whose luminance can be controlled by the value of the current flowing through the element.
The EL element may be an organic EL element or an inorganic EL element.
In addition to the EL element, for example, a field emission display (FE
D) is a type of FED called SED (Surface-conduction
A light-emitting element such as an electron-emitter display can be used.

In addition, various types of transistors can be used as the transistors described in this document (specification, claims, drawings, etc.). Therefore, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also called microcrystal or semi-amorphous) silicon, etc. can be used. When a TFT is used, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, it is possible to reduce the manufacturing cost or increase the size of the manufacturing equipment. Since the manufacturing equipment can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, the transmission of light in a display element can be controlled by using a transistor on a transparent substrate. Alternatively, since the film thickness of the transistor is thin, a part of the film constituting the transistor can transmit light. Therefore, the aperture ratio can be improved.

In addition, by using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. As a result, it is possible to manufacture transistors with good electrical characteristics such as gate driver circuits (scanning line driver circuits) and source driver circuits (signal line driver circuits).
Signal processing circuits (signal generation circuits, gamma correction circuits, DA conversion circuits, etc.) can be integrally formed on the substrate.

In addition, by using a catalyst (such as nickel) when manufacturing microcrystalline silicon, it is possible to further improve the crystallinity and manufacture transistors with good electrical properties. In this case, the crystallinity can be improved by simply applying heat treatment without using a laser. As a result, the gate driver circuit (scanning line driving circuit) and part of the source driver circuit (such as an analog switch) can be integrally formed on the substrate. Furthermore, when a laser is not used for crystallization, unevenness in the crystallinity of the silicon can be suppressed. Therefore, a beautiful image can be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, transistors can be formed using a semiconductor substrate, an SOI substrate, or the like. This makes it possible to manufacture transistors that have little variation in characteristics, size, shape, and the like, have a high current supply capability, and are small in size. By using these transistors, it is possible to reduce the power consumption of a circuit or to increase the integration density of the circuit.

Alternatively, a transistor having a compound semiconductor or oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor formed by thinning these compound semiconductors or oxide semiconductors, can be used. This allows the manufacturing temperature to be lowered, and it becomes possible to manufacture a transistor at room temperature, for example. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a film substrate. It should be noted that these compound semiconductors or oxide semiconductors can be formed by:
They can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, and transparent electrodes. Furthermore, they can be formed or deposited simultaneously with transistors, which reduces costs.

Alternatively, transistors formed using an inkjet or printing method can be used. These methods allow manufacturing at room temperature, at a low vacuum, or on a large substrate. In addition, since manufacturing is possible without using a mask (reticle), the layout of the transistors can be easily changed. Furthermore, since there is no need to use a resist, material costs are reduced and the number of steps can be reduced. Furthermore, since a film is applied only to the necessary parts, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

Alternatively, a transistor having an organic semiconductor or a carbon nanotube can be used, which allows a transistor to be formed on a bendable substrate.
This makes it resistant to impacts.

Furthermore, transistors of various structures can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistors described in this document (specification, claims, drawings, etc.). By using MOS transistors, the size of the transistors can be reduced. Therefore,
A large number of transistors can be mounted. By using bipolar transistors, a large current can be passed, allowing the circuit to operate at high speed.

It is also possible to form a mixture of MOS transistors and bipolar transistors on one substrate, thereby achieving low power consumption, miniaturization, high speed operation, and the like.

Various other transistors can also be used.

The type of substrate on which the transistors are formed may be of various types and is not limited to a specific type. Examples of the substrate on which the transistors are formed include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, regenerated polyester)), leather substrates, rubber substrates, stainless steel substrates, and substrates having stainless steel foil. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a transistor may be formed on a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of the substrate on which the transistors are transferred include single crystal substrates, SOI substrates,
A glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester) or the like), a leather substrate, a rubber substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like can be used. Alternatively, the skin (skin epidermis, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a transistor may be formed on a substrate, and the substrate may be polished to make it thinner. Substrates to be polished include a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester) or the like), a leather substrate, a rubber substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. By using such a substrate, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, and reduce the weight or thickness of the device.

In this document (such as the specification, claims, or drawings), being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed in this invention, in addition to a predetermined connection relationship, other elements (such as another element or a switch) that enable electrical connection may be disposed between the predetermined connection relationships.

The switches shown in this document (specification, claims, drawings, etc.) may be of various types, such as electrical switches and mechanical switches. In other words, as long as they can control the flow of current, they are not limited to a specific type and may be of various types. For example, they may be transistors or diodes (e.g., P
The switch may be a transistor (such as an N-type diode, a PIN diode, a Schottky diode, or a diode-connected transistor), a thyristor, or a logic circuit that combines these. Therefore, when a transistor is used as a switch, the transistor operates simply as a switch, and therefore the polarity (conductivity type) of the transistor is not particularly limited. However,
When a smaller off-current is desired, it is preferable to use a transistor having a polarity with a smaller off-current. Examples of transistors with a smaller off-current include transistors with an LDD region and transistors with a multi-gate structure. In addition, when the potential of the source terminal of a transistor operated as a switch is close to a low-potential power supply (VSS, GND, 0V, etc.), it is preferable to use an N-channel type, and conversely, when the potential of the source terminal is close to a high-potential power supply (VDD, etc.), it is preferable to use a P-channel type. This is because the absolute value of the gate-source voltage can be increased, making it easier to function as a switch.
It is also possible to use both N-channel and P-channel switches to form a CMOS switch. When a CMOS switch is used, a current can flow if either the P-channel or N-channel switch is conductive, making it easier to function as a switch. For example,
Whether the voltage of the input signal to the switch is high or low, the appropriate voltage can be output.In addition, the voltage amplitude of the signal for turning the switch on and off can be reduced, which also reduces power consumption.

In this document (specification, claims, drawings, etc.), the words "formed on" or "formed on" do not necessarily mean that the material is directly on top of the material. They also include cases where the material is not directly on top of the material, that is, where another material is sandwiched between the material and the material. Thus, for example, when layer B is formed on layer A (or on layer A), it means that layer B is formed on layer A in direct contact with the material, and layer A is formed on layer A in direct contact with another material (e.g. layer C).
This includes cases where a layer (such as layer C or layer D) is formed on top of and layer B is formed directly on top of it. Similarly, the description "above" is not limited to being directly on top of a certain object, but also includes cases where another object is sandwiched between them. Thus, for example, when it is said that layer B is formed above layer A, it includes cases where layer B is formed directly on top of layer A and cases where another layer (such as layer C or layer D) is formed directly on top of layer A and layer B is formed directly on top of that. The same is true for the cases of "below" or "under" and includes cases where the layers are directly on top of each other and cases where they are not in contact.

According to the present invention, it is possible to suppress the variation in current value caused by the variation in threshold voltage of the transistor. Therefore, it is possible to supply a desired current to a load including a light-emitting element. In particular, when a light-emitting element is used as a load, the display device of the present invention can compensate for the variation in threshold voltage of the transistor, so that the current flowing through the light-emitting element is determined in a manner independent of the threshold voltage of the transistor. This makes it possible to reduce the variation in luminance of the light-emitting element, thereby improving the image quality of the display device.

FIG. 1 is a diagram showing an example of a basic configuration of a pixel in a display device of the present invention. FIG. 1 is a diagram showing an example of a basic configuration of a pixel in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. 3A to 3C are diagrams illustrating the operation of a pixel circuit in a display device of the present invention. 3A to 3C are diagrams illustrating the operation of a pixel circuit in a display device of the present invention. 3A to 3C are diagrams illustrating the operation of a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. 4A and 4B are diagrams illustrating a timing chart of a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. 3A to 3C are diagrams illustrating the operation of a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. 3A to 3C are diagrams illustrating the operation of a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 4 is a timing chart for explaining a pixel circuit in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a pixel configuration in a display device of the present invention. FIG. 2 is a diagram showing an example of a layout of a pixel configuration in a display device of the present invention. FIG. 1 illustrates a configuration example of a display device of the present invention. FIG. 2 is a diagram showing a configuration example of a scanning line driver circuit in a display device of the present invention. FIG. 2 is a diagram showing a configuration example of a signal line driver circuit in a display device of the present invention. FIG. 1 illustrates a configuration example of a display device of the present invention. FIG. 1 illustrates a configuration example of a display device of the present invention. FIG. 1 illustrates a configuration example of a display device of the present invention. FIG. 1 is a diagram showing an example of the configuration of a display panel used in a display device of the present invention. FIG. 2 is a diagram showing an example of the structure of a light-emitting element used in a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. FIG. 1 illustrates an example of a configuration of a display device of the present invention. 1A to 1C are diagrams illustrating a structure of a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. 2A to 2C are diagrams illustrating a method for manufacturing a transistor used in a display device of the present invention. FIG. 2 is a diagram showing an example of hardware for controlling a display device of the present invention. FIG. 1 is a diagram showing an example of an EL module using a display device of the present invention. FIG. 1 is a diagram showing a configuration example of a display panel using a display device of the present invention. FIG. 1 is a diagram showing a configuration example of a display panel using a display device of the present invention. FIG. 13 is a diagram showing an example of an EL television receiver using a display device of the present invention. 1A to 1C are diagrams illustrating examples of electronic devices to which a display device of the present invention is applied. FIG. 1 shows a conventional pixel configuration.

Hereinafter, the embodiments of the present invention will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the present invention can be implemented in many different forms, and that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the present embodiment.

(Embodiment 1)
First, the basic configuration of a pixel circuit in the display device of this embodiment will be described with reference to Fig. 3. Note that the description will be given taking an EL element as an example of a light emitting element.

1 is a diagram showing a circuit configuration for acquiring a voltage based on a video signal voltage and a threshold voltage of a transistor in the pixel configuration of this embodiment. FIG. 1 shows first and second transistors 101 and 102, a storage capacitor 103, a scanning line 104, a signal line 105, a power supply line 106,
It is composed of a capacitance line 107 and a light emitting element 108 .

In FIG. 1, the first and second transistors 101 and 102 are both P-channel transistors.

The gate electrode of the first transistor 101 is connected to the second electrode of the second transistor 102.
and a first electrode of a storage capacitor 103, the first electrode of which is connected to a signal line 105;
The second electrode of the second transistor 102 is connected to a first electrode of the second transistor 102. The gate electrode of the second transistor 102 is connected to a scanning line 104. The second electrode of the storage capacitor 103 is connected to a capacitor line 107. The second electrode of the light-emitting element is connected to a power supply line 106.
is connected to

A video signal voltage _Vdata is applied to the signal line 105, and a potential _VCL is applied to the capacitance line 107. The magnitude relationship between the potentials is _Vdata > _VCL . A power supply potential VSS is applied to the power supply line .

Here, the first transistor 101 has a function of supplying a current to the light-emitting element 108 .
In addition, the second transistor functions as a switch that puts the first transistor 101 into a diode-connected state.

In this specification, the term "diode connection" refers to a state in which the gate electrode and the first or second electrode of a transistor are connected.

In the pixel circuit shown in FIG. 1, when the second transistor 102 is turned on, the first transistor 101 is brought into a diode-connected state, and a current flows through the storage capacitor 103.
The storage capacitor 103 is charged. The charging of the storage capacitor 103 continues until the voltage stored in the storage capacitor 103 becomes a difference V _data - |V _th |-V _CL between the video signal voltage V _data , the threshold voltage |V _{th | of the first transistor 101, and the potential V CL of the capacitance line 107. When the voltage stored in the storage capacitor 103 becomes V data - |V th | -V CL ,} the first transistor 101 is turned off and no current flows through the storage capacitor 103.

Through the above operation, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 101 can be held in the storage capacitor 103 .

FIG. 2 shows a circuit configuration for acquiring the threshold voltage of the first transistor when the first transistor is an n-channel transistor.

FIG. 2 shows a first and second transistors 201 and 202, a storage capacitor 203, a scanning line 204,
It is composed of a signal line 205 , a power line 206 , a capacitance line 207 , and a light emitting element 208 .

Note that in FIG. 2, the second transistor 202 is an N-channel type.

A video signal voltage V _data is applied to the signal line 205, and a potential V _CL is applied to the capacitance line 207. The magnitude relationship of the potentials is V _CL >V _data . A power supply potential VDD is applied to the power supply line 206.

In the pixel circuit shown in FIG. 2, when the second transistor 202 is turned on, the first transistor 201 is brought into a diode-connected state, and a current flows through the storage capacitor 203.
The storage capacitor 203 is charged. The voltage stored in the storage capacitor 203 is determined by the potential _VCL of the capacitance line 207, the video signal voltage _Vdata , and the potential Vcc of the first transistor 20
This continues until the voltage held in the storage capacitor 203 becomes V _CL - V _data - |V _th |, which is the difference between the threshold voltage |V _th | of the first transistor 201 and the threshold voltage |V th | of the first transistor 201 . When the voltage held in the storage capacitor 203 becomes V _CL - V _data - |V _th |, the first transistor 201 is turned off and no current flows through the storage capacitor 203 .

Through the above operation, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 101 can be held in the storage capacitor 203 .

1 and 2, the second transistor functions as a switch that puts the first transistor into a diode-connected state. Therefore, instead of the second transistor, another element having a switch function may be used. For example, a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), a thyristor, or a logic circuit combining these may be used.

Next, a description will be given of a pixel configuration of this embodiment having the basic circuit configuration shown in Fig. 1 or 2. Note that the description will be given taking an EL element as an example of a light emitting element.

FIG. 3 is a circuit diagram of a pixel circuit according to the present embodiment.
1 to 5 transistors 301 to 305, a storage capacitor 306, a signal line 307, first to fourth scanning lines 308 to 311, first and second power supply lines 312 and 313, a capacitor line 314, and a light-emitting element 3
It consists of 15 etc.

Here, the first transistor 301 is used as a transistor for supplying a current to a light emitting element 316, and the second to fifth transistors 302 to 305 are used as switches for selecting whether or not a wiring is connected.

The gate electrode of the first transistor 301 is connected to the second electrode of the fourth transistor 304.
and a first electrode of the storage capacitor 306, the first electrode of which is connected to the second transistor 302.
and a second electrode of the third transistor 303,
The second transistor 302 has a gate electrode connected to a first scanning line 308 and a first electrode connected to a signal line 307. The third transistor 303 has a gate electrode connected to a first scanning line 308 and a first electrode connected to a signal line 307.
The gate electrode of the fourth transistor 304 is connected to the second scanning line 309, and the first electrode of the fourth transistor 304 is connected to the third scanning line 310. The gate electrode of the fifth transistor 305 is connected to the fourth scanning line 311, and the second electrode of the fifth transistor 305 is connected to the first electrode of the light-emitting element 315. The storage capacitor 306 is
The second electrode of the light emitting element 315 is connected to the capacitance line 314.
is connected to the power supply line 313.

A power supply potential VDD is applied to the first power supply line 312, and a power supply potential VDD is applied to the second power supply line 313.
A power supply potential VSS is applied to the capacitor line 314, and a potential _VCL is applied to the capacitor line 314. The magnitude relationships of the potentials are VDD>VSS and VDD> _VCL .

In the pixel circuit shown in FIG. 3, the first to fifth transistors 301 to 305 are all P-channel transistors.

Note that the first transistor 301 in FIG. 3 corresponds to the first transistor 10 in FIG.
1. Moreover, a fourth transistor 304 in Fig. 3 corresponds to the second transistor 102 in Fig. 1. Moreover, a second power supply line 313 in Fig. 3 corresponds to the power supply line 106 in Fig. 1.

Next, the operation of the pixel circuit of this embodiment will be explained using Figures 4 to 7.

FIG. 4 shows a timing chart of the video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311, which are divided into three periods, the first to third periods T1 to T3, in accordance with the operations of the pixel circuits shown in FIGS. 5 to 7.

5 to 7 are diagrams showing the connection state of the pixel circuit in each period according to the present embodiment.
5 to 7, the solid lines indicate that the portions are electrically connected, and the dashed lines indicate that the portions are not electrically connected.

First, the operation of the pixel circuit in the first period T1 will be described with reference to Fig. 5. Fig. 5 is a diagram showing a connection state of the pixel circuit in the first period T1. In the first period T1, the second to fourth scanning lines 309 to 311 are at the L level, and the third to fifth transistors 303 to
Also, the first scanning line 308 becomes H level, and the second transistor 3
02 is turned off. As a result, the first transistor 301 is in a diode-connected state, and a current flows through the light-emitting element 315. As a result, the second electrode of the first transistor 301,
The potential of the first electrode of the storage capacitor 306 drops, and a certain initial voltage is stored in the storage capacitor 306 .

By the above operation, a certain initial voltage is held in the storage capacitor 306 during the first period T1.
In this specification, this operation is called initialization.

Next, the operation of the pixel circuit in the second period T2 will be described with reference to Fig. 6. Fig. 6 is a diagram showing the connection state of the pixel circuit in the second period T2. In the second period T2, the first and third scanning lines 308 and 310 are at the L level, and the second and fourth transistors 30
The second and fourth scanning lines 309 and 311 are turned on.
The third and fifth transistors 303 and 305 are turned off. Also, a video signal voltage V _data is applied to the signal line 307. As a result, the second electrode of the first transistor 301 is connected to the signal line 307, and the first transistor 301 is in a diode-connected state, so that a current flows through the storage capacitor 306, and the storage capacitor 306 is charged.
The charging of the capacitor 306 is performed when the voltage held in the holding capacitor 306 is a difference V _data between the video signal voltage V _data , the threshold voltage |V _th | of the first transistor 301, and the potential V _CL of the capacitance line 314.
This continues until the voltage held in the holding capacitor 306 becomes V _data −|V _th |−V _CL .
When |V _th |−V _CL , the first transistor 301 is turned off and no current flows through the storage capacitor 306 .

By the above operation, in the second period T2, the video signal voltage V _data is stored in the storage capacitor 306.
and holds a voltage based on the threshold voltage |V _th | of the first transistor 301 .

In addition, in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V th | of the first transistor 301 in the storage capacitor 306 during the second period T2, the potential of the second electrode of the first transistor 301 must be set in advance to be lower than the difference V _data - |V _th | between the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301. Therefore, by flowing a current to the light-emitting element 315 during _the first period T1,
The potential of the second electrode of the first transistor 301 can be reliably set to be lower than V _data - |V _th |, so that the threshold voltage can be reliably obtained.

Next, the operation of the pixel circuit in the third period T3 will be described with reference to Fig. 7. Fig. 7 is a diagram showing a connection state of the pixel circuit in the third period T3. In the third period T3, the second and fourth scanning lines 309 and 311 are at the L level, and the third and fifth transistors 30
Also, the first and third scanning lines 308 and 310 are at H level.
The second and fourth transistors 302 and 304 are turned off. As a result, the second electrode of the first transistor 301 is connected to the first power supply line 312. In addition, the gate electrode of the first transistor 301 is supplied with the voltage V _data −|V
Since _the sum V _data -|V _th | of the potential V _CL of the capacitance line 314 and the potential V _CL of the capacitance line 314 is added, the gate-source voltage of the first transistor 301 in the period T3 is V _gs (T3)
Then, V _gs (T3) is expressed by the following formula (1).

Therefore, the current _IOLED flowing between the drain and source of the first transistor 301 is expressed by the following equation (2), and this current flows through the fifth transistor 305 to the light-emitting element 315, causing the light-emitting element 315 to emit light.

Here, β is a constant given by the mobility and size of the transistor, the capacitance of the oxide film, and the like.

By the above operation, in the third period T3, a current _IOLED that depends on the video signal voltage _Vdata is supplied to the light emitting element 315, causing the light emitting element 315 to emit light.

In the operation process of the pixel circuit shown in FIG.
The functions of 305 will be explained again.

The first transistor 301 has a function of supplying a current to the light-emitting element 315 in the third period T3.

The second transistor 302 functions as a switch that connects the first electrode of the first transistor 301 and the signal line 307 in order to input a video signal voltage V _data to the pixel in the second period T2.

The third transistor 303 is connected to the first transistor 30
In order to apply the potential of the first power supply line 312 to the first electrode of the first transistor 3
01 and the first power supply line 312.

The fourth transistor 304 supplies the first transistor 3
01 threshold voltage |V _th |, the first transistor 301
It functions as a switch that puts the

The fifth transistor 305 operates to pass a current to the light-emitting element 315 in the first and third periods T1 and T3, and not to pass a current to the light-emitting element 315 in the second period T2. That is, the fifth transistor 305 functions as a switch that connects the second electrode of the first transistor 301 and the first electrode of the light-emitting element 315 in order to control the supply of a current to the light-emitting element 315.

Through the above-described operation process, the current I _OLED is supplied to the light emitting device 315, and the light emitting device 3
The light emitting element 315 can be made to emit light with a luminance corresponding to the current I _OLED . At this time, as shown in the formula (2), the current I _OLED flowing through the light emitting element 315 is expressed in a form independent of the threshold voltage |V _th | of the first transistor 301, so that the variation in the threshold voltage of the transistor can be compensated for.

Note that in order to enable a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 to be held in the holding capacitor 306 in the second period T2 and to turn on the first transistor 301 in the third period T3, the range of the video signal voltage V _data is set to V _CL + |V _th |<V _data ≦VDD.

The potential _VCL of the capacitance line 314 is a voltage VCL between the video signal voltage _Vdata and the first transistor 3
It is sufficient that the potential is lower than the difference V _data - |V _th | between the threshold voltage |V th | of 01 and the potential |V data - |V _th |.
Note that in order to reliably hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 in the storage capacitor 306, it is preferable that the potential V _CL of the capacitance line 314 be lower.

3, the first transistor 301 is a P-channel transistor, but the first transistor may be an N-channel transistor. A pixel configuration in which the first transistor is an N-channel transistor is shown in FIG.

FIG. 8 is a circuit diagram of a pixel circuit according to the present embodiment.
1 to 5 transistors 801 to 805, a storage capacitor 806, a signal line 807, first to fourth scanning lines 808 to 811, first and second power supply lines 812 and 813, a capacitor line 814, a light-emitting element 8
It consists of 15 parts.

In the pixel circuit of FIG. 8, the second to fifth transistors 802 to 805 are all N-channel transistors.

Here, the first transistor 801 is used as a transistor for supplying a current to a light emitting element 815, and the second to fifth transistors 802 to 805 are used as switches for selecting whether or not a wiring is connected.

The gate electrode of the first transistor 801 is connected to the second electrode of the fourth transistor 804.
and a first electrode of a storage capacitor 806, the first electrode of which is connected to the second transistor 802.
and a second electrode of the third transistor 803,
The second transistor 802 has a gate electrode connected to a first scanning line 808 and a first electrode connected to a signal line 807. The third transistor 803 has a gate electrode connected to a first scanning line 808 and a first electrode connected to a signal line 807.
The gate electrode of the fourth transistor 804 is connected to the second scanning line 809, and the first electrode of the fourth transistor 804 is connected to the third scanning line 810. The gate electrode of the fifth transistor 805 is connected to the fourth scanning line 811, and the second electrode of the fifth transistor 805 is connected to the second electrode of the light-emitting element 815. The storage capacitor 806 is
The second electrode is connected to a capacitor line 814.
is connected to the power supply line 813.

A power supply potential VSS is applied to the first power supply line 812, and a power supply potential VSS is applied to the second power supply line 813.
A power supply potential VDD is applied to the capacitor line 814, and a potential _VCL is applied to the capacitor line 814. Note that the magnitude relationship between the potentials is VDD>VSS and _VCL >VSS.

Note that the first transistor 801 in FIG. 8 is the same as the first transistor 20 in FIG.
2. A fourth transistor 804 in Fig. 8 corresponds to the second transistor 202 in Fig. 2. A second power supply line 813 in Fig. 8 corresponds to the power supply line 206 in Fig. 2.

Next, the operation of the pixel circuit of this embodiment will be explained using FIG. 9.

9 shows a timing chart of the video signal voltage and pulses input to the signal line 807 and the first to fourth scanning lines 808 to 811. Since the first to fifth transistors are all N-channel type, the timing of the pulses input to the first to fourth scanning lines 808 to 811 is inverted in H and L levels compared to the case where all the transistors are P-channel type (FIG. 4). In addition, in accordance with the operation of each pixel circuit, the first to third periods T1 to
It is divided into three periods: T1, T2, T3, and T4.

8 in the first to third periods T1 to T3 is the same as the pixel circuit shown in FIG. 3. That is, in the first period T1, a certain initial voltage is held in the storage capacitor 806. In other words, initialization is performed. Next, in the second period T2, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 is held in the storage capacitor 806. Then, in the third period T3, a current I _OLED depending on the video signal voltage V _data is supplied to the light-emitting element 815, causing the light-emitting element 815 to emit light. Note that the light-emitting element 815
The current I _OLED flowing through the element is expressed by the following formula (3).

In addition, in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V th | of the first transistor 801 in the storage capacitor 806 during the second period T2, the potential of the second electrode of the first transistor 801 must be set higher than the sum V _data +|V _th | of the video signal voltage _{V data} and the threshold voltage |V _th | of the first transistor 801. Therefore, by flowing a current to the light-emitting element 815 during the first period T1,
The potential of the second electrode of the first transistor 801 can be reliably set to be higher than V _data +|V _th |, so that the threshold voltage can be reliably obtained and compensated for.

In the operation process of the pixel circuit shown in FIG.
The functions of the first to fifth transistors 301 to 305 are the same as those of the first to fifth transistors 301 to 305 in the pixel circuit shown in FIG.

Through the above-described operation process, a current I _OLED is supplied to the light emitting device 815, and the light emitting device 8
The light emitting element 815 can be made to emit light with a luminance corresponding to the current I _OLED . At this time, as shown in the formula (3), the current I _OLED flowing through the light emitting element 815 is expressed in a form independent of the threshold voltage |V _th | of the first transistor 801, so that the variation in the threshold voltage of the transistor can be compensated for.

Note that in order to enable a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 to be held in the holding capacitor 806 in the second period T2 and to turn on the first transistor 801 in the third period T3, the range of the video signal voltage V _data is set to VSS≦V _data <V _CL −|V _th |.

The potential _VCL of the capacitance line 814 is a voltage VCL between the video signal voltage _Vdata and the first transistor 3
01 and the threshold voltage |V _th | of the first transistor, V _data +|V _th |.
Note that in order to reliably hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 in the storage capacitor 806, the potential V _CL of the capacitor line 814 is preferably higher.

As described above, the pixel configuration of this embodiment can compensate for variations in the threshold voltage of the transistors and reduce variations in luminance, thereby improving image quality.

In addition, in the pixel circuit of this embodiment, as shown in formulas (2) and (3), the current _IOLED flowing through the light-emitting element becomes substantially constant when the magnitude of the video signal voltage _Vdata is determined. Therefore, a constant current according to the video signal voltage can be supplied to the light-emitting element, and the light-emitting element can be made to emit light with a constant luminance, thereby reducing luminance unevenness during the light-emitting period (T3).

In addition, since the current I _OLED flowing through the light-emitting element does not depend on the capacitance value of the storage capacitor, it is possible to supply a constant current to the light-emitting element even if the capacitance value varies from pixel to pixel due to a manufacturing error such as a misalignment of a mask pattern during manufacturing.

In addition, in the pixel circuit of this embodiment, the threshold voltage | _Vth | of the first transistor and the video signal voltage _Vdata are acquired within the same period, so that the preparation period before the light emitting element is made to emit light can be shortened, and the light emitting period can be made longer for one frame period. Therefore, the duty ratio (the ratio of the light emitting period to one frame period) can be increased, and the voltage applied to the light emitting element can be reduced.
This makes it possible to reduce power consumption and to reduce deterioration of the light emitting element.

Furthermore, since the preparation period before the light emitting element is made to emit light can be made shorter, the length of one frame period can be made shorter, and the frame frequency can be made higher.
This makes it possible to suppress false contours and flickering when displaying moving images, etc., thereby improving image quality.

In this embodiment, when the initialization is performed in the period T1, the first electrode of the first transistor is connected to the first power supply line via the third transistor, but the connection destination of the first electrode of the first transistor is not limited to this.
The first transistor may be connected to a signal line via a second transistor, and a potential that turns on the first transistor may be applied to the signal line, thereby performing initialization.

In this embodiment, when a current is supplied to the light-emitting element in the period T3, the first electrode of the first transistor is connected to the first power supply line via the third transistor.
The connection destination of the first electrode of the transistor is not limited to this. The first electrode of the first transistor may be connected to a signal line via a second transistor, and a potential that turns on the first transistor may be applied to the signal line to supply a current to the light-emitting element.

In this embodiment, the storage capacitor may be formed of a metal or a MOS transistor. In particular, when the storage capacitor is formed of a MOS transistor, the area occupied by the storage capacitor can be made smaller than when the storage capacitor is formed of a metal, and therefore the aperture ratio of the pixel can be increased.

For example, in the pixel circuit shown in FIG. 3, an example in which the storage capacitor is formed of a MOS transistor is shown in FIGS.

FIG. 10 shows a case where the storage capacitor 306 is formed of a P-channel transistor.
When forming a storage capacitor using a P-channel transistor, it is necessary to induce a channel region in the P-channel transistor in order to store electric charges, so the potential of the gate electrode of the P-channel transistor must be lower than the potentials of the first and second electrodes of the P-channel transistor.
In this case, the first electrode has a higher potential than the second electrode. Therefore, in order to make the P-channel transistor function as a storage capacitor, the first and second electrodes of the P-channel transistor are used as the first electrodes of a storage capacitor 306 and are connected to the gate electrode of the first transistor 301 and the second electrode of the fourth transistor 304. In addition, the gate electrode of the P-channel transistor is used as the second electrode of the storage capacitor 306 and is connected to a capacitance line 314.

FIG. 11 shows a case where the storage capacitor 306 is formed of an N-channel transistor.
When forming a storage capacitor with an N-channel transistor, it is necessary to induce a channel region in the N-channel transistor in order to store electric charges, so the potential of the gate electrode of the N-channel transistor must be higher than the potentials of the first and second electrodes of the N-channel transistor.
The first electrode of the N-channel transistor 302 is connected to the gate electrode of the first transistor 301 and the second electrode of the fourth transistor 304. The first and second electrodes of the N-channel transistor 302 are connected to the gate electrode of the first transistor 301 and the second electrode of the fourth transistor 304. In addition, the first and second electrodes of the N-channel transistor 302 are connected to the second electrode of the storage capacitor 306 and to a capacitor line 314.

As another example, in the pixel circuit shown in FIG. 8, the first and second storage capacitors are MOS
An example in which the transistor is used is shown in FIG. 12 and FIG.

12 shows a case where the storage capacitor 806 is formed of an N-channel transistor. In the case of the pixel circuit shown in FIG. 8, the second electrode of the storage capacitor 806 has a higher potential than the first electrode. Therefore, in order to make the N-channel transistor function as a storage capacitor, the first and second electrodes of the N-channel transistor are used as the first electrode of the storage capacitor 806, and the gate electrode of the first transistor 801 and the second electrode of the fourth transistor 804 are used as the gate electrode of the storage capacitor 806.
In addition, the gate electrode of the N-channel transistor is used as a second electrode of the storage capacitor 806 and is connected to a capacitor line 814.

FIG. 13 shows a case where the storage capacitor 806 is formed of a P-channel transistor.
In order to make the P-channel transistor function as a storage capacitor, a gate electrode of the P-channel transistor is used as a first electrode of a storage capacitor 806 and is connected to a gate electrode of the first transistor 801 and a second electrode of the fourth transistor 804. In addition, the first and second electrodes of the P-channel transistor are used as second electrodes of the storage capacitor 806 and are connected to a capacitance line 814.

As in this embodiment, by connecting the storage capacitor between the gate electrode of the first transistor and the capacitance line, particularly when the storage capacitor is formed of a MOS transistor, a voltage greater than the threshold voltage of the MOS transistor is always applied between the gate and source of the MOS transistor, so that the MOS transistor can always induce a channel region and always function as a storage capacitor. Therefore, it becomes possible to correctly store a desired voltage in the storage capacitor during the operation process of the pixel circuit.

Furthermore, in the pixel configuration of this embodiment, among the values of the ratio W/L of the channel length L to the channel width W of each of the first to fifth transistors, if the value of W/L of the first transistor is set to be the largest, the current flowing between the drain and source of the first transistor can be made larger. As a result, when acquiring a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor in the period T2, a larger current can be used to operate, so that a faster operation can be achieved. Also, the current I _OLED flowing to the light-emitting element in the period T3 can be made larger, and the luminance can be increased.

In this embodiment, since the timing of the pulses input to the second scanning line and the fourth scanning line is the same, the third transistor and the fifth transistor may be controlled by either the second scanning line or the fourth scanning line.

For example, in the pixel circuit shown in FIG. 3, an example in which the third and fifth transistors 303 and 305 are controlled by the second scan line 309 is shown in FIG.
A gate electrode of the first transistor 303 and a gate electrode of the fifth transistor 305 are connected to a second scan line 309 .

As another example, in the pixel circuit shown in FIG.
An example in which the scanning lines 3 and 805 are controlled by the fourth scanning line 811 is shown in FIG.
In No. 5 , a gate electrode of a third transistor 803 and a gate electrode of a fifth transistor 805 are connected to a fourth scan line 811 .

In this way, by controlling the third and fifth transistors by the same scanning line, the number of scanning lines can be reduced, and the aperture ratio of the pixel can be increased.

In this embodiment, the second to fifth transistors are all P-channel transistors or all N-channel transistors, which are transistors of the same conductivity type, but the present invention is not limited to this. A circuit may be configured using both P-channel and N-channel transistors.

3, the fourth transistor 304 may be an N-channel type, and the transistors other than the fourth transistor 304 may be a P-channel type. This pixel circuit is shown in Fig. 16. Also, a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311 is shown in Fig. 17.

In this way, if the fourth transistor 304 is an N-channel type,
Since the leakage current at the transistor 304 is smaller than that in the case of a P-channel transistor,
The leakage of the electric charge held in the storage capacitor 306 is reduced, and the fluctuation of the voltage held in the storage capacitor 306 is reduced. As a result, a constant voltage is always applied to the gate electrode of the first transistor 301, particularly during the light emission period (T3), so that a constant current can be supplied to the light emitting element 315. As a result, the light emitting element 315 can emit light with a constant luminance, and luminance unevenness can be reduced.

3, the second transistor 302 may be an N-channel type, and the transistors other than the second transistor 302 may be a P-channel type. This pixel circuit is shown in Fig. 18. Also, a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311 is shown in Fig. 19.

In this way, when the second transistor 302 is an N-channel type, the timing of the pulses input to the first scanning line 308, the second scanning line 309, and the fourth scanning line 311 is the same.
05 can be controlled by any one of the first scanning line 308 , the second scanning line 309 , and the fourth scanning line 311 .

Here, the second transistor 302, the third transistor 303, and the fifth transistor 3
20 shows an example in which the gate electrodes of the second transistor 302, the third transistor 303, and the fifth transistor 305 are controlled by the first scanning line 308. Note that in FIG. 20, the gate electrodes of the second transistor 302, the third transistor 303, and the fifth transistor 305 are connected to the first scanning line 308.

In this manner, by making the second transistor have a different conductivity type from the transistors other than the second transistor, the number of scanning lines can be reduced and the aperture ratio of the pixel can be increased.

It should be noted that which of the second to fifth transistors has which conductivity type is not limited to the above.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 2)
In the first embodiment, a separate capacitance line is provided, but other existing wiring may be used in place of the capacitance line. For example, by using any one of the first to fourth scanning lines of a pixel in another row as a capacitance line, it is possible to eliminate the capacitance line of the pixel. In this embodiment, the first to fourth scanning lines of a pixel in another row are used in place of the capacitance line of the pixel.
A case where any one of the fourth scanning lines is used will be described.
An explanation will be given by taking the L element as an example.

For example, FIG. 21 shows an example of a pixel circuit in which the second scanning line of the pixel in the previous row is used instead of the capacitance line of the pixel in question in the pixel circuit shown in FIG.

21 shows the configuration of a pixel Pixel(i) in a certain row i and a pixel Pixel(i-1) in the previous row (i-1).
) is composed of first to fifth transistors 2101 to 2105, a storage capacitor 2106, first to fourth scanning lines 2108 to 2111, a light emitting element 2115, etc. Also, the pixel Pixel(i) in the i-th row is composed of first to fifth transistors 2121 to 2125, a storage capacitor 21
26, first to fourth scanning lines 2128 to 2131, and a light-emitting element 2135. In addition, the pixel Pixel(i) in the i-th row and the pixel Pixel(i-1) in the (i-1)-th row
A signal line 2107 and first and second power supply lines 2112 and 2113 are shared by these.

In Fig. 21, the connections of each element in each pixel are almost the same as those in the pixel circuit shown in Fig. 3, so detailed explanations will be omitted. The difference between Fig. 3 and Fig. 21 is that instead of the capacitance line of the pixel Pixel(i) in the i-th row, the second scanning line 2109 of the pixel Pixel(i-1) in the (i-1)-th row is used.
is used, and the second electrode of the storage capacitor 2126 of the pixel Pixel(i) in the i-th row is connected to the second scanning line 2109 of the pixel Pixel(i-1) in the (i-1)-th row.

In addition, in the pixel Pixel(i-1) in the (i-1)th row,
Instead of the capacitance line of l(i-1), the second scanning line 2149 of the pixel Pixel(i-2) in the (i-2)th row is used, and the storage capacitance 21 of the pixel Pixel(i-1) in the (i-1)th row is
The second electrode of pixel Pixel(i-2) in the (i-2)th row is connected to the second scanning line 214
9.

Here, the signal line 2107 and the first to fourth pixels Pixel(i-1) in the (i-1)th row
FIG. 2 is a timing chart of the video signal voltages and pulses input to the scanning lines 2108 to 2111 of the i-th row and the first to fourth scanning lines 2128 to 2131 of the pixel Pixel(i) of the i-th row.
2. Note that periods T1 to T3 shown in Fig. 22 correspond to the operation of pixel Pixel(i) in the i-th row.

In the pixel configuration shown in FIG. 21, the storage capacitor 212 of the pixel Pixel(i) in the i-th row
The second electrode of the sixth row is connected to the second scanning line 210 of the pixel Pixel(i-1) in the (i-1)th row.
9 is applied to the second electrode of the storage capacitor 2126 of the pixel Pixel(i) in the i-th row.
In this way, a potential of L level is applied to the pixel Pixel (i
Since a constant potential can be applied to the second electrode of the storage capacitor 2126 of the pixel circuit 2122, the pixel circuit can operate as described in Embodiment Mode 1.

21, the same operation as above can be performed by using the fourth scanning line of the pixel in the previous row instead of the capacitance line of the pixel in question, because the timing of the pulses input to the second scanning line and the fourth scanning line of the pixel Pixel(i-1) in the (i-1)th row is the same.

The scanning line used in place of the capacitance line of the pixel is the second capacitance line of the pixel in the previous row.
Alternatively, the capacitance line of the pixel in question may be replaced by the first or third scanning line of the pixel in the previous row.
Any one of the fourth scan lines may be used.

In addition, in the pixel, it is desirable to apply a constant potential to the capacitance line during periods T2 and T3. It is also desirable to apply a low potential to the capacitance line during periods T2 and T3. In this way, the threshold voltage and video signal voltage of the first transistor can be obtained more accurately, and the current flowing through the light-emitting element during the light-emitting period of the pixel can be kept at a constant value, allowing the light-emitting element to emit light at a constant brightness. In view of the above, it is desirable to use the second or fourth capacitance line of the pixel in the previous row as a substitute for the capacitance line of the pixel.
It is preferable to use scan lines of 100 MHz or less.

As another example, FIG. 23 shows a case where the second scanning line of the pixel in the previous row is used instead of the capacitance line of the pixel in question in the pixel circuit shown in FIG.

23 shows the configuration of a pixel Pixel(i) in a certain row i and a pixel Pixel(i-1) in the previous row (i-1).
) is composed of first to fifth transistors 2301 to 2305, a storage capacitor 2306, first to fourth scanning lines 2308 to 2311, a light emitting element 2315, etc. Also, the pixel Pixel(i) in the i-th row is composed of first to fifth transistors 2321 to 2325, a storage capacitor 23
26, first to fourth scanning lines 2328 to 2331, and a light-emitting element 2335. In addition, the pixel Pixel(i) in the i-th row and the pixel Pixel(i-1) in the (i-1)-th row
A signal line 2307 and first and second power supply lines 2312 and 2313 are shared by these.

In Fig. 23, the connections of each element in each pixel are almost the same as those in the pixel circuit shown in Fig. 8, so detailed explanations will be omitted. The difference between Fig. 8 and Fig. 23 is that instead of the capacitance line of the pixel Pixel(i) in the i-th row, the second scanning line 2309 of the pixel Pixel(i-1) in the (i-1)-th row is used.
is used, and the second electrode of the storage capacitor 2326 of the pixel Pixel(i) in the i-th row is connected to the second scanning line 2309 of the pixel Pixel(i-1) in the (i-1)-th row.

In addition, in the pixel Pixel(i-1) in the (i-1)th row,
Instead of the capacitance line of l(i-1), the second scanning line 2349 of the pixel Pixel(i-2) in the (i-2)th row is used, and the storage capacitance 23 of the pixel Pixel(i-1) in the (i-1)th row is
The second electrode of pixel Pixel(i-2) in the (i-2)th row is connected to the second scanning line 234
9.

Here, the signal line 2307 and the first to fourth pixels Pixel(i-1) in the (i-1)th row
FIG. 2 is a timing chart of the video signal voltages and pulses input to the scanning lines 2308 to 2311 of the i-th row and the first to fourth scanning lines 2328 to 2331 of the pixel Pixel(i) of the i-th row.
24. Note that periods T1 to T3 shown in FIG. 24 correspond to the operation of pixel Pixel(i) in the i-th row.

In the pixel configuration shown in FIG. 23, the storage capacitor 232 of the pixel Pixel(i) in the i-th row
The second electrode of the sixth row is connected to the second scanning line 230 of the pixel Pixel(i-1) in the (i-1)th row.
9 is applied to the second electrode of the storage capacitor 2326 of the pixel Pixel(i) in the i-th row.
In this way, a high-level potential is applied to the pixel Pixel (i
Since a constant potential can be applied to the second electrode of the storage capacitor 2326 of the pixel circuit 2322, the pixel circuit can operate as described in Embodiment Mode 1.

23, the same operation as above can be performed by using the fourth scanning line of the pixel in the previous row instead of the capacitance line of the pixel in question, because the timing of the pulses input to the second scanning line and the fourth scanning line of the pixel Pixel(i-1) in the (i-1)th row is the same.

The scanning line used in place of the capacitance line of the pixel is the second capacitance line of the pixel in the previous row.
Alternatively, the capacitance line of the pixel in question may be replaced by the first or third scanning line of the pixel in the previous row.
Any one of the fourth scan lines may be used.

In addition, in the pixel, it is desirable to apply a constant potential to the capacitance line during periods T2 and T3. It is also desirable to apply a high potential to the capacitance line during periods T2 and T3. In this way, it is possible to more accurately obtain the threshold voltage and video signal voltage of the first transistor, and to maintain a constant current flowing through the light-emitting element during the light-emitting period of the pixel, thereby allowing the light-emitting element to emit light at a constant brightness. In view of the above, it is desirable to use the second or fourth capacitance line of the pixel in the previous row as a substitute for the capacitance line of the pixel.
It is preferable to use scan lines of 100 MHz or less.

In this way, by using the second scanning line of the pixel in the previous row as a substitute for the capacitance line of the pixel, it is no longer necessary to provide a new capacitance line in the pixel, so the number of wirings can be reduced and the aperture ratio of the pixel can be increased. In addition, it is no longer necessary to generate a new voltage to be applied to the capacitance line, so the circuit for this purpose can be reduced and power consumption can be reduced.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 3)
In the first and second embodiments, a current is passed through the light-emitting element when the element is initialized. However, the element can be initialized by adding an initialization transistor to the pixel circuit described above. In this embodiment, a method of performing initialization using an initialization transistor will be described. Note that an EL element will be described as an example of the light-emitting element.

In order to perform the initialization, it is necessary to set the second electrode of the first transistor to a certain initial potential. At this time, the second electrode of the first transistor and an electrode of another element or another wiring are connected via an initialization transistor, and the initialization transistor is turned on, so that the second electrode of the first transistor can be set to the potential of the electrode or wiring to which it is connected.

In other words, the initialization transistor functions as a switch that connects the second electrode of the first transistor to an electrode of another element or another wiring in order to set the potential of the second electrode of the first transistor to a certain initial potential.

For example, in the case of the pixel circuit shown in FIG. 3, in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 in the storage capacitor 306, the potential of the second electrode of the first transistor 301 is previously set to the video signal voltage V _data and the threshold voltage |V th | of the first transistor 301.
The threshold voltage |V _th | of the first transistor 301 must be lower than the difference V _data - |V _th | between the first transistor 301 and the threshold voltage |V th | of the second transistor 301.
By connecting the electrode of the first transistor 301 to an electrode of another element or another wiring through an initialization transistor, the potential of the second electrode of the first transistor 301 can be set to an initial voltage lower than V _data −|V _th |.

Here, an example in which an initialization transistor is provided in the pixel circuit shown in Fig. 3 is shown in Fig. 25. Fig. 25 shows an example in which a second electrode of a first transistor 301 and a capacitance line 314 are connected via an initialization transistor.

In FIG. 25, a sixth transistor 2516 which is an initialization transistor and a fifth scan line 2517 are newly added to the pixel circuit shown in FIG.
6 has a gate electrode connected to the fifth scanning line 2517, a first electrode connected to the second electrode of the first transistor 301, the first electrode of the fourth transistor 304, and the first electrode of the fifth transistor 305, and a second electrode connected to the capacitance line 314.

Next, the operation of the pixel circuit shown in Figure 25 will be explained using Figures 26 and 27.

FIG. 26 shows a timing chart of the video signal voltages and pulses input to the signal line 307 and the first to fifth scanning lines 308 to 311 and 2517, which are divided into three periods T1 to T3 in accordance with the operations of the pixel circuits.

The operation of the pixel circuit in the first period T1 will be described with reference to FIG. 27. In the period T1, the second, third, and fifth scanning lines 309, 310, and 2517 are at the L level, and the third, fourth
, the sixth transistors 303, 304, and 2516 are turned on. In addition, the first and fourth scanning lines 308 and 311 are set to H level, and the second and fifth transistors 302 and 305 are turned off. As a result, the second electrode of the first transistor 302 is connected to the capacitance line 314, so that the potentials of the second electrode of the first transistor 301, the first electrode of the first storage capacitor 306, and the first electrode of the storage capacitor 306 become equal to the potential _VCL of the capacitance line 314.

Through the above operation, in the period T1, the potentials of the second electrode of the first transistor 301 and the first electrode of the storage capacitor 306 are set to the potential _VCL of the capacitor line 314 as initial potentials.

In this manner, in the period T1, the potential of the second electrode of the first transistor 301 is set to V _data
By setting the potential V _CL of the capacitance line 314 to a potential lower than −|V _th |, the potential of the second electrode of the first transistor 301 can be reliably set lower than V _data −|V _th |, and the threshold voltage can be reliably compensated.

In the periods T2 and T3, the fifth scan line 2517 is set to H level, and the sixth transistor 2516 is turned off. Then, the same operation as that of the pixel circuit shown in FIG. 3 is performed. That is, in the period T2, the video signal voltage V _data is applied to the storage capacitor 306 and the sixth transistor 2516 is turned off.
Then, in a period T3, _a current I _OLED depending on the video signal voltage V _data is supplied to the light emitting element 315, and the light emitting element 315
to emit light.

Note that the sixth transistor 2516 has a second electrode connected to the first transistor 301 and a second _electrode connected to the
_ata -|V _th |. For example, in FIG.
As shown in FIG. 1, the first electrode of the sixth transistor 2516 is connected to the first transistor 301
a gate electrode of the fourth transistor 304, a second electrode of the fourth transistor 304, and a first electrode of the storage capacitor 306
The electrode may be connected to the

25, the second electrode of the sixth transistor 2516 is connected to the capacitance line 314, but the second electrode of the sixth transistor 2516 may be connected to an existing wiring other than the capacitance line. In particular, it is sufficient if the wiring is applied with a potential lower than V _data - |V _th | during the period T1.

29, the second electrode of the sixth transistor 2516 may be connected to the second scan line 309. In the period T1, an L-level potential is applied to the second scan line 309, and therefore the potential of the second electrode of the first transistor 301 is set to V _data −|V _th |
It is possible to set the potential lower than

Note that in the period T 1 , an L-level potential is also applied to the third scan line 310 ; therefore, the second electrode of the sixth transistor 2516 may be connected to the third scan line 310 .

In addition, in order to set the second electrode of the first transistor 301 to a certain initial potential, an initialization line (initialization power supply line) may be newly provided.

For example, Fig. 30 shows an example in which an initialization transistor and an initialization line are provided in the pixel circuit shown in Fig. 3. In Fig. 30, a sixth transistor 2516 which is an initialization transistor, a fifth scan line 2517, and an initialization line 3018 are newly added to the pixel circuit shown in Fig. 3.
Note that the sixth transistor 2516 has a gate electrode connected to the fifth scan line 2517 and a first electrode connected to the second electrode of the first transistor 301 and the fourth transistor 30
A first electrode of a transistor 304 and a first electrode of a fifth transistor 305 are connected to the first electrode of the fifth transistor 305 , and a second electrode of the fifth transistor 304 is connected to an initialization line 3018 .

An initialization potential V _ini is applied to the initialization line 3018. The magnitude relationship of the potentials is V _ini <V _data -|V _th |.

31 shows the operation of the pixel circuit shown in FIG. 30 in the first period T1. In the period T1, the first transistor 301 is in a diode-connected state, and a current flows through the initialization line 3018. As a result, the potentials of the second electrode of the first transistor 301 and the first electrode of the storage capacitor 306 become equal to the potential of the initialization line 3018, and the initialization potential V _in
The difference between _i and the potential V _CL of the capacitance line 314 (V _ini −V _CL ) is held.

By the above operation, in the period T1, the storage capacitor 306 is supplied with an initial voltage by the initialization line 3018.
The difference V _ini −V _CL between the potential V _ini of the capacitor line 312 and the potential V _CL of the capacitor line 314 is held.

In this way, by providing the initialization line 3018 and setting the potential of the second electrode of the first transistor 301 to the initialization potential V _ini , which is a potential lower than V _data - |V _th |, the potential of the second electrode of the first transistor 301 can be reliably made lower than V _data - |V _th |, and the threshold voltage can be reliably compensated.

In particular, by providing a new initialization line, the initialization potential V _ini is set to V _data −|V _th
Therefore, the potential of the second transistor 301 can be set to any potential lower than |
Therefore, the potential of the electrode can be made lower than V _data - |V _th | more reliably, and the threshold voltage can be compensated more reliably.

Note that the sixth transistor 2516 may be connected so that the second electrode of the first transistor 301 is set to the initialization potential V _ini . For example, as shown in FIG.
A first electrode of the second transistor 2516 may be connected to a gate electrode of the first transistor 301 , a second electrode of the fourth transistor 304 , and a first electrode of the storage capacitor 306 .

In this way, by performing initialization by adding a new initialization transistor and initialization line, it becomes possible to more reliably obtain and compensate the threshold voltage of the first transistor.

In addition, in the initialization method described in embodiment 1, a current flows through the light-emitting element during initialization, causing the light-emitting element to emit light during period T1. However, in the method shown in this embodiment, no current flows through the light-emitting element during initialization, causing the light-emitting element to not emit light during period T1, and light emission by the light-emitting element outside the light-emitting period can be suppressed.

In this embodiment, the sixth transistor, which is an initialization transistor, is a P-channel type, but is not limited to this, and may be an N-channel type.

In this embodiment, the sixth transistor is controlled using the fifth scanning line, but other existing wiring of the pixel in another row may be used instead of the fifth scanning line. In particular, it is preferable to use a wiring to which a voltage is applied so that the sixth transistor is turned on during the initialization period T1. For example, when the sixth transistor is a P-channel type, the fifth transistor of the pixel is
Instead of the scan line of the pixel in the previous row, the first scan line of the pixel in the previous row may be used. Also, if the sixth transistor is an N-channel type, the second scan line of the pixel in the previous row may be used instead of the fifth scan line of the pixel in question. By using an existing wiring instead of the fifth scan line in this way, it is not necessary to newly provide a fifth scan line in the pixel in question, so that the number of wirings can be reduced and the aperture ratio of the pixel can be increased.

In this embodiment, only the example in which the first transistor is a P-channel type (FIG. 3) has been described, but the contents of this embodiment can be similarly applied to the case in which the first transistor is an N-channel type, such as in the pixel circuit shown in FIG.

In addition, when an initialization transistor is added to the pixel circuit shown in FIG. 8, the potential of the second electrode of the first transistor 801 is set to the video signal voltage V _data and the potential of the first transistor 801 is set to the
The potential V _ini applied to the initialization line is set to a potential higher than the sum V _data + |V _{th |} of the threshold voltage |V _th | of the initialization line.
_ta +|V _th | is set to a potential higher than that.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 4)
In the first to third embodiments, the potential of the second power supply line is a fixed potential.
The potential of the second power supply line may be changed depending on the fourth period.
A case will be described in which the potential of the second power supply line is changed depending on the period of time. Note that an EL element will be taken as an example of the light emitting element.

For example, in the pixel circuit shown in FIG. 3, in the second period T2, the fifth transistor 30
However, for example, by deleting the fifth transistor 305 and directly connecting the second electrode of the first transistor 301 and the first electrode of the light-emitting element 315, and setting the potential of the second power supply line 313 higher than the potential of the first electrode of the light-emitting element 315 in the second period T2, it is possible to prevent a current from flowing through the light-emitting element 315.
This is because by making the potential of the first electrode higher than that of the second electrode, a reverse bias is applied to the light emitting element 315. Examples of this case are shown in FIGS.

33, the second electrode of the first transistor 301 is directly connected to the first electrode of the light emitting element 316 in the pixel circuit shown in FIG. 3. Also, FIG. 34 shows a timing chart of video signal voltages and pulses input to the signal line 307, the first to third scanning lines 308 to 310, and the second power supply line 313. Note that the first to third scanning lines 308 to 310
The timing of the pulses input to the pixel circuit is the same as that of the pixel circuit shown in FIG.

In the second period T2, the potential of the second power supply line 313 is set to be equal to or greater than the difference V _data - |V _th | between the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301. This allows a reverse bias to be applied to the light-emitting element 315.
In 2, it is possible to prevent current from flowing to the light emitting element 315.

In _{the first and third periods T1 and T3, the potential of the second power supply line 313 is set to a value equal to the difference V data − |} V
By making the potential lower than _th |, a forward bias can be applied to the light-emitting element 315. This allows a current to flow through the light-emitting element 315 in the periods T1 and T3.

As a method of initialization, the method of performing initialization using an initialization transistor described in the embodiment mode 3 may be used. An example of this case is shown in FIG.

35, in the diagram (FIG. 25) showing an example of the case where initialization is performed using an initialization transistor, the fifth transistor 305 and the fourth scan line 311 are removed, and the second electrode of the first transistor 301 and the first electrode of the light-emitting element 315 are connected. In this case, by setting the potential of the second power supply line 313 higher than the potential of the second electrode of the first transistor 301 in the period T1, it is possible to perform initialization without flowing a current to the light-emitting element 315.

Alternatively, the initialization method may be the method described in the third embodiment, in which initialization is performed using an initialization transistor and an initialization line. An example of this case is shown in FIG.

In the pixel circuit shown in FIG. 36, the fifth transistor 305 and the fourth scanning line 31 in the diagram (FIG. 30) showing an example in which initialization is performed using an initialization transistor and an initialization line are
1 is removed, and the second electrode of the first transistor 301 and the first electrode of the light-emitting element 315 are connected. In this case, in the period T1, the potential of the second power supply line 313 is set to the initialization potential V _in
By making it _i or more, it becomes possible to perform initialization without flowing a current to the light emitting element 315 .

In this embodiment, only the example in which the first transistor is a P-channel type (FIG. 3) has been described, but the contents of this embodiment can be similarly applied to the case in which the first transistor is an N-channel type, such as in the pixel circuit shown in FIG.

In the pixel circuit shown in FIG. 8, when the potential of the second power supply line 813 is changed depending on the period,
In the period T2, the potential of the second power supply line 813 is made lower than the potential of the second electrode of the light-emitting element 815, so that a reverse bias can be applied to the light-emitting element 815. This can prevent current from flowing to the light-emitting element 815 in the period T2.

Note that in the period T2, the above operation can be performed by setting the potential of the second power supply line 813 to a value equal to or lower than the sum V _data +|V _th | of the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801.

In _{the first and third periods T1 and T3, the potential of the second power supply line 813 is set to the sum V data + |} V
By making the voltage higher than _th |, a forward bias can be applied to the light emitting element 815. This allows a current to flow through the light emitting element 815 in the periods T1 and T3.

As a method of initialization, the method of performing initialization using an initialization transistor described in Embodiment 3 may be used. In this case, in the period T1, the potential of the second power supply line 813 is set lower than the potential of the second electrode of the first transistor 801, thereby
This makes it possible to perform initialization without passing a current through the memory cell.

Alternatively, as a method of initialization, the method of performing initialization using an initialization transistor and an initialization line described in the embodiment mode 3 may be used. In this case, in the period T1,
By setting the potential of the pixel 814 to the initialization potential V _ini or lower, it is possible to perform initialization without flowing a current to the light emitting element 815 .

In this way, by changing the potential of the second power line depending on the period, the light emission period (T3
Since the current is not passed through the light-emitting element during the period other than the light-emitting period, the light emission of the light-emitting element during the period other than the light-emitting period can be suppressed. In addition, since it is not necessary to provide the fifth transistor and the fourth scan line, the aperture ratio of the pixel can be increased. In addition, the number of scan line driver circuits can be reduced, so that power consumption can be reduced.

In addition, by changing the potential of the second power line depending on the period, a reverse bias can be applied to the light emitting element. In particular, when the light emitting element is an EL element, applying a reverse bias can improve the deterioration state of the EL element, improve its reliability, and extend its lifespan.

The pixel configuration of the present invention may be applied to a pixel configuration in which an area gradation method is performed. That is, in a pixel configuration in which one pixel is divided into a plurality of sub-pixels, the pixel configuration of the present invention may be applied to each of the sub-pixels. This makes it possible to reduce the variation in luminance for each sub-pixel, and to display a high-quality image with multiple gradations.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 5)
In this embodiment, the layout of pixels in the display device of the present invention will be described. For example,
Fig. 37 shows a layout diagram of the pixel circuit shown in Fig. 3. Note that the numbers given in Fig. 37 are the same as those given in Fig. 3. Note that the layout diagram is not limited to Fig. 37.

The pixel circuit shown in FIG. 3 includes first to fifth transistors 301 to 305, a storage capacitor 306,
A signal line 307, first to fourth scanning lines 308 to 311, first and second power supply lines 312, 31
3, a capacitance line 314, and a light emitting element 315.

The first to fourth scanning lines 308 to 311 are formed by the first wiring, and the signal line 307 and the first
The second power supply lines 312 and 313 and the capacitance line 314 are formed of the second wiring.

In the case of a top gate structure, the films are configured in the order of the substrate, the semiconductor layer, the gate insulating film, the first wiring, the interlayer insulating film, and the second wiring, whereas in the case of a bottom gate structure, the films are configured in the order of the substrate, the first wiring, the gate insulating film, the semiconductor layer, the interlayer insulating film, and the second wiring.

In the pixel configuration of this embodiment, among the values of the ratio W/L of the channel length L to the channel width W of each of the first to fifth transistors, when the value of W/L of the first transistor is maximized, the current flowing between the drain and source of the first transistor can be increased. As a result, when a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor is acquired in the period T2, a larger current can be used for operation, so that a faster operation can be performed. In addition, the current I _OLED flowing to the light-emitting element in the period T3 can be increased, and the luminance can be increased. Therefore, in order to maximize the value of W/L of the first transistor, in FIG. 37, the channel width W of the first transistor 301 is maximized among the first to fifth transistors.

In this embodiment, the first to fifth transistors 301 to 305 are described as having a single gate structure, but the present invention is not limited thereto. The structures of the first to fifth transistors 301 to 305 can take various forms. For example, a multi-gate structure having two or more gate electrodes may be used. With a multi-gate structure, the channel regions are connected in series, resulting in a configuration in which a plurality of transistors are connected in series. By using a multi-gate structure, the off-current can be reduced, the withstand voltage of the transistor is improved to improve reliability, and even if the drain-source voltage changes when operating in the saturation region, the drain-source current does not change much, resulting in flat characteristics. In addition, a structure in which gate electrodes are arranged above and below the channel may be used. By using a structure in which gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased, and a depletion layer can be easily formed, resulting in a smaller S coefficient (subthreshold coefficient). When gate electrodes are arranged above and below the channel, a configuration in which a plurality of transistors are connected in parallel is obtained. Also, the gate electrode may be disposed above the channel, or may be disposed below the channel, or may be in a positive staggered structure or an inverse staggered structure, or the channel region may be divided into a plurality of regions, or may be connected in parallel or in series. Also, the source electrode or drain electrode may overlap the channel (or a part thereof). By adopting a structure in which the source electrode or drain electrode overlaps the channel (or a part thereof), it is possible to prevent charges from accumulating in a part of the channel, causing the operation to become unstable. Also, L
By providing the LDD region, the off-current can be reduced, the withstand voltage of the transistor can be improved to improve reliability, and the drain-gate can be reduced when the transistor operates in the saturation region.
Even if the source voltage changes, the drain-source current does not change significantly, making it possible to achieve flat characteristics.

The wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. are made of aluminum (Al).
, tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (
Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P
), boron (B), arsenic (As), gallium (Ga), indium (In), tin (
Sn), or oxygen (O), or a compound or alloy material containing one or more elements selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (
It is preferable that the wiring, electrodes, conductive layers, conductive films, terminals, etc. are formed of a material that is a combination of these compounds. It is preferable that the wiring, electrodes, conductive layers, conductive films, terminals, etc. are formed of a compound (silicide) of one or more elements selected from the above group and silicon (e.g., aluminum silicon, molybdenum silicon, nickel silicide, etc.), or a compound of one or more elements selected from the above group and nitrogen (e.g., titanium nitride, tantalum nitride, molybdenum nitride, etc.).

Silicon (Si) can contain n-type impurities (such as phosphorus) or p-type impurities (such as boron).
When silicon contains impurities, its electrical conductivity improves and it can behave like a normal conductor, making it easier to use as wiring, electrodes, etc.

Silicon having various crystallinity such as single crystal, polycrystalline (polysilicon), microcrystalline (microcrystal silicon), etc. can be used. Alternatively, silicon having no crystallinity such as amorphous silicon can be used. By using single crystal silicon or polycrystalline silicon, the resistance of wiring, electrodes, conductive layers, conductive films, terminals, etc. can be reduced. By using amorphous silicon or microcrystalline silicon, wiring, etc. can be formed in a simple process.

Incidentally, aluminum or silver has high electrical conductivity, and therefore can reduce signal delay.
Furthermore, since it is easy to etch, it is easy to pattern and can be subjected to fine processing.

In addition, copper has high conductivity, so it can reduce signal delay. When using copper,
In order to improve adhesion, a laminated structure is preferable.

Molybdenum or titanium is preferable because it has advantages such as not causing defects even when in contact with an oxide semiconductor (ITO, IZO, etc.) or silicon, being easy to etch, and having high heat resistance.

Tungsten is preferable because it has advantages such as high heat resistance.

Neodymium is desirable because it has the advantage of being highly heat resistant. In particular, when neodymium is alloyed with aluminum, the heat resistance is improved and aluminum is less likely to develop hillocks.

Silicon is preferable because it has advantages such as being able to be formed simultaneously with a semiconductor layer of a transistor and having high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
Since cadmium tin oxide (CTO) and cadmium tin oxide (CTO) are transparent, they can be used in light transmitting portions, for example, as pixel electrodes and common electrodes.

IZO is preferable because it is easy to etch and process. When IZO is etched, it is unlikely that residues will remain. Therefore, when IZO is used as a pixel electrode, it is possible to reduce problems (such as short circuits and alignment disorders) in liquid crystal elements and light-emitting elements.

In addition, wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. may have a single-layer structure.
It may have a multi-layer structure. By making it a single-layer structure, the manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, etc. can be simplified, the number of process days can be reduced, and costs can be reduced. Alternatively, by making it a multi-layer structure, it is possible to form wiring, electrodes, etc. with good performance by taking advantage of the advantages of each material while reducing its disadvantages.
For example, by including a low-resistance material (such as aluminum) in the multi-layer structure, it is possible to reduce the resistance of the wiring. Also, by sandwiching a low-heat-resistant material between high-heat-resistant materials in a multi-layer structure, it is possible to improve the heat resistance of wiring, electrodes, etc. while taking advantage of the advantages of the low-heat-resistant material. For example, it is desirable to have a multi-layer structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, etc.

In addition, when wiring, electrodes, etc. are in direct contact with each other, they may have a detrimental effect on each other. For example, one wiring, electrode, etc. may penetrate into the material of the other wiring, electrode, etc., changing the properties and making it impossible to fulfill the original purpose. As another example, when forming or manufacturing a high resistance part, a problem may occur and it may become impossible to manufacture normally. In such a case, it is advisable to sandwich or cover a material that is easily reactive due to the laminated structure with a material that is less likely to react. For example, when connecting ITO and aluminum, it is desirable to sandwich titanium, molybdenum, or neodymium alloy between ITO and aluminum. Also, when connecting silicon and aluminum, it is desirable to sandwich titanium, molybdenum,
It is preferable to sandwich a neodymium alloy.

The term "wiring" refers to an arrangement of conductors. The wiring may extend linearly or may be arranged short and not extend. Therefore, electrodes are included in the wiring.

Carbon nanotubes may be used as wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. Furthermore, carbon nanotubes have translucency and can be used in light transmitting portions, for example, as pixel electrodes and common electrodes.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 6)
In this embodiment, the configurations and operations of a signal line driving circuit, a scanning line driving circuit, and the like in a display device will be described.

First, a case where a pixel configuration in which operation is controlled using signal lines and first to fourth scanning lines as shown in Fig. 3 or Fig. 8 is used will be described. Here, a case where the pixel configuration shown in Fig. 3 is used will be described as an example. An example of the configuration of a display device in this case is shown in Fig. 38.

The display device shown in FIG. 38 includes a pixel portion 3801, first to fourth scanning line driver circuits 3802 to 3803, and a pixel portion 3804.
The pixel circuit has a first scanning line driver circuit 3802 and a first scanning line 308, a second scanning line driver circuit 3803 and a second scanning line 309, a third scanning line driver circuit 3804 and a third scanning line 310, a fourth scanning line driver circuit 3805 and a fourth scanning line 311, and a signal line driver circuit 3806 and a signal line 307. The reference characters attached to the first to fourth scanning lines and the signal lines are the same as those in FIG.
These correspond to the symbols attached to the

First, the scanning line driver circuit will be described. The first scanning line driver circuit 3802 is a circuit for sequentially outputting selection signals to the first scanning line 308. The second to fourth scanning line driver circuits 3
The same applies to 803 to 3805. As a result, a selection signal is written to the pixel portion 3801.

Here, a configuration example of the first to fourth scanning line driver circuits 3802 to 3805 is shown in FIG.
Each of the fourth to fourth scanning line driver circuits 3802 to 3805 mainly includes a shift register 3901, an amplifier circuit 3902, and the like.

Next, the operation of the first to fourth scanning line driving circuits 3802 to 3805 shown in FIG. 39 will be briefly described. A shift register 3901 receives a clock signal (G-CLK), a start pulse (
A clock inversion signal (G-SP) and a clock inversion signal (G-CLKB) are input, and sampling pulses are output in sequence according to the timing of these signals. The output sampling pulses are amplified by an amplifier circuit 3902 and input to the pixel section (X54)01 from each scanning line.

The amplifier circuit 3902 may include a buffer circuit or a level shifter circuit.
In addition to 02, a pulse width control circuit and the like may be provided.

Next, a signal line driver circuit 3806 will be described. The signal line driver circuit 3806 is a circuit for sequentially outputting video signals to a signal line 307 connected to a pixel portion.
The video signal output from the pixel portion 3801 is input to the pixel portion 3801. In the pixel portion 3801, an image is displayed by controlling the light emission state of the pixel in accordance with the video signal.

Here, a configuration example of the signal line driver circuit 3806 is shown in Fig. 40. Fig. 40A shows an example of the signal line driver circuit 3806 in the case where signals are supplied to pixels by line sequential driving. In this case, the signal line driver circuit 3806 mainly includes a shift register 4001, a first latch circuit 4002, and a second latch circuit 4003.
, a second latch circuit 4003, an amplifier circuit 4004, etc.
The configuration of 04 may include a buffer circuit, a level shifter circuit, a circuit having a function of converting a digital signal into analog, or a circuit having a function of performing gamma correction.

Next, the operation of the signal line driver circuit 3806 shown in Fig. 40A will be briefly described. A clock signal (S-CLK), a start pulse (S-SP), and a clock inversion signal (S-CLKB) are input to a shift register 4001, and sampling pulses are output in sequence according to the timing of these signals.

The sampling pulse output from the shift register 4001 is input to the first latch circuit 400
A video signal is input to the first latch circuit 4002 at a voltage _Vdata from a video signal line, and the video signal is held in each column according to the timing at which the sampling pulse is input.

When the first latch circuit 4002 has completed holding the video signals up to the last column, a latch signal is input from a latch control line during a horizontal retrace period, and the video signals held in the first latch circuit 4002 are simultaneously transferred to the second latch circuit (X56) 03. After that, the video signals held in the second latch circuit 4003 are simultaneously transferred to the amplifier circuit 400 for one row.
The video signal voltage V data is input to the amplifier circuit 4004. The amplitude of the video signal voltage V _data is amplified in the amplifier circuit 4004, and the video signal is input to the pixel portion 3801 from each signal line.

The video signal held in the second latch circuit 4003 is input to the amplifier circuit 4004, and while being input to the pixel portion 3801, a sampling pulse is output again from the shift register 4001. That is, two operations are performed at the same time. This enables line-sequential driving. Thereafter, this operation is repeated.

In addition, there are cases where signals are supplied to pixels by dot sequential driving. In that case, the signal line driving circuit 380
An example of the signal line driver circuit 3806 in this case includes a shift register 4001 and a sampling circuit 4005.
The sampling pulse is output to the sampling circuit 4005. A video signal is input to the sampling circuit 4005 from a video signal line at a voltage _Vdata , and the video signal is output to the pixel portion 3801 in sequence in response to the sampling pulse. This enables dot sequential driving.

It is to be noted that the signal line driver circuit or a part thereof (such as a current source circuit or an amplifier circuit) may not be present on the same substrate as the pixel portion 3801 and may be formed using, for example, an external IC chip.

By using the above-described scanning line driver circuit and signal line driver circuit, the pixel circuit of the present invention can be driven.

In the pixel circuits shown in Fig. 3 and Fig. 8, for example, mutually inverted selection signals are input to the first and second scanning lines. Therefore, using either the first or second scanning line driver circuit, a selection signal input to either the first or second scanning line may be controlled, and an inverted signal may be input to the other scanning line. An example of the configuration of a display device in this case is shown in Fig. 41.
As shown in.

The display device shown in FIG. 41 includes a pixel portion 3801, first, third and fourth scanning line driver circuits 380,
2, 3804, 3805, a signal line driver circuit 3806, and an inverter 3807.
The first scanning line driver circuit 3802 and the first scanning line 308 are connected, and the second scanning line 309
is connected to a first scanning line driver circuit 3802 via an inverter 3807. The other connections of the scanning line driver circuit and the signal line driver circuit are the same as those in the display device shown in Fig. 38, and therefore the description thereof will be omitted here. Note that the reference numerals given to the first to fourth scanning lines and the signal line correspond to those given in Fig. 3.

In the display device shown in FIG. 41, the first scanning line 30 is driven by a first scanning line driving circuit 3802.
The selection signal input to the first scanning line 308 is controlled by the inverter 3807 , and an inverted signal of the selection signal input to the first scanning line 308 , which is generated by the inverter 3807 , is input to the second scanning line 309 .

Also, for example, in the pixel configurations shown in Figures 3 and 8, the same selection signal is input to the second and fourth scanning lines. Therefore, as in the pixel configurations shown in Figures 14 and 15, the third and fifth transistors may be controlled using the same scanning line. An example of the configuration of a display device in this case is shown in Figure 42. Note that the pixel configuration shown in Figure 14 will be described as an example.

42 shows a configuration example of a display device in which the third and fifth transistors 303 and 305 are controlled using a second scanning line 309. The display device shown in FIG.
The display device has first to third scanning line driver circuits 3802 to 3804 and a signal line driver circuit 3806. The connections of the driver circuits are similar to those of the display device shown in Fig. 38, and therefore will not be described here. Note that the reference characters attached to the first to third scanning lines, the signal line, and the third and fifth transistors correspond to those in Fig. 14.

In addition, for example, as in the pixel configuration shown in FIG. 20, the second transistor is made to have a different conductivity type from the transistors other than the second transistor.
The first transistor, the third transistor, and the fifth transistor can be controlled by the same scan line. An example of the configuration of a display device in this case is shown in FIG.

FIG. 43 shows the second, third and fifth transistors 302, 303 and 305 connected to the first scanning line 3.
43 is a configuration example of a display device controlled by the pixel portion 3801, first and third scanning line driver circuits 3802 and 3804, a signal line driver circuit 380, and a display device shown in FIG.
6. The connection of each driving circuit is the same as that of the display device shown in Fig. 38, and therefore the description will be omitted here. Note that the reference characters attached to the first and third scanning lines, the signal lines, and the second, third, and fifth transistors correspond to the reference characters attached to Fig. 20.

In this manner, by configuring the display device as shown in FIGS. 41 to 43, the pixel circuit of the present invention can be driven.

41 to 43, the number of scanning lines and scanning line driver circuits can be reduced, and therefore the aperture ratio of the pixel portion can be increased. Also, power consumption can be reduced. Furthermore, by reducing the number of scanning line driver circuits, the frame can be narrowed and the area occupied by the pixel portion can be increased.

Note that the configurations of the signal line driving circuit, scanning line driving circuit, etc. are not limited to those shown in Figures 38 to 43.

The transistors in the present invention may be of any type and may be formed on any substrate. Therefore, the circuits as shown in Figs. 38 to 43 may all be formed on a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, or any other substrate. Alternatively, a part of the circuits in Figs. 38 to 43 may be formed on a certain substrate, and another part of the circuits in Figs. 38 to 43 may be formed on another substrate. In other words, all of the circuits in Figs. 38 to 43 do not have to be formed on the same substrate. For example, in Figs. 38 to 43, the pixel portion and the scanning line driver circuit are formed on a glass substrate using transistors, and the signal line driver circuit (or a part thereof) is formed on a single crystal substrate, and the IC chip is formed by COG (Chip On Glass).
Alternatively, the IC chip may be connected by TAB (Ta
The glass substrate may be connected using a printed circuit board or a PE Automated Bonding (PCB). In this way, by forming a part of the circuit on the same substrate, the number of components can be reduced to reduce costs, and the number of connections with the circuit components can be reduced to improve reliability. In addition, since a part with a high driving voltage or a part with a high driving frequency consumes a lot of power, if such a part is not formed on the same substrate, the increase in power consumption can be prevented.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Seventh embodiment)
In this embodiment, a display panel used in a display device of the present invention will be described with reference to FIG. 44 and the like. Note that FIG. 44(a) is a top view showing the display panel, and FIG. 44(b) is a cross-sectional view taken along line AA' in FIG. 44(a). A signal line driver circuit 4401 and a pixel portion 44
02, a first scanning line driver circuit 4403, and a second scanning line driver circuit 4406.
A sealing substrate 4404 and a sealant 4405 are provided, and the inside surrounded by the sealant 4405 forms a space 4407 .

The wiring 4408 is a wiring for transmitting signals input to the first scanning line driver circuit 4403, the second scanning line driver circuit 4406, and the signal line driver circuit 4401, and receives a video signal, a clock signal, a start signal, and the like from an FPC 4409 serving as an external input terminal.
On the joint between C4409 and the display panel, IC chips (semiconductor chips with memory circuits, buffer circuits, etc.) 4422 and 4423 are mounted on the COG (Chip On Glass)
) or the like. Although only an FPC is shown here, a printed wiring board (PWB) may be attached to this FPC.

Next, a cross-sectional structure will be described with reference to FIG.
02 and its peripheral driving circuits (first scanning line driving circuit 4403, second scanning line driving circuit 440
6 and a signal line driver circuit 4401) are formed.
1 and a pixel portion 4402 are shown.

Note that the signal line driver circuit 4401 is composed of a large number of transistors such as a transistor 4420 and a transistor 4421. Although this embodiment shows a display panel in which a peripheral driver circuit is integrally formed on a substrate, this is not necessarily required, and all or a part of the peripheral driver circuit may be formed on an IC chip or the like and mounted by COG or the like.

The pixel portion 4402 has a plurality of circuits that constitute a pixel, each of which includes a switching transistor 4411 and a driving transistor 4412.
The source electrode 412 is connected to the first electrode 4413.
An insulator 4414 is formed to cover the end portion of the semiconductor device 441. Here, the insulator 4414 is formed by using a positive type photosensitive acrylic resin film.

In order to improve coverage, a curved surface having a curvature is formed at the upper end or lower end of the insulator 4414. For example, when a positive photosensitive acrylic is used as the material of the insulator 4414, a curvature radius (0.2 μm to 3 μm) is formed only at the upper end of the insulator 4414.
It is preferable that the insulator 4414 has a curved surface having a shape having a curvature of 0.1 mm. In addition, the insulator 4414 can be either a negative type that is photosensitive and becomes insoluble in an etchant when exposed to light, or a positive type that is photosensitive and becomes soluble in an etchant when exposed to light.

A layer 4416 containing an organic compound and a second electrode 4417 are formed on the first electrode 4413. Here, it is desirable to use a material with a large work function as a material used for the first electrode 4413 functioning as an anode. For example, in addition to a single layer film such as an ITO (indium tin oxide) film, an indium zinc oxide (IZO) film, a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a laminated film of a film mainly composed of titanium nitride and aluminum, or a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film can be used. Note that a laminated structure provides low resistance as a wiring, good ohmic contact, and the electrode can function as an anode.

The layer 4416 containing an organic compound is formed by a deposition method using a deposition mask or an inkjet method. The layer 4416 containing an organic compound is formed by using a metal complex of Group 4 of the periodic table as a part thereof, and other materials that can be used in combination with the layer 4416 may be low molecular weight materials or high molecular weight materials. Although the material used for the layer containing an organic compound is usually a single layer or a laminated layer of an organic compound in many cases, this embodiment also includes a structure in which an inorganic compound is used as a part of a film made of an organic compound.
Furthermore, known triplet materials can also be used.

Furthermore, a material having a small work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used as a material for the second electrode 4417, which is a cathode formed on the layer 4416 containing an organic compound. When light generated in the layer 4416 containing an organic compound is transmitted through the second electrode 4417, the second electrode 4417 may be a stack of a thin metal thin film and a transparent conductive film (ITO (indium tin oxide)), an indium oxide zinc oxide alloy (In ₂ O ₃ -ZnO), zinc oxide (ZnO), or the like).

Furthermore, the sealing substrate 4404 is attached to the substrate 4410 with a sealant 4405, so that a light-emitting element 4418 is provided in a space 4407 surrounded by the substrate 4410, the sealing substrate 4404, and the sealant 4405. Note that the space 4407 is filled with an inert gas (
In addition to the case where the cavity is filled with a gas such as nitrogen or argon, a configuration where the cavity is filled with a sealant 4405 is also included.

It is preferable to use an epoxy resin for the sealing material 4405. In addition, it is preferable that these materials are materials that do not transmit moisture or oxygen as much as possible.
Materials used for 4 include glass substrates, quartz substrates, and FRP (Fiberglass-Resin)
Inforced Plastics), PVF (Polyvinyl Fluoride), Mylar,
A plastic substrate made of polyester, acrylic or the like can be used.

In this manner, a display panel having the pixel configuration of the present invention can be obtained.

As shown in FIG. 44, the signal line driver circuit 4401, the pixel portion 4402, the first scanning line driver circuit 4403, and the second scanning line driver circuit 4406 are integrally formed, whereby the cost of the display device can be reduced.
By making the transistors used in the signal line driver circuit 403 and the second scanning line driver circuit 4406 have the same conductivity type, the manufacturing process can be simplified, and therefore the cost can be further reduced.
401, a pixel portion 4402, a first scanning line driver circuit 4403, and a second scanning line driver circuit 44
Further cost reduction can be achieved by using amorphous silicon for the semiconductor layers of the transistors used in 06.

The display panel is configured as follows:
The present invention is not limited to a configuration in which the pixel portion 4402, the first scanning line driver circuit 4403, and the second scanning line driver circuit 4406 are integrally formed, and a signal line driver circuit corresponding to the signal line driver circuit 4401 may be formed as an I
It may also be configured such that it is formed on a C chip and mounted on the display panel by COG or the like.

In other words, only the signal line driver circuit, which requires high speed operation, is implemented using CMOS or the like.
In addition, by forming the IC chip on a semiconductor chip such as a silicon wafer, it is possible to achieve higher speed operation and lower power consumption.

Furthermore, by forming the scanning line driver circuit integrally with the pixel portion, costs can be reduced. Note that by configuring the scanning line driver circuit and the pixel portion using transistors of the same conductivity type, costs can be further reduced. The structures shown in any of the embodiments 1 to 4 can be applied to the pixel structure of the pixel portion. In addition, by using amorphous silicon for the semiconductor layer of the transistor, the manufacturing process can be simplified, and costs can be further reduced.

In this way, the cost of a high-definition display device can be reduced.
By mounting an IC chip on which a functional circuit (memory or buffer) is formed at the connection portion with the MOSFET, the board area can be used effectively.

In addition, the signal line driver circuit 4401, the first scanning line driver circuit 4403 and the second scanning line driver circuit 4404 in FIG.
A signal line driver circuit, a first scanning line driver circuit, and a second scanning line driver circuit, which correspond to the scanning line driver circuit 4406 in the above embodiment, may be formed on an IC chip and mounted on a display panel by COG or the like. In this case, it is possible to reduce the power consumption of a high-definition display device. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use polysilicon for the semiconductor layer of a transistor used in a pixel portion.

In addition, costs can be reduced by using amorphous silicon for a semiconductor layer of a transistor in the pixel portion 4402. Furthermore, a large-sized display panel can also be manufactured.

Note that the scanning line driver circuit and the signal line driver circuit are not limited to being provided in the row and column directions of the pixels.

Next, an example of a light-emitting element that can be applied to the light-emitting element 4418 is shown in Figure 45.

The device structure is formed by laminating an anode 4502, a hole injection layer 4503 made of a hole injection material, a hole transport layer 4504 made of a hole transport material, a light emitting layer 4505, an electron transport layer 4506 made of an electron transport material, an electron injection layer 4507 made of an electron injection material, and a cathode 4508 on a substrate 4501. The light emitting layer 4505 may be formed of only one type of light emitting material, or may be formed of two or more types of materials. The device structure of the present invention is as follows:
The invention is not limited to this structure.

In addition to the laminated structure in which each functional layer is laminated as shown in Fig. 45, there are a wide variety of variations, such as elements using polymer compounds, highly efficient elements using triplet light-emitting materials that emit light from triplet excited states in the light-emitting layer, etc. It can also be applied to white light-emitting elements obtained by controlling the carrier recombination region with a hole blocking layer and dividing the light-emitting region into two regions.

Next, a method for fabricating an element according to the present invention shown in FIG. 45 will be described. First, an anode 4502 (IT
A hole injection material, a hole transport material, and a light emitting material are evaporated in this order onto a substrate 4501 having indium tin oxide (O). Next, an electron transport material and an electron injection material are evaporated, and finally a cathode 4508 is formed by evaporation.

Next, materials suitable for the hole injection material, hole transport material, electron transport material, electron injection material, and light emitting material will be listed below.

As hole injection materials, organic compounds such as porphyrin compounds and phthalocyanine (
Effective examples of the hole injection material include copper phthalocyanine (hereinafter referred to as "H ₂ Pc") and copper phthalocyanine (hereinafter referred to as "CuPc"). In addition, any material that has a smaller ionization potential value than the hole transport material used and has a hole transport function can also be used as the hole injection material. There are also materials in which conductive polymer compounds have been chemically doped, such as polyethylenedioxythiophene (hereinafter referred to as "PEDOT") doped with polystyrene sulfonate (hereinafter referred to as "PSS") and
Examples of suitable anode materials include polyaniline. Insulating polymer compounds are also effective in flattening the anode, and polyimide (hereinafter referred to as "PI") is often used. Inorganic compounds are also used, such as thin metal films of gold and platinum, as well as ultra-thin films of aluminum oxide (hereinafter referred to as "alumina").

The most widely used hole transport materials are aromatic amine compounds (i.e., those having a benzene ring-nitrogen bond).
Examples of the aromatic amine compounds include starburst aromatic amine compounds such as 4,4'-bis(diphenylamino)-biphenyl (hereinafter referred to as "TAD") and its derivatives, 4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "TPD") and 4,4'-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (hereinafter referred to as "α-NPD"). Examples of the aromatic amine compounds include starburst aromatic amine compounds such as 4,4',4"-tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as "TDATA") and 4,4',4"-tris[N-(3-methylphenyl)-N-phenyl-amino]-triphenylamine (hereinafter referred to as "MTDATA").

Metal complexes are often used as the electron transport material, and examples of such materials include tris(8-quinolinolato)aluminum (hereinafter referred to as "Alq ₃ "), BAlq, tris(4-methyl-8-quinolinolato)aluminum (hereinafter referred to as "Almq"), bis(10-hydroxybenzo[h]-
Metal complexes having a quinoline skeleton or a benzoquinoline skeleton, such as bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to as “Zn(BOX) 2 ”), bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to as “Zn(BOX) ₂ ”), and the like, are also useful.
There are also metal complexes having oxazole-based or thiazole-based ligands, such as 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3-dimethylphenyl-benzothiazolato zinc (hereinafter referred to as "Zn(BTZ) ₂ ").
3,4-Oxadiazole (hereinafter referred to as "PBD"), oxadiazole derivatives such as OXD-7, TAZ, 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (hereinafter referred to as "p-EtTAZ")
Triazole derivatives such as phenyltriazole (hereinafter referred to as "BPhen"), and phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as "BPhen") and BCP have electron transport properties.

The electron injection material may be the electron transport material described above. In addition, ultra-thin films of insulators such as metal halides, such as calcium fluoride, lithium fluoride, and cesium fluoride, and alkali metal oxides, such as lithium oxide, are often used. In addition, alkali metal complexes, such as lithium acetylacetonate (hereinafter, referred to as "Li(acac)") and 8-quinolinolato-lithium (hereinafter, referred to as "Liq"), are also effective.

The luminescent materials include the above-mentioned _Alq3 , Almq, BeBq, BAlq, and Zn(BOX
In addition to metal complexes such as Zn(BTZ) ₂ and Zn(BTZ) ₂ , various fluorescent dyes are effective. Fluorescent dyes include blue 4,4'-bis(2,2-diphenyl-vinyl)-biphenyl and red-orange 4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4
H-pyran, etc. Triplet luminescent materials are also possible, and are mainly complexes with platinum or iridium as the central metal. Triplet luminescent materials include tris(2-phenylpyridine)iridium, bis(2-(4'-tolyl)pyridinato-N,C ^2' )acetylacetonatoiridium (hereinafter referred to as "acacIr(tpy) ₂ "),
, 13,17,18-octaethyl-21H,23H porphyrin-platinum and the like are known.

By combining the materials having the above-described functions, a highly reliable light-emitting element can be manufactured.

It is also possible to use a light-emitting element in which layers are formed in the reverse order to that in Fig. 45. That is, the element structure is such that a cathode 4508, an electron injection layer 4507 made of an electron injection material, an electron transport layer 4506 made of an electron transport material thereon, a light-emitting layer 4505, a hole transport layer 4504 made of a hole transport material, a hole injection layer 4503 made of a hole injection material, and an anode 4502 are laminated on a substrate 4501.

In addition, the light-emitting element only needs to have at least one of the anode and cathode transparent in order to extract light emission. The transistor and light-emitting element are formed on a substrate, and light-emitting elements may have a top emission structure in which light emission is extracted from the surface opposite to the substrate, a bottom emission structure in which light emission is extracted from the surface on the substrate side, or a double-sided emission structure in which light emission is extracted from the substrate side and the surface opposite to the substrate. The pixel configuration of the present invention can be applied to light-emitting elements of any emission structure.

First, we will explain the light-emitting element with a top emission structure using Figure 46 (a).

A driving transistor 4601 is formed on a substrate 4600.
A first electrode 4602 is formed in contact with the source electrode of the first electrode 4602, and a layer 4603 containing an organic compound is formed thereon.
4603 and a second electrode 4604 are formed.

The first electrode 4602 is an anode of the light-emitting element, and the second electrode 4604 is a cathode of the light-emitting element. In other words, the layer 4603 containing an organic compound is sandwiched between the first electrode 4602 and the second electrode 4604 to form a light-emitting element.

In addition, it is desirable to use a material with a large work function as the material used for the first electrode 4602 functioning as an anode. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a laminated film of a film mainly composed of titanium nitride and aluminum, or a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, can be used. In addition, a laminated structure has low resistance as a wiring, good ohmic contact can be obtained, and the film can function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed.

The material used for the second electrode 4604 functioning as a cathode is a material having a small work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, C
It is preferable to use a laminate of a thin metal film made of calcium fluoride ( _CaF2 , CaF2+ ...

In this way, it becomes possible to extract light from the light-emitting element from the top surface as shown by the arrow in Fig. 46(a). That is, when applied to the display panel in Fig. 44, light is emitted toward the sealing substrate 4404. Therefore, when a light-emitting element having a top emission structure is used in a display device, a substrate having optical transparency is used as the sealing substrate 4404.

In addition, in the case of providing an optical film, the optical film may be provided on the sealing substrate 4404 .

The first electrode 4602 can also be formed using a metal film made of a material having a small work function, such as MgAg, MgIn, or AlLi, which functions as a cathode.
The electrode 4604 is made of an ITO (indium tin oxide) film, an indium zinc oxide (IZO) film,
Thus, with this configuration, the transmittance of the top emission can be increased.

Next, a light emitting element having a bottom emission structure will be described with reference to Fig. 46(b). Since the light emitting element has the same structure as that of Fig. 46(a) except for the emission structure, the same reference numerals will be used for the description.

Here, as a material used for the first electrode 4602 functioning as an anode, a material having a large work function is desirably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

The material used for the second electrode 4604 functioning as a cathode is a material having a small work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, C
In this way, a metal film made of a light-reflecting metal such as calcium fluoride (CaF ₂ , or calcium nitride) can be used. By using a light-reflecting metal film, a light-opaque cathode can be formed.

In this way, it becomes possible to extract light from the light emitting element to the bottom surface, as shown by the arrow in Fig. 46(b). In other words, when applied to the display panel of Fig. 44, light is emitted to the substrate 4410 side. Therefore, when a light emitting element with a bottom emission structure is used in a display device, the substrate 4
A substrate 410 having optical transparency is used.

If an optical film is provided, the optical film may be provided on the substrate 4410.

Next, a light emitting element having a dual emission structure will be described with reference to Fig. 46(c). Since the light emitting element has the same structure as Fig. 46(a) except for the emission structure, the same reference numerals will be used for the description.

Here, as a material used for the first electrode 4602 functioning as an anode, a material having a large work function is desirably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

The material used for the second electrode 4604 functioning as a cathode is a material having a small work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, C
aF ₂ or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium oxide zinc oxide alloy (In ₂ O ₃ -ZnO), zinc oxide (ZnO)
In this way, a cathode capable of transmitting light can be formed by using a thin metal film and a transparent conductive film having transparency.

In this way, light from the light-emitting element can be extracted on both sides as shown by the arrows in Fig. 46(c). That is, when applied to the display panel in Fig. 44, light is emitted to the substrate 4410 side and the sealing substrate 4404 side. Therefore, when a light-emitting element having a dual emission structure is used in a display device, both the substrate 4410 and the sealing substrate 4404 are optically transparent.

In addition, in the case where an optical film is provided, the optical film may be provided on both the substrate 4410 and the sealing substrate 4404 .

The present invention can also be applied to a display device that realizes a full-color display using white light-emitting elements and color filters.

As shown in Figure 47, a base film 4702 is formed over a substrate 4700, a driving transistor 4701 is formed over the base film 4702, a first electrode 4703 is formed in contact with a source electrode of the driving transistor 4701, and a layer 4704 containing an organic compound and a second electrode 4705 are formed over the first electrode 4703.

The first electrode 4703 is an anode of the light-emitting element. The second electrode 4705 is a cathode of the light-emitting element. In other words, the layer 4704 containing an organic compound is sandwiched between the first electrode 4703 and the second electrode 4705 to form the light-emitting element. In the configuration of FIG. 47, white light is emitted. A red color filter 4706R, a green color filter 4706G, and a blue color filter 4706B are provided above the light-emitting element, and full-color display can be performed. In addition, a black matrix (also referred to as BM) 4707 is provided to separate these color filters.

The above-mentioned configurations of the light-emitting element can be used in combination and can be appropriately used in the display device of the present invention. In addition, the above-mentioned display panel configuration and the light-emitting element are only examples, and can be applied to a display device having a different configuration from the above-mentioned configuration.

Next, a partial cross-sectional view of the pixel section of the display panel is shown.

First, a case where a polysilicon (p-Si:H) film is used for the semiconductor layer of a transistor will be described with reference to FIGS.

Here, the semiconductor layer is, for example, an amorphous silicon (a-Si) film formed on a substrate by a known film formation method. Note that it is not necessary to be limited to an amorphous silicon film, and any semiconductor film (including a microcrystalline semiconductor film) containing an amorphous structure may be used. Furthermore, a compound semiconductor film containing an amorphous structure, such as an amorphous silicon germanium film, may also be used.

The amorphous silicon film is then crystallized by a laser crystallization method, a thermal crystallization method using RTA or an annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. Of course, these methods may be combined.

The above-mentioned crystallization results in the formation of partially crystallized regions in the amorphous semiconductor film.

Furthermore, the crystalline semiconductor film, the crystallinity of which has been partially increased, is patterned into a desired shape to form an island-shaped semiconductor film from the crystallized region, which is used as a semiconductor layer of a transistor.

As shown in FIG. 48A, a base film 4802 is formed on a substrate 4801, and a semiconductor layer is formed thereon. The semiconductor layer includes a channel forming region 4802 of a driving transistor 4818.
803, an LDD region 4804 and an impurity region 4805 which becomes a source region or a drain region
, a channel forming region 4806 which becomes the lower electrode of a capacitor element 4819, and an LDD region 48
07 and an impurity region 4808. Note that the channel formation region 4803 and the channel formation region 4806 may be channel doped.

The substrate may be a glass substrate, a quartz substrate, a ceramic substrate, etc. The base film 4802 may be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a laminate of these layers.

A gate electrode 4810 and a capacitor element 481 are provided on the semiconductor layer with a gate insulating film 4809 interposed therebetween.
Nine upper electrodes 4811 are formed.

An interlayer insulating film 4812 is formed to cover the capacitor element 4819 and the driving transistor 4818. A wiring 4813 is formed on the interlayer insulating film 4812 through a contact hole.
A pixel electrode 4814 is formed in contact with the wiring 4813, and the pixel electrode 481
An insulator 4815 is formed to cover the end portion of the pixel electrode 4814 and the wiring 4813. Here, a positive type photosensitive acrylic resin film is used to form the insulator 4815. Then, a layer 4816 containing an organic compound and a counter electrode 4817 are formed over the pixel electrode 4814, and a light-emitting element 4820 is formed in a region where the layer 4816 containing an organic compound is sandwiched between the pixel electrode 4814 and the counter electrode 4817.

As shown in FIG. 48B, the LDD that constitutes a part of the lower electrode of the capacitance element 4819
A region 4821 may be provided so as to overlap with the upper electrode 4811 of the capacitor element 4819. Note that common reference numerals are used for parts common to FIG.

As shown in FIG. 49A, the capacitor 4823 is formed in the same layer as the wiring 4813 that is in contact with the impurity region 4805 of the driving transistor 4818.
48A. The same reference numerals are used for the same parts as in FIG. 48A, and the description thereof will be omitted. Since the second upper electrode 4822 is in contact with the impurity region 4808, the upper electrode 48
The first insulating film 4809 is sandwiched between the first insulating film 4801 and the channel forming region 4806.
The first capacitor and a second capacitor formed by sandwiching an interlayer insulating film 4812 between an upper electrode 4811 and a second upper electrode 4822 are connected in parallel to form a capacitor 4823 consisting of a first capacitor and a second capacitor. The capacitance of this capacitor 4823 is a composite capacitance obtained by adding the capacitances of the first capacitor and the second capacitor, so that a capacitor with a large capacitance can be formed in a small area. In other words, when used as a capacitor in the pixel configuration of the present invention, the aperture ratio can be improved.

49B may be used. A base film 4902 is formed on a substrate 4901, and a semiconductor layer is formed thereon. The semiconductor layer has a channel formation region 4903 of a driving transistor 4918, an LDD region 4904, and an impurity region 4905 which becomes a source region or a drain region. Note that the channel formation region 4903 may be channel doped.

The substrate can be a glass substrate, a quartz substrate, a ceramic substrate, etc. The base film 4902 can be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a stack of these layers.

A gate electrode 4907 and a first electrode 49 are provided on the semiconductor layer via a gate insulating film 4906.
08 is formed.

A first interlayer insulating film 4909 is formed to cover the driving transistor 4918 and the first electrode 4908.
A wiring 4910 is in contact with the impurity region 4905 through a contact hole on the first interlayer insulating film 4909. A second electrode 4911 made of the same material as the wiring 4910 is formed in the same layer as the wiring 4910.

Further, a second interlayer insulating film 4912 is formed so as to cover the wiring 4910 and the second electrode 4911, and a pixel electrode 4913 is formed on the second interlayer insulating film 4912 so as to be in contact with the wiring 4910 through a contact hole.
A third electrode 4914 made of the same material as the first electrode 4913 is formed.
A capacitor element 4919 is formed by the gate electrode 908, a second electrode 4911, and a third electrode 4914.

A layer 4916 containing an organic compound and a counter electrode 4917 are formed on the pixel electrode 4913. In a region where the layer 4916 containing an organic compound is sandwiched between the pixel electrode 4913 and the counter electrode 4917,
A light emitting element 4920 is formed.

As described above, examples of the structure of a transistor using a crystalline semiconductor film as a semiconductor layer include the structures shown in FIG. 48 and FIG. 49. The structure of the transistor shown in FIG. 48 and FIG. 49 is an example of a transistor with a top gate structure. That is, the LDD region may overlap with the gate electrode, or may not overlap with the gate electrode. Also, a part of the LDD region may overlap with the gate electrode. Furthermore, the gate electrode may have a tapered shape, and the LDD region may be provided in a self-aligned manner under the tapered part of the gate electrode. Also, the number of gate electrodes is not limited to two, and a multi-gate structure of three or more may be used, or a single gate electrode may be used.

By using a crystalline semiconductor film for the semiconductor layer (channel formation region, source region, drain region, etc.) of the transistor constituting the pixel of the present invention, it becomes easy to form the scanning line driver circuit and the signal line driver circuit integrally with the pixel portion. In addition, a part of the signal line driver circuit may be formed integrally with the pixel portion, and a part of the signal line driver circuit may be formed on an IC chip and mounted by COG or the like as shown in the display panel of FIG. 44. By adopting such a configuration, it is possible to reduce the manufacturing cost.

In addition, as the configuration of a transistor using polysilicon (p-Si:H) in the semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom-gate structure transistor in which a gate electrode is located under a semiconductor layer may be applied. Here, a partial cross-sectional view of a pixel portion of a display panel to which a bottom-gate structure transistor is applied is shown in FIG.

50A, a base film 5002 is formed on a substrate 5001. Further, a gate electrode 5003 is formed on the base film 5002. Also, a first electrode 5004 made of the same material as the gate electrode 5003 is formed in the same layer as the gate electrode 5003.
Polycrystalline silicon doped with phosphorus can be used as the material for the gate electrode 5003. In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may also be used.

A gate insulating film 5005 is formed so as to cover the gate electrode 5003 and the first electrode 5004. As the gate insulating film 5005, a silicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer is formed over a gate insulating film 5005. The semiconductor layer has a channel formation region 5006 of a driving transistor 5022, an LDD region 5007, and an impurity region 5008 which becomes a source region or a drain region, as well as a channel formation region 5009 which becomes a second electrode of a capacitor 5023, an LDD region 5010, and an impurity region 5011. Note that the channel formation region 5006 and the channel formation region 5009 may be channel doped.

The substrate may be a glass substrate, a quartz substrate, a ceramic substrate, etc. The base film 5002 may be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a laminate of these layers.

A first interlayer insulating film 5012 is formed to cover the semiconductor layer, and a wiring 5013 is in contact with the impurity region 5008 through a contact hole on the first interlayer insulating film 5012. A third electrode 5014 is formed in the same layer as the wiring 5013 and from the same material as the wiring 5013.
A capacitor element 5023 is formed by the first electrode 5004 , the second electrode, and the third electrode 5014 .

An opening 5015 is formed in the first interlayer insulating film 5012. The second interlayer insulating film 5012 is formed so as to cover the driving transistor 5022, the capacitor element 5023, and the opening 5015.
16 is formed, and the pixel electrode 5 is formed on the second interlayer insulating film 5016 through a contact hole.
017 is formed. An insulator 5018 is formed covering the end of the pixel electrode 5017. For example, a positive-type photosensitive acrylic resin film can be used. A layer 5019 containing an organic compound and a counter electrode 5020 are formed on the pixel electrode 5017, and a light-emitting element 5021 is formed in a region where the layer 5019 containing an organic compound is sandwiched between the pixel electrode 5017 and the counter electrode 5020. An opening 5015 is located below the light-emitting element 5021. In other words, when light emitted from the light-emitting element 5021 is extracted from the substrate side, the opening 5015 can increase the transmittance.

50(a), a fourth electrode 5024 may be formed in the same layer as the pixel electrode 5017 using the same material, to obtain a structure as shown in FIG.
A capacitor element 5025 including the first electrode 5014, the second electrode, the third electrode 5014, and the fourth electrode 5024 can be formed.

Next, a case where an amorphous silicon (a-Si:H) film is used for a semiconductor layer of a transistor will be described with reference to FIGS.

51 shows a partial cross-sectional view of a pixel portion of a display panel to which a top-gate structure transistor using amorphous silicon for a semiconductor layer is applied. As shown in FIG. 51(a),
A base film 5102 is formed on the insulating film 5101. Further, a pixel electrode 5103 is formed on the base film 5102.
A first electrode 5104 made of the same material as the pixel electrode 5103 is formed in the same layer as the pixel electrode 5103.

The substrate may be a glass substrate, a quartz substrate, a ceramic substrate, etc. The base film 5102 may be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a laminate of these layers.

Wirings 5105 and 5106 are formed on an underlayer 5102, and an end of a pixel electrode 5103 is covered with the wiring 5105. An N-type semiconductor layer 5107 and an N-type semiconductor layer 5108 having N-type conductivity are formed on the wirings 5105 and 5106. A semiconductor layer 5109 is formed on the underlayer 5102 between the wirings 5105 and 5106. A part of the semiconductor layer 5109 is connected to the N-type semiconductor layer 5107 and the N-type semiconductor layer 5108.
108. This semiconductor layer 5109 is made of amorphous silicon (
The insulating film is formed of a semiconductor film having non-crystalline properties, such as a-Si:H, or a microcrystalline semiconductor (μ-Si:H).

A gate insulating film 5110 is formed on the semiconductor layer 5109.
An insulating film 5111 made of the same material as the gate insulating film 5110 is formed in the same layer as the gate insulating film 5110 over the first electrode 5104. As the gate insulating film 5110, a silicon oxide film, a silicon nitride film, or the like is used.

A gate electrode 5112 is formed on the gate insulating film 5110.
A second electrode 5113 made of the same material as the gate electrode 5112 is formed on the first electrode 5104 via an insulating film 5111 in the same layer as the first electrode 5112.
A capacitor element 5119 is formed in such a structure that an insulating film 5111 is sandwiched between a first electrode 5104 and a second electrode 5113. In addition, an interlayer insulating film 5114 is formed to cover an end portion of the pixel electrode 5103, a driving transistor 5118, and the capacitor element 5119.

A layer 5115 containing an organic compound and a counter electrode 5116 are formed on the interlayer insulating film 5114 and the pixel electrode 5103 located in its opening, and a light-emitting element 5117 is formed in the region where the layer 5115 containing an organic compound is sandwiched between the pixel electrode 5103 and the counter electrode 5116.

51(a) may be replaced with a first electrode 5120 as shown in FIG. 51(b). The first electrode 5120 shown in FIG.
It is formed in the same layer as the wirings 5105 and 5106 and made of the same material as the wirings 5105 and 5106 .

Next, partial cross-sectional views of a pixel portion of a display panel to which a bottom-gate transistor using amorphous silicon for a semiconductor layer is applied are shown in FIGS.

As shown in FIG. 52A, a base film 5202 is formed on a substrate 5201. Further, a gate electrode 5203 is formed on the base film 5202.
A first electrode 5204 made of the same material as the gate electrode 5203 is formed in the same layer. Polycrystalline silicon doped with phosphorus can be used as the material of the gate electrode 5203. In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may also be used.

A gate insulating film 5205 is formed so as to cover the gate electrode 5203 and the first electrode 5204. As the gate insulating film 5205, a silicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer 5206 is formed on the gate insulating film 5205.
A semiconductor layer 5207 made of the same material as the semiconductor layer 5206 is formed in the same layer as the semiconductor layer 6 .

The substrate may be a glass substrate, a quartz substrate, a ceramic substrate, etc. The base film 5202 may be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a stack of these layers.

N-type semiconductor layers 5208 and 5209 having N-type conductivity are formed on the semiconductor layer 5206 , and an N-type semiconductor layer 5210 is formed on the semiconductor layer 5207 .

Wirings 5211 and 5212 are formed on the N-type semiconductor layers 5208 and 5209, respectively.
In addition, a conductive layer 5213 made of the same material as the wirings 5211 and 5212 is formed on the N-type semiconductor layer 5210 in the same layer as the wirings 5211 and 5212 .

As a result, a second semiconductor layer 5207, an N-type semiconductor layer 5210, and a conductive layer 5213 are formed.
The second electrode and the first electrode 5204 form a gate insulating film 520.
A capacitance element 5220 is formed by sandwiching the capacitor 5 therebetween.

One end of the wiring 5211 is extended, and a pixel electrode 5214 is formed in contact with the upper part of the extended wiring 5211 .

In addition, an insulator 5215 is formed so as to cover an end portion of the pixel electrode 5214 , the driving transistor 5219 , and the capacitor element 5220 .

A layer 5216 containing an organic compound and a counter electrode 5217 are formed on the pixel electrode 5214 and the insulator 5215. The pixel electrode 5214 and the counter electrode 5217 form a layer 5216 containing an organic compound.
A light emitting element 5218 is formed in the region where 16 is sandwiched.

The semiconductor layer 5207 and the N-type semiconductor layer 5208 which are to be a part of the second electrode of the capacitor 5220
210 may not be provided. That is, the second electrode of the capacitor 5220 may be the conductive layer 5213, and the capacitor 5220 may have a structure in which a gate insulating film is sandwiched between the first electrode 5204 and the conductive layer 5213.

In addition, by forming the pixel electrode 5214 before forming the wiring 5211 in FIG. 52A, it is possible to form the second electrode 5221 made of the same material as the pixel electrode 5214 in the same layer as the pixel electrode 5214 as shown in FIG. 52B.
A capacitor element 522 having a structure in which a gate insulating film 5205 is sandwiched between the first electrode 5204 and the first electrode 5204.
2 can be formed.

52 shows an example in which a transistor having an inverse staggered channel etch structure is applied, but a transistor having a channel protection structure may also be applied. The case in which a transistor having a channel protection structure is applied will be described with reference to FIGS. 53(a) and 53(b).

The transistor having a channel-protection type structure shown in Figure 53(a) differs from the driving transistor 5219 having a channel-etched structure shown in Figure 52(a) in that an insulator 5301 serving as an etching mask is provided on a region in which a channel is formed in the semiconductor layer 5206, and other common parts are designated by common symbols.

Similarly, the transistor having the channel protection structure shown in FIG.
5A and 5B, in that an insulator 5301 serving as an etching mask is provided over a region in which a channel is formed of a semiconductor layer 5206 of a driving transistor 5219 having a channel etch structure as shown in FIG. 5A, and the same symbols are used for other common parts.

By using an amorphous semiconductor film for a semiconductor layer (such as a channel formation region, a source region, or a drain region) of a transistor constituting a pixel of the present invention, manufacturing costs can be reduced.

Note that the structures of a transistor and a capacitor that can be applied to a pixel portion of a display device of the present invention are not limited to the above-described structures, and various transistor structures and capacitor structures can be used.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 8)
In this embodiment mode, a method for manufacturing a semiconductor device such as a transistor will be described, in which a plasma treatment is used to manufacture the semiconductor device.

54A and 54B are diagrams showing examples of the structure of a semiconductor device including a transistor. In addition, in FIG. 54B, FIG. 54A corresponds to a cross-sectional view taken along line a-b, and FIG. 54C corresponds to a cross-sectional view taken along line a-b in FIG.
This corresponds to the cross-sectional view between cd in (A).

The semiconductor device shown in FIG. 54 includes semiconductor films 5403a and 5403b provided on a substrate 5401 with an insulating film 5402 interposed therebetween, and a gate insulating film 5403a and a gate insulating film 5403b provided on the semiconductor films 5403a and 5403b.
54 includes a gate electrode 5405 provided through a gate electrode 5404, insulating films 5406 and 5407 provided to cover the gate electrode, and a conductive film 5408 connected to the source or drain regions of the semiconductor films 5403a and 5403b and provided on the insulating film 5407. Note that, although Fig. 54 shows a case where an N-channel transistor 5410a using a part of the semiconductor film 5403a as a channel region and a P-channel transistor 5410b using a part of the semiconductor film 5403b as a channel region are provided, the present invention is not limited to this configuration. For example, in Fig. 54, an LDD region is provided in the N-channel transistor 5410a and an LDD region is not provided in the P-channel transistor 5410b, but it is possible to provide an LDD region in both or to provide neither.

In this embodiment, the substrate 5401, the insulating film 5402, the semiconductor film 5403a and the
54 is manufactured by oxidizing or nitriding the semiconductor film or insulating film by performing oxidation or nitriding using plasma treatment on at least one layer of the gate insulating film 5404, the insulating film 5406, or the insulating film 5407. In this manner, by oxidizing or nitriding the semiconductor film or insulating film using plasma treatment, the surface of the semiconductor film or insulating film is modified, and a denser insulating film can be formed compared to an insulating film formed by a CVD method or a sputtering method, so that defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

In this embodiment, a method for manufacturing a semiconductor device by performing plasma treatment on the semiconductor films 5403a and 5403b or the gate insulating film 5404 in FIG. 54 and oxidizing or nitriding the semiconductor films 5403a and 5403b or the gate insulating film 5404 will be described with reference to the drawings.

First, a case will be described in which an island-shaped semiconductor film is provided over a substrate, and the edge of the island-shaped semiconductor film is formed to have a shape close to a right angle.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (FIG. 55(A)
) The island-shaped semiconductor films 5403a and 5403b can be provided by forming an amorphous semiconductor film using a material (e.g., Si _x Ge _1-x , etc.) mainly composed of silicon (Si) on an insulating film 5402 previously formed on a substrate 5401 by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), crystallizing the amorphous semiconductor film, and selectively etching the semiconductor film. The crystallization of the amorphous semiconductor film can be performed by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. In FIG. 55, the ends of the island-shaped semiconductor films 5403a and 5403b are provided in a shape close to a right angle (θ=85 to 100°).

Next, the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment, so that oxide films or nitride films 5403a and 5403b are formed on the surfaces of the semiconductor films 5403a and 5403b, respectively.
21a and 5421b (hereinafter also referred to as insulating films 5421a and 5421b) are formed ( FIG. 55B ). For example, when Si is used as the semiconductor films 5403a and 5403b,
The insulating film 5421a and the insulating film 5421b are formed of silicon oxide (SiOx) or silicon nitride (
In addition, the semiconductor films 5403a and 5403b may be oxidized by plasma treatment and then nitrided by performing another plasma treatment. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 5403a and 5403b, and silicon nitride oxide (SiNxOy) (x>y) is formed on the surface of the silicon oxide. When the semiconductor film is oxidized by plasma treatment, the semiconductor film is oxidized in an oxygen atmosphere (for example, a mixture of oxygen (O ₂ ) and rare gas (He
, Ne, Ar, Kr, Xe) atmosphere or oxygen and hydrogen (H ₂ )
and a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere).
When the semiconductor film is nitrided by plasma treatment, the semiconductor film is nitrided in a nitrogen atmosphere (e.g., nitrogen (N ₂ )
Plasma treatment is performed in an atmosphere of nitrogen, hydrogen, and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe), in an atmosphere of nitrogen, hydrogen, and a rare gas, or in an atmosphere of _NH3 and a rare gas). For example, Ar can be used as the rare gas. Alternatively, a mixed gas of Ar and Kr may be used. Therefore, the insulating films 5421a and 5421b are formed by the rare gas (H
When Ar is used, the insulating films 5421a and 5421b contain Ar.

The plasma treatment is carried out in an atmosphere of the above gas with an electron density of 1×10 ¹¹ cm ⁻³
and the electron temperature of ^the plasma is 0.5 eV to 1.5 eV ^.
The electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor films 5403a and 5403b) formed on the substrate 5401 is low, so that damage to the object to be processed by the plasma can be prevented.
Because of the high density of 10 ¹¹ cm ^-3 or more, the oxide or nitride film formed by oxidizing or nitriding the irradiated object using the plasma treatment has excellent uniformity in film thickness, etc., and can form a dense film, compared to films formed by a CVD method, a sputtering method, or the like.
In addition, since the electron temperature of the plasma is as low as 1 eV or less, the oxidation or nitriding treatment can be performed at a lower temperature than in the conventional plasma treatment or thermal oxidation method. For example, the oxidation or nitriding treatment can be performed sufficiently even if the plasma treatment is performed at a temperature 100 degrees or more lower than the distortion point temperature of the glass substrate. The frequency for generating the plasma is microwave (2.4
In addition, unless otherwise specified below, the plasma treatment is performed under the above conditions.

Next, a gate insulating film 5404 is formed so as to cover the insulating films 5421a and 5421b (FIG. 55C). The gate insulating film 5404 can be formed as a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), by using a known method (sputtering, LPCVD, plasma CVD, or the like), or as a laminated structure of these. For example, by using Si as the semiconductor films 5403a and 5403b and oxidizing the Si by plasma treatment, the insulating films 5421a and 5421b are formed on the surfaces of the semiconductor films 5403a and 5403b.
In the case where silicon oxide is formed as the insulating film 5421b, silicon oxide (SiOx) is formed as a gate insulating film over the insulating films 5421a and 5421b. In addition, in FIG. 55B, when the insulating films 5421a and 5421b formed by oxidizing or nitriding the semiconductor films 5403a and 5403b by plasma treatment have a sufficient thickness, the insulating films 5421a and 5421b are formed as a gate insulating film over the insulating films 5421a and 5421b.
1a and 5421b can also be used as a gate insulating film.

Next, by forming a gate electrode 5405 and the like on the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions can be manufactured (Figure 55 (D)).

In this manner, before the gate insulating film 5404 is provided on the semiconductor films 5403a and 5403b,
By oxidizing or nitriding the surfaces of the semiconductor films 5403a and 5403b by plasma treatment, it is possible to prevent a short circuit between the gate electrode and the semiconductor film caused by poor coverage of the gate insulating film 5404 at the ends 5451a and 5451b of the channel region. In other words, when the ends of the island-shaped semiconductor film have a shape close to a right angle (θ=85 to 100°),
When a gate insulating film is formed to cover a semiconductor film by a VD method, a sputtering method, or the like, there is a risk of a problem of poor coverage due to a step in the gate insulating film at the end of the semiconductor film.
By oxidizing or nitriding the surface of the semiconductor film in advance by using a plasma treatment, it becomes possible to prevent insufficient coverage of the gate insulating film at the edge of the semiconductor film.

55, the gate insulating film 5404 may be oxidized or nitrided by performing plasma treatment after the gate insulating film 5404 is formed. In this case, the gate insulating film 5404 (FIG. 56A) formed to cover the semiconductor films 5403a and 5403b may be oxidized or nitrided.
The gate insulating film 5404 is oxidized or nitrided by plasma treatment to form an oxide film or nitride film (hereinafter, also referred to as an insulating film 5423) on the surface of the gate insulating film 5404 (FIG. 56B). The plasma treatment can be performed under the same conditions as those in FIG. 55B. The insulating film 5523 contains a rare gas used in the plasma treatment, for example, Ar.
When using the insulating film 5523, Ar is contained in the insulating film 5523.

56B, the gate insulating film 5404 may be oxidized by performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) is used for the semiconductor films 5403a and 5403b.
Alternatively, silicon oxynitride (SiOxNy) (x>y) is formed, and silicon nitride oxide (SiNxOy) (x>y) is formed in contact with the gate electrode 5405. After that, by forming the gate electrode 5405 and the like on the insulating film 123, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions can be manufactured (FIG. 56(C)). In this way, by performing plasma treatment on the gate insulating film, the surface of the gate insulating film can be oxidized or nitrided, thereby modifying the surface of the gate insulating film to form a dense film. The insulating film obtained by the plasma treatment is denser and has fewer defects such as pinholes compared to insulating films formed by a CVD method or a sputtering method, and therefore the characteristics of the transistor can be improved.

56 shows a case where the surfaces of the semiconductor films 5403a and 5403b are oxidized or nitrided by performing plasma treatment on the semiconductor films 5403a and 5403b in advance, but a method of performing plasma treatment after forming the gate insulating film 5404 without performing plasma treatment on the semiconductor films 5403a and 5403b may also be used. By performing plasma treatment before forming the gate electrode in this manner, even if poor coverage occurs at the end of the semiconductor film due to a step or the like in the gate insulating film, the semiconductor film exposed due to the poor coverage can be oxidized or nitrided, and therefore it is possible to prevent a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film.

In this way, even if the end of the island-shaped semiconductor film is provided in a shape close to a right angle, by performing plasma treatment on the semiconductor film or the gate insulating film and oxidizing or nitriding the semiconductor film or the gate insulating film, it is possible to prevent a short circuit between the gate electrode and the semiconductor film caused by insufficient coverage of the gate insulating film at the end of the semiconductor film.

Next, a case will be described in which an island-shaped semiconductor film is provided over a substrate, and the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ=30 to 85°).

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (FIG. 57(A)
)) The island-shaped semiconductor films 5403a and 5403b can be provided by forming an amorphous semiconductor film using a material (e.g., Si _x Ge _1-x , etc.) mainly composed of silicon (Si) on an insulating film 5402 formed in advance on a substrate 5401 by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), crystallizing the amorphous semiconductor film by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization, and selectively etching and removing the semiconductor film. Note that in FIG. 57, the end of the island-shaped semiconductor film is tapered (θ=3
The angle is set at 0 to 85°.

Next, a gate insulating film 5404 is formed so as to cover the semiconductor films 5403a and 5403b (
57B). The gate insulating film 5404 can be formed by a known method (such as a sputtering method, an LPCVD method, or a plasma CVD method) to have a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), or a laminated structure of these.

Next, the gate insulating film 5404 is oxidized or nitrided by plasma treatment to form an oxide film or a nitride film (hereinafter, also referred to as an insulating film 5424) on the surface of the gate insulating film 5404 (FIG. 57C). Note that the conditions of the plasma treatment can be the same as those described above. For example, when silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) is used as the gate insulating film 5404, a dense film with fewer defects such as pinholes can be formed on the surface of the gate insulating film by oxidizing the gate insulating film 5404 by plasma treatment in an oxygen atmosphere, as compared with a gate insulating film formed by a CVD method, a sputtering method, or the like. On the other hand, silicon nitride oxide (SiNxOy) (x>y) can be provided as the insulating film 5424 on the surface of the gate insulating film 5404 by nitriding the gate insulating film 5404 by plasma treatment in a nitrogen atmosphere. Alternatively, the gate insulating film 5404 may be oxidized by once performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. The insulating film 5424 contains a rare gas used in the plasma treatment. For example, when Ar is used, the insulating film 5424 contains Ar.

Next, by forming a gate electrode 5405 and the like on the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions can be manufactured (Figure 57 (D)).

In this manner, by subjecting the gate insulating film to a plasma treatment, an insulating film made of an oxide film or a nitride film is provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified.
An insulating film oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by CVD or sputtering, and therefore the characteristics of a transistor can be improved. In addition, by forming the end of the semiconductor film into a tapered shape, short circuits between the gate electrode and the semiconductor film caused by poor coverage of the gate insulating film at the end of the semiconductor film can be suppressed, and short circuits between the gate electrode and the semiconductor film can be further prevented by performing plasma treatment after forming the gate insulating film.

Next, a method for manufacturing a semiconductor device different from that shown in Fig. 57 will be described with reference to the drawings. Specifically, the method will be described with respect to a case where a plasma treatment is selectively performed on an end portion of a semiconductor film having a tapered shape.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (FIG. 58(A)
The island-shaped semiconductor films 5403a and 5403b are formed by forming an amorphous semiconductor film on an insulating film 5402 formed in advance on a substrate 5401 using a known method (sputtering, LPCVD, plasma CVD, etc.) using a material mainly composed of silicon (Si) (e.g., Si _x Ge _1-x , etc.), crystallizing the amorphous semiconductor film, and then forming resists 5425a and 5425b on the insulating film 5402.
The insulating film 5b can be provided by selectively etching the semiconductor film using the insulating film 5b as a mask.
The crystallization of the amorphous semiconductor film can be carried out by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or an annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods.

Next, before removing the resists 5425a and 5425b used for etching the semiconductor films, a plasma treatment is performed to selectively oxidize or nitride the ends of the island-shaped semiconductor films 5403a and 5403b, thereby forming oxide films or nitride films (hereinafter also referred to as insulating films 5426) at the ends of the semiconductor films 5403a and 5403b (FIG. 58B). The plasma treatment is performed under the above-mentioned conditions. The insulating film 5426 contains the rare gas used in the plasma treatment.

Next, a gate insulating film 5404 is formed so as to cover the semiconductor films 5403a and 5403b (
58(C)). The gate insulating film 5404 can be provided in the same manner as described above.

Next, by forming a gate electrode 5405 and the like on the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions can be manufactured (Figure 58 (D)).

When the ends of the semiconductor films 5403a and 5403b are tapered, the semiconductor film 5403
The ends 5452a and 5452b of the channel region formed in a part of the channel region 5403a and 5403b are also tapered, and the thickness of the semiconductor film and the thickness of the gate insulating film are changed compared to the central part.
Therefore, in this embodiment, the edge of the channel region is selectively oxidized or nitrided by plasma treatment to form an insulating film on the semiconductor film that becomes the edge of the channel region, thereby reducing the effect of the edge of the channel region on the transistor.

In FIG. 58, an example in which the end portions of the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment is shown. However, as shown in FIG. 57, it is also possible to oxidize or nitride the gate insulating film 5404 by plasma treatment (FIG. 60(A)).
)).

Next, a method for manufacturing a semiconductor device, which is different from the above, will be described with reference to the drawings. Specifically, the case where plasma treatment is performed on a semiconductor film having a tapered shape will be described.

First, island-shaped semiconductor films 5403a and 5403b are formed over a substrate 5401 in the same manner as described above (FIG. 59A).

Next, the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment, so that oxide films or nitride films 5403a and 5403b are formed on the surfaces of the semiconductor films 5403a and 5403b, respectively.
27a and 5427b (hereinafter also referred to as insulating films 5427a and 5427b) are formed (FIG. 59B). The plasma treatment can be performed under the above-mentioned conditions. For example,
When Si is used for the semiconductor films 5403a and 5403b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 5427a and 5427b. The semiconductor films 5403a and 5403b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, the semiconductor films 5403a and 5403b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again.
Silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) is formed in contact with the insulating films 5427a and 5427b, and silicon nitride oxide (SiNxOy) (x>y) is formed on the surface of the silicon oxide. Therefore, the insulating films 5427a and 5427b contain a rare gas used in the plasma treatment.
By performing the plasma treatment, the ends of the semiconductor films 5403a and 5403b are also oxidized or nitrided at the same time.

Next, a gate insulating film 5404 is formed so as to cover the insulating films 5427a and 5427b (FIG. 59C). The gate insulating film 5404 can be formed by a known method (sputtering, LPCVD, plasma CVD, etc.) in a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y), or in a laminate structure of these. For example, the insulating films 5427a and 5427b are formed on the surfaces of the semiconductor films 5403a and 5403b by oxidizing the semiconductor films 5403a and 5403b using Si by plasma treatment.
In the case where silicon oxide is formed as the insulating film 5427b, silicon oxide (SiOx) is formed as a gate insulating film over the insulating films 5427a and 5427b.

Next, by forming a gate electrode 5405 and the like on the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions can be manufactured (Figure 59 (D)).

When the end of the semiconductor film is tapered, the ends 5453a and 5453b of the channel region formed in part of the semiconductor film also become tapered, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, the end of the channel region is also oxidized or nitrided as a result, so that the effect on the semiconductor element can be reduced.

In FIG. 59, an example in which only the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment is shown. However, as shown in FIG. 57, the gate insulating film 540
It is also possible to oxidize or nitride the gate insulating film 5404 by performing plasma treatment on the semiconductor films 5403a and 5403b (FIG. 60B). In this case, the gate insulating film 5404 may be oxidized by performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOx) may be used for the semiconductor films 5403a and 5403b.
SiOxNy) (x>y) is formed, and silicon nitride oxide (Si
NxOy) (x>y) is formed.

In this way, by modifying the surface of the semiconductor film or gate insulating film by oxidizing or nitriding the semiconductor film or gate insulating film through plasma processing, it is possible to form a dense insulating film with good film quality. As a result, even when the insulating film is formed thin, defects such as pinholes can be prevented, and miniaturization and high performance of semiconductor elements such as transistors can be realized.

54, the semiconductor films 5403a and 5403b or the gate insulating film 5404 are oxidized or nitrided, but the layer to be oxidized or nitrided using the plasma treatment is not limited to this. For example, the substrate 5401 or the insulating film 5402 may be subjected to the plasma treatment, or the insulating film 5406 or the insulating film 5407 may be subjected to the plasma treatment.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 9)
In this embodiment, hardware for controlling the driving methods described in the first to sixth embodiments will be described.

A rough configuration diagram is shown in Fig. 61. A pixel portion 6104, a signal line driver circuit 6106, and a scanning line driver circuit 6105 are arranged on a substrate 6101. In addition, a power supply circuit, a precharge circuit, a timing generation circuit, and the like may be arranged. In addition, the signal line driver circuit 6106 and the scanning line driver circuit 6105 may not be arranged. In that case, the substrate 610
The IC may be formed on the substrate 6101.
Alternatively, the IC may be disposed on a connection board 6107 that connects the peripheral circuit board 6102 and the board 6101.

A signal 6103 is input to the peripheral circuit board 6102.
The signal 6103 is controlled to be stored in memories 6109, 6110, etc. If the signal 6103 is an analog signal, it is converted from analog to digital and then stored in the memories 6109, 6110, etc.
0. The controller 6108 then stores the data in the memory 6109,
10, etc., is used to output a signal to the substrate 6101.

In order to realize the driving methods described in the first to sixth embodiments, a controller 6108
It controls the order in which the subframes appear, etc., and outputs a signal to the substrate 6101.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 10)
In this embodiment, a configuration example of an EL module and an EL television receiver using the display device of the present invention will be described.

62 shows an EL module in which a display panel 6201 and a circuit board 6202 are combined. The display panel 6201 has a pixel portion 6203, a scanning line driver circuit 6204, and a signal line driver circuit 6205. The circuit board 6202 includes, for example, a control circuit 6206.
A display panel 6201 and a circuit board 6202 are formed on the display panel 6201.
are connected by a connection wiring 6208. An FPC or the like can be used for the connection wiring.

The control circuit 6206 is the same as the controller 6108 and the memory 6
It corresponds to 109, 6110, etc. The control circuit 6206 mainly controls the order in which the subframes appear.

In the display panel 6201, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed on a substrate using transistors, and some peripheral driver circuits (a driver circuit having a high operating frequency among a plurality of driver circuits) are formed on an IC chip, and the IC chip is mounted on the display panel 6201 by COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 6201 by TAB (Tape Automated Bonding) or the like.
) or a printed circuit board may be used to mount the display panel 6201 .

Furthermore, by using a buffer circuit to convert the impedance of signals set in the scanning lines and signal lines, the writing time for each row of pixels can be shortened, thereby making it possible to provide a high-definition display device.

In order to further reduce power consumption, a pixel section is formed on a glass substrate using transistors, and all signal line driving circuits are formed on an IC chip. The IC chip is then mounted on a COG (cobalt-on-glass) substrate.
The display device may be mounted on a IPS On Glass display panel.

For example, the entire screen of the display panel may be divided into several regions, and an IC chip on which some or all of the peripheral driving circuits (signal line driving circuits, scanning line driving circuits, etc.) are formed may be disposed in each region, and the IC chip may be mounted on the display panel by COG (Chip On Glass) or the like. The configuration of the display panel in this case is shown in FIG.

In FIG. 63, the entire screen is divided into four regions, and eight IC chips are used for driving the display panel. The display panel is configured as follows: a substrate 6310, a pixel portion 6311, FPCs 6312a to 6312b, and a display panel 631c.
2h, and IC chips 6313a to 6313h. Of the eight IC chips, 6313
A signal line driver circuit is formed in 6313a to 6313d, and a scanning line driver circuit is formed in 6313e to 6313h. By driving an arbitrary IC chip, it is possible to drive only an arbitrary screen area among the four screen areas. For example, IC chip 6
By driving only 313a and 6313e, it is possible to drive only the upper left area of the four screen areas, thereby making it possible to reduce power consumption.

An example of a display panel having another structure is shown in Fig. 64. The display panel in Fig. 64 includes a pixel portion 6421 in which a plurality of pixels 6430 are arranged, a scanning line driver circuit 6422 for controlling signals of a scanning line 6433, a signal line driver circuit 6423 for controlling signals of a signal line 6431, and a display panel having a display panel.
23. In addition, a monitor circuit 6424 for correcting a luminance change of a light-emitting element included in the pixel 6430 may be provided. The light-emitting element included in the pixel 6430 and the light-emitting element included in the monitor circuit 6424 have the same structure. The light-emitting element has a structure in which a layer containing a material that exhibits electroluminescence is sandwiched between a pair of electrodes.

At the periphery of the substrate 6420, there are an input terminal 6425 for inputting a signal from an external circuit to the scanning line driver circuit 6422, and an input terminal 6426 for inputting a signal from an external circuit to the signal line driver circuit 6423.
, and an input terminal 6429 for inputting a signal to the monitor circuit 6424 .

In order to make the light emitting element provided in the pixel 6430 emit light, it is necessary to supply power from an external circuit. The power supply line 6432 provided in the pixel portion 6421 is connected to an external circuit through an input terminal 6427. Since the power supply line 6432 generates resistance loss due to the length of the wiring to be drawn, it is preferable to provide the input terminal 6427 at a plurality of places in the periphery of the substrate 6420.
are provided at both ends of the substrate 6420 and arranged so that luminance unevenness is not noticeable within the surface of the pixel portion 6421. In other words, it prevents one side of the screen from being bright and the other side from being dark. In addition, the electrode of the light-emitting element having a pair of electrodes on the opposite side to the electrode connected to the power line 6432 is formed as a common electrode shared by multiple pixels 6430, and multiple terminals 6428 are provided to reduce the resistance loss of this electrode.

Such a display panel is particularly effective when the screen size is large, since the power supply lines are made of a low resistance material such as Cu. For example, the diagonal length is 340 mm for a 13-inch screen size, but is 1500 mm or more for a 60-inch screen size. In such a case, since the wiring resistance cannot be ignored, it is preferable to use a low resistance material such as Cu for the wiring. In addition, when considering wiring delay, signal lines and scanning lines may be formed in a similar manner.

An EL television receiver can be completed by using an EL module having the above-mentioned panel configuration. Fig. 65 is a block diagram showing the main components of an EL television receiver. A tuner 6501 receives a video signal and an audio signal. The video signal is amplified by a video signal amplifier circuit 6502.
The video signal is then processed by a video signal processing circuit 6503 which converts the output signal into a color signal corresponding to each of the colors red, green, and blue, and a control circuit 6206 which converts the video signal into an input specification for a drive circuit. The control circuit 6206 outputs signals to the scanning line side and the signal line side. In the case of digital drive, a signal division circuit 6207 may be provided on the signal line side to divide the input digital signal into M parts and supply them.

Of the signals received by the tuner 6501, the audio signal is sent to an audio signal amplifier circuit 6504, the output of which is supplied to a speaker 6506 via an audio signal processing circuit 6505. A control circuit 6507 receives control information on the receiving station (receiving frequency) and volume from an input unit 6508, and sends signals to the tuner 6501 and the audio signal processing circuit 6505.

A television set can be completed by incorporating the EL module into a housing. The EL module forms the display section. In addition, speakers, video input terminals, etc. are also provided as appropriate.

Of course, the present invention is not limited to television receivers, but can be used in a variety of devices, including personal computer monitors.
The present invention can be applied to a variety of applications, particularly as a large-area display medium, such as information display boards at railway stations and airports, and advertising display boards on the street.

In this way, by using the display device and the driving method thereof according to the present invention, it becomes possible to view clear images with reduced luminance variations.

In addition, this embodiment is an example of a case where the contents (or a part thereof) described in the other embodiments are embodied, a slightly modified example, a partially changed example, an improved example,
The following describes an example of a detailed description, an example of an application, an example of a related part, etc. Therefore, the contents described in the other embodiments can be freely applied to, combined with, or substituted for this embodiment.

In this embodiment, various figures have been used to describe the present invention.
(or a part of) the contents described in another figure (or a part of)
Furthermore, in the figures described above, by combining each part with another part, more figures can be constructed.

Similarly, the contents (or even a part of them) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or even a part of them) described in the figures of other embodiments. Furthermore, by combining each part of the figures of this embodiment with parts of other embodiments, even more figures can be configured.

(Embodiment 11)
Examples of electronic devices using the display device of the present invention include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, audio components, etc.), notebook personal computers, game devices, and portable information terminals (mobile computers, mobile phones, portable game machines, e-books, etc.).
An image reproducing device equipped with a storage medium (specifically, a Digital Versatile Digital
Examples of such electronic devices include a display device that can play back a storage medium such as a DVD (DVD) and display the image. Specific examples of such electronic devices are shown in FIG.

Fig. 66A shows a self-luminous display, which includes a housing 6601, a support stand 6602, a display portion 6603, a speaker portion 6604, a video input terminal 6605, and the like. The present invention can be used in the display device constituting the display portion 6603, and the present invention makes it possible to view a beautiful image with reduced luminance variation. Since the display is a self-luminous type, a backlight is not necessary, and the display portion can be thinner than a liquid crystal display. The display includes all display devices for displaying information, such as those for personal computers, those for receiving TV broadcasts, and those for displaying advertisements.

FIG. 66B shows a digital still camera, which includes a main body 6606, a display unit 6607, and an image receiving unit 6
608, operation keys 6609, an external connection port 6610, a shutter 6611, etc. The present invention can be used for a display device constituting the display portion 6607, and the present invention makes it possible to view a beautiful image with reduced luminance variation.

FIG. 66C shows a notebook personal computer, which includes a main body 6612, a housing 6613,
The display unit 6614 includes a keyboard 6615, an external connection port 6616, a pointing mouse 6617, and the like. The present invention can be used in a display device that constitutes the display unit 6614,
According to the present invention, it becomes possible to view clear images with reduced luminance variations.

66D shows a mobile computer, which includes a main body 6618, a display unit 6619, a switch 6620, an operation key 6621, an infrared port 6622, etc.
The present invention can be used in a display device constituting the LCD panel 9, and the LCD panel 9 can display clear images with reduced luminance variations.

Figure 66 (E) shows an image playback device (specifically, for example, a DVD playback device) equipped with a storage medium reading unit, and includes a main body 6623, a housing 6624, a display unit A 6625, a display unit B 6626, a storage medium (DVD, etc.) reading unit 6627, operation keys 6628, a speaker unit 6629, etc.
The display unit A6625 mainly displays image information, and the display unit B6626 mainly displays text information. The present invention can be used in the display device constituting the display unit A6625 and the display unit B6626, and the present invention makes it possible to view beautiful images with reduced luminance variation. Note that image reproducing devices equipped with a recording medium also include home game devices.

FIG. 66(F) shows a goggle-type display (head-mounted display),
The display device includes a display portion 6630, a display portion 6631, and an arm portion 6632. The present invention can be used in a display device constituting the display portion 6631, and the present invention allows a clear image to be viewed with reduced luminance variation.

FIG. 66G shows a video camera, which includes a main body 6633, a display section 6634, a housing 6635, an external connection port 6636, a remote control receiving section 6637, an image receiving section 6638, and a battery 6639.
, a voice input unit 6640, and operation keys 6641. The present invention can be used in the display device constituting the display unit 6634, and the present invention enables a clear image with reduced luminance variation to be viewed.

Fig. 66(H) shows a mobile phone, which includes a main body 6642, a housing 6643, a display unit 6644, an audio input unit 6645, an audio output unit 6646, operation keys 6647, an external connection port 6648, an antenna 6649, and the like. The present invention can be used in a display device constituting the display unit 6644. Note that the display unit 6644 can reduce current consumption of the mobile phone by displaying white characters on a black background. Furthermore, the present invention allows a beautiful image with reduced luminance variation to be viewed.

If a light-emitting material with high luminance is used, the light containing the output image information can be enlarged and projected using a lens or the like and used in a front or rear projector.

In recent years, the electronic devices are increasingly displaying information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, there are increasing opportunities to display moving image information. The response speed of the light-emitting material is very high, so that the light-emitting device is preferable for displaying moving images.

Furthermore, since light-emitting display devices consume power in the light-emitting parts, it is desirable to display information with as few light-emitting parts as possible. Therefore, when a light-emitting display device is used for a display section that mainly displays text information, such as a portable information terminal, particularly a mobile phone or an audio player, it is desirable to drive the display so that the text information is formed by the light-emitting parts against a background of non-light-emitting parts.

As described above, the present invention has a very wide range of application and can be used in electronic devices in a variety of fields. In addition, the electronic devices of this embodiment may use a display device having any of the configurations shown in Embodiments 1 to 10.

101 transistor 102 transistor 103 storage capacitor 104 scanning line 105 signal line 106 power supply line 107 capacitor line 108 light emitting element 123 insulating film 201 transistor 202 transistor 203 storage capacitor 204 scanning line 205 signal line 206 power supply line 207 capacitor line 208 light emitting element 301 transistor 302 transistor 303 transistor 304 transistor 305 transistor 306 storage capacitor 307 signal line 308 first scanning line 309 second scanning line 310 third scanning line 311 fourth scanning line 312 power supply line 313 power supply line 314 capacitor line 315 light emitting element 316 light emitting element 801 transistor 802 transistor 803 transistor 804 transistor 805 transistor 806 storage capacitor 807 signal line 808 first scanning line 809 second scanning line 810 Third scanning line 811 Fourth scanning line 812 Power supply line 813 Power supply line 814 Capacitor line 815 Light-emitting element 2101 Transistor 2102 Transistor 2103 Transistor 2104 Transistor 2105 Transistor 2106 Storage capacitor 2107 Signal line 2108 First scanning line 2109 Second scanning line 2110 Third scanning line 2111 Fourth scanning line 2112 Power supply line 2113 Power supply line 2115 Light-emitting element 2121 Transistor 2122 Transistor 2123 Transistor 2124 Transistor 2125 Transistor 2126 Storage capacitor 2128 First scanning line 2129 Second scanning line 2130 Third scanning line 2131 Fourth scanning line 2135 Light-emitting element 2149 Second scanning line 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Storage capacitor 2307 Signal line 2308 First scanning line 2309 Second scanning line 2310 Third scanning line 2311 Fourth scanning line 2312 Power supply line 2315 Light-emitting element 2321 Transistor 2322 Transistor 2323 Transistor 2324 Transistor 2325 Transistor 2326 Storage capacitor 2328 First scanning line 2329 Second scanning line 2330 Third scanning line 2331 Fourth scanning line 2335 Light-emitting element 2349 Second scanning line 2516 Transistor 2517 Fifth scanning line

Claims (6)

a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor is electrically connected to a fourth gate line different from the third gate line;
a gate of the second transistor is electrically connected to the fourth gate line;
When an L-level signal is input to the gate of the first transistor to turn the first transistor on,
An H-level signal is input to the gate of the second transistor to turn off the second transistor,
An H-level signal is input to the gate of the third transistor to turn the third transistor on,
An H-level signal is input to the gate of the fourth transistor to turn off the fourth transistor,
When the light emitting element emits light,
An H-level signal is input to the gate of the first transistor to turn off the first transistor,
An L-level signal is input to the gate of the second transistor to turn the second transistor on,
An L-level signal is input to the gate of the third transistor to turn off the third transistor,
A display device in which an L-level signal is input to the gate of the fourth transistor to turn the fourth transistor on. a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor is electrically connected to a fourth gate line different from the third gate line;
a gate of the second transistor is electrically connected to the fourth gate line;
When an L-level signal is input to the gate of the first transistor to turn the first transistor on,
An H-level signal is input to the gate of the second transistor to turn off the second transistor,
An H-level signal is input to the gate of the third transistor to turn the third transistor on,
An H-level signal is input to the gate of the fourth transistor to turn off the fourth transistor,
When the light emitting element emits light,
An H-level signal is input to the gate of the first transistor to turn off the first transistor,
An L-level signal is input to the gate of the second transistor to turn the second transistor on,
An L-level signal is input to the gate of the third transistor to turn off the third transistor,
An L-level signal is input to the gate of the fourth transistor to turn the fourth transistor on,
The third transistor includes an oxide semiconductor in a channel formation region. a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor is electrically connected to a fourth gate line different from the third gate line;
a gate of the second transistor is electrically connected to the fourth gate line;
the first transistor functions as a first switching element;
the second transistor functions as a second switching element;
the third transistor functions as a third switching element;
The fourth transistor functions as a fourth switching element. a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor is electrically connected to a fourth gate line different from the third gate line;
a gate of the second transistor is electrically connected to the fourth gate line;
the first transistor functions as a first switching element;
the second transistor functions as a second switching element;
the third transistor functions as a third switching element;
the fourth transistor functions as a fourth switching element;
The third transistor includes an oxide semiconductor in a channel formation region. a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the first transistor is electrically connected to a first gate line;
a gate of the second transistor electrically connected to a second gate line;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor electrically connected to the second gate line different from the third gate line; a first P-channel transistor, a second P-channel transistor, a third N-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a capacitance element, a light-emitting element, a signal line, and a power supply line;
one of a source and a drain of the first transistor is electrically connected to the signal line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
a gate of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitance element;
the other of the source and the drain of the fourth transistor is electrically connected to the light emitting element;
a gate of the first transistor is electrically connected to a first gate line;
a gate of the second transistor electrically connected to a second gate line;
a gate of the third transistor is electrically connected to a third gate line;
a gate of the fourth transistor is electrically connected to the second gate line different from the third gate line;
The third transistor includes an oxide semiconductor in a channel formation region.

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