JP7543882B2 - Optical Node Device - Google Patents

Description

The present invention relates to an optical node device.

Optical networks are used to support modern demands for high-speed, high-capacity telecommunications. These networks typically use a technique known as optical wavelength division multiplexing (WDM) to utilize as much of the optical spectrum as possible.

Many optical networks use optical node equipment that corresponds to branching points of the optical network. It is often desirable to use reconfigurable optical add/drop multiplexer (ROADM) devices with reconfigurable add/drop capabilities in the optical node equipment.

To realize a ROADM system, a wavelength selective switch (WSS) may be used for routing any wavelength channel. In the WSS, an optical beam deflection device such as a spatial light modulator may be used to select a wavelength for deflection to a desired output port. WSSs using reflective spatial light modulators are currently in use.

Patent No. 5733154

In the above-mentioned reflective spatial light modulator, it is desirable to be able to suppress burn-in in order to increase reliability.

In view of the above problems, the present invention aims to provide an optical node device that can increase reliability.

An optical node device according to one aspect of the present invention comprises an input/output unit having an input port for receiving incident light and an output port for emitting output light corresponding to each wavelength contained in the incident light; a wavelength disperser that spatially disperses light of each wavelength contained in the incident light according to each wavelength and emits the output light to the input/output unit; an optical coupler that focuses the light of each wavelength dispersed by the wavelength disperser onto a two-dimensional plane for each wavelength and emits the reflected light of each wavelength to the wavelength disperser; a spatial light modulator that is arranged at a position on the two-dimensional plane, has a plurality of pixels, and reflects the light of each wavelength focused by the optical coupler in a direction determined by routing for each wavelength by expressing gradation using the plurality of pixels; and a spatial light modulator drive unit that drives the plurality of pixels of the spatial light modulator. The gradation is formed by inputting normal gradation data to each of the plurality of pixels during one subframe period among a plurality of subframe periods obtained by dividing one frame period, and inputting inverted gradation data to each of the plurality of pixels during another subframe period by the spatial light modulator driving unit. Each of the plurality of pixels includes a first switching circuit that samples the normal gradation data or the inverted gradation data from a data line, a first signal holding circuit that holds the normal gradation data or the inverted gradation data sampled by the first switching circuit, a second switching circuit that samples the normal gradation data or the inverted gradation data held in the first signal holding circuit at a timing common to all of the plurality of pixels, and a second signal holding circuit that holds the normal gradation data or the inverted gradation data sampled by the second switching circuit for one subframe period and applies it to a reflective electrode of a liquid crystal display element. The spatial light modulator driving unit applies a positive/negative AC voltage to the liquid crystal of the liquid crystal display element by inverting the voltage of the common electrode of the liquid crystal display element at the timing, and supplies a voltage of an amplitude different from the amplitude between the normal gradation data and the inverted gradation data to the common electrode. The first switching circuit and the first signal holding circuit constitute a first dynamic random access memory. The second switching circuit and the second signal holding circuit constitute a first static random access memory. The first signal holding circuit is composed of a capacitance.

The present invention makes it possible to increase reliability.

FIG. 1 is a diagram showing a configuration of a wavelength selective switch array according to the first embodiment. FIG. 2 is a diagram showing a configuration of a wavelength selective switch array according to the first embodiment. FIG. 3 is a diagram showing a reflective liquid crystal display device of a wavelength selection array according to the first embodiment. FIG. 4 is a diagram showing the configuration of a reflective liquid crystal display device according to the second embodiment. FIG. 5 is a diagram showing a pixel configuration of a reflective liquid crystal display device according to the second embodiment. FIG. 6 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the third embodiment. FIG. 7 is a diagram showing a circuit configuration of a CMOS inverter. FIG. 8 is a diagram for explaining the magnitude relationship of the driving forces between the inverters. FIG. 9 is a timing chart showing the operation of the reflective liquid crystal display device according to the third embodiment. FIG. 10 is a diagram showing the relationship between the voltage applied to the liquid crystal and the gray scale value. FIG. 11 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the fourth embodiment. FIG. 12 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the fifth embodiment. FIG. 13 is a diagram showing a cross-sectional configuration of a pixel of a reflective liquid crystal display device according to the fifth embodiment. FIG. 14 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the sixth embodiment. FIG. 15 is a diagram showing a cross-sectional configuration of a pixel of a reflective liquid crystal display device according to the sixth embodiment. FIG. 16 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the seventh embodiment. FIG. 17 is a diagram showing a cross-sectional configuration of a pixel of a reflective liquid crystal display device according to the seventh embodiment.

The following describes in detail an embodiment of the present invention with reference to the drawings. Note that the present invention is not limited to the embodiment described below. In addition, the components in the following embodiment include those that are replaceable and easy for a person skilled in the art, or those that are substantially the same.

First Embodiment
1 and 2 are diagrams showing the configuration of a wavelength selective switch (WSS) array according to a first embodiment. Fig. 1 is a diagram showing the WSS array 10 viewed in a direction opposite to the x-axis direction. Fig. 2 is a diagram showing the WSS array 10 viewed in a direction opposite to the y-axis direction.

The WSS array 10 corresponds to an example of an "optical node device" in this disclosure.

The WSS array 10 of the present disclosure uses at least two WSSs in a single package. The WSS array 10 of the present disclosure allows for independent operation of each WSS in the WSS array 10 without the need for dedicated optical elements. Rather, many of the optical elements can be shared between the individual WSS devices, thus reducing cost and size. Such devices are ideally suited for use in modern communications networks, for example as reconfigurable optical add/drop multiplexers (ROADMs). Furthermore, an array having one or more coupled two WSSs may be ideally suited as a component in a branching node using a route and select (RS) architecture.

Referring to FIG. 1, the WSS array 10 includes two independent WSS devices WSS1 and WSS2, each of which may operate as an independent WSS device. In this disclosure, the term "independent" refers to the ability of WSS device WSS1 to independently process one or more WDM signals independent of WSS device WSS2, and vice versa. In this disclosure, the term "processing" is used broadly to include, for example, modulating, attenuating, blocking, redirecting, and/or switching individual wavelength channels that make up each WDM signal.

The WSS array 10 includes an input/output unit 11 and an optical system 12. The optical system 12 is configured to beam shape each WDM signal beam. The optical system 12 is also configured to spectrally disperse (demultiplex) each WDM signal into its constituent wavelength channels (or groups of wavelength channels). The optical system 12 is further configured to spectrally combine (multiplex) the dispersed wavelength channels (or groups of wavelength channels) into one or more WDM signals. The WSS array 10 further includes a reflective liquid crystal display 13. The reflective liquid crystal display 13 is configured to optically process the dispersed wavelength channels, for example to redirect individual wavelength channels along a predetermined path within the WSS array 10.

The reflective liquid crystal display device 13 corresponds to an example of a "spatial light modulator" in this disclosure. The reflective liquid crystal display device 13 will be described in detail in the second embodiment and thereafter.

The WSS array 10 uses a symmetrical architecture about an axis of symmetry 14, allowing a single optical system 12 and reflective liquid crystal display 13 to be shared among several WSS devices of the WSS array 10, in this example WSS devices WSS1 and WSS2. However, while WSS devices WSS1 and WSS2 may share many of the same optical components, the architecture of the first embodiment allows the WSS devices WSS1 and WSS2 of the WSS array 10 to be independently controllable devices. Thus, the WSS array 10 of the first embodiment is smaller and less optically complex. In addition, the WSS array 10 provides a multi-WSS device that retains the independent processing capabilities inherent in larger and more costly devices.

In the present disclosure, the input/output unit 11 may include several input and output ports for transmitting one or more optical WDM signals. For example, the device may include several optical fibers, planar waveguides, etc., any of which may be assigned as an input or output port. In the first embodiment described below, the input or output port is implemented as an optical fiber 15. However, any other type of port may be used without departing from the scope of the present invention.

The input/output unit 11 includes an input/output unit 11-1 for the WSS device WSS1. The input/output unit 11-1 includes an input fiber 1 and several output fibers 1a, 1b, ..., 1n, where n is a natural number. The input/output unit 11 further includes an input/output unit 11-2 for the WSS device WSS2. The input/output unit 11-2 includes an input fiber 2 and several output fibers 2a, 2b, ..., 2n, where n is a natural number. Thus, FIG. 1 shows an example of an array of two 1×N WSS devices including the WSS devices WSS1 and WSS2. In other words, the input/output unit 11 of the WSS array 10 includes an array of input fiber 1, output fibers 1a, 1b, ..., 1n, input fiber 2, output fibers 2a, 2b, ..., 2n forming an optical fiber stack arranged along the y-axis direction.

The input/output section 11 further includes an array of collimating lenses 16 in the form of a microlens array. The array of collimating lenses 16 is disposed in front (z-direction) of a corresponding array of optical power elements, e.g., optical fibers, each of which is an output and/or an input. In the present disclosure, the collimating lenses 16 include any optical element capable of directing and/or changing the direction of a light beam and/or focusing a set of light rays. A first group including the input fiber 1 and the output fibers 1a, 1b, ..., 1n is combined with a first group of mating collimating lenses 16 to form the input/output section 11-1 of the WSS device WSS1. A second group including the input fiber 2 and the output fibers 2a, 2b, ..., 2n is combined with a second group of mating collimating lenses 16 to form the input/output section 11-2 of the WSS device WSS2. FIG. 1 shows the WSS array 10 implemented as a microlens array, but other types of WSS arrays may be used without departing from the scope of the present invention.

In the present disclosure, for example, the optical axes of the first group of optical fibers are displaced relative to the optical axes of the first group of collimating lenses 16. This relative misalignment between the array of input and output ports and the array of collimating lenses 16 causes the first group of input and output beams to enter (or exit) the optical system 12 at an angle θ1 relative to the axis of symmetry 14. This causes the group of input and output beams from the WSS device WSS1 to be directed generally along a downward angle θ1 (opposite the y-axis direction).

Similarly, the optical axes of the fibers of the second group are displaced relative to the optical axes of the collimating lenses 16 of the second group. The input and output beams of the second group are directed into (or out of) the optical system 12 at an angle θ2 relative to the axis of symmetry 14. This causes the group of input and output beams from the WSS device WSS2 to be directed generally along an angle θ2 in the upward direction (y-axis direction).

As previously mentioned, the illustrative example shown in FIG. 1 is a WSS array 10 using two 1×N WSSs, namely WSS devices WSS1 and WSS2. Thus, in the example shown in FIG. 1, WSS device WSS1 includes one input fiber 1 through which a WDM signal beam 31 is launched into the device, and one input fiber 2 through which a WDM signal beam 32 is launched into the device. The input fiber/output fiber configuration shown here is shown for illustrative purposes only and is not intended to limit the scope of the invention. Rather, any useful input port/output port combination may be used without departing from the scope of the invention.

The WDM signal beam 31 is launched from the input fiber 1 into the device and travels through the optics 12 in the y-z plane at an angle θ1 after passing through the collimating lens 16. The WDM signal beam 31 is then incident on the lens 21 which shapes the WDM signal beam 31 in the x-direction. In one example, the lens 21 may be a cylindrical lens with a cylindrical axis extending along the y-direction. Therefore, the lens 21 does not affect the WDM signal beam 31 when viewed from the perspective shown in FIG. 1.

After passing through lens 21, the WDM signal beam 31 enters lens 22. In the example shown in FIG. 1, lens 22 may be a cylindrical lens with a cylindrical axis extending along the x-direction. The action of lens 22 depends on the reflective liquid crystal display device 13 being positioned in the focal plane of lens 22. Furthermore, lens 22 has its center (cylindrical axis) on the axis of symmetry 14. Since the reflective liquid crystal display device 13 is positioned in the focal plane of lens 22, any set of parallel light rays entering lens 22 will be focused at the same height on the reflective liquid crystal display device 13. Conversely, any set of light rays starting from the same height on the reflective liquid crystal display device 13 will exit lens 22 as a set of parallel light rays.

For example, as shown in FIG. 1, any incident beam (e.g., WDM signal beam 31) traveling along an angle θ1 is directed by lens 22 toward y-axis position LC1 on reflective LCD 13. Conversely, a group of light rays 41 originating from position LC1 on reflective LCD 13 exit lens 22 as parallel light rays traveling at the same angle θ1 as shown in FIG. 1. Similarly, any incident beam (e.g., WDM signal beam 32) traveling along an angle θ2 is directed by lens 22 toward y-axis position LC2 on reflective LCD 13. Conversely, a group of light rays 42 originating from position LC2 on reflective LCD 13 exit lens 22 as parallel light rays traveling at the same angle θ2 as shown in FIG. 1.

Returning to the propagation of the WDM signal beam 31 through the optical system 12, after passing through the lens 22, the WDM signal beam 31 passes through a dispersive element 24, which angularly disperses the wavelength channels of the WDM signal beam 31, as shown in Figures 1 and 2. In this disclosure, the dispersive element 24 may be a transmissive optical component, such as a diffraction grating, a prism, or the like.

The dispersion element 24 corresponds to an example of a "wavelength disperser" in this disclosure.

After passing through the dispersive element 24, the dispersed wavelength channels pass through a lens 23 that focuses the dispersed wavelength channels onto the surface of the reflective liquid crystal display device 13 for each wavelength channel, as shown in Figures 1 and 2. In the present disclosure, the lens 23 may be a cylindrical lens.

Lens 23 corresponds to an example of an "optical coupler" in this disclosure.

The reflective liquid crystal display 13 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator. The two-dimensional pixelated optical element may reflect or redirect one or more of the dispersed wavelength channels so that one or more of the dispersed wavelength channels are routed to any one of the output fibers, as described in more detail below.

For the WSS device WSS1, according to the present disclosure, since there is a lens 22, all of the light rays starting from the position LC1 on the reflective liquid crystal display 13 are output from the lens 22 along the angle θ1 as shown in FIG. 1. However, all of the light rays starting from the position LC1 on the reflective liquid crystal display 13 will be displaced relative to each other by an amount depending on the deflection angle from the reflective liquid crystal display 13. Thus, if the deflection angle is appropriately set, the reflected output light rays can be routed to any of the output fibers 1a, 1b, ..., 1n. Here, the reflected output light rays are, for example, reflected output light rays corresponding to a group of light rays 41, each of which may include one or more of the wavelength channels of the WDM signal beam 31. Furthermore, in the present disclosure, since each of the collimating lenses 16 is displaced by the same amount relative to its corresponding output fiber, the individual output beams can be recombined into their respective output fibers with improved efficiency.

Similarly, for the WSS device WSS2, according to the present disclosure, since there is a lens 22, all of the light rays starting from the position LC2 on the reflective liquid crystal display 13 are output from the lens 22 along the angle θ2 as shown in FIG. 1. However, all of the light rays starting from the position LC2 on the reflective liquid crystal display 13 are displaced relative to each other by an amount depending on the deflection angle from the reflective liquid crystal display 13. Thus, when the deflection angle is appropriately set, the reflected output light rays can be routed to any of the output fibers 2a, 2b, ..., 2n. Here, the reflected output light rays are, for example, reflected output light rays corresponding to a group of light rays 42, each of which may include one or more of the wavelength channels of the WDM signal beam 32. Furthermore, in the present disclosure, since each of the collimating lenses 16 is displaced by the same amount relative to its corresponding output fiber, the individual output beams can be recombined into their respective output fibers with improved efficiency.

Therefore, the combination of the input/output section 11 and the lens 22 sends out a given set of beams along a given angle (e.g., angle θ1 for WSS device WSS1, angle θ2 for WSS device WSS2). The combination of the input/output section 11 and the lens 22 then results in a WSS array device that directs these beams toward positions (positions LC1 and LC2) on the reflective liquid crystal display 13 that depend only on the input angle. Thus, the WSS array 10 allows two sets of WDM signal beams 31 and 32 from WSS devices WSS1 and WSS2, or rays 41 and 42 to WSS devices WSS1 and WSS2, to share the same optical system 12 and reflective liquid crystal display 13. Meanwhile, the WSS array 10 simultaneously preserves the ability of the WSS array to process individual wavelength channels separately.

Referring to FIG. 2, the stack of fibers and microlenses that make up the input/output section 11 is viewed from the top of the fiber stack, so that only the input fiber 1 is visible along with its corresponding collimating lens 16. The following description focuses on WSS device WSS1, but due to the symmetry of the system, exactly the same description applies to WSS device WSS2.

As mentioned above, for WSS device WSS1, the WDM signal beam 31 is launched into the system via input fiber 1. In FIG. 2, the angle θ1 is not visible because it is directed into the page. In this disclosure, the WDM signal beam 31 includes several wavelength channels, which have a wavelength range from a longest wavelength λ1 to a shortest wavelength λn. In some examples, the number of wavelength channels may be higher, for example 96 wavelength channels with 50 GHz or 100 GHz spacing on a fixed grid. In other examples, the device may be used in an adaptive grid system, for example using a frequency spacing of 12.5 GHz, and having 97 or more wavelength channels, for example 130 or more wavelength channels.

The WDM signal beam 31 is first incident on the lens 21. The lens 21 functions to expand the beam to a diameter suitable for achieving a desired beam size on the dispersive element 24. For example, the collimating lens 16 and the lens 21 may function as a beam expansion telescope. In the present disclosure, the dispersive element 24 functions to angularly disperse the wavelength channels of the WDM signal beam 31 in the x-axis direction, as shown in FIG. 2. Each of the wavelength channels 51 to 5n is angularly dispersed in the x-axis direction by the dispersive element 24 and then focused on the surface of the reflective liquid crystal display device 13 by the lens 23. As a result, the wavelength channels 51 to 5n are spatially dispersed in the wavelength dispersion direction (x-axis direction) on the reflective liquid crystal display device 13 according to their wavelengths.

Figure 3 is a diagram showing a reflective liquid crystal display device of a WSS array according to the first embodiment. Figure 3 shows the reflective liquid crystal display device 13 as viewed from the z-axis direction.

An example of the distribution of wavelength channels on the surface of the reflective liquid crystal display 13 is shown more clearly in FIG. 3. More generally, the wavelength channels may be arranged on the two-dimensional surface of the reflective liquid crystal display 13 as long strips or elliptical spots. In brief, the wavelength channels are processed as discrete wavelength signals that can be acted on independently by the reflective liquid crystal display 13. However, in the present disclosure, the reflective liquid crystal display 13 need not be limited to acting on individual wavelength channels, but may act on groups of wavelength channels. Furthermore, as shown in FIG. 3, the wavelength channels or groups of wavelength channels need not have a fixed bandwidth themselves, because the reflective liquid crystal display 13 may be implemented as a spatial light modulator that is dynamically and fully reconfigurable. Thus, the present disclosure may be implemented in current fixed grid architectures and/or in current or future developed adaptive grid architectures.

2, the reflective liquid crystal display 13 selectively redirects one or more of the wavelength channels 51 to 5n in a certain direction. The reflective liquid crystal display 13 may then redirect the selected one or more of the wavelength channels 51 to 5n to ultimately one or more output ports (e.g., one or more output fibers (see FIG. 1) that are beyond the page of FIG. 2). In the case shown in FIG. 2, the redirection achieved by the reflective liquid crystal display 13 is along an angle that lies in a plane perpendicular to the page (y-z plane). The wavelength channels 51 to 5n are redirected, for example, as shown and described in more detail above with reference to FIG. 1. After being reflected by the reflective liquid crystal display 13, the redirected wavelength channels 51 to 5n re-enter the lens 23 and are further redirected to the dispersive element 24 where they are recombined. For example, those wavelength channels 51 to 5n that are redirected along the same angle are recombined into a single beam that is then redirected along a direction that may enable output of the processed signal at one of the output ports.

For example, consider a WDM signal beam 31 that includes three WDM channels with wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3, respectively. In the example shown in FIG. 1, the WDM signal beam 31 enters the system at an angle θ1. Furthermore, the WDM signal beam 31 traveling at angle θ1 passes through the center of the lens 22 and is not deflected away from the angle θ1. After passing through the dispersive element 24, the three wavelength channels of the WDM signal beam 31 are angularly dispersed in an orthogonal plane (the x-z plane), while all of the angularly dispersed channels still travel at the angle θ1. These three dispersed wavelength channels are then focused by the lens 23 at different positions on the reflective liquid crystal display device 13, as shown in FIG. 3.

Regarding the routing function of the device, several different routing combinations are possible here. Consider, for example, the case where all three wavelength channels are desired to be routed to the output fiber 1n shown in FIG. 1. The corresponding part of the reflective liquid crystal display 13 deflects each of the wavelength channels of wavelengths λ1, λ2 and λ3 so that each of the wavelength channels of wavelengths λ1, λ2 and λ3 returns along one of the light rays 41 shown in FIG. 1. The effect of the dispersive element 24 on the return path for these wavelength channels is to recombine (multiplex) each of the wavelength channels into the same beam currently propagating. This combined beam is then redirected by the lens 22 with an angle θ1 to propagate along the output beam 31c now displaced from the WDM signal beam 31. The effect of the collimating lens 16 is to couple the recombined and redirected output beam 31c into the output fiber 1n. Thus, in this mode of operation, the effect of WSS device WSS1 is to pass all three wavelength channels of WDM signal beam 31 from input fiber 1 to output fiber 1n.

In another example, it may be desirable to route some of the wavelength channels separately to different output fibers. For example, in some cases, the reflective liquid crystal display 13 deflects the wavelength channel with wavelength λ1 along output beam 31a, the wavelength channel with wavelength λ2 along output beam 31b, and the wavelength channel with wavelength λ3 along output beam 31c. Again, the function of the dispersive element 24 is to redirect each of these output beams. However, in this case, rather than recombining the output beams into a single beam, the dispersive element 24 creates three output beams that fan out. Furthermore, because each of these output beams originates from the same y-axis location LC1 on the reflective liquid crystal display 13, the output beams emerge from the lens 22 as a set of parallel rays propagating along the same angle θ1 as the original WDM signal beam 31. However, because each output beam enters the lens 22 at a different height (different y-axis location), the output beams will be displaced from each other. Thus, for example, the wavelength channel of wavelength λ1 propagates along output beam 31a, the wavelength channel of wavelength λ2 propagates along output beam 31b, and the wavelength channel of wavelength λ3 propagates along output beam 31c. Thus, in this configuration, the function of WSS device WSS1 is to route the wavelength channel of wavelength λ1 from input fiber 1 to output fiber 1a. Also, the function of WSS device WSS1 is to route the wavelength channel of wavelength λ2 from input fiber 1 to output fiber 1b. Also, the function of WSS device WSS1 is to route the wavelength channel of wavelength λ3 from input fiber 1 to output fiber 1n.

In view of the above, it is clear that the WSS array 10 of the present disclosure allows any wavelength channel of the WDM signal beam to be routed to any of the output fibers as desired. Furthermore, due to the symmetry of the system shown in FIG. 1, the above description also applies to routing the WDM signal beam 32 using the WSS device WSS2 as well. This is because the dispersed wavelength channels of the WSS devices WSS1 and WSS2 are ultimately focused onto different portions of the reflective liquid crystal display device 13, respectively, as shown in FIG. 3. Furthermore, while the examples shown in FIGS. 1-3 use one input port and n output ports, it will be understood that the output ports can be reconfigured as input ports and vice versa. Furthermore, any number of input and output ports can be used without departing from the scope of the present invention. Similarly, while the examples explicitly shown in FIGS. 1-3 are WSS array 10 using two WSS devices WSS1 and WSS2, any number of WSS devices can be used without departing from the scope of the present invention. For example, if the input/output section 11 is designed to use four separate launch angles, the WSS array 10 may provide four independent WSS devices.

Second Embodiment
FIG. 4 is a diagram showing the configuration of a reflective liquid crystal display device according to the second embodiment.

The reflective LCD device 13 uses a subframe drive method as a grayscale display method. In the subframe drive method, which is a type of time-axis modulation method, a predetermined period (for example, one frame period, which is the display unit of one image in the case of a moving image) is divided into multiple subframe periods, and pixels are driven with a combination of subframes according to the grayscale to be displayed. The grayscale to be displayed is determined by the proportion of the pixel drive period that occupies the predetermined period, and this proportion is determined by the combination of subframes.

The reflective liquid crystal display device 13 includes an image display section 61 in which a number of pixels Pix are regularly arranged, a timing generator 62, a vertical shift register 63, a data latch circuit 64, and a horizontal driver 65. The horizontal driver 65 includes a horizontal shift register 65a, a latch circuit 65b, and a level shifter/pixel driver 65c.

The timing generator 62, the vertical shift register 63, the data latch circuit 64, and the horizontal driver 65 correspond to an example of the "spatial light modulator driver" of this disclosure.

m (m is a natural number of 2 or more) row scanning lines g1 to gm extend in the row direction (x direction), and one end of each is connected to the vertical shift register 63. In addition to the row scanning lines g1 to gm, inverted row scanning lines gb1 to gbm may also be provided. n (n is a natural number of 2 or more) column data lines d1 to dn extend in the column direction (y direction), and one end of each is connected to the level shifter/pixel driver 65c. In addition to the column data lines d1 to dn, inverted column data lines db1 to dbn may also be provided.

The image display unit 61 has a plurality of pixels Pix provided at each intersection of row scanning lines g1 to gm and column data lines d1 to dn. In other words, the plurality of pixels Pix are arranged in a two-dimensional matrix.

All pixels Pix in the image display unit 61 are commonly connected to a trigger line trig, one end of which is connected to the timing generator 62. In addition to the trigger line trig, an inverted trigger line trigb may also be provided.

The normal (non-inverted) row scan pulses transmitted by row scan lines g1 to gm and the inverted row scan pulses transmitted by inverted row scan lines gb1 to gbm always have an inverted logical value relationship (complementary relationship).

In addition, the normal (non-inverted) data transmitted by the column data lines d1 to dn and the inverted data transmitted by the inverted column data lines db1 to dbn are always in an inverse logical value relationship (complementary relationship).

In addition, the forward trigger pulse TRIG transmitted by the trigger line trig and the inverted trigger pulse TRIGB transmitted by the inverted trigger line trigb always have an inverse logical value relationship (complementary relationship).

The timing generator 62 receives external signals such as a vertical synchronization signal Vst, a horizontal synchronization signal Hst, and a basic clock signal CLK as input signals from the higher-level device 71. Based on the external signals, the timing generator 62 generates internal signals such as an AC signal FR, a vertical start pulse VST, a horizontal start pulse HST, clock signals VCK and HCK, a latch pulse LT, a forward trigger pulse TRIG, and an inverted trigger pulse TRIGB.

The AC signal FR is a signal whose polarity is inverted every subframe, and is supplied to the common electrode of the liquid crystal element in the pixel Pix that constitutes the image display unit 61 as a common electrode voltage Vcom, which will be described later. The vertical start pulse VST is a pulse signal that is output at the start timing of each subframe, which will be described later, and this vertical start pulse VST controls the switching of subframes. The horizontal start pulse HST is a pulse signal that is output at the start timing of input to the horizontal shift register 65a. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 63, and the vertical shift register 63 performs a shift operation at the timing of the clock signal VCK. The clock signal HCK is a shift clock in the horizontal shift register 65a, and is a signal for shifting data in a 32-bit width.

The latch pulse LT is a pulse signal that is output when the horizontal shift register 65a finishes shifting data for one horizontal row of pixels. The timing generator 62 supplies the normal trigger pulse TRIG through the trigger line trig and the inverted trigger pulse TRIGB through the inverted trigger line trigb to all pixels Pix in the image display unit 61. The normal trigger pulse TRIG and the inverted trigger pulse TRIGB are output immediately after sequentially writing data to the first signal holding circuit (described later) in each pixel Pix in the image display unit 61 during the subframe period. The normal trigger pulse TRIG and the inverted trigger pulse TRIGB are signals for transferring data in the first signal holding circuit (described later) of all pixels Pix in the image display unit 61 to the second signal holding circuit (described later) in the same pixel Pix at once during the output subframe period.

The vertical shift register 63 transfers the vertical start pulse VST, which is supplied at the beginning of each subframe, in accordance with the clock signal VCK. The vertical shift register 63 also supplies forward row scanning pulses to the row scanning lines g1 to gm and reverse row scanning pulses to the reverse row scanning lines gb1 to gbm in a sequential and exclusive manner in units of 1H. In one frame period, the vertical shift register 63 supplies forward row scanning pulses to all row scanning lines g1 to gm and reverse row scanning pulses to all reverse row scanning lines gb1 to gbm. As a result, in one frame period, the row scanning lines g and reverse row scanning lines gb are selected one by one in units of 1H in the image display section 61 from the top row scanning line g1 and reverse row scanning line gb1 to the bottom row scanning line gm and reverse row scanning line gbm.

The data latch circuit 64 latches the 32-bit data divided for each subframe, which is supplied from an external circuit (not shown), based on the basic clock signal CLK from the upper device 71. The data latch circuit 64 then outputs the latched data to the horizontal shift register 65a in synchronization with the basic clock signal CLK. In the second embodiment, the reflective liquid crystal display device 13 divides one frame of the video signal into a plurality of subframes each having a display period shorter than one frame period of the video signal, and performs gradation display by combining the subframes. Therefore, the external circuit converts the gradation data indicating the gradation of each pixel of the video signal into 1-bit subframe data for each subframe for displaying the gradation of each pixel in the entire plurality of subframes. The external circuit then further aggregates the subframe data for 32 pixels in the same subframe, and supplies it to the data latch circuit 64 as the 32-bit data.

When viewed as a processing system for 1-bit serial data, the horizontal shift register 65a starts shifting in response to a horizontal start pulse HST supplied from the timing generator 62 at the beginning of 1H. The horizontal shift register 65a then shifts the 32-bit data supplied from the data latch circuit 64 in synchronization with the clock signal HCK. The latch pulse LT is supplied from the timing generator 62 when the horizontal shift register 65a has finished shifting n bits of data, which is the same as the number of pixels n in one row of the image display unit 61. The latch circuit 65b latches n bits of data (i.e., subframe data for n pixels in the same row) supplied in parallel from the horizontal shift register 65a in accordance with the latch pulse LT, and outputs the data to the level shifter of the level shifter/pixel driver 65c. When the data transfer to the latch circuit 65b is completed, the horizontal start pulse HST is output again from the timing generator 62, and the horizontal shift register 65a resumes shifting the 32-bit data from the data latch circuit 64 in accordance with the clock signal HCK.

The level shifter in the level shifter/pixel driver 65c shifts the signal level of the n subframe data corresponding to the n pixels in one row, which are latched and supplied by the latch circuit 65b, to the liquid crystal drive voltage amplitude. The pixel driver in the level shifter/pixel driver 65c outputs the level-shifted n subframe data corresponding to the n pixels in one row in parallel to the n column data lines d1 to dn.

The horizontal driver 65 performs, in parallel, the output of data for the pixel row to which data is currently written within 1H and the shifting of data for the pixel row to which data is to be written within the next 1H. During a certain horizontal scanning period, n subframe data for one row that have been latched are output in parallel and simultaneously as data signals to n column data lines d1 to dn.

The n pixels Pix in one row selected by the forward row scan pulse from the vertical shift register 63 sample the n subframe data for one row output simultaneously from the level shifter/pixel driver 65c via the n column data lines d1 to dn. Then, the n pixels Pix in one row write the sampled n subframe data for one row to the first signal holding circuit (described later) in each pixel Pix.

Figure 5 shows the pixel configuration of a reflective LCD device according to the second embodiment.

The pixel Pix is disposed at the intersection of the row scanning line g and the column data line d. The pixel Pix includes a first memory 81 and a second memory 82, each of which stores 1-bit gradation data (pixel data). The first memory 81 includes a switch 81a and a first signal holding circuit 81b. The second memory 82 includes a switch 82a and a second signal holding circuit 82b.

The pixel Pix includes a liquid crystal display element LC. The liquid crystal display element LC has a liquid crystal LCM sandwiched between a reflective electrode PE and a common electrode CE arranged opposite each other. The common electrode CE is, for example, formed on the opposing substrate of the reflective liquid crystal display device 13, but the present disclosure is not limited thereto.

The column data lines d are connected to a horizontal driver 65 (see FIG. 4). The horizontal driver 65 changes the drive timing to drive a specific column data line d. The row scanning lines g are connected to a vertical shift register 63 (see FIG. 4). The vertical shift register 63 changes the drive timing to drive a specific row scanning line g.

When a positive row scanning pulse is supplied to the row scanning line g, the switch 81a is turned on. At this time, the grayscale data supplied from the column data line d is written to the first signal holding circuit 81b via the switch 81a. When a positive trigger pulse TRIG is supplied to the trigger line trig, the switch 82a is turned on. At this time, the grayscale data held in the first signal holding circuit 81b is transferred to the second signal holding circuit 82b via the switch 82a. The grayscale data transferred to the second signal holding circuit 82b is supplied to the reflective electrode PE of the liquid crystal display element LC.

When a pixel Pix at a specific intersection is selected by the column data line d and row scanning line g, 1 bit of gradation data is written to the first memory 81 in the pixel Pix. This is repeated for all pixels Pix with different timing, so that 1 bit of gradation data is written to all pixels Pix. After that, a forward trigger pulse TRIG is supplied to a trigger line trig commonly connected to all pixels Pix, so that the gradation data held in the first memory 81 in all pixels Pix is transferred to a second memory 82. A reflective electrode PE is connected to the second memory 82, and the gradation data held in the second memory 82 is applied to the liquid crystal display element LC.

When the transfer of the gradation data from the first memory 81 to the second memory 82 is completed, the supply of the forward trigger pulse TRIG ends, causing a discontinuity between the first memory 81 and the second memory 82. Then, 1 bit of gradation data is written again to the first memory 81 of all pixels Pix. While the gradation data is being written to the first memory 81, the gradation data held in the second memory 82 continues to be applied to the liquid crystal display element LC.

The grayscale data will be explained. First, the normal subframe grayscale data is written to all pixels Pix, and the liquid crystal display element LC performs display based on the normal subframe grayscale data. Next, the inverted grayscale data is written to the first memory 81 of all pixels Pix. When the writing of the inverted grayscale data to the first memory 81 is completed, a normal trigger pulse TRIG is supplied, and the inverted grayscale data is transferred to the second memory 82 of all pixels Pix at once. Then, the liquid crystal display element LC performs display based on the inverted grayscale data. At this timing, the common electrode voltage Vcom supplied to the common electrode CE of the liquid crystal display element LC is inverted. The voltage relationship between the inverted grayscale data and the common electrode voltage Vcom is the opposite voltage compared to when the normal subframe grayscale data is applied to the liquid crystal display element LC. In other words, the normal subframe grayscale data and the inverted grayscale data are input sequentially to the pixels Pix, and the liquid crystal display element LC can perform positive and negative AC driving. This makes it possible to realize a highly reliable reflective LCD device 13 without burn-in of the LCD element LC.

According to the configuration of the pixel Pix, the time for writing gradation data to the first memory 81 of the pixel Pix can be separated from the time for applying gradation data to the reflective electrode PE of the liquid crystal display element LC. In other words, the gradation data written to the first memory 81 during the gradation data writing time is not applied to the liquid crystal display element LC at the time when it is written to the first memory 81. Therefore, the voltage relationship between the voltage of the reflective electrode PE and the common electrode voltage Vcom does not collapse during the writing of gradation data to the first memory 81. Therefore, as in the conventional case, it is not necessary to set the reflective electrode PE and the common electrode CE to the same potential and turn off the liquid crystal display element LC during the gradation data writing time. In this way, it is possible to eliminate the display loss time of the liquid crystal display element LC during the gradation data writing time, so that a high-performance reflective liquid crystal display device 13 with good gradation can be provided. In addition, the constraint that the liquid crystal display element LC cannot display during the gradation data writing time is eliminated. Therefore, it is possible to realize a high-performance reflective LCD device 13 without sacrificing gradation, even for displays with a large number of pixels, such as FHD (1920 x 1080) or 4K2K.

Third Embodiment
FIG. 6 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the third embodiment.

The column data line d and the inverted column data line db extend in the column direction (y direction) with one end each connected to the level shifter/pixel driver 65c (see FIG. 4). The column data line d and the inverted column data line db are any pair of n pairs of column data lines in total, where one pair is a column data line dj for normal subframe gradation data and an inverted column data line dbj for inverted gradation data. The pixel Pix1 is provided at the intersection of any pair of the column data line d and the inverted column data line db and any row scanning line g.

Pixel Pix1 includes a first memory 91, a second memory 92, and a liquid crystal display element LC. The first memory 91 includes switches SW11a and SW11b, and a first signal holding circuit SM11. The second memory 92 includes switches SW12a and SW12b, and a second signal holding circuit SM12.

In pixel Pix1, each of the first memory 91 and the second memory 92 is composed of a static random access memory (SRAM).

The switches SW11a and SW11b correspond to an example of a "first switching circuit" in the present disclosure. The first signal holding circuit SM11 corresponds to an example of a "first signal holding circuit" in the present disclosure. The first memory 91 corresponds to an example of a "first static random access memory" in the present disclosure. The switches SW12a and SW12b correspond to an example of a "second switching circuit" in the present disclosure. The second signal holding circuit SM12 corresponds to an example of a "second signal holding circuit" in the present disclosure. The second memory 92 corresponds to an example of a "second static random access memory" in the present disclosure.

The switch SW11a is composed of an N-channel MOS (Metal Oxide Semiconductor) (hereinafter, NMOS) transistor with a gate connected to the row scanning line g, a drain connected to the column data line d, and a source connected to one input terminal of the first signal holding circuit SM11. The switch SW11b is composed of an NMOS transistor with a gate connected to the row scanning line g, a drain connected to the inverted column data line db, and a source connected to the other input terminal of the first signal holding circuit SM11.

The first signal holding circuit SM11 is a self-holding memory composed of two inverters INV1 and INV2, one of which has an output terminal connected to the input terminal of the other. The input terminal of the inverter INV1 is connected to the output terminal of the inverter INV2, the source of the NMOS transistor constituting the switch SW11a, and the switch SW12a. The input terminal of the inverter INV2 is connected to the output terminal of the inverter INV1, the source of the NMOS transistor constituting the switch SW11b, and the switch SW12b.

The switch SW12a is configured as an NMOS transistor with a gate connected to the trigger line trig, a drain connected to the connection point between the first signal holding circuit SM11 and the switch SW11a, and a source connected to one input terminal of the second signal holding circuit SM12. The switch SW12b is configured as an NMOS transistor with a gate connected to the trigger line trig, a drain connected to the connection point between the first signal holding circuit SM11 and the switch SW11b, and a source connected to the other input terminal of the second signal holding circuit SM12.

The second signal holding circuit SM12 is a self-holding memory composed of two inverters INV3 and INV4, one of which has an output terminal connected to the input terminal of the other. The input terminal of the inverter INV3 is connected to the output terminal of the inverter INV4, the source of the NMOS transistor that constitutes the switch SW12a, and the reflective electrode PE. The input terminal of the inverter INV4 is connected to the output terminal of the inverter INV3 and the source of the NMOS transistor that constitutes the switch SW12b.

Each of the inverters INV1, INV2, INV3, and INV4 is exemplified by a CMOS (Complementary Metal Oxide Semiconductor) inverter configuration.

Figure 7 is a diagram showing the circuit configuration of a CMOS inverter. The source of the PMOS transistor Ptr is connected to the power supply voltage VDD. The drain of the PMOS transistor Ptr is connected to the drain of the NMOS transistor Ntr. The source of the NMOS transistor Ntr is connected to the reference voltage GND. The gates of the PMOS transistor Ptr and NMOS transistor Ntr are connected to each other, forming the input terminal IN of the CMOS inverter. The drains of the PMOS transistor Ptr and NMOS transistor Ntr are connected to each other, forming the output terminal OUT of the CMOS inverter.

Referring again to FIG. 6, the writing of gradation data to the first memory 91 is performed via two switches SW11a and SW11b operated by a forward row scanning pulse. Grayscale data of opposite polarity is supplied to the column data line d and the inverted column data line db. The two switches SW11a and SW11b are composed of NMOS transistors. The drain of the NMOS transistor of one of the switches SW11a and SW11b is supplied with the power supply voltage VDD, and the drain of the NMOS transistor of the other switch is supplied with the reference voltage GND. When the power supply voltage VDD is supplied to the drain of one of the NMOS transistors, only a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor is output from the source of the NMOS transistor. Moreover, with this voltage, the NMOS transistor is driven near the threshold voltage Vth, so that almost no current flows. Therefore, the gradation data is written to the first memory 91 by the NMOS transistor to which the other reference voltage GND is supplied.

The writing of gradation data to the second memory 92 is performed via two switches SW12a and SW12b operated by a forward trigger pulse TRIG. The wiring m between the output terminal of the inverter INV2 and the switch SW12a, and the wiring mb between the output terminal of the inverter INV1 and the switch SW12b are supplied with gradation data of opposite polarity. The two switches SW12a and SW12b are composed of NMOS transistors. The drain of the NMOS transistor of one of the switches SW12a and SW12b is supplied with the power supply voltage VDD, and the drain of the NMOS transistor of the other switch is supplied with the reference voltage GND. When the power supply voltage VDD is supplied to the drain of one of the NMOS transistors, only a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor is output from the source of the NMOS transistor. Moreover, with this voltage, the NMOS transistor is driven near the threshold voltage Vth, so that almost no current flows. Therefore, the gradation data is written to the second memory 92 by the NMOS transistor to which the other reference voltage GND is supplied.

When the forward trigger pulse TRIG is supplied, the gradation data in the second memory 92 must be rewritten by the gradation data in the first memory 91. In other words, the gradation data in the first memory 91 must not be rewritten by the gradation data in the second memory 92. For this reason, the driving force of the inverters INV3 and INV4 constituting the second memory 92 must be smaller than the driving force of the inverters INV1 and INV2 constituting the first memory 91. In other words, if the gradation data in the first memory 91 and the second memory 92 are different, the output of the inverter INV1 and the output of the inverter INV3 will compete when the forward trigger pulse TRIG is supplied. In order to reliably rewrite the gradation data in the inverter INV4 by the gradation data in the inverter INV1, the driving force of the inverter INV1 must be larger than the driving force of the inverter INV3.

Similarly, in the competition between inverters INV2 and INV4, it is necessary to be able to reliably rewrite the gradation data of inverter INV3 with the gradation data of inverter INV2. Therefore, the driving force of inverter INV2 needs to be greater than the driving force of inverter INV4.

Figure 8 is a diagram that explains the magnitude relationship of the driving forces between inverters.

To briefly explain the relationship between inverters INV1 and INV3, when the gradation data of the first memory 91 on the wiring mb is at the "H" level, the PMOS transistor PT1 of the inverter INV1 is on. On the other hand, when the gradation data on the mb side of the second memory 92 is already at the "L" level, the NMOS transistor NT2 of the inverter INV3 is on.

Consider the case where the NMOS transistor that constitutes switch SW12b is turned on by the "H" level of the forward trigger pulse TRIG, and the outputs of inverters INV1 and INV3 are conductive to each other. Current flows from the power supply voltage VDD through the PMOS transistor PT1 of inverter INV1 and the NMOS transistor NT2 of inverter INV3 to the reference voltage GND. At this time, the voltage of wiring mb is determined by the ratio of the on-resistance of the PMOS transistor PT1 of inverter INV1 and the NMOS transistor NT2 of inverter INV3.

Conversely, when the gradation data of the first memory 91 on the wiring mb is at the "L" level, the NMOS transistor NT1 of the inverter INV1 is in an on state. On the other hand, when the gradation data on the mb side of the second memory 92 is already at the "H" level, the PMOS transistor PT2 of the inverter INV3 is in an on state.

Let us consider the case where the NMOS transistor constituting switch SW12b is turned on by the "H" level of the forward trigger pulse TRIG, and the outputs of inverters INV1 and INV3 are conductive to each other. Current flows from the power supply voltage VDD through the PMOS transistor PT2 of inverter INV3 and the NMOS transistor NT1 of inverter INV1 to the reference voltage GND. At this time, the voltage of wiring mb is determined by the ratio of the on-resistance of the PMOS transistor PT2 of inverter INV3 and the NMOS transistor NT1 of inverter INV1.

The input gate of the inverter INV4 (see FIG. 6) is connected to the wiring mb. The output data of the inverter INV4 is determined to be at the "L" level or "H" level by the input of the voltage level of the wiring mb. In other words, the output data of the second memory 92 is determined by the voltage level of the wiring mb. Therefore, in order to rewrite the gradation data of the second memory 92 by the gradation data of the first memory 91, the on-resistance of the transistors of the inverters INV1 and INV2 must be lower than the on-resistance of the transistors of the inverters INV3 and INV4. Since the on-resistance of the transistors of the inverters INV1 and INV2 is lower than the on-resistance of the transistors of the inverters INV3 and INV4, the gradation data of the first memory 91 is reliably written to the second memory 92 regardless of the gradation data level of the second memory 92.

Using transistors with low on-resistance means using transistors with high driving power, which can be achieved by shortening the gate length or increasing the gate width.

Referring again to FIG. 6, when the gradation data stored in the first memory 91 is transferred to the second memory 92 of all pixels Pix1 at once, the forward trigger pulse TRIG goes to the "L" level, and the switches SW12a and SW12b are turned off. Therefore, the second memory 92 holds the transferred gradation data, and can fix the potential of the reflective electrode PE to a potential corresponding to the gradation data for any time (here, one subframe period).

Note that switches SW11a, SW11b, SW12a, and SW12b may be configured with PMOS transistors. In that case, they can be considered to have the opposite polarity to that described above, so illustrations and explanations will be omitted.

In addition, the switches SW11a, SW11b, SW12a, and SW12b may be transmission gates composed of PMOS transistors and NMOS transistors.

Figure 9 is a timing diagram showing the operation of the reflective LCD device of the third embodiment.

As described above, in the reflective liquid crystal display device 13 (see FIG. 4), the row scanning lines g are selected one by one in 1H units, starting from row scanning line g1 to row scanning line gm, by the forward row scanning pulse output from the vertical shift register 63. As a result, the multiple pixels Pix1 constituting the image display unit 61 are written with grayscale data in units of n pixels Pix1 in one row commonly connected to the selected row scanning line g. Then, after writing to all of the multiple pixels Pix1 constituting the image display unit 61 is completed, the forward trigger pulse TRIG transfers all the pixels Pix1 from the first memory 91 to the second memory 92 at the same time.

Figure 9(A) shows a schematic diagram of the write and read periods for one pixel of 1-bit subframe gradation data output from the horizontal driver 65 to the column data lines d1 to dn. The diagonal lines slanting downward to the right indicate the write period. In Figure 9(A), bits B0b, B1b, and B2b are the inverted data of the gradation data of bits B0, B1, and B2.

Figure 9 (B) shows the forward trigger pulse TRIG output from the timing generator 62 to the trigger line trig. The forward trigger pulse TRIG is output every subframe.

Figure 9(C) shows a schematic representation of the bits of subframe grayscale data applied to the reflective electrode PE. Figure 9(D) shows the common electrode voltage Vcom. Figure 9(E) shows the voltage applied to the liquid crystal LCM.

First, in a row of pixels Pix1 selected by a forward row scan pulse output from the timing generator 62, the switches SW11a and SW11b are turned on by the forward row scan pulse. At that time, the forward subframe gradation data of bit B0 (FIG. 9A) output to the column data line d is sampled by the switch SW11a and written to the first signal holding circuit SM11. Thereafter, in a similar manner, the forward subframe gradation data of bit B0 is written to the first signal holding circuits SM11 of all pixels Pix1 constituting the image display unit 61. At timing T1 after the writing operation is completed, a forward trigger pulse TRIG (FIG. 9B) of "H" level is supplied simultaneously to all pixels Pix1 constituting the image display unit 61.

As a result, the switches SW12a and SW12b of all pixels Pix1 are turned on. Therefore, the normal subframe gradation data of bit B0 stored in the first signal holding circuit SM11 is simultaneously transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the normal subframe gradation data of bit B0 is applied to the reflective electrode PE. The period during which the normal subframe gradation data of bit B0 is held by the second signal holding circuit SM12 is one subframe period from timing T1 to timing T2 when the next "H" level normal trigger pulse TRIG is input.

Here, when the bit value of the subframe gradation data is "1", i.e., the "H" level, the power supply voltage VDD (e.g., 3.3 V) is applied to the reflective electrode PE. When the bit value of the subframe gradation data is "0", i.e., the "L" level, the reference voltage GND (e.g., 0 V) is applied to the reflective electrode PE. On the other hand, the common electrode CE is not limited to the reference voltage GND or the power supply voltage VDD, and any voltage can be applied as the common electrode voltage Vcom. The common electrode voltage Vcom is switched to a specified voltage at the same timing as when the "H" level forward trigger pulse TRIG is supplied. Here, the common electrode voltage Vcom is set to a voltage lower than 0 V by the liquid crystal threshold voltage Vtt during the subframe period (e.g., from timing T1 to timing T2) in which the forward subframe gradation data is applied to the reflective electrode PE, as shown in FIG. 9(D).

The liquid crystal display element LC displays gradations according to the voltage applied to the liquid crystal LCM, which is the absolute value of the difference voltage between the voltage applied to the reflective electrode PE and the common electrode voltage Vcom. During one subframe period from timing T1 to timing T2, the normal subframe gradation data of bit B0 is applied to the reflective electrode PE. Therefore, as shown in FIG. 9(E), when the bit value of the subframe gradation data is "1", the voltage applied to the liquid crystal LCM is 3.3V+Vtt (=3.3V-(-Vtt)). On the other hand, when the bit value of the subframe gradation data is "0", the voltage applied to the liquid crystal LCM is +Vtt (=0V-(-Vtt)).

Figure 10 shows the relationship between the applied voltage (RMS (root mean square) voltage) to the liquid crystal and the grayscale value.

As shown in FIG. 10, the grayscale value curve 101 is shifted to the higher voltage side. Specifically, the black grayscale value corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal LCM, and the white grayscale value corresponds to the RMS voltage of the saturation voltage Vsat (=3.3V+Vtt) of the liquid crystal LCM. It is possible to make the grayscale value coincide with the effective portion of the grayscale value curve 101. Therefore, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3V+Vtt) as described above, and displays black when the applied voltage is +Vtt.

Referring again to FIG. 9, during the subframe period in which the normal subframe gradation data of bit B0 is displayed, writing of the inverted subframe gradation data of bit B0b (see FIG. 9(A)) to the first signal holding circuit SM11 of pixel Pix1 is started in sequence. Then, the inverted subframe gradation data of bit B0b is written to the first signal holding circuit SM11 of all pixels Pix1 in the image display section 61. At timing T2 after the writing is completed, a normal trigger pulse TRIG of "H" level is supplied simultaneously to all pixels Pix1 constituting the image display section 61.

As a result, the switches SW12a and SW12b of all the pixels Pix1 are turned on. Therefore, the inverted subframe gradation data of the bit B0b stored in the first signal holding circuit SM11 is transferred to the second signal holding circuit SM21 via the switches SW12a and SW21b.
12 and held therein. At the same time, the inverted subframe grayscale data of bit B0b is applied to the reflective electrode PE. The holding period of the inverted subframe grayscale data of bit B0b by the second signal holding circuit SM12 is one subframe period from timing T2 to timing T3 when the next "H" level normal trigger pulse TRIG is supplied. Here, the inverted subframe grayscale data of bit B0b is always in an inverse logical value relationship with the normal subframe grayscale data of bit B0. Therefore, the inverted subframe grayscale data of bit B0b is "0" when the normal subframe grayscale data of bit B0 is "1", and is "1" when the normal subframe grayscale data of bit B0 is "0".

On the other hand, the common electrode voltage Vcom is set to a voltage higher than 3.3V by the threshold voltage Vtt of the liquid crystal LCM during one subframe period from timing T2 to timing T3 when the inverted subframe gradation data is applied to the reflective electrode PE, as shown in FIG. 9(D). Therefore, during one subframe period from timing T2 to timing T3, the voltage applied to the liquid crystal LCM is -Vtt (=3.3V-(3.3V+Vtt)) when the bit value of the subframe gradation data is "1", as shown in FIG. 9(E). On the other hand, the voltage applied to the liquid crystal LCM is -3.3V-Vtt (=0V-(3.3V+Vtt)) when the bit value of the subframe gradation data is "0".

When the bit value of the normal subframe gradation data of bit B0 is "1", the bit value of the inverted subframe gradation data of bit B0b input subsequently is "0". Therefore, the voltage applied to the liquid crystal LCM is -(3.3V+Vtt), and the direction of the potential applied to the liquid crystal LCM is opposite to that of the normal subframe gradation data of bit B0, but the absolute value is the same. Therefore, pixel Pix1 displays white, just as when the normal subframe gradation data of bit B0 is displayed. Similarly, when the bit value of the normal subframe gradation data of bit B0 is "0", the bit value of the inverted subframe gradation data of bit B0b input subsequently is "1". Therefore, the voltage applied to the liquid crystal LCM is -Vtt, and the direction of the potential applied to the liquid crystal LCM is opposite to that of the normal subframe gradation data of bit B0, but the absolute value is the same. Therefore, pixel Pix1 displays black, just as when the normal subframe gradation data of bit B0 is displayed.

As a result, as shown in FIG. 9(E), pixel Pix1 displays the same gray scale with bit B0 and bit B0b, which is the complementary bit of bit B0, during the two subframe periods from timing T1 to T3. At the same time, pixel Pix1 performs AC driving in which the potential direction of the liquid crystal LCM is inverted every subframe. This allows pixel Pix1 to prevent burn-in of the liquid crystal LCM.

Next, during the subframe period in which the inverted subframe gradation data of bit B0b is displayed, writing of the normal subframe gradation data of bit B1 (see FIG. 9A) to the first signal holding circuit SM11 of pixel Pix1 is started in sequence. Then, the normal subframe gradation data of bit B1 is written to the first signal holding circuit SM11 of all pixels Pix1 in the image display section 61. At timing T3 after the writing is completed, a normal trigger pulse TRIG of "H" level is supplied simultaneously to all pixels Pix1 constituting the image display section 61.

As a result, the switches SW12a and SW12b of all pixels Pix1 are turned on. Therefore, the normal subframe gradation data of bit B1 stored in the first signal holding circuit SM11 is transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the normal subframe gradation data of bit B1 is applied to the reflective electrode PE. The period during which the second memory 92 holds the normal subframe gradation data of bit B1 is one subframe period from timing T3 to timing T4 when the next "H" level normal trigger pulse TRIG is supplied.

On the other hand, during the subframe period in which the normal subframe gradation data is applied to the reflective electrode PE, the common electrode voltage Vcom is set to a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal LCM, as shown in FIG. 9(D). During one subframe period from timing T3 to timing T4, the normal subframe gradation data of bit B1 is applied to the reflective electrode PE. Therefore, as shown in FIG. 9(E), when the bit value of the subframe gradation data is "1", the voltage applied to the liquid crystal LCM is 3.3V+Vtt (=3.3V-(-Vtt)). On the other hand, when the bit value of the subframe gradation data is "0", the voltage applied to the liquid crystal LCM is +Vtt (=0V-(-Vtt)).

Next, during the subframe period in which the normal subframe gradation data of bit B1 is displayed, writing of the inverted subframe gradation data of bit B1b (see FIG. 9A) to the first signal holding circuit SM11 of pixel Pix1 is started in sequence. Then, the inverted subframe gradation data of bit B1b is written to the first signal holding circuit SM11 of all pixels Pix1 in the image display section 61. At timing T4 after the writing is completed, a normal trigger pulse TRIG of "H" level is supplied simultaneously to all pixels Pix1 constituting the image display section 61.

As a result, the switches SW12a and SW12b of all pixels Pix1 are turned on. Therefore, the inverted subframe gradation data of bit B1b stored in the first signal holding circuit SM11 is transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the inverted subframe gradation data of bit B1b is applied to the reflective electrode PE. The holding period of the inverted subframe gradation data of bit B1b by the second signal holding circuit SM12 is one subframe period from timing T4 to timing T5 when the next "H" level forward trigger pulse TRIG is supplied. Here, the inverted subframe gradation data of bit B1b is always in an inverted logical value relationship with the forward subframe gradation data of bit B1.

On the other hand, the common electrode voltage Vcom is set to a voltage higher than 3.3V by the threshold voltage Vtt of the liquid crystal LCM during the subframe period in which the inverted subframe gradation data is applied to the reflective electrode PE, as shown in FIG. 9(D). During one subframe period from timing T4 to timing T5, the inverted subframe gradation data of bit B1b is applied to the reflective electrode PE. Therefore, as shown in FIG. 9(E), when the bit value of the subframe gradation data is "1", the voltage applied to the liquid crystal LCM is -Vtt (=3.3V-(3.3V+Vtt)). On the other hand, when the bit value of the subframe gradation data is "0", the voltage applied to the liquid crystal LCM is -3.3V-Vtt (=0V-(3.3V+Vtt)).

As a result, as shown in FIG. 9(E), pixel Pix1 displays the same gray scale with bit B1 and bit B1b, which is the complementary bit of bit B1, during the two subframe periods from timing T3 to T5. At the same time, pixel Pix1 performs AC driving in which the potential direction of the liquid crystal LCM is inverted every subframe. This allows pixel Pix1 to prevent burn-in of the liquid crystal LCM.

Then, the same operation as above is repeated, and the reflective liquid crystal display device 13 including pixel Pix1 can display gradations by combining multiple subframes.

The display period length of bit B0 and the display period length of bit B0b, which is the complementary bit, are the same first subframe period length. The display period length of bit B1 and the display period length of bit B1b, which is the complementary bit, are the same second subframe period length. However, the first subframe period length and the second subframe period length are not necessarily the same. Here, as an example, the second subframe period length is set to twice the first subframe period length. The third subframe period length, which is the display period length of bit B2 and the display period length of bit B2b, which is the complementary bit, is set to twice the second subframe period length. The same is true for the other subframe periods, and each subframe period length is determined to a predetermined length according to the system, and the number of subframes is also determined to an arbitrary number.

(summary)
The grayscale data written to the second memory 92 is normal subframe grayscale data and inverted subframe grayscale data that are switched every subframe. Meanwhile, the common electrode voltage Vcom is alternately switched to a predetermined potential every subframe in synchronization with the writing. This allows the pixel Pix1 to perform positive and negative AC driving of the liquid crystal display element LC. Therefore, the reflective liquid crystal display device 13 can suppress burn-in of the liquid crystal display element LC, thereby improving reliability.

In addition, during the gradation data writing time, pixel Pix1 does not need to have the reflective electrode PE and common electrode CE at the same potential to turn off the liquid crystal display element LC. Therefore, the reflective liquid crystal display device 13 can eliminate the display loss time of the liquid crystal display element LC during the gradation data writing time, thereby improving the gradation. Furthermore, since the reflective liquid crystal display device 13 is no longer restricted in that the liquid crystal display element LC cannot display during the gradation data writing time, the gradation is not sacrificed even for devices with a large number of pixels such as FHD and 4K2K.

In addition, pixel Pix1 has the driving force of inverters INV1 and INV2 set to be greater than the driving force of inverters INV3 and INV4, allowing for stable and accurate gradation display.

In addition, pixel Pix1 can set the applied voltage of the liquid crystal display element LC high, and can widen the dynamic range. This allows the reflective liquid crystal display device 13 to suppress a decrease in contrast and a decrease in brightness. In addition, the reflective liquid crystal display device 13 can increase the reflection angle of reflected light.

When the reflective liquid crystal display device 13 of the third embodiment, which can suppress the decrease in contrast and the decrease in brightness, is applied to the WSS array 10, the decrease in contrast of the output beams 31a to 31c (see FIG. 1) can be suppressed, and the decrease in brightness can be suppressed. This enables the WSS array 10 to improve the S/N (signal/noise) ratio of the wavelength channels.

In addition, when the reflective liquid crystal display device of the third embodiment, which can increase the reflection angle of reflected light, is applied to the WSS array 10 of the first embodiment, the spatial interval between the output beams 31a to 31c (see FIG. 1) can be increased. This allows the WSS array 10 to improve the signal-to-noise ratio of the wavelength channels. Alternatively, the WSS array 10 can output a new output beam while maintaining the spatial interval between the output beams 31a to 31c. This allows the WSS array 10 to increase the number of wavelength channels.

In addition, in pixel Pix1, the first signal holding circuit SM11 and the second signal holding circuit SM12 are static random access memories. Therefore, pixel Pix1 can have high noise resistance.

<Fourth embodiment>
FIG. 11 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the fourth embodiment.

Of the components of pixel Pix2 of the reflective LCD device of the fourth embodiment, the same components as those of pixel Pix1 of the third embodiment are given the same reference numerals and will not be described.

Pixel Pix2 is located at the intersection of any one column data line d and any one row scanning line g.

Pixel Pix2 includes a first memory 111, a second memory 112, and a liquid crystal display element LC. The first memory 111 includes a switch SW13 and a first signal holding circuit SM13. The second memory 112 includes a switch SW14 and a second signal holding circuit SM14.

In pixel Pix2, the first memory 111 and the second memory 112 are each composed of SRAM.

The switch SW13 corresponds to an example of a "first switching circuit" in the present disclosure. The first signal holding circuit SM13 corresponds to an example of a "first signal holding circuit" in the present disclosure. The first memory 111 corresponds to an example of a "first static random access memory" in the present disclosure. The switch SW14 corresponds to an example of a "second switching circuit" in the present disclosure. The second signal holding circuit SM14 corresponds to an example of a "second signal holding circuit" in the present disclosure. The second memory 112 corresponds to an example of a "second static random access memory" in the present disclosure.

Like pixel Pix1 (see Figure 6), pixel Pix2 is configured with two stages of SRAM, but is characterized in that writing to the first signal holding circuit SM13 and the second signal holding circuit SM14 is performed via switches SW13 and SW14.

The switch SW13 is composed of an NMOS transistor whose gate is connected to the row scanning line g, whose drain is connected to the column data line d, and whose source is connected to one input terminal of the first signal holding circuit SM13.

The first signal holding circuit SM13 is a self-holding memory composed of two inverters INV11 and INV12, one of which has an output terminal connected to the input terminal of the other. The input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NMOS transistor that constitutes the switch SW13. The input terminal of the inverter INV12 is connected to the output terminal of the inverter INV11 and the drain of the NMOS transistor that constitutes the switch SW14.

The switch SW14 is composed of an NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the output terminal of the first signal holding circuit SM13, and whose source is connected to the input terminal of the second signal holding circuit SM14.

The second signal holding circuit SM14 is a self-holding memory composed of two inverters INV13 and INV14, one of which has an output terminal connected to the input terminal of the other. The input terminal of the inverter INV13 is connected to the output terminal of the inverter INV14 and to the reflective electrode PE. The input terminal of the inverter INV14 is connected to the output terminal of the inverter INV13 and to the source of the NMOS transistor that constitutes the switch SW14.

Each of the inverters INV11, INV12, INV13, and INV14 is exemplified by a CMOS inverter (see FIG. 7).

Pixel Pix2 performs the same operation as that described in the third embodiment together with the timing diagram of FIG. 9.

First, the switch SW13 of the pixels Pix2 in one row selected by the forward row scan pulse output from the timing generator 62 is turned on by the forward row scan pulse. At that time, the forward subframe gradation data output to the column data line d is sampled by the switch SW13 and written to the first signal holding circuit SM13. Thereafter, the forward subframe gradation data is written in the same manner to the first signal holding circuits SM13 of all the pixels Pix2 constituting the image display unit 61. At the timing after the writing operation is completed, a forward trigger pulse TRIG of "H" level is supplied simultaneously to all the pixels Pix2 constituting the image display unit 61.

As a result, the switches SW14 of all pixels Pix2 are turned on. Therefore, the normal subframe gradation data stored in the first signal holding circuit SM13 is simultaneously transferred to the second signal holding circuit SM14 via the switches SW14 and held there. At the same time, the normal subframe gradation data is applied to the reflective electrode PE. The period during which the normal subframe gradation data is held by the second signal holding circuit SM14 is one subframe period until the next "H" level normal trigger pulse TRIG is input.

Next, each pixel Pix2 in the image display unit 61 is selected row by row by the forward row scan pulse in the same manner as described above, and inverted subframe grayscale data of the opposite logical value to the immediately preceding forward subframe grayscale data is written to the first signal holding circuit SM13 for each pixel Pix2. When writing of the inverted subframe grayscale data to the first signal holding circuit SM13 of all pixels Pix2 constituting the image display unit 61 is completed, a forward trigger pulse TRIG of "H" level is supplied simultaneously to all pixels Pix2 constituting the image display unit 61.

As a result, the switches SW14 of all pixels Pix2 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit SM13 is simultaneously transferred to and held in the second signal holding circuit SM14 via the switches SW14. At the same time, the inverted subframe gradation data is applied to the reflective electrode PE. The period during which the inverted subframe gradation data is held by the second signal holding circuit SM14 is one subframe period until the next "H" level forward trigger pulse TRIG is supplied.

Data is written to the first signal holding circuit SM13 via one switch SW13 as described above. In this case, the transistors in the inverter INV11 on the input side as viewed from the switch SW13 have a larger driving force than the transistors in the inverter INV12 on the output side as viewed from the switch SW13. Furthermore, the NMOS transistors constituting the switch SW13 have a larger driving force than the transistors constituting the inverter INV12.

This is relevant when the gradation data of the first signal holding circuit SM13 is rewritten. In particular, when the voltage a on the switch SW13 side of the first signal holding circuit SM13 is at the "L" level and the data on the column data line d is at the "H" level, the voltage a needs to be higher than the input voltage (threshold voltage) at which the inverter INV11 inverts.

That is, the voltage a in the case of the "H" level is determined by the ratio of the current of the NMOS transistor constituting the inverter INV12 to the current of the NMOS transistor constituting the switch SW13. The switch SW13 is an NMOS transistor. Therefore, when the switch SW13 is in the on state, even if the "H" level power supply voltage VDD is input to the drain from the column data line d, the voltage output from the source is lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor. In other words, the "H" level voltage of the voltage a is a voltage lower than the power supply voltage VDD by the threshold voltage Vth. Moreover, at this voltage, the NMOS transistor of the switch SW13 operates near the threshold voltage Vth, so almost no current flows. In other words, the higher the voltage a that turns on the switch SW13, the less current the switch SW13 passes.

In other words, when voltage a is at the "H" level, in order for voltage a to reach a voltage equal to or higher than the voltage at which the NMOS transistor of inverter INV11 inverts, the current flowing through switch SW13 must be greater than the current flowing through the NMOS transistor of inverter INV12. Therefore, the NMOS transistor that constitutes switch SW13 must have a greater driving force than the NMOS transistor that constitutes inverter INV12. Taking into account this magnitude relationship in driving force, the transistor size of the NMOS transistor that constitutes switch SW13 and the transistor size of the NMOS transistor that constitutes inverter INV12 must be determined.

In addition, data is written to the second signal holding circuit SM14 via one switch SW14. In this case, the transistor in the inverter INV14 on the input side as viewed from the switch SW14 uses a transistor with a larger driving force than the transistor in the inverter INV13 on the output side as viewed from the switch SW14.

Let us consider the case where the forward trigger pulse TRIG becomes "H" level and the switch SW14 is turned on. If the gradation data held by the first signal holding circuit SM13 and the gradation data held by the second signal holding circuit SM14 are different, the output of the inverter INV11 and the output of the inverter INV13 will compete with each other. However, the driving force of the inverter INV11 is greater than the driving force of the inverter INV13. Therefore, the gradation data of the first signal holding circuit SM13 is not rewritten by the gradation data of the second signal holding circuit SM14, but the gradation data of the second signal holding circuit SM14 is rewritten by the gradation data of the first signal holding circuit SM13.

Furthermore, the NMOS transistor that constitutes switch SW14 has a larger driving force than the NMOS transistor that constitutes inverter INV13.

This is relevant when the gradation data of the second signal holding circuit SM14 is rewritten. In particular, when the voltage b on the switch SW14 side of the second signal holding circuit SM14 is at the "L" level and the gradation data of the first signal holding circuit SM13 is at the "H" level, it is necessary to make the voltage b higher than the threshold voltage at which the inverter INV14 inverts.

That is, the voltage b in the case of the "H" level is determined by the ratio of the current of the NMOS transistor constituting the inverter INV13 to the current of the NMOS transistor constituting the switch SW14. The switch SW14 is an NMOS transistor. Therefore, when the switch SW14 is in the on state, even if the "H" level power supply voltage VDD is input to the drain from the first signal holding circuit SM13, the voltage output from the source is a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor. In other words, the "H" level voltage of voltage b is a voltage lower than the power supply voltage VDD by the threshold voltage Vth. Moreover, at this voltage, the NMOS transistor of the switch SW14 operates near the threshold voltage Vth, so almost no current flows. In other words, the higher the voltage b that conducts the switch SW14, the less current the switch SW14 passes.

In other words, when voltage b is at the "H" level, in order for voltage b to reach a voltage at which the NMOS transistor of inverter INV14 inverts or exceeds that voltage, the current flowing through switch SW14 must be greater than the current flowing through the NMOS transistor of inverter INV13. Therefore, the NMOS transistor that constitutes switch SW14 must have a greater driving force than the NMOS transistor that constitutes inverter INV13. Taking into account this magnitude relationship in driving force, the transistor size of the NMOS transistor that constitutes switch SW14 and the transistor size of the NMOS transistor that constitutes inverter INV13 must be determined.

When the gradation data stored in the first memory 111 is transferred to the second memory 112 of all pixels Pix2 at once, the forward trigger pulse TRIG goes to the "L" level and the switch SW14 goes to the off state. Therefore, the second memory 112 holds the transferred gradation data and can fix the potential of the reflective electrode PE to a potential corresponding to the gradation data for any time (here, one subframe period).

Note that switches SW13 and SW14 may be configured with PMOS transistors. In that case, they can be considered to have the opposite polarity to that described above, so illustrations and explanations will be omitted.

In addition, switches SW13 and SW14 may be transmission gates composed of PMOS and NMOS transistors.

(summary)
The pixel Pix2 has the same effect as the pixel Pix1 of the third embodiment.

In addition, pixel Pix2 has the effect of being able to be miniaturized. The reason for this is as follows. Each of inverters INV11 to INV14 is composed of two transistors. Therefore, pixel Pix2 is composed of a total of 10 transistors, and can be composed of a smaller number of elements than pixel Pix1 (a total of 12 transistors).

Fifth embodiment
The pixel Pix1 in the third embodiment requires a total of 12 transistors, and the pixel Pix2 in the fourth embodiment requires a total of 10 transistors.

In addition, the liquid crystal display element LC is required to be driven at 3V to 5V, and the transistors need to be driven at 3.3V or 5V. Therefore, it is necessary to use transistors with high voltage resistance and large size.

Furthermore, in order to ensure that data is rewritten reliably in pixels Pix1 and Pix2, the transistor sizes of each switch and SRAM must be taken into consideration when designing. Transistors that require a large driving force must be made larger in size.

On the other hand, the pixel density of reflective LCD devices is increasing year by year, and there is a strong demand for smaller pixels. With a small pixel pitch, it is necessary to configure a two-stage memory as shown in Figure 5 with a small number of transistors.

Pixel Pix3 of the fifth embodiment can meet the above requirements.

Figure 12 shows the circuit configuration of a pixel in a reflective liquid crystal display device according to the fifth embodiment.

Of the components of pixel Pix3 of the reflective LCD device of the fifth embodiment, the same components as those of pixel Pix1 of the third embodiment or pixel Pix2 of the fourth embodiment are given the same reference numerals and will not be described.

Pixel Pix3 is located at the intersection of any one column data line d and any one row scanning line g.

The pixel Pix3 includes a first memory 111, a second memory 121, and a liquid crystal display element LC. The second memory 121 includes a switch SW21 and a second signal holding circuit DM21.

In pixel Pix3, the first memory 111 is composed of an SRAM, and the second memory 121 is composed of a dynamic random access memory (DRAM).

The switch SW13 corresponds to an example of a "first switching circuit" in the present disclosure. The first signal holding circuit SM13 corresponds to an example of a "first signal holding circuit" in the present disclosure. The first memory 111 corresponds to an example of a "first static random access memory" in the present disclosure. The switch SW21 corresponds to an example of a "second switching circuit" in the present disclosure. The second signal holding circuit DM21 corresponds to an example of a "second signal holding circuit" in the present disclosure. The second memory 121 corresponds to an example of a "first dynamic random access memory" in the present disclosure.

The switch SW21 is a known transmission gate composed of an NMOS transistor Tr1 and a PMOS transistor Tr2 whose drains are connected to each other and whose sources are connected to each other. The gate of the NMOS transistor Tr1 is connected to the trigger line trig, and the gate of the PMOS transistor Tr2 is connected to the inverted trigger line trigb.

The switch SW21 has one terminal connected to the first signal holding circuit SM13 and the other terminal connected to the second signal holding circuit DM21 and the reflective electrode PE. Therefore, when the normal trigger pulse TRIG is at the "H" level (in this case, the inverted trigger pulse TRIGB is at the "L" level), the switch SW21 is in the ON state. Therefore, the switch SW21 reads out the gradation data of the first signal holding circuit SM13 and transfers it to the second signal holding circuit DM21 and the reflective electrode PE. Furthermore, when the normal trigger pulse TRIG is at the "L" level (in this case, the inverted trigger pulse TRIGB is at the "H" level), the switch SW21 is in the OFF state and does not read out the gradation data of the first signal holding circuit SM13.

The switch SW21 is a known transmission gate composed of an NMOS transistor Tr1 and a PMOS transistor Tr2, and can turn on and off a voltage ranging from the reference voltage GND to the power supply voltage VDD. In other words, when the signal applied to the gates of the NMOS transistor Tr1 and the PMOS transistor Tr2 is a voltage on the reference voltage GND side ("L" level), the PMOS transistor Tr2 cannot be conductive. Instead, the NMOS transistor Tr1 can be conductive with low resistance. On the other hand, when the signal applied to the gates of the NMOS transistor Tr1 and the PMOS transistor Tr2 is a voltage on the power supply voltage VDD side ("H" level), the NMOS transistor Tr1 cannot be conductive. Instead, the PMOS transistor Tr2 can be conductive with low resistance. Therefore, the transmission gate constituting the switch SW21 is controlled to be turned on and off by the forward trigger pulse TRIG and the inverted trigger pulse TRIGB. This control allows switch SW21 to switch between low and high resistance in the voltage range from the reference voltage GND to the power supply voltage VDD.

The second signal holding circuit DM21 is composed of a capacitance C1. Here, consider the case where the gradation data of the first signal holding circuit SM13 and the gradation data of the second signal holding circuit DM21 are different. When the switch SW21 is turned on and the gradation data of the first signal holding circuit SM13 is transferred to the second signal holding circuit DM21, it is necessary to rewrite the gradation data of the second signal holding circuit DM21 with the gradation data of the first signal holding circuit SM13.

When the grayscale data of the capacitor C1 constituting the second signal holding circuit DM21 is rewritten, the grayscale data changes by charging or discharging. The charging and discharging of the capacitor C1 is driven by the output signal of the inverter INV11.

When the grayscale data of the capacitor C1 is rewritten from the "L" level to the "H" level by charging, the output signal of the inverter INV11 is "H". At this time, the PMOS transistor (see PMOS transistor Ptr in FIG. 7) constituting the inverter INV11 is in the ON state, and the NMOS transistor (see NMOS transistor Ntr in FIG. 7) is in the OFF state. Therefore, the capacitor C1 is charged by the power supply voltage VDD connected to the source of the PMOS transistor of the inverter INV11.

On the other hand, when the grayscale data of the capacitor C1 is rewritten from the "H" level to the "L" level by discharging, the output signal of the inverter INV11 is at the "L" level. At this time, the NMOS transistor (see NMOS transistor Ntr in FIG. 7) constituting the inverter INV11 is in the ON state, and the PMOS transistor (see PMOS transistor Ptr in FIG. 7) is in the OFF state. Therefore, the charge of the capacitor C1 is discharged to the reference voltage GND via the NMOS transistor of the inverter INV11. The switch SW21 is configured as an analog switch using a transmission gate, which enables high-speed charging and discharging of the capacitor C1.

Furthermore, the driving force of the inverter INV11 is set to be greater than the driving force of the inverter INV12. Therefore, the inverter INV11 can quickly charge and discharge the capacitance C1 that constitutes the second signal holding circuit DM21.

When the switch SW21 is turned on, the charge stored in the capacitor C1 may also affect the input gate of the inverter INV12. However, because the driving force of the inverter INV11 is set to be greater than that of the inverter INV12, the charging and discharging of the capacitor C1 by the inverter INV11 takes priority over the data inversion of the inverter INV12. Therefore, the gradation data of the first signal holding circuit SM13 is not overwritten by the gradation data of the second signal holding circuit DM21.

Pixel Pix3 can transfer 1-bit gradation data from the first signal holding circuit SM13 to the second signal holding circuit DM21 with an amplitude between the reference voltage GND and the power supply voltage VDD. Therefore, when pixel Pix3 is driven with the same power supply voltage VDD, it becomes possible to set the applied voltage of the liquid crystal display element LC higher, and the dynamic range can be widened.

In addition, pixel Pix3 has the effect of being able to be miniaturized. The first reason is as follows. Each of inverters INV11 and INV12 is composed of two transistors. Therefore, pixel Pix3 is composed of a total of seven transistors and one capacitor C1, and can be composed of a smaller number of elements than pixel Pix1 (total of 12 transistors) and pixel Pix2 (total of 10 transistors). The second reason is that, as explained below, the first signal holding circuit SM13, the second signal holding circuit DM21, and the reflective electrode PE can be effectively arranged in the height direction of the element.

Figure 13 is a diagram showing the cross-sectional configuration of a pixel in a reflective liquid crystal display device according to the fifth embodiment.

Capacitor C1 can be an MIM (Metal-Insulator-Metal) capacitor that forms a capacitance between wiring, a diffusion capacitor that forms a capacitance between the substrate and polysilicon, or a PIP (Poly-Insulator-Poly) capacitor that forms a capacitance between two layers of polysilicon. Figure 13 shows the cross-sectional configuration of a reflective LCD device in which capacitor C1 is formed using MIM.

In FIG. 13, a PMOS transistor PTr11 of an inverter INV11 and a PMOS transistor Tr2 of a switch SW21, whose drains are connected to each other by sharing a common diffusion layer, are formed on an N well 201 formed on a silicon substrate 200. Also, an NMOS transistor NTr11 of an inverter INV11 and an NMOS transistor Tr1 of a switch SW21, whose drains are connected to each other by sharing a common diffusion layer, are formed on a P well 202 formed on the silicon substrate 200. Note that the NMOS transistor and PMOS transistor constituting the inverter INV12 are not shown in FIG. 13.

Above the PMOS transistors PTr11 and Tr2, and the NMOS transistors Tr1 and NTr12, the first metal 206, the second metal 208, the third metal 210, the electrode 212, the fourth metal 214, and the fifth metal 216 are laminated with the interlayer insulating film 205 interposed between the metals. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel. The two diffusion layers constituting the sources of the NMOS transistor Tr1 and the PMOS transistor Tr2 constituting the switch SW21 are electrically connected to the first metal 206 by two contacts 218. Furthermore, the two diffusion layers are electrically connected to the second metal 208, the third metal 210, the fourth metal 214, and the fifth metal 216 via through holes 219a, 219b, 219c, and 219e. That is, the sources of the NMOS transistor Tr1 and the PMOS transistor Tr2 that make up the switch SW21 are electrically connected to the reflective electrode PE.

Furthermore, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216) and is disposed opposite and spaced from the common electrode CE, which is a transparent electrode. Liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form the liquid crystal display element LC.

Here, an electrode 212 is formed on the third metal 210 via an interlayer insulating film 205. This electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute a capacitance C1.

When the capacitance C1 is constructed using MIM, the first signal holding circuit SM13, the switch SW13, and the switch SW12 can be constructed using transistors on the silicon substrate 200 and the first and second layer wiring of the first metal 206 and the second metal 208. The second signal holding circuit DM21 can be constructed using MIM wiring that utilizes the third metal 210 above the transistor.

The electrode 212 is electrically connected to the fourth metal 214 via the through hole 219d. Furthermore, the fourth metal 214 is electrically connected to the reflective electrode PE via the through hole 219e. Therefore, the capacitance C1 is electrically connected to the reflective electrode PE.

Light from a light source (not shown) passes through the common electrode CE and liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels back along the original incident path, and is emitted through the common electrode CE.

As shown in FIG. 13, by allocating the fifth metal 216 to the reflective electrode PE, pixel Pix3 allows the first signal hold circuit SM13, the second signal hold circuit DM21, and the reflective electrode PE to be effectively arranged in the height direction. Therefore, pixel Pix3 can achieve pixel miniaturization. As a result, pixel Pix3 can be configured with pixels with a pitch of, for example, 3 μm or less, using transistors with a power supply voltage of 3.3 V. This 3 μm pitch pixel can realize an LCD panel with a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

Pixel Pix3 performs the same operation as that described in the third embodiment together with the timing diagram of FIG. 9.

First, the switch SW13 of the pixels Pix3 in one row selected by the forward row scan pulse output from the timing generator 62 is turned on by the forward row scan pulse. At that time, the forward subframe gradation data output to the column data line d is sampled by the switch SW13 and written to the first signal holding circuit SM13. Thereafter, the forward subframe gradation data is written in the same manner to the first signal holding circuits SM13 of all the pixels Pix3 constituting the image display unit 61. At the timing after the writing operation is completed, a "H" level forward trigger pulse TRIG and an "L" level inverted trigger pulse TRIGB are simultaneously supplied to all the pixels Pix3 constituting the image display unit 61.

As a result, the switches SW21 of all pixels Pix3 are turned on. Therefore, the normal subframe gradation data stored in the first signal holding circuit SM13 is simultaneously transferred to the second signal holding circuit DM21 via the switches SW21 and held there. At the same time, the normal subframe gradation data is applied to the reflective electrode PE. The period during which the normal subframe gradation data is held by the second signal holding circuit DM21 is one subframe period until the next "H" level normal trigger pulse TRIG and "L" level inverted trigger pulse TRIGB are input.

Next, each pixel Pix3 in the image display section 61 is selected row by row by the forward row scanning pulse in the same manner as described above, and inverted subframe grayscale data of the opposite logical value to the immediately preceding forward subframe grayscale data is written to the first signal holding circuit SM13 for each pixel Pix3. When writing of the inverted subframe grayscale data to the first signal holding circuit SM13 of all pixels Pix3 in the image display section 61 is completed, a "H" level forward trigger pulse TRIG and an "L" level inverted trigger pulse TRIGB are simultaneously supplied to all pixels Pix3.

As a result, the switches SW21 of all pixels Pix3 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit SM13 is simultaneously transferred to the second signal holding circuit DM21 via the switches SW21 and held there. At the same time, the inverted subframe gradation data is applied to the reflective electrode PE. The holding period of the inverted subframe gradation data by the second signal holding circuit DM21 is one subframe period until the next "H" level normal trigger pulse TRIG and "L" level inverted trigger pulse TRIGB are supplied.

The switch SW13 may be configured with a PMOS transistor. In that case, it can be considered as having the opposite polarity to the above description, so illustrations and explanations are omitted.

In addition, switch SW13 may be a transmission gate composed of a PMOS transistor and an NMOS transistor.

In addition, switch SW21 may be configured with a PMOS transistor or an NMOS transistor.

(summary)
The pixel Pix3 provides the same effects as the pixels Pix1 and Pix2 of the third and fourth embodiments.

In addition, pixel Pix3 has the advantage of being able to be miniaturized.

Sixth embodiment
FIG. 14 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the sixth embodiment.

Of the components of pixel Pix4 of the reflective LCD device of the sixth embodiment, the same components as those of pixels Pix1 to Pix3 of the third to fifth embodiments are given the same reference numerals and will not be described.

Pixel Pix4 is located at the intersection of any one column data line d and any one pair of row scanning line g and inverted row scanning line gb.

Pixel Pix4 includes a first memory 131, a second memory 132, and a liquid crystal display element LC. The first memory 131 includes a switch SW31 and a first signal holding circuit DM31. The second memory 132 includes a switch SW32 and a second signal holding circuit SM32.

In pixel Pix4, the first memory 131 is composed of DRAM, and the second memory 132 is composed of SRAM.

The switch SW31 corresponds to an example of a "first switching circuit" in the present disclosure. The first signal holding circuit DM31 corresponds to an example of a "first signal holding circuit" in the present disclosure. The first memory 131 corresponds to an example of a "first dynamic random access memory" in the present disclosure. The switch SW32 corresponds to an example of a "second switching circuit" in the present disclosure. The second signal holding circuit SM32 corresponds to an example of a "second signal holding circuit" in the present disclosure. The second memory 132 corresponds to an example of a "first static random access memory" in the present disclosure.

The switch SW31 is a known transmission gate composed of an NMOS transistor Tr31 and a PMOS transistor Tr32 whose drains are connected to each other and whose sources are connected to each other. The gate of the NMOS transistor Tr31 is connected to the row scanning line g, and the gate of the PMOS transistor Tr32 is connected to the inverted row scanning line gb.

In addition, one terminal of the switch SW31 is connected to the column data line d, and the other terminal is connected to the first signal holding circuit DM31. Therefore, when the forward row scanning pulse is at the "H" level (in this case, the inverted row scanning pulse is at the "L" level), the switch SW31 is turned on and reads out the grayscale data of the column data line d and transfers it to the first signal holding circuit DM31. In addition, when the forward row scanning pulse is at the "L" level (in this case, the inverted row scanning pulse is at the "H" level), the switch SW31 is turned off and does not read out the grayscale data of the column data line d.

The switch SW31 is a known transmission gate composed of an NMOS transistor Tr31 and a PMOS transistor Tr32, and can turn on and off a voltage ranging from the reference voltage GND to the power supply voltage VDD. In other words, when the signal applied to the gates of the NMOS transistor Tr31 and the PMOS transistor Tr32 is a voltage on the reference voltage GND side ("L" level), the PMOS transistor Tr32 cannot be conductive. Instead, the NMOS transistor Tr31 can be conductive with low resistance. On the other hand, when the signal applied to the gates of the NMOS transistor Tr31 and the PMOS transistor Tr32 is a voltage on the power supply voltage VDD side ("H" level), the NMOS transistor Tr31 cannot be conductive. Instead, the PMOS transistor Tr32 can be conductive with low resistance. Therefore, by controlling the on/off of the transmission gate that constitutes switch SW31 using a forward row scan pulse and an inverted row scan pulse, it is possible to switch between low and high resistance in the voltage range from the reference voltage GND to the power supply voltage VDD.

The first signal holding circuit DM31 is composed of a capacitor C2. Here, consider the case where the grayscale data of the column data line d and the grayscale data of the first signal holding circuit DM31 are different. When the switch SW31 is turned on and the grayscale data of the column data line d is transferred to the first signal holding circuit DM31, it is necessary to rewrite the grayscale data of the first signal holding circuit DM31 with the grayscale data of the column data line d.

When the grayscale data of the capacitance C2 constituting the first signal holding circuit DM31 is rewritten, the grayscale data changes by charging or discharging. When the grayscale data of the column data line d is transferred to the capacitance C2, the grayscale data is written by charge transfer between the data line capacitance of the column data line d and the capacitance C2. Typically, the capacitance ratio between the data line capacitance of the column data line d and the capacitance C2 is large, about 1000:1. Therefore, the pixel Pix4 can reliably rewrite the grayscale data of the capacitance C2.

The switch SW32 is a known transmission gate composed of an NMOS transistor Tr33 and a PMOS transistor Tr34 whose drains are connected to each other and whose sources are connected to each other. The gate of the NMOS transistor Tr33 is connected to the trigger line trig, and the gate of the PMOS transistor Tr34 is connected to the inverted trigger line trigb.

The switch SW32 has one terminal connected to the first signal holding circuit DM31 and the other terminal connected to the second signal holding circuit SM32. Therefore, when the normal trigger pulse TRIG is at the "H" level (in this case, the inverted trigger pulse TRIGB is at the "L" level), the switch SW32 is turned on and reads out the gradation data of the first signal holding circuit DM31 and transfers it to the second signal holding circuit SM32. When the normal trigger pulse TRIG is at the "L" level (in this case, the inverted trigger pulse TRIGB is at the "H" level), the switch SW32 is turned off and does not read out the gradation data of the first signal holding circuit DM31.

The second signal holding circuit SM32 is a self-holding memory composed of two inverters INV33 and INV34, one of which has an output terminal connected to the input terminal of the other. The input terminal of the inverter INV33 is connected to the output terminal of the inverter INV34 and the reflective electrode PE. The input terminal of the inverter INV34 is connected to the output terminal of the inverter INV33 and the switch SW32.

Each of the inverters INV33 and INV34 is exemplified by a CMOS inverter (see FIG. 7).

Data is written to the second signal holding circuit SM32 via one switch SW32 as described above. In this case, the transistors in the inverter INV34 on the input side as viewed from the switch SW32 have a greater driving force than the transistors in the inverter INV33 on the output side as viewed from the switch SW32. Furthermore, the transistors constituting the switch SW32 have a greater driving force than the transistors constituting the inverter INV33. This makes it easier for data to be input to the second signal holding circuit SM32 from the capacitor C2, but harder for data to be input to the liquid crystal display element LC.

When the switch SW32 is turned on, the charge stored in the capacitance C2 drives the input gate of the inverter INV34 and rewrites the gradation data of the second signal holding circuit SM32. When the switch SW32 is turned on, the output of the inverter INV33 can affect the capacitance C2. However, the capacitance on the input side of the inverter INV33 is only the gate capacitance constituting the inverter INV33 and the liquid crystal capacitance of the liquid crystal display element LC, and is significantly smaller than the gate capacitance constituting the input of the inverter INV34 and the capacitance C2. In addition, the inverter INV34 is set to have a larger driving force than the inverter INV33. Therefore, the driving of the inverter INV34 by the capacitance C2 takes precedence over the output of the inverter INV33, and the gradation data of the capacitance C2 is not rewritten by the gradation data of the second signal holding circuit SM33.

The gradation data of the capacitor C2 is a charge transfer from the column data line d. Also, effects such as gate feedthrough occur when the NMOS transistor and PMOS transistor constituting the switch SW31 are turned off. Therefore, the potential of the capacitor C2 is determined with potential fluctuations, and the voltage becomes a voltage that is shifted in the direction of reducing the dynamic range from the reference voltage GND and the power supply voltage VDD. However, the voltage finally applied to the reflective electrode PE is shaped by the second signal holding circuit SM33, so that an accurate reference voltage GND or power supply voltage VDD voltage is applied. Therefore, the pixel Pix4 can have a wide dynamic range.

In addition, when light hits the diffusion electrode portion of the transistors that make up the switches SW31 and SW32 connected to the capacitor C2, a leakage current occurs, which can reduce the charge held in the capacitor C2 and cause potential fluctuations.

However, the voltage held in the capacitance C2 is for driving the second signal holding circuit SM33. Therefore, even if the voltage held in the capacitance C2 fluctuates somewhat, it does not affect the voltage of the reflective electrode PE unless it fluctuates beyond the threshold at which the second signal holding circuit SM33 can hold the grayscale data at the "L" level or "H" level. At this time, the voltage of the reflective electrode PE applied to the liquid crystal display LCM is supplied from the second signal holding circuit SM33. When the voltage of the reflective electrode PE is at the "H" level, the PMOS transistor in the inverter INV34 constituting the second signal holding circuit SM33 is on, and the power supply voltage VDD is applied to the reflective electrode PE. When the voltage of the reflective electrode PE is at the "L" level, the NMOS transistor in the inverter INV34 constituting the second signal holding circuit SM33 is on, and the reference voltage GND is applied. Therefore, the voltage of the reflective electrode PE is not affected by the leakage current due to light, and the reflective electrode PE can apply a stable voltage to the liquid crystal LCM.

As explained above, even if the voltage of the capacitor C2 fluctuates slightly due to charge transfer, gate feedthrough, light leakage, etc., there is no problem as long as the gradation data of the second signal holding circuit SM33 can be rewritten.

For this reason, the switch SW31 constituting the first memory 131 and the switch SW32 constituting the second memory 132 do not have to be complementary switches using NMOS and PMOS transistors.

For example, consider the case where the switches SW31 and SW32 are composed only of NMOS transistors. In this case, the switches SW31 and SW32 can only pass the "H" level voltage of the input signal up to VDD-Vth, including the substrate effect. In other words, if the switch SW31 is composed only of NMOS transistors, even if a voltage of 3.3V is supplied to the column data line d, the voltage a at the connection point between the switch SW31 and the capacitance C2 will be VDD-Vth or less, for example, 2.5V. Therefore, a voltage of 2.5V is stored in the capacitance C2. Next, the switch SW32 is turned on to rewrite the gradation data of the second signal holding circuit SM33. If the switch SW32 is also composed only of NMOS transistors, the voltage b at the connection point between the switch SW32 and the second signal holding circuit SM33 will be 2.5V, just like the voltage a. However, if the voltage b is VDD/2, or 1.65V or more, it is possible to input the "H" level to the second signal holding circuit SM33 (applying the "L" level to the output reflective electrode PE). Therefore, the second signal holding circuit SM33 can write either "H" level gradation data or "L" level gradation data.

If switches SW31 and SW32 are composed of only PMOS transistors, the voltage range that is not input will be the opposite of the above.

In this way, switch SW31 and switch SW32 may be switches using a single MOS transistor instead of complementary switches. In this case, the number of transistors constituting one pixel is reduced, which has the effect of enabling pixel Pix4 to be further miniaturized.

The reflective electrode PE is applied with a voltage that is the logical inverse of the voltage of the capacitor C2. Therefore, the gradation data to be written to pixel Pix4 must be the inverse of the data (voltage) to be applied to the reflective electrode PE.

The pixel Pix4 has the effect of enabling the pixel to be miniaturized. The first reason is as follows. Each of the inverters INV33 and INV34 is composed of two transistors. Therefore, the pixel Pix4 is composed of a total of eight transistors and one capacitor C1, and can be configured with a smaller number of elements than the pixel Pix1 (total of 12 transistors) and the pixel Pix2 (total of 10 transistors). In addition to the first reason, the second reason is that the first signal holding circuit DM31, the second signal holding circuit SM32, and the reflective electrode PE can be effectively arranged in the height direction of the element, as described below.

Figure 15 is a diagram showing the cross-sectional configuration of a pixel in a reflective liquid crystal display device according to the sixth embodiment.

Capacitor C2 can be an MIM capacitor, a diffusion capacitor, a PIP capacitor, or the like. Figure 15 shows the cross-sectional configuration of a reflective LCD device in which capacitor C2 is constructed using an MIM capacitor.

In FIG. 15, a PMOS transistor PTr11 of the inverter INV33 and a PMOS transistor Tr2 of the switch SW32, whose drains are connected to each other by sharing a common diffusion layer, are formed on an N well 201 formed on a silicon substrate 200. Also, an NMOS transistor NTr11 of the inverter INV33 and an NMOS transistor Tr1 of the switch SW32, whose drains are connected to each other by sharing a common diffusion layer, are formed on a P well 202 formed on the silicon substrate 200. Note that the NMOS transistor and PMOS transistor constituting the inverter INV34 are not shown in FIG. 15.

Above the PMOS transistors Tr2 and PTr11, and the NMOS transistors NTr11 and Tr1, the first metal 206, the second metal 208, the third metal 210, the electrode 212, the fourth metal 214, and the fifth metal 216 are laminated with the interlayer insulating film 205 interposed between the metals. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel. The diffusion layers constituting the drains of the NMOS transistor and the PMOS transistor constituting the inverter INV34 (not shown), the gate electrode of the NMOS transistor NTr11, and the gate electrode of the PMOS transistor PTr11 are each electrically connected to the first metal 206 via a contact (not shown). Furthermore, the diffusion layers and the gate electrodes are electrically connected to the second metal 208, the third metal 210, the fourth metal 214, and the fifth metal 216 via the through holes 219a, 219b, 219c, and 219e. That is, the drains of the NMOS transistor and PMOS transistor that make up the inverter INV34 (not shown) are electrically connected to the reflective electrode PE.

Furthermore, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216) and is disposed opposite and spaced from the common electrode CE, which is a transparent electrode. Liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form the liquid crystal display element LC.

Here, an electrode 212 is formed on the third metal 210 via an interlayer insulating film 205. This electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute a capacitance C2.

When the capacitance C2 is constructed using MIM, the second signal holding circuit SM32, the switch SW31, and the switch SW32 can be constructed using transistors on the silicon substrate 200 and the first and second layer wiring of the first metal 206 and the second metal 208. In addition, the first signal holding circuit DM31 can be constructed using MIM wiring that utilizes the third metal 210 above the transistor.

The electrode 212 is electrically connected to the fourth metal 214 via the through hole 219d. Furthermore, the fourth metal 214 is electrically connected to the switches SW31 and SW32 at a location not shown.

Light from a light source (not shown) passes through the common electrode CE and liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels back along the original incident path, and is emitted through the common electrode CE.

As shown in FIG. 15, by allocating the fifth metal 216 to the reflective electrode PE, pixel Pix4 can effectively arrange the first signal hold circuit DM31, the second signal hold circuit SM32, and the reflective electrode PE in the height direction. Therefore, pixel Pix4 can achieve pixel miniaturization. As a result, pixel Pix4 can be configured with pixels with a pitch of, for example, 3 μm or less, using transistors with a power supply voltage of 3.3 V. This 3 μm pitch pixel can realize an LCD panel with a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

Pixel Pix4 performs the same operation as that described in the third embodiment together with the timing diagram of FIG. 9.

First, the switches SW31 of the pixels Pix4 in one row selected by the forward row scanning pulse and the inverted row scanning pulse output from the timing generator 62 are turned on by the forward row scanning pulse and the inverted row scanning pulse. At that time, the forward subframe gradation data output to the column data line d is sampled by the switch SW31 and written to the first signal holding circuit DM31. Thereafter, the forward subframe gradation data is written in the same manner to the first signal holding circuits DM31 of all the pixels Pix4 constituting the image display unit 61. At the timing after the writing operation is completed, a forward trigger pulse TRIG of "H" level and an inverted trigger pulse TRIGB of "L" level are simultaneously supplied to all the pixels Pix4 constituting the image display unit 61.

As a result, the switches SW32 of all pixels Pix4 are turned on. Therefore, the normal subframe gradation data stored in the first signal holding circuit DM31 is simultaneously transferred to the second signal holding circuit SM32 via the switches SW32 and held there. At the same time, the normal subframe gradation data is applied to the reflective electrode PE. The period during which the normal subframe gradation data is held by the second signal holding circuit SM32 is one subframe period until the next "H" level normal trigger pulse TRIG and "L" level inverted trigger pulse TRIGB are input.

Next, each pixel Pix4 in the image display section 61 is selected row by row by the normal row scan pulse and the inverted row scan pulse in the same manner as described above. Then, inverted subframe grayscale data having the opposite logical value to the previous normal subframe grayscale data is written to the first signal holding circuit DM31. When writing of the inverted subframe grayscale data to the first signal holding circuits DM31 of all pixels Pix4 in the image display section 61 is completed, a normal trigger pulse TRIG of "H" level and an inverted trigger pulse TRIGB of "L" level are supplied simultaneously to all pixels Pix4.

As a result, the switches SW32 of all pixels Pix4 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit DM31 is simultaneously transferred to the second signal holding circuit SM32 via the switches SW32 and held there. At the same time, the inverted subframe gradation data is applied to the reflective electrode PE. The period during which the inverted subframe gradation data is held by the second signal holding circuit SM32 is one subframe period until the next "H" level normal trigger pulse TRIG and "L" level inverted trigger pulse TRIGB are supplied.

(summary)
The pixel Pix4 has the same effects as the pixels Pix1 to Pix3 in the third to fifth embodiments.

In addition, pixel Pix4 has the advantage of being able to be miniaturized.

Seventh embodiment
FIG. 16 is a diagram showing a circuit configuration of a pixel of a reflective liquid crystal display device according to the seventh embodiment.

Of the components of pixel Pix5 of the reflective LCD device of the seventh embodiment, the same components as those of pixels Pix1 to Pix4 of the third to sixth embodiments are given the same reference numerals and will not be described.

Pixel Pix5 is located at the intersection of any one column data line d and any one row scanning line g.

Pixel Pix5 includes a first memory 141, a second memory 142, and a liquid crystal display element LC. The first memory 141 includes a switch SW41 and a first signal holding circuit DM41. The second memory 142 includes a switch SW42 and a second signal holding circuit DM42.

In pixel Pix5, the first memory 141 and the second memory 142 are composed of DRAM.

The switch SW41 corresponds to an example of a "first switching circuit" in the present disclosure. The first signal holding circuit DM41 corresponds to an example of a "first signal holding circuit" in the present disclosure. The first memory 141 corresponds to an example of a "first dynamic random access memory" in the present disclosure. The switch SW42 corresponds to an example of a "second switching circuit" in the present disclosure. The second signal holding circuit DM42 corresponds to an example of a "second signal holding circuit" in the present disclosure. The second memory 142 corresponds to an example of a "second dynamic random access memory" in the present disclosure.

The switch SW41 is composed of an NMOS transistor whose gate is connected to the row scanning line g, whose drain is connected to the column data line d, and whose source is connected to the first signal holding circuit DM11.

The first signal holding circuit DM41 is composed of a capacitor C3. Here, consider the case where the grayscale data of the column data line d and the grayscale data of the first signal holding circuit DM41 are different. When the switch SW41 is turned on and the grayscale data of the column data line d is transferred to the first signal holding circuit DM41, it is necessary to rewrite the grayscale data of the first signal holding circuit DM41 with the grayscale data of the column data line d.

When the grayscale data of the capacitance C3 constituting the first signal holding circuit DM41 is rewritten, the grayscale data changes by charging or discharging. When the grayscale data of the column data line d is transferred to the capacitance C3, the grayscale data is written by charge transfer between the data line capacitance of the column data line d and the capacitance C3. Typically, the capacitance ratio between the data line capacitance of the column data line d and the capacitance C3 is large, about 1000:1. Therefore, the pixel Pix5 can reliably rewrite the grayscale data of the capacitance C3.

The switch SW42 is composed of an NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the first signal holding circuit DM41, and whose source is connected to the second signal holding circuit DM42 and the reflective electrode PE.

The second signal holding circuit DM42 is composed of a capacitor C4. Here, consider the case where the gradation data of the first signal holding circuit DM41 and the gradation data of the second signal holding circuit DM42 are different. When the switch SW42 is turned on and the capacitors C3 and C4 are conductive, it is necessary to rewrite the gradation data of the second signal holding circuit DM42 with the gradation data of the first signal holding circuit DM41.

When the charge level of the capacitance C3 (grayscale data of the first signal holding circuit DM41) differs from the charge level of the capacitance C4 (grayscale data of the second signal holding circuit DM42), charge neutralization occurs. Therefore, in the present disclosure, the capacitance C3 is made larger than the capacitance C4. In other words, C3>C4. For example, when the capacitance C3 holds "H" level grayscale data and the capacitance C4 holds "L" level grayscale data, charge neutralization occurs. However, by making C3>C4, even if charge neutralization occurs, the voltage after neutralization can be made higher than the threshold voltage. In other words, it is possible to write "H" level grayscale data to the capacitance C4. This allows the pixel Pix5 to reliably rewrite the grayscale data of the capacitance C4 with the grayscale data of the capacitance C3.

Note that switches SW41 and SW42 may be configured with PMOS transistors. In that case, they can be considered to have the opposite polarity to that described above, so illustrations and explanations will be omitted.

In addition, switches SW41 and SW42 may be transmission gates composed of PMOS and NMOS transistors.

The pixel Pix5 has the effect of being miniaturized. The first reason is as follows. The pixel Pix5 is composed of a total of two transistors and two capacitors C3 and C4. In other words, the pixel Pix5 can be composed of a smaller number of elements than the pixel Pix1 (total of 12 transistors), the pixel Pix2 (total of 10 transistors), the pixel Pix3 (total of 7 transistors and 1 capacitor), and the pixel Pix4 (total of 8 transistors and 1 capacitor). The second reason is that the first signal holding circuit DM41, the second signal holding circuit DM42, and the reflective electrode PE can be effectively arranged in the height direction of the element, as described below.

Figure 17 shows the cross-sectional structure of a pixel in a reflective LCD device according to the seventh embodiment.

Capacitors C3 and C4 can be MIM capacitors, diffusion capacitors, PIP capacitors, etc. Figure 17 shows the cross-sectional configuration of a reflective LCD device in which capacitors C3 and C4 are constructed using MIM.

In FIG. 17, an NMOS transistor of switch SW41 is formed on a P-well 202 formed on a silicon substrate 200. The drain of the NMOS transistor of switch SW41 is electrically connected to a column data line d (not shown) via contact 218a and first metal 206.

The NMOS transistor of switch SW42 is formed on a P-well 203 formed on the silicon substrate 200. The drain of the NMOS transistor of switch SW42 is electrically connected to the source of the NMOS transistor of switch SW41 via contact 218b and first metal 206.

Above the NMOS transistor of switch SW41 and the NMOS transistor of switch SW42, a first metal 206, a second metal 208, a third metal 210, an electrode 212, a fourth metal 214, and a fifth metal 216 are laminated with an interlayer insulating film 205 interposed between the metals. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel.

Furthermore, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216) and is disposed opposite and spaced from the common electrode CE, which is a transparent electrode. Liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form the liquid crystal display element LC.

Here, electrodes 212a and 212b are formed on the third metal 210 via an interlayer insulating film 205. The electrode 212a, the third metal 210, and the interlayer insulating film 205 between the electrode 212a and the third metal 210 form a capacitance C3. The electrode 212b, the third metal 210, and the interlayer insulating film 205 between the electrode 212b and the third metal 210 form a capacitance C4.

Here, electrode 212a is larger than electrode 212b. This makes capacitance C3 larger than capacitance C4. In other words, C3>C4.

When the capacitors C3 and C4 are constructed using MIM, the switches SW41 and SW42 can be constructed using transistors on the silicon substrate 200 and first and second layer wiring of the first metal 206 and second metal 208. The first signal holding circuit DM41 and second signal holding circuit DM42 can be constructed using MIM wiring that utilizes the third metal 210 above the transistors.

The source of the NMOS transistor of switch SW41 is electrically connected to electrode 212a via contact 218c and through holes 219d, 219e, 219f, and 219g. The third metal 210 facing electrode 212a is electrically connected to the reference potential (ground potential) via through hole 219h.

The source of the NMOS transistor of switch SW42 is electrically connected to electrode 212b via contact 218d and through holes 219j, 219k, 219l, and 219m. The third metal 210 facing electrode 212b is electrically connected to the reference potential (ground potential) via through hole 219n. Electrode 212b is electrically connected to the reflective electrode PE via through holes 219m and 219o.

Light from a light source (not shown) passes through the common electrode CE and liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels back along the original incident path, and is emitted through the common electrode CE.

As shown in FIG. 17, by allocating the fifth metal 216 to the reflective electrode PE, pixel Pix5 allows the first signal hold circuit DM41 and second signal hold circuit DM42, and the reflective electrode PE to be effectively positioned in the height direction. Therefore, pixel Pix5 can achieve pixel miniaturization. As a result, pixel Pix5 can be configured with pixels having a pitch of, for example, 3 μm or less, using transistors with a power supply voltage of 3.3 V. This 3 μm pitch pixel can realize an LCD panel with a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

Pixel Pix5 performs the same operation as that described in the third embodiment together with the timing diagram of FIG. 9.

First, the switches SW41 of the pixels Pix5 in one row selected by the forward row scan pulse output from the timing generator 62 are turned on by the forward row scan pulse. At that time, the forward subframe gradation data output to the column data line d is sampled by the switch SW41 and written to the first signal holding circuit DM41. Thereafter, the forward subframe gradation data is written in the same manner to the first signal holding circuits DM41 of all the pixels Pix5 constituting the image display unit 61. At the timing after the writing operation is completed, a forward trigger pulse TRIG of "H" level is supplied simultaneously to all the pixels Pix5 constituting the image display unit 61.

As a result, the switches SW42 of all the pixels Pix5 are turned on. Therefore, the non-inverted subframe gradation data stored in the first signal holding circuit DM41 is
2, the normal subframe grayscale data is simultaneously transferred to and held in the second signal holding circuit DM42. At the same time, the normal subframe grayscale data is applied to the reflective electrode PE. The period during which the normal subframe grayscale data is held by the second signal holding circuit DM42 is one subframe period until the next "H" level normal trigger pulse TRIG is input.

Next, each pixel Pix5 in the image display unit 61 is selected row by row by the forward row scanning pulse in the same manner as described above, and inverted subframe grayscale data of the opposite logical value to the immediately preceding forward subframe grayscale data is written to the first signal holding circuit DM41 for each pixel Pix5. When writing of the inverted subframe grayscale data to the first signal holding circuit DM41 for all pixels Pix5 constituting the image display unit 61 is completed, a forward trigger pulse TRIG of "H" level is supplied simultaneously to all pixels Pix5 constituting the image display unit 61.

As a result, the switches SW42 of all the pixels Pix5 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit DM41 is
2, the inverted subframe grayscale data is simultaneously transferred to the second signal holding circuit DM42 and held therein. At the same time, the inverted subframe grayscale data is applied to the reflective electrode PE. The holding period of the inverted subframe grayscale data by the second signal holding circuit DM42 is one subframe period until the next "H" level normal trigger pulse TRIG is supplied.

(summary)
The pixel Pix5 has the same effects as the pixels Pix1 to Pix4 in the third to sixth embodiments.

In addition, pixel Pix5 has the effect of being able to be miniaturized. Although pixel Pix5 may experience the above-mentioned charge neutralization and has lower noise resistance than SRAM, it can be made even smaller than pixels Pix1 to Pix4. Therefore, it is only necessary to decide which of pixels Pix1 to Pix5 to adopt depending on the specifications required for the reflective liquid crystal display device 13 (e.g., priority given to miniaturization, priority given to noise resistance, etc.).

<Additional Notes>
3, the pixels in the portion 13a where the diffused wavelength channels are incident are inverted every subframe period. However, the pixels in the portion (frame portion) 13b where the diffused wavelength channels are not incident do not need to be inverted every subframe. From the viewpoint of power consumption, it is better to reduce the number of inversions.

Therefore, the common electrode CE may be divided into portions 13a and 13b, which may be driven separately, to reduce the number of inversions in portion 13b. In this case, portion 13a may be inverted every subframe, but portion 13b may not be inverted for a predetermined number of frames (in other words, inversion may be performed every predetermined number of frames).

In this case, if the pixel in portion 13b has a configuration like pixel Pix3 (see FIG. 12), the potential of the reflective electrode PE drops if there is a charge leak from the capacitance C1. Therefore, it is a good idea to turn on the forward trigger pulse TRIG and the inverted trigger pulse TRIGB at regular intervals to perform a rewrite operation to the capacitance C1. Alternatively, it is a good idea to reduce the number of frames required until inversion compared to other pixel circuit configurations.

In addition, it is better to write part 13b to the first memory as close to the inversion as possible. If the contents of the first memory 111 and the second memory 121 are inverted, a leakage current will occur through the switch SW21, increasing power consumption.

Note that in the configuration of pixel Pix1 (see Figure 6), writing to the first memory 91 can be performed most quickly, so it is better to rewrite the contents of the first memory 91 immediately before.

The technical scope of the present invention is not limited to the above-described embodiments, and appropriate modifications can be made without departing from the spirit of the present invention.

REFERENCE SIGNS LIST 10 WSS array 11 Input/output section 12 Optical system 13 Reflective liquid crystal display device 16 Collimator lens 21, 22, 23 Lens 24 Dispersion element 61 Image display section 62 Timing generator 63 Vertical shift register 64 Data latch circuit 65 Horizontal driver 65a Horizontal shift register 65b Latch circuit 65c Level shifter/pixel driver 81, 91, 111, 131, 141 First memory 81a, 82a, SW11a, SW11b, SW12a, SW12b, SW13, SW14, SW21, SW31, SW32, SW41, SW42 Switch 81b, SM11, SM13, DM31, DM41 First signal holding circuit 82, 92, 112, 121, 132, 142 Second memory 82b, SM12, SM14, DM21, SM32, DM42 Second signal holding circuit INV1, INV2, INV3, INV4, INV11, INV12, INV13, INV14, INV33, INV34 Inverter Pix, Pix1, Pix2, Pix3, Pix4, Pix5 Pixel PT1, PT2 PMOS transistor NT1, NT2 NMOS transistor C1, C2, C3, C4 Capacitor LC Liquid crystal display element LCM Liquid crystal PE Reflective electrode CE Common electrode

Claims (7)

an input/output unit having an input port for receiving incident light and an output port for emitting output light corresponding to each wavelength contained in the incident light;
a wavelength disperser that spatially disperses light of each wavelength included in the incident light according to the wavelength and outputs the output light to the input/output unit;
an optical coupler that collects the light of each wavelength dispersed by the wavelength disperser onto a two-dimensional plane for each wavelength and outputs the reflected light of each wavelength toward the wavelength disperser;
a spatial light modulator that is arranged at a position on the two-dimensional plane, has a plurality of pixels, and expresses gradations using the plurality of pixels, thereby reflecting the light of each wavelength collected by the optical combiner in a direction determined by routing for each wavelength;
a spatial light modulator driver that drives the plurality of pixels of the spatial light modulator;
a common electrode divided into a first common electrode which is an area where the incident light is incident and a second common electrode which is an area where the incident light is not incident;
Equipped with
the gradation is formed by inputting non-inverted gradation data to each of the plurality of pixels during one subframe period among a plurality of subframe periods obtained by dividing one frame period, and inputting inverted gradation data to another subframe period of the plurality of subframe periods by the spatial light modulator driving unit;
Each of the plurality of pixels is
a first switching circuit for sampling the non-inverted gray scale data or the inverted gray scale data from a data line;
a first signal holding circuit that holds the non-inverted grayscale data or the inverted grayscale data sampled by the first switching circuit;
a second switching circuit that samples the non-inverted grayscale data or the inverted grayscale data held in the first signal holding circuit at a timing common to all of the plurality of pixels;
a second signal holding circuit for holding the non-inverted gray scale data or the inverted gray scale data sampled by the second switching circuit for one subframe period and applying the data to a reflective electrode of a liquid crystal display element;
Equipped with
The spatial light modulator driving unit
applying a positive/negative AC voltage to the liquid crystal of the liquid crystal display element by inverting the voltage of the first common electrode of the liquid crystal display element at the timing;
applying a positive/negative AC voltage to the liquid crystal of the liquid crystal display element by inverting a voltage of the second common electrode of the liquid crystal display element every predetermined number of subframes;
supplying a voltage having an amplitude different from an amplitude between the normal grayscale data and the inverted grayscale data to the common electrode;
the first switching circuit and the first signal holding circuit constitute a first dynamic random access memory;
the second switching circuit and the second signal holding circuit constitute a first static random access memory;
The first signal holding circuit is composed of a capacitance.
Optical node equipment. The first switching circuit is a complementary switching circuit composed of a P-channel transistor and an N-channel transistor.
The optical node device according to claim 1 . The first switching circuit is composed of one transistor.
The optical node device according to claim 1 . the second signal holding circuit is composed of a first inverter and a second inverter, one of whose output terminals is connected to the other of whose input terminals;
a driving force of a transistor constituting the first inverter on the input side as viewed from the second switching circuit side is greater than a driving force of a transistor constituting the second inverter on the output side as viewed from the second switching circuit side;
The optical node device according to claim 1 . the second switching circuit is a complementary switching circuit configured with a P-channel transistor and an N-channel transistor;
The optical node device according to claim 1 . The second switching circuit is composed of one transistor.
The optical node device according to claim 1 . The spatial light modulator driving unit
The number of frames of pixels in an area of the spatial light modulator where the light is not incident is made smaller than the number of frames of pixels in an area of the spatial light modulator where the light is incident.
The optical node device according to claim 1 .

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