JP7532567B2 - Display device - Google Patents

Description

The present invention relates to an electronic display (electro-optical device) formed by fabricating EL (electroluminescence) elements on a substrate, in particular to a display device using semiconductor elements (elements using semiconductor thin films), and to an electronic device using an EL display device in its display section.

In recent years, the technology of forming thin film transistors (hereinafter referred to as TFTs in this specification) on a substrate has made great progress, and the application and development of TFTs to active matrix display devices is being promoted. In particular, TFTs using polycrystalline semiconductor films such as polysilicon have higher field effect mobility (also called mobility) than conventional TFTs using amorphous semiconductor films such as amorphous silicon, and therefore can operate at high speed. As a result, it is now possible to control pixels using a drive circuit formed on the same substrate as the pixels, instead of using a drive circuit outside the substrate.

In an active matrix display device using such a polycrystalline semiconductor film, it is possible to fabricate various circuits and elements on the same substrate, which provides various advantages such as reduced manufacturing costs, smaller display devices, increased yields, and improved throughput.

Furthermore, research into active matrix EL display devices having EL elements as self-luminous elements is becoming more active. EL display devices are also known as organic EL displays (OELDs).
Organic Light Emitting Diode (OL)
It is also called ED (Organic Light Emitting Diode).

An EL element has a structure in which an EL layer is sandwiched between a pair of electrodes (anode and cathode).
The layers are usually of a laminated structure. A representative example is the laminated structure of "hole transport layer, light emitting layer, electron transport layer" proposed by Tang et al. of Kodak Eastman Company. This structure has very high light emitting efficiency, and most of the EL display devices currently being researched and developed adopt this structure.

Alternatively, a structure in which a hole injection layer, a hole transport layer, a light emitting layer, and an electron transport layer are laminated on an anode in this order, or a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer may be laminated on the anode in this order. The light emitting layer may be doped with a fluorescent dye or the like.

In this specification, all layers provided between the cathode and the anode are collectively referred to as the EL layer.
Therefore, the above-mentioned hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer, etc. are all E
It is included in the L layer.

When a predetermined voltage is applied to the EL layer having the above structure from a pair of electrodes, recombination of carriers occurs in the light-emitting layer, causing light to be emitted. In this specification, the act of an EL element emitting light is referred to as the EL element being driven. In this specification, a light-emitting element formed by an anode, an EL layer, and a cathode is referred to as an EL element.

In this specification, the EL element includes both those that utilize light emission from a singlet excited state (fluorescence) and those that utilize light emission from a triplet excited state (phosphorescence).

Methods for driving an EL display device include an analog driving method (analog driving) and a digital driving method (digital driving). First, the analog driving method of an EL display device will be described with reference to FIGS.

1 shows the structure of a pixel section 100 of an analog-driven EL display device. Gate signal lines (G1 to Gy) that input selection signals from a gate signal line driving circuit are connected to the gate electrode of a switching TFT 101 of each pixel. One of the source region and drain region of the switching TFT 101 of each pixel is connected to a source signal line (also called a data signal line) (S1 to Sx) that inputs an analog video signal, and the other is connected to the gate electrode of a driving TFT 104 of each pixel and a storage capacitor 108 of each pixel.

The source region and the drain region of the driving TFT 104 of each pixel are connected to a power supply line (V1 to Vx) on one side and to an EL element 106 on the other side.
The potentials of the power supply lines (V1 to Vx) are called power supply potentials. The power supply lines (V1 to Vx) are connected to the storage capacitors 108 of the respective pixels.

The EL element 106 has an anode, a cathode, and an EL layer provided between the anode and the cathode. When the anode of the EL element 106 is connected to the source region or the drain region of the driving TFT 104, the anode of the EL element 106 becomes a pixel electrode, and the cathode becomes a counter electrode.
When the cathode of the TFT 06 is connected to the source region or drain region of the driving TFT 104,
The anode of the EL element 106 serves as a counter electrode, and the cathode serves as a pixel electrode.

In this specification, the potential of the counter electrode is called the counter potential. The power source that provides the counter potential to the counter electrode is called the counter power source. The potential difference between the potential of the pixel electrode and the potential of the counter electrode is the EL drive voltage, and this EL drive voltage is applied to the EL layer.

Fig. 2 shows a timing chart for the EL display device shown in Fig. 1 when it is driven in an analog manner. The period from when one gate signal line is selected to when another gate signal line is selected next is called one line period (L). Also, the period from when one image is displayed to when the next image is displayed corresponds to one frame period (F). In the case of the EL display device in Fig. 1, there are y gate signal lines, so y line periods (L1 to Ly) are provided during one frame period.

First, the power supply lines (V1 to Vx) are maintained at a constant power supply potential. The counter potential, which is the potential of the counter electrode, is also maintained at a constant potential. The counter potential has a potential difference with the power supply potential that is sufficient to cause the EL element to emit light.

In the first line period (L1), a selection signal is input to the gate signal line G1 from the gate signal line driving circuit. Analog video signals are input to the source signal lines (S1 to Sx) in sequence. Since all switching TFTs connected to the gate signal line G1 are turned on, the analog video signal input to the source signal line is input to the gate electrode of the driving TFT via the switching TFT.

The amount of current flowing through the channel forming region of the driving TFT is controlled by the gate voltage.

Here, an example will be described in which the source region of the driving TFT is connected to a power supply line and the drain region is connected to an EL element.

Since the source region of the driving TFT is connected to the power supply line, the same potential is input to each pixel of the pixel section. When an analog signal is input to the source signal line, the difference between the potential of this signal voltage and the potential of the source region of the driving TFT becomes the gate voltage.
The current flowing through the element is determined by the gate voltage of the driving TFT. The luminance of the EL element is proportional to the current flowing between the two electrodes of the EL element. Thus, the EL element emits light under the control of the voltage of an analog video signal.

The above-mentioned operation is repeated, and when the input of the analog video signals to the source signal lines (S1 to Sx) is completed, the first line period (L1) is completed.
The period until the input of the analog video signal to the gate signal line Gx is completed and the horizontal blanking period may be combined to form one line period.
As in the first line period (L1), a selection signal is input to the source signal lines (S1 to
Sx) in turn receive analog video signals.

When the selection signal is input to all the gate signal lines (G1 to Gy), all the line periods (L
When all the line periods (L1 to Ly) are completed, one frame period is completed. During one frame period, all pixels perform display and one image is formed. Note that one frame period may be a combination of all the line periods (L1 to Ly) and the vertical blanking period.

As described above, the amount of light emitted by the EL element is controlled by an analog video signal, and the gradation display is achieved by controlling the amount of light emitted. This method is a driving method known as an analog driving method, and the gradation display is achieved by changing the voltage of the analog video signal input to the source signal line.

Next, a digital drive of the EL display device will be described. In the digital gray scale method, the gate-source voltage Vg of the EL drive TFT 104 is set to a value between two values, that is, a range where no current flows through the EL element 106 (below the lighting start voltage) and a range where the maximum current flows (above the brightness saturation voltage).
That is, the EL element can only be in a lit or unlit state.

EL displays mainly use a digital gray scale method, which is less susceptible to variations in characteristics such as the threshold value of TFTs, etc. However, since the digital gray scale method can only display two gray scales as it is, several technologies have been proposed to combine it with other methods to achieve multiple gray scales.

One of them is a method that combines area gray scale and digital gray scale. Area gray scale is a method that produces gray scale by controlling the area of the lit part.
A pixel is divided into multiple sub-pixels, and the number and area of the sub-pixels that are turned on are controlled to express gradation. The drawback of this method is that it is difficult to increase the number of sub-pixels, making it difficult to achieve high resolution or multiple gradations.
, Non-Patent Document 2, and other publications.

Another method for achieving multiple gradations is to combine the time gradation method and the digital gradation method. The time gradation method is a method for producing gradations by utilizing the difference in the time for which the display is turned on. In other words, one frame period is divided into multiple subframe periods, and the number and length of the subframe periods in which the display is turned on are controlled to produce gradations (see Patent Document 1).

A combination of the digital gray scale method, the area gray scale method and the time gray scale method is reported in Non-Patent Document 3.

Next, constant current driving and constant voltage driving in the case of gray scale display using digital gray scale will be described.

The constant current drive is a drive method in which the drive TFT 104 is operated in a saturation region when the EL element 106 is turned on, and a constant current is supplied to all pixels.
Even if the voltage-current characteristic changes due to deterioration, a constant current can be supplied to the EL element 106, which has the advantage of extending the life of the EL display device.

On the other hand, the constant voltage drive is a drive method in which the drive TFT 104 is operated in a linear region when the EL element 106 is lit, and a constant voltage is supplied to all pixels.
Even if the characteristics of the FT 104 vary, a constant voltage can be supplied to the EL element 106 in all pixels, so there is an advantage that there is no unevenness in the luminance between pixels and high display quality can be obtained.

Japanese Patent Application Publication No. 2001-324958

Euro Display 99 Late News: P71:”TFT-LEPDwith Image Uniformity by Area Ratio Gray Scale” IEDM 99: P107: “Technology for Active Matrix Light Emitting Polymer Displays” IDW’99: P171: “Low-Temperature Poly-Si TFT Driven Light-Emitting-Polymer Displays and Digital Gray Scale for Uniformity”

The object of the present invention is to provide a large-sized, high-resolution EL device that can be manufactured with high yield and low cost.
The object of the present invention is to provide a display device. However, there are some problems to be solved in order to achieve this object.

First, problems associated with combining digital gray scale and time gray scale as a driving method for an EL display device will be described. When digital gray scale and time gray scale are combined, in order to express multiple gray scales, one frame period is divided into multiple subframe periods, and the number and length of the subframe periods that are turned on are controlled to express gray scales. In other words, compared to the time that can be spent to display one image with analog gray scale, when digital gray scale and time gray scale are combined, the time that can be spent to display one picture is one times the number of subframes, and the driving circuit must operate at a much higher speed than with analog gray scale.

In addition, there is a limit to the operating frequency of the driving circuit, and if the number of subframes is too large or the resolution is high, the writing time becomes insufficient. In other words, one of the problems when digital grayscale and time grayscale are combined as a driving method for a display device is the lack of writing time. In order to achieve the object of the present invention, it is necessary to make the writing time as long as possible.

Next, the problem of increased parasitic capacitance will be described. The larger the display device and the higher the resolution, the longer the wiring in the pixel area becomes, and the more wirings cross the longer the wiring becomes, so the parasitic capacitance of the wiring in the pixel area becomes large.

When the parasitic capacitance increases, it causes the waveform of the electric signal transmitted through the wiring to become more distorted. The distorted waveform prevents the signal from being transmitted correctly, resulting in a decrease in display quality.
One of the problems in obtaining a large-sized EL display device with high resolution is an increase in parasitic capacitance.
To achieve the object of the present invention, the parasitic capacitance must be made as small as possible.

Next, we will discuss the problems involved in producing them at low cost. Currently, TFTs and electronic circuits using them are generally manufactured by laminating various thin films of semiconductors, insulators, conductors, etc. on a substrate and forming a predetermined pattern using appropriate photolithography technology. Photolithography is a technology that uses light to transfer a circuit pattern, etc., formed on a transparent flat surface called a photomask using a material that does not transmit light, onto the target substrate, and is widely used in the manufacturing process of semiconductor integrated circuits, etc.

The manufacturing process using photolithography requires many steps, including exposure, development, baking, and processing, just to handle the mask pattern formed using a photosensitive organic resin material called photoresist.
Therefore, the more photolithography steps are required, the higher the manufacturing cost will be.

Next, the problem of wiring resistance will be described. First, a case where analog driving is used as a driving method for an EL display device will be described.

3 is a graph showing the characteristics of a driving TFT in the saturation region (Vds>Vg-Vth). Here, Vds is the source-drain voltage, Vg is the gate-source voltage, and Vth is the threshold voltage. 301 is called the Id-Vg characteristic (or Id-Vg curve). Here, Id is the drain current. This graph makes it possible to know the amount of current that flows for an arbitrary gate voltage.

In the analog driving method, the saturation region is used in the driving TFT, and the drain current is changed by changing the gate voltage.

When the switching TFT is turned on, the analog video signal input from the source signal line into the pixel is applied to the gate electrode of the driving TFT. This changes the gate voltage of the driving TFT. At this time, the drain current is determined one-to-one with respect to the gate voltage according to the Id-Vg characteristics shown in Figure 3. Thus, a predetermined drain current flows through the EL element in response to the voltage of the analog video signal input to the gate electrode of the driving TFT, and the EL element emits light with an amount of light corresponding to the amount of current.

As described above, the amount of light emitted by the EL element is controlled by an analog video signal, and gradation display is achieved by controlling the amount of light emitted.

Here, the gate voltage of the driving TFT of each pixel changes when the potential of the source region of the driving TFT changes, even if the same signal is input from the source signal line. Here, the potential of the source region of the driving TFT is provided from the power supply line. However, the potential of the power supply line changes depending on the position inside the pixel section due to a potential drop caused by wiring resistance.

In addition, when the wiring resistance of the power supply line is small, or when the display device is relatively small,
When the current flowing through the power supply line is relatively small, this does not pose much of a problem. However, when this is not the case, particularly when the display device is relatively large, the change in potential of the power supply line due to this wiring resistance becomes large.

In particular, the larger the display device, the greater the variation in the distance from the external input terminal to each power supply line of the pixel section, and therefore the greater the variation in the wiring length of the power supply line wiring section, which results in a greater change in the potential of the power supply line due to a potential drop in the power supply line wiring section.

The potential variations in the power supply lines due to these factors affect the luminance of the EL element of each pixel, causing a change in the display luminance, resulting in uneven display.

Below is a specific example of the potential variation of the power supply line.

As shown in Figure 4, when a white or black box is displayed on the display screen, a phenomenon called crosstalk occurs, in which a difference in luminance occurs between the area above or below the box and the area to the side of the box.

Crosstalk occurs when the driving transistors are connected to the upper and lower pixels of the box and in the horizontal direction.
This occurs due to a difference in the current flowing through the FT 104. The cause of this difference is that the power supply lines V1 and V2 are arranged in parallel with the source signal lines S1 and S2.

For example, as shown in FIG. 4, when a white box is displayed on a part of the display screen, in the power supply line corresponding to the pixel that displays this box, a current flows to the EL element via the source and drain of the driving TFT of the pixel that displays the box, and the potential drop due to the wiring resistance of this power supply line is larger than that of a power supply line that supplies power only to pixels that do not display a box.
Therefore, there are some pixels above and below the box that are darker than other pixels that are not boxed.
Here, when the size of the display screen of the display device is small, no problem occurs. However, when the size of the display screen of the display device becomes large, the EL
The total current flowing through the elements increases.

For example, when comparing the sum of currents flowing through the EL elements of a display device having a 4-inch diagonal display screen with a display device having a 20-inch diagonal display screen, the area of the latter display screen is 25 times that of the former, so the sum of currents flowing through the EL elements is also approximately 25 times larger.

Therefore, in a display device having a large display screen, the above-mentioned problem of potential drop becomes a major issue.

For example, in a 20-inch display device, even if the wiring length is 700 mm, the wiring width is 10 mm, and the sheet resistance is 0.1 ohms, when a current of about 1 A flows, the potential drop becomes 10 V, making normal display impossible.

Next, a problem with wiring resistance when constant voltage driving is used in digital driving as a driving method for an EL display device will be described.

When constant voltage driving is used, the voltage supplied to the EL element 106 is constant for each pixel.
The luminance of each pixel is not affected by the characteristic variation of the driving TFT 104, and an EL display device having a display capability of very high image quality can be obtained. However, if the wiring resistance is large,
It becomes impossible to satisfy the condition required for constant voltage driving, that is, the voltage supplied to the EL element 106 must be constant for each pixel. This will be described with reference to FIGS.

Fig. 5A shows a case where one-third of the total number of pixels are lit at the same time, while Fig. 5B shows a case where two-thirds of the total number of pixels are lit at the same time.

Since the number of pixels that are lit at the same time is different between FIG. 5A and FIG. 5B, the current value that flows through the power supply lines (V1 to Vx) of the pixel unit when lit is different between FIG. 5A and FIG. 5B.
) Here, if there is a wiring resistance in the power supply lines (V1 to Vx) of the pixel section, the voltage drops according to the magnitude of the current value.
The voltage supplied to each pixel is different between FIG. 5B and FIG. 5C. The difference in the voltage supplied means that the luminance of the EL element is different between the display shown in FIG. 5A and the display shown in FIG.
This means that the display will be different from that shown in FIG. 5B.

The change in luminance per pixel due to the lighting rate of the display image has an adverse effect when displaying gradations by time gradation. For example, in FIG.
5A ) are displayed continuously for the same period of time to display three gradations. In this case, gradation 0 should be displayed in display area 503, gradation 2 in display area 504, and gradation 1 in display area 505. However, if there is wiring resistance, the luminance per pixel in FIG. 5A is greater than that in FIG. 5B , and so the gradation displayed in area 505 is smaller than 1. In this way, if there is wiring resistance, the intended gradation cannot be obtained when constant voltage driving is used in digital driving.

This difference in brightness increases as the wiring resistance of the power supply lines (V1 to Vx) increases. Furthermore, the larger the display device, the longer the power supply lines become, and the greater the wiring resistance becomes. In other words, one of the problems in obtaining a large, high-resolution EL display device is an increase in wiring resistance. In order to achieve the object of the present invention, the wiring resistance must be made as small as possible.

The present invention has been made in consideration of the above problems, and has an object to provide an active matrix EL display device capable of clear multi-tone color display, and a high-performance electronic device using such an active matrix EL display device.

The object of the present invention is to provide a large-sized, high-resolution EL device that can be manufactured with high yield and low cost.
The object of the present invention is to provide a display device. As a means for achieving this object, the configuration of the present invention will be described below.

The configuration of the present invention is characterized in that the display device has a plurality of source signal lines, a plurality of gate signal lines, a plurality of power supply lines in a row direction, a plurality of power supply lines in a column direction, and a plurality of pixels in a matrix, each of the plurality of pixels having a switching thin film transistor, a driving thin film transistor, and a light-emitting element, each of the plurality of pixels being connected to one of the plurality of power supply lines in the row direction and one of the plurality of power supply lines in the column direction, and an insulating thin film being formed in a portion below at least one of the plurality of source signal lines, the plurality of gate signal lines, the plurality of power supply lines in the row direction, and the plurality of power supply lines in the column direction.

In the above invention, the electrodes of the switching thin film transistors or the electrodes of the driving thin film transistors may be formed by a droplet discharge method or a printing method. Any one of the source signal lines, the gate signal lines, the row power supply lines, and the column power supply lines may be formed by a droplet discharge method or a printing method, or may be formed by a sputtering method or a C
The CVD method may be a plasma CVD method (RF plasma CVD method, microwave CVD method, electron cyclotron resonance CVD method, hot filament CVD method, etc.).
This includes the CVD method, the LPCVD method, and the thermal CVD method.

In addition, insulating thin films may be formed by droplet ejection or printing methods.

Another configuration of the present invention is characterized in that a plurality of source signal lines are formed, a plurality of gate signal lines are formed, and a plurality of pixels in a matrix are formed, each of the plurality of pixels having a switching thin film transistor, a driving transistor, and a light-emitting element, a plurality of power supply lines are formed in a row direction, and a plurality of power supply lines are formed in a column direction, and each of the plurality of pixels is connected to one of the plurality of power supply lines in the row direction and one of the plurality of power supply lines in the column direction by a droplet discharge method or a printing method.

In the above invention, an insulating thin film may be formed by a droplet discharge method or a printing method under at least one of the source signal lines, the gate signal lines, the power supply lines in the row direction, and the power supply lines in the column direction. Any one of the source signal lines, the gate signal lines, the power supply lines in the row direction, and the power supply lines in the column direction may be formed by a droplet discharge method or a printing method, or may be formed by a sputtering method or a CVD method.

Another configuration of the present invention is characterized in that a source signal line, a gate signal line, a power supply line, a switching thin film transistor, a driving thin film transistor, and a pixel including a light-emitting element are formed, and an insulating thin film is formed in a portion below at least one of the source signal line, the gate signal line, and the power supply line.

In the above invention, the insulating thin film may be formed by a droplet discharge method or a printing method, and any one of the source signal line, the gate signal line, and the power supply line may be formed by a droplet discharge method or a printing method, or may be formed by a sputtering method or a CVD method.

The present invention also relates to a personal computer, a television receiver, a camera, an image display device, a head mounted display, and a mobile information terminal, which use the display device according to the above invention.

According to the present invention, a large-sized, high-resolution EL device can be manufactured with good yield and low cost.
It is possible to provide a display device. In addition, since the signal writing time can be increased, accurate signals can be input to the pixels, and a clear image can be displayed. In addition, since the influence of wiring resistance can be reduced, image quality defects caused by wiring resistance can be reduced.

FIG. 2 is a diagram illustrating a pixel circuit of an EL display device. FIG. 4 is a diagram for explaining the drive timing of analog driving. FIG. 4 is a diagram illustrating driving TFT characteristics. FIG. 13 is a diagram for explaining crosstalk caused by box display. 1A and 1B are diagrams for explaining the influence of a potential effect due to wiring resistance of a power supply line; 1A and 1B are diagrams illustrating a structure for reducing parasitic capacitance between wirings. 1A and 1B are diagrams for explaining shapes that cause variations in wiring resistance; FIG. 1 is a diagram illustrating a first embodiment of the present invention. FIG. 11 is a diagram illustrating a second embodiment of the present invention. FIG. 11 is a diagram for explaining a third embodiment of the present invention. FIG. 13 is a diagram for explaining a fourth embodiment of the present invention. FIG. 13 is a diagram for explaining a fifth embodiment of the present invention. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A and 1B are diagrams illustrating a configuration of a droplet ejection device that can be applied to the present invention. FIG. 1 is a top view of a pixel circuit of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a display device that can be applied to the present invention. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a manufacturing method of a display device to which the present invention can be applied. 1A to 1C are diagrams illustrating a display device to which the present invention can be applied. 1 is a top view of a panel which is one embodiment of a semiconductor device to which the present invention is applied. FIG. 1 is a block diagram showing a main configuration of an electronic device of the present invention. 1 is a diagram showing an electronic device to which the present invention is applied; 1 is a diagram showing an electronic device to which the present invention is applied; 1 is a diagram showing an electronic device to which the present invention is applied;

The embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted.

In the present invention, there is no limitation on the type of transistor that can be applied, and examples thereof include thin film transistors (TFTs) using non-single crystal semiconductor films, such as amorphous silicon and polycrystalline silicon,
The transistors may be MOS transistors, junction transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, or other transistors formed using a semiconductor substrate or an SOI (Silicon On Insulator) substrate. There is no limitation on the type of substrate on which the transistors are disposed, and the substrate may be a single crystal substrate, an S
It can be disposed on an OI substrate, a glass substrate, or the like.

(Embodiment 1)
The embodiment of the present invention will be described with reference to Figs. 13, 14, 15, 16, 8 and 6. First, one of the problems to be overcome in the present invention is to manufacture an EL display device at low cost. In order to realize the cost reduction, the photolithography process is eliminated to reduce the number of T
Attempts have been made to produce FT.

As a method for reducing the number of photolithography steps, a method for producing a display device has been devised in which at least one or more of the patterns required for producing a display panel, such as a conductive layer for forming a wiring layer or an electrode, and a mask layer for forming a predetermined pattern, are formed by a method capable of selectively forming a pattern. As a method capable of selectively forming a pattern, a droplet discharge method (also called an inkjet method depending on the method) capable of selectively discharging droplets of a composition prepared for a specific purpose to form a predetermined pattern has been devised. In addition, a method capable of transferring or depicting a pattern, such as a printing method (a method for forming a pattern, such as screen printing or offset printing), can be used to achieve low costs. That is, one of the problems in obtaining an EL display device at low cost is the large number of photolithography steps. In order to achieve the object of the present invention, the number of photolithography steps must be reduced as much as possible. As a method for this purpose, a method capable of selectively forming a pattern is effective.

Therefore, in this embodiment, the selectively patternable EL device described below is used.
The EL display device is manufactured by a droplet discharge method, which is one of the manufacturing methods of a display device, however, this is only an example and the present embodiment is not limited to this method.

First, a method for manufacturing a display device having a channel protective thin film transistor in which a means for improving adhesion is applied to manufacture a gate electrode and a source or drain wiring will be described with reference to FIGS.

On the substrate 800, a base film 801 for improving adhesion is formed as a base pretreatment. The substrate 800 is a glass substrate made of barium borosilicate glass, aluminoborosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process. The surface of the substrate 800 may be polished by a CMP (Chemical Mechanical Polishing) method or the like so as to be planarized. An insulating layer may be formed on the substrate 800. The insulating layer is formed as a single layer or a laminated layer using an oxide material or a nitride material containing silicon by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer is not necessarily formed, but has the effect of blocking contaminants from the substrate 800. In the case where a base layer is formed to prevent contamination from a glass substrate, a base film 801 is formed thereon as a pretreatment for conductive layers 802 and 803 which are formed by a droplet discharge method.

One embodiment of a droplet discharge device used to form a pattern is shown in Figure 15. Each head 905 of the droplet discharge means 903 is connected to a control means 907, which is controlled by a computer 910 to draw a pre-programmed pattern. The timing of drawing may be determined, for example, based on a marker 911 formed on the substrate 900. Alternatively, a reference point may be determined based on the edge of the substrate 900. This is detected by an imaging means 904 such as a CCD, and converted into a digital signal by an image processing means 909, which is recognized by a computer 910, which generates a control signal and sends it to the control means 907. Of course, the timing of drawing may be determined based on a marker 911 formed on the substrate 900. Alternatively, a reference point may be determined based on the edge of the substrate 900.
Information on the pattern to be formed on the droplet ejection means 903 is stored in a storage medium 908, and based on this information, a control signal is sent to a control means 907, which controls each head 905 of the droplet ejection means 903.
Each of the nozzles can be controlled individually. A single head can discharge and draw conductive materials, organic materials, inorganic materials, etc., and when drawing on a wide area such as an interlayer film, the same material can be discharged simultaneously from multiple nozzles to improve throughput. When a large substrate is used, the head 905 can freely scan the substrate and freely set the area to be drawn, and the same pattern can be drawn multiple times on a single substrate.

In this embodiment, a substance having a photocatalytic function is used as a base film having a function of improving adhesion. The photocatalytic substance is formed by a dip coating method of the sol-gel method, a spin coating method, a droplet discharge method, an ion plating method, an ion beam method, a CVD method, a sputtering method, an RF magnetron sputtering method, a plasma spray method, a plasma spray method, or the like.
Or it can be formed by anodization. In addition, the material does not have to have continuity as a film depending on the formation method. In the case of a photocatalytic material made of an oxide semiconductor containing multiple metals, it can be formed by mixing and melting salts of the constituent elements. When forming a photocatalytic material by a coating method such as a dip coating method or a spin coating method, it is sufficient to bake or dry it when it is necessary to remove the solvent. Specifically, it is sufficient to heat it at a predetermined temperature (for example, 300 ° C. or more), preferably in an atmosphere containing oxygen. For example, when Ag is used as a conductive paste and baked in an atmosphere containing oxygen and nitrogen, organic substances such as thermosetting resins are decomposed, so that Ag that does not contain organic substances can be obtained. As a result, the flatness of the Ag surface can be improved.

This heat treatment allows the photocatalytic material to have a specific crystal structure. For example, it can have an anatase type or a rutile-anatase mixed type. In the low-temperature phase, the anatase type is preferentially formed. Therefore, even if the photocatalytic material does not have a specific crystal structure, it can be heated.
When the photocatalytic substance is formed by a coating method, the photocatalytic substance can be formed multiple times to obtain a desired film thickness.

In this embodiment, a case will be described in which TiO _x (typically TiO ₂ ) crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

The TiOX thus formed has a photocatalytic function even if it is a very thin film (about 1 nm to 1 μm).

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 801 made of a metal material such as molybdenum (O) or an oxide thereof.

The undercoat film 801 may be formed to a thickness of 0.01 to 10 nm, but since it is sufficient to form it very thin, it does not necessarily have to have a layer structure. When a high melting point metal material is used as the undercoat film, it is desirable to treat the undercoat film exposed on the surface by carrying out one of the following two steps after forming the conductive layers 802 and 803 that will become the gate electrode layers.

As a first method, the base film 801 that does not overlap the conductive layers 802 and 803 is insulated,
This is a step of forming an insulating layer.
is oxidized to insulate the base film 801. When the base film 801 is oxidized to insulate it, it is preferable to form the base film 801 to a thickness of 0.01 to 10 nm, so that the base film 801 can be easily oxidized. As a method for oxidation, a method of exposing the base film to an oxygen atmosphere or a method of carrying out heat treatment may be used.

The second method is a process of etching and removing the base film 801 using the conductive layers 802 and 803 as a mask. When this process is used, there is no restriction on the thickness of the base film 801.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion of the pattern formed by the droplet discharge method to the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic) or siloxane may be used. Note that the skeletal structure of siloxane is composed of bonds between silicon (Si) and oxygen (O). An organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Next, a composition containing a conductive material is discharged to form a conductive layer 80 which will later function as a gate electrode.
2, 803.

The droplet discharge means is a general term for a nozzle having a composition discharge port, a head having one or more nozzles, or other means for discharging droplets. The diameter of the nozzle of the droplet discharge means is set to 0.02 to 100 μm (preferably 30 μm or less), and the amount of the composition discharged from the nozzle is set to 0.001 pl to 100 pl (preferably 10 pl or less). The amount of the composition discharged increases in proportion to the size of the nozzle diameter. In addition, the distance between the workpiece and the nozzle discharge port is preferably as close as possible in order to drip the composition onto the desired location, and is preferably set to about 0.1 to 3 mm (preferably 1 mm or less).

The composition to be discharged from the discharge port is prepared by dissolving or dispersing a conductive material in a solvent.
The conductive material corresponds to metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, metal sulfides of Cd and Zn, oxides such as Fe, Ti, Zr, and Ba, and fine particles or dispersible nanoparticles of silver halide. It may also contain oxides of Si and Ge. It also corresponds to indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, etc., which are used as transparent conductive films. However, it is preferable to use a composition discharged from the discharge port in which any of the materials gold, silver, and copper is dissolved or dispersed in a solvent, taking into account the resistivity value, and more preferably, low-resistance silver,
Copper is preferably used. However, when silver or copper is used, a barrier film should be provided in addition to the silver or copper to prevent impurities. The barrier film may be a silicon nitride film or nickel boron (NiB).

Alternatively, particles may be used that have multiple layers, with another conductive material coated around the conductive material. For example, particles with a three-layer structure in which nickel boron (NiB) is coated around copper, and silver is coated around the NiB may be used. The solvent may be an ester such as butyl acetate or ethyl acetate, an alcohol such as isopropyl alcohol or ethyl alcohol, or an organic solvent such as methyl ethyl ketone or acetone. The viscosity of the composition is 50.
The viscosity of the composition is preferably 5 to 100 mPa·S (cps) or less, in order to prevent drying and to enable the composition to be smoothly discharged from the discharge port. The surface tension of the composition is preferably 40 mN/m or less. However, the viscosity of the composition may be adjusted appropriately depending on the solvent used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 50 mPa·S, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa·S, and the viscosity of a composition in which gold is dissolved or dispersed in a solvent is 10 to 20 mPa·S.
It is recommended to set the viscosity to 20 mPa·S or less.

The conductive layer may be formed by laminating a plurality of conductive materials. Alternatively, silver may be used as the conductive material first, and the conductive layer may be formed by a droplet discharge method, after which plating may be performed with copper or the like. Plating may be performed by electroplating or chemical (electroless) plating. Plating may be performed by immersing the substrate surface in a container filled with a solution containing the plating material, or by placing the substrate in an upright position (or vertically) and applying the solution containing the plating material to the substrate surface in a flowing manner. Plating by applying the solution to the substrate in an upright position has the advantage of making the process equipment smaller.

Although it depends on the diameter of each nozzle and the desired pattern shape, it is preferable that the diameter of the conductive particles is as small as possible, and preferably the particle size is 0.1 μm or less, in order to prevent clogging of the nozzle and to create a high-definition pattern. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and the particle size is generally about 0.01 to 10 μm. However, when formed by the gas evaporation method, the nanomolecules protected by the dispersant are fine at about 7 nm, and when the surface of each particle is covered with a coating agent, these nanoparticles do not aggregate in the solvent, are stably dispersed at room temperature, and behave almost the same as a liquid. Therefore, it is preferable to use a coating agent.

When the composition is discharged under reduced pressure, the solvent of the composition evaporates between the time when the composition is discharged and the time when the composition lands on the workpiece, and the subsequent drying and baking steps can be omitted. In addition, it is preferable to perform the composition under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. In addition, after the composition is discharged, one or both of the drying and baking steps are performed. Both the drying and baking steps are heat treatment steps, but for example, the drying step is performed at 100 degrees for 3 minutes, and the baking step is performed at 200 to 350 degrees for 15 to 30 minutes, and the purpose, temperature, and time are different. The drying step and the baking step are performed under normal pressure or reduced pressure by irradiation of laser light, instantaneous thermal annealing, a heating furnace, or the like. The timing of the heat treatment is not particularly limited. In order to perform the drying and baking steps well, the substrate may be heated, and the temperature at that time depends on the material of the substrate, etc., but is generally 100 to 800 degrees (preferably 200 to 350 degrees).
This process volatilizes the solvent in the composition or chemically removes the dispersant, and the surrounding resin hardens and shrinks, bringing the nanoparticles into contact with each other and accelerating their fusion and adhesion.

The laser light irradiation may be performed using a continuous wave or pulsed gas laser or solid-state laser. The former gas laser may be an excimer laser, and the latter solid-state laser may be a laser using a crystal such as YAG or _YVO4 doped with Cr, Nd, or the like. In addition, it is preferable to use a continuous wave laser in terms of the absorptance of the laser light. Also, a so-called hybrid laser irradiation method that combines pulsed and continuous wave may be used. However, depending on the heat resistance of the substrate 800, the heat treatment by irradiation with laser light may be performed.
In order to prevent the substrate 800 from being destroyed, the treatment should be performed instantaneously for a period ranging from several microseconds to several tens of seconds.
Rapid thermal annealing (RTA) is performed in an inert gas atmosphere by using an infrared lamp or halogen lamp that irradiates ultraviolet or infrared light to rapidly raise the temperature and apply heat instantaneously for a few minutes to a few microseconds. Since this treatment is performed instantaneously, it is possible to heat only the thin film on the outermost surface, and the underlying film is not affected. In other words, it does not affect substrates with poor heat resistance, such as plastic substrates.

In addition, as a pretreatment for the conductive layer to be formed by the droplet discharge method, the above-mentioned base film 801
However, this treatment step may be carried out after the conductive layer is formed.

Next, a gate insulating layer is formed on the conductive layers 802 and 803 (see FIG. 13A). The gate insulating layer may be formed of a known material such as an oxide material or a nitride material of silicon, and may be a laminated layer or a single layer. For example, a laminated layer of three layers of a silicon nitride film, a silicon oxide film, and a silicon nitride film may be used, or a laminated layer of a single layer or two layers of these or a silicon oxynitride film may be used. In this embodiment mode, a silicon nitride film is used for the insulating layer 804, and a silicon nitride oxide film is used for the gate insulating layer 805. It is preferable to use a silicon nitride film having a dense film quality. In addition, when silver or copper is used for the conductive layer formed by the droplet discharge method, forming a silicon nitride film or a NiB film as a barrier film on it has the effect of preventing diffusion of impurities and flattening the surface. In order to form a dense insulating film with a small gate leakage current at a low film formation temperature, it is preferable to include a rare gas element such as argon in the reaction gas and mix it into the insulating film to be formed.

Next, a conductive layer (also referred to as a first electrode) 806 is formed on the gate insulating film by selectively discharging a composition containing a conductive material (see FIG. 13B).
When emitting light from the 00 side, or when manufacturing a transmissive EL display panel, a predetermined pattern may be formed from a composition containing indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO2), or the like, and then fired.

Also, preferably, the conductive layer (first electrode) 8 is formed by sputtering using indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), or the like. More preferably, indium tin oxide containing silicon oxide is used, which is formed by sputtering using a target in which ITO contains 2 to 10% by weight of silicon oxide. In addition, an oxide conductive material formed by using a target in which indium oxide containing silicon oxide is mixed with 2 to 20% by weight of zinc oxide (ZnO) may be used. The conductive layer (first electrode) 8 is formed by sputtering.
After forming the conductive layer 806, a mask layer may be formed by droplet discharge and etched into a desired pattern. In this embodiment mode, the conductive layer 806 is formed by droplet discharge using a conductive material having light transmitting properties, specifically, indium tin oxide (ITSO) composed of ITO and silicon oxide. Although not shown, a photocatalytic substance may be formed in the region where the conductive layer 806 is to be formed, in the same manner as when the conductive layers 802 and 803 are formed. The photocatalytic substance improves adhesion, and the conductive layer 806 can be formed by thinning into a desired pattern. This conductive layer 806 becomes a first electrode that functions as a pixel electrode.

In this embodiment mode, the gate insulating layer is an example of three layers of a silicon nitride film made of silicon nitride, a silicon oxynitride film (silicon oxide film), and a silicon nitride film. In a preferred configuration, a conductive layer (first electrode) 806 made of indium tin oxide containing silicon oxide is formed in close contact with an insulating layer made of silicon nitride contained in the gate insulating layer 805, thereby increasing the proportion of light emitted from the electroluminescent layer that is radiated to the outside.

In addition, in the case of a structure in which emitted light is radiated to the opposite side to the substrate 800 side, a composition containing metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), and Al (aluminum) as a main component can be used when manufacturing a reflective EL display panel. As another method, a transparent conductive film or a light-reflective conductive film may be formed by a sputtering method, a mask pattern may be formed by a droplet discharge method, and the first electrode layer may be formed by combining with an etching process.

The conductive layer (first electrode) 806 may be wiped and polished with a CMP method or a polyvinyl alcohol-based porous body so that the surface thereof is planarized. After polishing using the CMP method,
The surface of the conductive layer (first electrode) 806 may be subjected to ultraviolet irradiation, oxygen plasma treatment, or the like.

The semiconductor layer may be formed by a known method (such as sputtering, LP (Low Pressure) CVD, or plasma CVD). The material of the semiconductor layer is not limited, but is preferably silicon or a silicon germanium (SiGe) alloy.

The semiconductor layer is made of an amorphous semiconductor (typically hydrogenated amorphous silicon) or a crystalline semiconductor (typically polysilicon).
These include so-called high-temperature polysilicon, which uses polycrystalline silicon formed through a process temperature of 100° C. or higher as the main material, so-called low-temperature polysilicon, which uses polycrystalline silicon formed at a process temperature of 600° C. or lower as the main material, and crystalline silicon that has been crystallized by adding elements that promote crystallization.

As another material, a semi-amorphous semiconductor or a semiconductor containing a crystalline phase in a part of the semiconductor layer can be used. A semi-amorphous semiconductor is a semiconductor having an amorphous structure and a crystalline structure (single crystal,
It is a semiconductor with an intermediate structure between the lattice distortion and the lattice distortion (including polycrystalline), and has a third state that is stable in terms of free energy. It is a crystalline material with short-range order and lattice distortion. It typically contains silicon as the main component, and has a Raman spectrum of 520 ^cm-
1 , which is a semiconductor layer shifted to a lower wave number side. Also, in order to terminate dangling bonds, hydrogen or halogen is contained at least 1 atomic % or more. Here, such a semiconductor is called a semi-amorphous semiconductor (hereinafter referred to as "SAS"). This SAS is also called a so-called microcrystalline semiconductor (representatively, microcrystalline silicon).

This SAS can be obtained by glow discharge decomposition (plasma CVD) of a silicon gas. A typical silicon gas is _SiH4 , and other silicon gases include _{Si2H6 ,} Si
_H2Cl2 , _SiHCl3 , _SiCl4 , _{SiF4 ,} etc. can be used.
_eF4 , _F2 may be mixed. The formation of SAS can be facilitated by diluting this silicide gas with hydrogen, or hydrogen and one or more rare gas elements selected from helium, argon, krypton, and neon. The dilution ratio of hydrogen to the silicide gas is preferably, for example, 2 to 1000 times in terms of flow rate. Of course, the formation of SAS by glow discharge decomposition is preferably carried out under reduced pressure, but it can also be formed by utilizing discharge at atmospheric pressure. Typically, it may be carried out in a pressure range of 0.1 Pa to 133 Pa. The power frequency for forming glow discharge is 1 MHz to 120 MHz, preferably 13 MHz to
The frequency is 60 MHz. The high frequency power can be set appropriately. The substrate heating temperature is preferably 300° C. or less, but it can also be formed at a substrate heating temperature of 100 to 200° C. Here, the impurity elements mainly taken in during film formation are impurities derived from atmospheric components such as oxygen, nitrogen, and carbon, and the like are 1×
It is desirable to set the concentration of oxygen to 10 ²⁰ cm ^-3 or less, and in particular, it is preferable to set the concentration of oxygen to 5×10 ¹⁹ cm ^-3 or less, and more preferably to 1×10 ¹⁹ cm ^-3 or less. In addition, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is increased and a good SAS can be obtained. In addition, a SAS layer formed from a hydrogen-based gas may be laminated on a SAS layer formed from a fluorine-based gas as a semiconductor layer.

When a crystalline semiconductor layer is used for the semiconductor layer, the crystalline semiconductor layer may be manufactured by a known method (laser crystallization, thermal crystallization, or thermal crystallization using an element that promotes crystallization such as nickel, etc.). When an element that promotes crystallization is not introduced, the amorphous silicon film is heated at 500° C. for 1 hour in a nitrogen atmosphere before being irradiated with laser light, thereby releasing hydrogen contained in the amorphous silicon film to a concentration of 1× ¹⁰²⁰ atoms/ ^cm3 or less.
This is because when an amorphous silicon film containing a large amount of hydrogen is irradiated with laser light, the film is destroyed.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as it is a method that can cause the metal element to exist on the surface or inside of the amorphous semiconductor layer. For example, a sputtering method, a CV method,
The method using a solution can be used, for example, the D method, the plasma treatment method (including the plasma CVD method), the adsorption method, or the method of applying a solution of a metal salt. Among these, the method using a solution is useful in that it is simple and easy to adjust the concentration of the metal element. In addition, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, a UV irradiation in an oxygen atmosphere is used.
It is preferable to form the oxide film by light irradiation, thermal oxidation, or treatment with ozone water or hydrogen peroxide containing hydroxyl radicals.

The amorphous semiconductor layer may be crystallized by a combination of heat treatment and crystallization by laser light irradiation, or by performing heat treatment or laser light irradiation alone a plurality of times.

The semiconductor may be an organic semiconductor using an organic material. As the organic semiconductor, a low molecular weight material or a high molecular weight material is used, and materials such as an organic dye or a conductive high molecular weight material can also be used.

In this embodiment, an amorphous semiconductor is used as the semiconductor. In order to form the semiconductor layer 807, which is an amorphous semiconductor layer, and to form the channel protective films 809 and 810, for example, an insulating film is formed by plasma CVD and selectively etched to have a desired shape in a desired region. At this time, the channel protective films 809 and 810 can be formed by exposing the back side of the substrate using the gate electrode as a mask. In addition, polyimide or polyvinyl alcohol may be dropped by a droplet discharge method to form the channel protective film. As a result, the exposure step can be omitted. After that, a semiconductor layer having one conductivity type, for example, an N-type semiconductor layer 808 is formed by using an N-type amorphous semiconductor layer by plasma CVD or the like (see FIG. 13C). The semiconductor layer having one conductivity type may be formed as necessary.

The channel protection film may be made of an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride), a photosensitive or non-photosensitive organic material (organic resin material) (such as polyimide, acrylic,
A film made of one or more of low-k materials having a low dielectric constant, such as polyamide, polyimide amide, resist, benzocyclobutene, etc., or a laminate of these films can be used. In addition, an organic group (e.g., an alkyl group, an aromatic hydrocarbon) whose skeleton structure is formed by bonding silicon (Si) and oxygen (O) and whose substituent contains at least hydrogen may be used. As the substituent, a fluoro group may be used, or an organic group containing at least hydrogen and a fluoro group may be used. When an inorganic material is used as the channel protection film, a vapor phase growth method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used as a manufacturing method. When an organic material is used, a droplet discharge method or a printing method (a method in which a pattern is formed, such as screen printing or offset printing) can also be used. An insulating film obtained by a coating method or a SOG film can also be used as the channel protection film.

Next, mask layers 811 and 812 made of an insulating material such as resist or polyimide are formed.
Using the mask layers 811 and 812, the semiconductor layer 807 and the N-type semiconductor layer 808 are simultaneously patterned.

Next, mask layers 813 and 814 made of an insulator such as resist or polyimide are formed by a droplet discharge method (see FIG. 13D). Using the mask layers 813 and 814, a through hole 818 is formed in a part of the gate insulating layers 805 and 804 by etching, and a part of the conductive layer 803 functioning as a gate electrode layer disposed thereunder is exposed. Either plasma etching (dry etching) or wet etching may be used for the etching, but plasma etching is suitable for processing a large-area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. In addition, if atmospheric pressure discharge etching is applied, localized discharge processing is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

After removing the mask layers 813 and 814, a composition containing a conductive material is discharged to form a conductive layer 8.
The conductive layers 815, 816, and 817 are formed, and the N-type semiconductor layer is patterned using the conductive layers 815, 816, and 817 as masks to form an N-type semiconductor layer (see FIG. 14A).
Although not shown, the conductive layers 815, 816, and 817 function as wiring layers.
Before forming the conductive layers 816 and 817, the above-mentioned base pretreatment step may be performed to selectively form a photocatalytic substance or the like in the portions where the conductive layers 815, 816, and 817 are in contact with the gate insulating layer 805. In this way, the conductive layers can be formed with good adhesion.

In addition, as a pretreatment for the base of the conductive layer formed by the droplet discharge method, the above-mentioned step of forming the base film may be performed, and this treatment step may be performed after the conductive layer is formed. This step improves the adhesion between layers, and therefore the reliability of the display device can be improved.

The conductive layer 817 functions as a source/drain wiring layer and is formed so as to be electrically connected to the first electrode formed previously.
In the figure, a conductive layer 816 which is a source or drain wiring layer and a conductive layer 8 which is a gate electrode layer are
The conductive material for forming this wiring layer is Ag (silver),
A composition containing metal particles such as Au (gold), Cu (copper), W (tungsten), and Al (aluminum) as a main component can be used. Indium tin oxide (
It is also possible to combine ITO, indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, and the like.

The step of forming a through hole 818 in a part of the gate insulating layers 805 and 804 is performed by the conductive layer 815,
After the formation of 816 and 817, the conductive layers 815, 816, and 817 may be used as masks to form a through hole 818. Then, a conductive layer is formed in the through hole 818 to electrically connect the conductive layer 816 to the conductive layer 803 which is a gate electrode layer. In this case, there is an advantage that the process is simplified.

Subsequently, an insulating layer 820 that becomes a partition wall is formed. Although not shown, a protective layer of silicon nitride or silicon nitride oxide may be formed on the entire surface under the insulating layer 820 so as to cover the thin film transistor. The insulating layer 820 is formed by forming an insulating layer on the entire surface by a spin coating method or a dip method, and then forming an opening by etching as shown in FIG. 14B. If the insulating layer 820 is formed by a droplet discharge method, the etching process is not necessarily required. When a wide area such as the insulating layer 820 is formed by using the droplet discharge method, the throughput is improved by discharging a composition from multiple nozzle discharge ports of a droplet discharge device and drawing and forming multiple lines so as to overlap each other.

The insulating layer 820 is formed with a through hole opening in accordance with the position where the pixel is formed corresponding to the conductive layer 806 which is the first electrode. The insulating layer 820 is made of silicon oxide, silicon nitride,
Silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, or acrylic acid, methacrylic acid and their derivatives, or polyimide (po
lyimide, aromatic polyamide, polybenzimidazole
It can be formed from a heat-resistant polymer such as tetrafluoroethylene (Teflon), or an inorganic siloxane containing a Si-O-Si bond among compounds consisting of silicon, oxygen, and hydrogen formed using a siloxane-based material as a starting material, or an organic siloxane-based insulating material in which hydrogen on silicon is replaced by an organic group such as methyl or phenyl. When it is formed using a photosensitive or non-photosensitive material such as acrylic or polyimide, the side surface has a shape in which the radius of curvature changes continuously, and the thin film on the upper layer is formed without being broken, which is preferable.

Through the above steps, a TFT substrate for an EL display panel is completed on the substrate 800, in which a bottom-gate type (also called an inverted staggered type) channel protective TFT and a first electrode (first electrode layer) are connected.

Before forming the electroluminescent layer 821, heat treatment is performed at 200° C. under atmospheric pressure to remove moisture adsorbed in or on the surface of the insulating layer 820. It is also preferable to perform heat treatment at 200 to 400° C., preferably 250 to 350° C. under reduced pressure, and then form the electroluminescent layer 821 by a vacuum deposition method or a droplet discharge method under reduced pressure without exposing the insulating layer 820 to the air.

For the electroluminescent layer 821, materials that emit red (R), green (G), and blue (B) light are used.
The red (R), green (G) and red (R) are selectively formed by a deposition method using a deposition mask.
A material that emits blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as the color filter. In this case, it is preferable because RGB can be colored without using a mask.
22 is laminated to complete a display device having a display function using light-emitting elements (FIG. 14(
See B).

Although not shown, it is effective to provide a passivation film so as to cover the second electrode. Examples of the passivation film include silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y : x>y>0), silicon nitride oxide (SiN _x O _y : x>y>0),
Aluminum nitride (AlN), aluminum oxynitride (AlO _x N _y : x>y>0), aluminum oxide nitride (AlN _x O _y : x>y>0) or aluminum oxide in which the nitrogen content is higher than the oxygen content, diamond-like carbon (DLC), nitrogen-containing carbon film (CN
_x ) and a single layer or a laminate of a combination of such insulating films can be used. For example, a laminate of a nitrogen-containing carbon film (CN _x ) and silicon nitride (SiN) can be used, or an organic material can be used, and a laminate of a polymer such as a styrene polymer can also be used. Siloxane resin can also be used. Siloxane has a skeletal structure formed by the bond between silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (e.g., an alkyl group,
A fluoro group may be used as a substituent. Alternatively, a fluoro group and an organic group containing at least hydrogen may be used as a substituent.

In this case, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, especially a DLC film. The DLC film can be formed in a temperature range from room temperature to 100° C., so it can be easily formed above an electroluminescent layer with low heat resistance. The DLC film can be formed by a plasma CVD method (typically, RF plasma CVD, microwave C
CVD method, electron cyclotron resonance (ECR) CVD method, hot filament CVD method, etc.),
The film can be formed by a combustion flame method, a sputtering method, an ion beam deposition method, a laser deposition method, etc. The reactive gas used for film formation is a mixture of hydrogen gas and a _hydrocarbon gas (e.g., _CH4 , _C2H2 ,
The CN film is formed by _{using C2H4 gas and N2 gas as reactive} gases. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the _{electroluminescent} layer. Therefore, the problem of oxidation of the electroluminescent layer during the subsequent sealing process can be prevented.

A top view of a pixel portion of a display device according to this embodiment is shown in FIG. 16(A), and a circuit diagram is shown in FIG.
1001 and 1002 are TFTs, 1003 is a light emitting element, 1004 is a capacitor element, 1005 is a source signal line, 1006 is a gate signal line, and 1007 is a power supply line. The TFT 1001 is a transistor (hereinafter, referred to as a "switching transistor" or "
The TFT 1001 is a transistor that controls a current flowing to a light-emitting element (hereinafter also referred to as a "driving transistor" or "driving TFT").
The driving TFT is connected in series with the light emitting element.
A voltage is maintained between the source and gate of the TFT 1002 which is an FT.

A detailed diagram of the display device of this embodiment is shown in Fig. 17. A substrate 800 having a switching TFT 1001 and a TFT 1002 which is a driving TFT connected to a light emitting element 1003 is fixed to a sealing substrate 850 by a sealant 851. Various signals supplied to each circuit formed on the substrate 800 are supplied at terminal portions.

A gate wiring layer 860 is formed in the terminal portion in the same process as the conductive layers 802 and 803. Of course, a photocatalytic substance is formed in the formation region of the gate wiring layer 860 as in the conductive layers 802 and 803, and when the gate wiring layer 860 is formed by the droplet discharge method, the adhesion between the formation region of the gate wiring layer 860 and the underlying layer can be improved. The etching for exposing the gate wiring layer 860 is performed by:
This can be performed at the same time as forming the through hole 818 in the gate insulating layer 805. A flexible wiring board (FPC) 862 can be connected to the gate wiring layer 860 by an anisotropic conductive layer 861.

In the above display device, the light-emitting element 1003 is sealed with a glass substrate. The sealing process is a process for protecting the light-emitting element from moisture, and any of the following methods is used: mechanical sealing with a cover material, sealing with a thermosetting resin or ultraviolet light curing resin, or sealing with a thin film with high barrier capacity such as metal oxide or nitride. The cover material may be glass, ceramic, plastic, or metal, but must be light-transmitting if light is to be emitted toward the cover material. The cover material and the substrate on which the light-emitting element is formed are attached together using a sealant such as a thermosetting resin or ultraviolet light curing resin,
The resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. It is also effective to provide a moisture absorbent material, such as barium oxide, in this sealed space. This moisture absorbent material may be provided in contact with the sealing material, or may be provided on the partition wall or in the peripheral area so as not to interfere with the light from the light emitting element. Furthermore, it is also possible to fill the space between the cover material and the substrate on which the light emitting element is formed with a thermosetting resin or an ultraviolet light curing resin. In this case, it is effective to add a moisture absorbent material, such as barium oxide, to the thermosetting resin or the ultraviolet light curing resin.

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, it is possible to produce a highly reliable display device with improved adhesion and peel resistance.

Circuit diagrams of the entire pixel section in this embodiment are shown in Fig. 8 and Fig. 16. This embodiment is characterized in that one vertical column of pixels has multiple source signal lines. Fig. 8 explains an example in which one vertical column of pixels has three source signal lines.

The number of source signal lines is not limited to three, but can be any number.

In Fig. 8, the circuit 854 of each pixel will be described as being the circuit shown in Fig. 16. However, this is only an example, and the circuit of each pixel is not limited to that shown in Fig. 16.

The pixel in the first row and first column of the pixel section includes a gate signal line G1, one of three source signal lines S1a, a power supply line V1, a switching TFT 1001, and a driving TFT 1002.
1002, an EL element 1003, and a capacitor element 1004.

The connection of the pixel to the circuit will be described. The gate signal line G1 is connected to the gate electrode of the switching TFT 1001, one of the three source signal lines S1a is connected to the source or drain electrode of the switching TFT 1001, and the power supply line V1 is connected to the driving TFT 1001.
A source or drain electrode of 1002 and one electrode of a capacitor element 1004 are connected to the
The other electrode of the capacitance element 1004 is connected to the other source or drain electrode of the switching TFT 1001 and the gate electrode of the driving TFT 1002.
The other source or drain electrode of 1002 is connected to an EL element 1003 .

The pixel in the second row and first column of the pixel section includes a gate signal line G2, one of the three source signal lines S1b, a power supply line V1, a switching TFT 1001, and a driving TFT 1002.
The display device includes an FT 1002 , an EL element 1003 , and a capacitor element 1004 .

The pixel in the second row and first column of the pixel section is configured by changing G1 to G2 and S
1a is replaced with S1b.

The pixel in the third row and first column of the pixel section includes a gate signal line G3, one of the three source signal lines S1c, a power supply line V1, a switching TFT 1001, and a driving TFT 1002.
1002, an EL element 1003, and a capacitor element 1004.

The pixel in the third row and first column of the pixel section is configured by changing G1 to G3 and S
1a is replaced with S1c.

In addition, in the above three rows of pixel columns, G1, G2, and G3 are electrically connected.

The first pixel row is also characterized by a repetition of the above configuration.

In addition, in the second pixel row, in the above configuration, V1 is changed to V2, S1a is changed to S2a, and S1b is changed to
is replaced with S2b, and S1c is replaced with S2c.

In addition, in the n-th pixel column, V1 is changed to Vn, S1a is changed to Sna, and S1b is changed to
is replaced with Snb, and S1c is replaced with Snc.

Furthermore, V1 to Vn are all electrically connected to each other.

Next, how the circuit in FIG. 8 operates will be described. First, the gate signal lines G1 and G
While the gate signal lines G1, G2, and G3 are on, signals are written to the pixels by the source signal lines S1a, S1b, S1c, . . ., Sna, Snb, and Snc. Next, the gate signal lines G4, G5, and G6 are turned on simultaneously.
While G4, G5, and G6 are on, the source signal lines S1a, S1b, S1c, . . . , S
A signal is written to the pixel by na, Snb, and Snc. This operation is performed on the gate signal line Gm-2
, Gm-1, Gm are repeated until the signal writing for one image is completed.

When operated in this manner, the gate signal lines operate in groups of three, so the time that the gate signal lines are on is three times longer than in a circuit with a single signal line. In other words, it is possible to overcome one of the problems to be overcome by the present invention, that is, the need to make the writing time as long as possible.

However, simply connecting as shown in Figure 8 may increase the parasitic capacitance between the wiring.

For this reason, in this embodiment, in addition to the configuration of Fig. 8, a process may be devised that takes advantage of the manufacturing method that allows selective pattern formation. In order to explain this, Fig. 6 is used as a diagram showing a cross section of a portion indicated by a line segment 855.

FIG. 6 shows the state in which the gate insulating layer 805 has been formed in the TFT fabrication process described above (FIG. 13(
The process shown in FIG. 6A) is a cross-sectional view of a semiconductor layer 605. Since no semiconductor layer is present in the cross-section, a conductive layer is usually formed after the gate insulating layer 605 is formed (FIG. 6A). However, in this embodiment, after the gate insulating layer 605 is formed, a part of the insulating layer in the area where the three source signal lines are to be disposed is selectively patterned by a droplet discharge method (FIG. 6B). Thereafter, a conductive layer is formed (FIG. 6C) and patterned as described above.

By carrying out such a process, the source signal line 6
In this embodiment, three source signal lines are formed: source signal lines 616 and source signal lines 615 and 617 below which insulating layer 606 does not exist. In this structure, the distance between the wirings is longer than when insulating layer 606 is not present, and the parasitic capacitance between the wirings can be reduced. In other words, the problem that the parasitic capacitance must be reduced as much as possible can be overcome. Moreover, the effect of the configuration of this embodiment becomes greater as the wiring becomes longer.

In this embodiment, the location, number, shape, etc. of the insulating layer may take various forms, but any form may be used as long as it does not deviate from the purpose of selectively forming an insulating layer to increase the distance between wirings in the same layer.
Moreover, the wiring selectively formed on the insulating layer is not limited to the source signal line. The insulating layer can be formed on the gate signal line and the power supply line in a similar manner, and the parasitic capacitance can be reduced.

(Embodiment 2)
An embodiment of the present invention will be described with reference to FIG. 9 and FIG.

In Fig. 9, the circuit 954 of each pixel will be described as being the circuit shown in Fig. 16. However, this is only an example, and the circuit of each pixel is not limited to that shown in Fig. 16.

The pixel in the first row and first column of the pixel section includes a gate signal line G1, a source signal line S1, a power supply line Vx1, a power supply line Vy1, a switching TFT 1001, and a driving TFT 100.
2, an EL element 1003, and a capacitor element 1004.

The connection of the pixel to the circuit will be described. The gate signal line G1 is connected to the gate electrode of the switching TFT 1001, the source signal line S1 is connected to the source or drain electrode of the switching TFT 1001, the power supply line Vx1 is connected to the source or drain electrode of the driving TFT 1002 and one electrode of the capacitance element 1004, the power supply line Vy1 is connected to the power supply line Vx1, and the other electrode of the capacitance element 1004 is connected to the switching TFT 1001.
The other source or drain electrode of the driving TFT 1002 is connected to the gate electrode of the EL element 10
It is connected to 03.

The pixel in the second row and first column of the pixel section includes a gate signal line G2, a source signal line S1, a power supply line Vx1, a power supply line Vy2, a switching TFT 1001, and a driving TFT
The pixel includes a pixel electrode 1002, an EL element 1003, and a capacitor element 1004.

The pixel in the second row and first column of the pixel section is configured as follows: G1 is changed to G2, and V
It is characterized in that y1 is replaced with Vy2.

The pixel in the first column of the mth row of the pixel section includes a gate signal line Gm, a source signal line S1, a power supply line Vx1, a power supply line Vym, a switching TFT 1001, and a driving TFT
The pixel includes a pixel electrode 1002, an EL element 1003, and a capacitor element 1004.

The pixel in the first row and nth column of the pixel section has a configuration in which S1 is replaced with Sn and Vx1 is replaced with Vxn in the configuration of the pixel in the first row and first column.

The pixel in the mth row and nth column of the pixel section is characterized in that, in the configuration of the pixel in the 1st row and 1st column, S1 is replaced with Sn, Vx1 with Vxn, G1 with Gm, and Vy1 with Vym.

Also, Vx1 to Vxn and Vy1 to Vyn are all characterized by being electrically connected to each other.

In this embodiment, in FIG. 9, the power supply lines of the pixel portion are source signal lines (S1 to Sn).
In addition to the wiring (Vx1 to Vxn) arranged in parallel to the pixel driver TFT 100, wiring (Vy1 to Vym) is also arranged in a vertical or nearly vertical direction.
A voltage is supplied to the source region or drain region of each of the transistors 2. The power supply lines (Vy1 to Vym) arranged in the vertical or nearly vertical direction are each a power supply line (
Vx1 to Vxn) for each pixel, and the power supply lines are arranged in a matrix. As a result, the current flowing through the EL element 1003 is supplied not only from a direction parallel to the source signal lines (S1 to Sn), but also from a direction perpendicular to the source signal lines, making it possible to overcome one of the problems to be overcome by the present invention, that is, the need to make the wiring resistance as small as possible.

Since the wiring resistance can be reduced, crosstalk is reduced when the EL display device is driven in an analog manner, and gray scale display defects are reduced when the EL display device is driven by a combination of digital driving and constant voltage driving.

However, as in embodiment 1, one of the challenges to be overcome in this embodiment is to manufacture an EL display device at low cost, so the EL display device may be manufactured by an EL display device manufacturing process using a droplet discharge method, which is one of the methods for manufacturing an EL display device that allows selective pattern formation.

Here, problems that arise when a droplet discharge method is used to reduce costs as a method for manufacturing an EL display device will be described.

7A and 7B are top views of a conductive layer formed as a wiring by using a droplet discharge method.
7A and 7B are cross-sectional views ((C) and (D)) of the conductive layer 7. When a conductive layer is formed by discharging a composition containing a conductive material, the conductive layer may not be formed in the intended location or shape due to the characteristics of the conductive material to be discharged, the water repellency of the base, an error in the discharge position, and the like (FIGS. 7B and 7D).

Here, the resistance of the wiring depends on the length and cross-sectional area of the wiring if the conductive material is the same.
7B and 7D, when the intended shape is not obtained, the resistance value of the wiring becomes larger than the design value. In other words, the wiring formed by the droplet discharge method has a larger variation in wiring resistance than the wiring formed by photolithography.

As already mentioned, high wiring resistance causes crosstalk in analog drive and causes poor gradation display in digital drive using constant voltage drive, but variation in wiring resistance means that the degree of these display defects differs depending on the power supply line of the pixel, which can be easily observed as uneven display.

That is, one of the problems when using the droplet discharge method to reduce costs is the variation in wiring resistance, which must be minimized in order to achieve the object of the present invention.

Here, it will be explained that by adopting this embodiment mode, the variation in wiring resistance caused by the droplet discharge method can also be reduced.

This can be explained by considering that when power supply lines are arranged in a matrix, the resistance of the wiring is all connected in parallel. In other words, if they are connected in parallel, the resistance of the power supply line up to a certain pixel depends on the resistance value of all the power supply lines, and the position dependency of the resistance that exists when the power supply lines are not arranged in a matrix is reduced.

That is, according to this embodiment, not only is it possible to reduce the wiring resistance of the power supply line, but it is also possible to overcome the problem that the variation in wiring resistance must be minimized when a droplet discharge method is used.

In this embodiment, the wiring does not need to be parallel to each other and may be in any direction. Also, the number of power supply lines does not need to be one for each pixel and may be any number. Also, the power supply lines do not need to be in a matrix form for the entire pixel section and may be in only a part of the pixel section.

This embodiment can also be freely combined with embodiment 1.

(Embodiment 3)
An embodiment of the present invention will be described with reference to FIG. 10 and FIG.

In Fig. 10, the circuit 1054 of each pixel will be described as being the circuit shown in Fig. 16. However, this is only an example, and the circuit of each pixel is not limited to that shown in Fig. 16.

The pixel in the first row and first column of the pixel section includes a gate signal line G1, a source signal line S1, a power supply line Vx1, a power supply line Vy1R, a switching TFT 1001, and a driving TFT 1002.
1002, an EL element 1003, and a capacitor element 1004.

The connection of the pixel to the circuit will be described. The gate signal line G1 is connected to the gate electrode of the switching TFT 1001, the source signal line S1 is connected to the source or drain electrode of the switching TFT 1001, the power supply line Vx1 is connected to the source or drain electrode of the driving TFT 1002 and one electrode of the capacitance element 1004, the power supply line Vy1R is connected to the power supply line Vx1, and the other electrode of the capacitance element 1004 is connected to the switching TFT 1
The other source or drain electrode of the driving TFT 1001 is connected to the gate electrode of the driving TFT 1002, and the other source or drain electrode of the driving TFT 1002 is connected to the gate electrode of the EL element 1
It is connected to 003.

The pixel in the second row and first column of the pixel section includes a gate signal line G2, a source signal line S1, a power supply line Vx1, a power supply line Vy2R, a switching TFT 1001, and a driving TFT 1002.
The pixel includes a T 1002 , an EL element 1003 , and a capacitance element 1004 .

The pixel in the second row and first column is configured by changing G1 to G2 and Vy1R to V
It is characterized in that it has a configuration in which y2R is replaced with

In addition, the pixel in the third row and first column of the pixel section is configured by changing G1 to G3 in the configuration of the pixel in the first row and first column.
In addition, Vy1R is replaced with Vy3R.

The pixels in the first column of the pixel section are characterized in that they have a configuration in which the above-mentioned three rows are repeated.

The pixel in the first row, second column of the pixel section has a configuration in which S1 is replaced with S2, Vx1 with Vx2, and Vy1R with Vy1G in the configuration of the pixel in the first row, first column.

The pixel in the second row, second column of the pixel section has a configuration in which G1 is replaced with G2 and Vy1G is replaced with Vy2G in the configuration of the pixel in the first row, second column.

The pixel in the third row and second column of the pixel section has a configuration in which G1 is replaced with G3 and Vy1G is replaced with Vy3G in the configuration of the pixel in the first row and second column.

The pixels in the second column of the pixel section are characterized in that they have a configuration in which the above-mentioned three rows are repeated.

The pixel in the first row, third column of the pixel section has a configuration in which S1 is replaced with S3, Vx1 with Vx3, and Vy1R with Vy1B in the configuration of the pixel in the first row, first column.

The pixel in the second row, third column of the pixel section has a configuration in which G1 is replaced with G2 and Vy1B is replaced with Vy2B in the configuration of the pixel in the first row, third column.

The pixel in the third row and third column of the pixel section has a configuration in which G1 is replaced with G3 and Vy1B is replaced with Vy3B in the configuration of the pixel in the first row and third column.

The pixels in the third column of the pixel section are characterized in that they have a configuration in which the above-mentioned three rows are repeated.

Furthermore, Vy1R to VymR are all electrically connected to each other.

Furthermore, Vy1G to VymG are all electrically connected to each other.

Furthermore, Vy1B to VymB are all electrically connected to each other.

In this embodiment, the power supply lines of the pixel portion are not only arranged in parallel with the source signal lines (S1 to Sn) but also arranged in a vertical or nearly vertical direction (
Vy1R to VymB), and the driving TFs for R, G, and B pixels are respectively
A voltage is supplied to the source region or drain region of T1002. In addition, the power supply lines (Vy1 to Vym) arranged in the vertical or nearly vertical direction are connected to the power supply lines (Vx1 to Vxn) for each R, G, and B pixel, and the power supply lines are arranged in a matrix. As a result, the current flowing through the EL element 1003 is supplied to the source signal line (
Since the power is supplied not only from the direction parallel to the R, G, and B electrodes (S1 to Sn) but also from the direction perpendicular to the R, G, and B electrodes, it is possible to overcome one of the problems to be overcome by the present invention, that is, to minimize the wiring resistance. Also, since the R, G, and B electrodes are connected separately, the voltage supplied to each of the R, G, and B electrodes may be different.

Since the wiring resistance can be reduced, crosstalk is reduced when the EL display device is driven in an analog manner, and gray scale display defects are reduced when the EL display device is driven by a combination of digital driving and constant voltage driving.

However, in the present embodiment, as in the first and second embodiments, the EL
Since the manufacturing of the display device is one of the problems to be overcome, the display device may be manufactured by a process for manufacturing an EL display device using a droplet discharge method, which is one of the methods for manufacturing an EL display device that allows selective patterning.

As already mentioned, when wiring is formed by the droplet discharge method, there is a problem that the wiring resistance varies. By adopting this embodiment mode, the variation in the wiring resistance caused by the droplet discharge method can also be reduced.

This can be explained by considering that when power supply lines are arranged in a matrix, the resistance of the wiring is all connected in parallel. In other words, if they are connected in parallel, the resistance of the power supply line up to a certain pixel depends on the resistance value of all the power supply lines, and the position dependency of the resistance that exists when the power supply lines are not arranged in a matrix is reduced.

That is, according to this embodiment, not only is it possible to reduce the wiring resistance of the power supply line, but it is also possible to overcome the problem that the variation in wiring resistance must be minimized when a droplet discharge method is used.

In this embodiment, the wiring does not need to be parallel to each other and may be in any direction. Also, the number of power supply lines per pixel does not need to be one and may be any number. Also, the power supply lines do not need to be in a matrix form over the entire pixel section and may be in only a part of the pixel section.

In addition, this embodiment mode can be freely combined with Embodiment Mode 1 and/or Embodiment Mode 2.

(Embodiment 4)
An embodiment of the present invention will be described with reference to FIGS.

In Fig. 11, the circuit 1154 of each pixel will be described as being the circuit shown in Fig. 16. However, this is just an example, and the circuit of each pixel is not limited to that shown in Fig. 16.

The pixel in the first row and first column of the pixel section includes a gate signal line G1, a source signal line S1, a power supply line Vx1, a power supply line Vy1, a switching TFT 1001, and a driving TFT 100.
2, an EL element 1003, and a capacitor element 1004.

The connection of the pixel to the circuit will be described. The gate signal line G1 is connected to the gate electrode of the switching TFT 1001, the source signal line S1 is connected to the source or drain electrode of the switching TFT 1001, the power supply line Vx1 is connected to the source or drain electrode of the driving TFT 1002 and one electrode of the capacitance element 1004, the power supply line Vy1 is connected to the power supply line Vx1, and the other electrode of the capacitance element 1004 is connected to the switching TFT 1001.
The other source or drain electrode of the driving TFT 1002 is connected to the gate electrode of the EL element 10
It is connected to 03.

In addition, the pixel in the second row and first column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and first column is replaced with G2, and in order to electrically separate the power supply lines for each of RGB, Vx1 may not be connected to another power supply line.

In addition, the pixel in the third row and first column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and first column is replaced with G3, and in order to electrically separate the power supply lines for each of RGB, Vx1 may not be connected to another power supply line.

The pixel in the fourth row and first column of the pixel section has a configuration in which G1 is replaced with G4 and Vy1 is replaced with Vy4 in the configuration of the pixel in the first row and first column.

In addition, the pixel in the 5th row and 1st column of the pixel section has a configuration in which G4 in the pixel in the 4th row and 1st column is replaced with G5, and in order to electrically separate the power supply lines for each RGB, Vx1 may not be connected to another power supply line.

In addition, the pixel in the 6th row and 1st column of the pixel section has a configuration in which G4 in the pixel in the 4th row and 1st column is replaced with G6, and in order to electrically separate the power supply lines for each RGB, Vx1 may not be connected to another power supply line.

The pixels in the first column of the pixel section are characterized in that they have a configuration in which the above-mentioned configuration for the three rows is repeated.

In addition, the pixel in the first row, second column of the pixel section has a configuration in which S1 is replaced with S2 and Vx1 is replaced with Vx2 in the configuration of the pixel in the first row, first column, and in order to electrically separate the power supply lines for each of RGB, Vx2 may not be connected to another power supply line.

In addition, the pixel in the second row and second column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and second column is replaced with G2, and Vx2 is connected to another power supply line Vy2.

In addition, the pixel in the third row and second column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and second column is replaced with G3, and in order to electrically separate the power supply lines for each of RGB, Vx2 may not be connected to another power supply line.

The pixels in the second column of the pixel section are characterized in that they have a configuration in which the above-mentioned configuration for the three rows is repeated.

In addition, the pixel in the first row and third column of the pixel section has a configuration in which S1 is replaced with S3 and Vx1 is replaced with Vx3 in the configuration of the pixel in the first row and first column described above, and Vx3 may not be connected to another power supply line in order to electrically separate the power supply lines for each RGB.

In addition, the pixel in the second row and third column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and third column is replaced with G2, and Vx3 is not connected to another power supply line.

In addition, the pixel in the third row and third column of the pixel section has a configuration in which G1 in the configuration of the pixel in the first row and third column is replaced with G3, and Vx3 may be connected to another power supply line Vy3 in order to electrically separate the power supply lines for each RGB.

The pixels in the third column of the pixel section are characterized in that they have a configuration in which the above-mentioned configuration for the three rows is repeated.

The remaining columns of the pixel section are characterized in that the configuration of the first to third columns is repeated.

In addition, Vx1, Vx4, ..., Vx(3i-2), Vy1, Vy4, ..., Vy(
3j-2) are all electrically connected to each other (i and j are natural numbers).

In addition, Vx2, Vx5, ..., Vx(3i-1), Vy2, Vy5, ..., Vy(
3j-1) are all electrically connected to each other (i and j are natural numbers).

Also, Vx3, Vx6, ..., Vx(3i), Vy3, Vy6, ..., Vy(3j
) are all electrically connected to each other (i and j are natural numbers).

In this embodiment, the power supply lines of the pixel portion are not only arranged in parallel with the source signal lines (S1 to Sn) but also arranged in a vertical or nearly vertical direction (
Vy1 to Vym), and the driving TFTs 1 for the R, G, and B pixels are
A voltage is supplied to the source region or drain region of the EL element 1002. The power supply lines (Vy1 to Vym) arranged in the vertical or nearly vertical direction are connected to the power supply lines (Vx1 to Vxn) for each R, G, and B pixel, and the power supply lines are arranged in a matrix. As a result, the current flowing through the EL element 1003 is
Since the voltage is supplied not only from the direction parallel to the R, G, and B electrodes but also from the direction perpendicular to the R, G, and B electrodes, it is possible to overcome one of the problems to be overcome by the present invention, that is, the wiring resistance must be made as small as possible. Also, since the R, G, and B electrodes are connected separately, the voltage supplied to each of the R, G, and B electrodes may be different.

Furthermore, since there is only one power supply line in parallel to the gate signal line in each pixel, the wiring resistance can be reduced without a significant decrease in the aperture ratio or an increase in the parasitic capacitance between the wirings.

Since the wiring resistance can be reduced, crosstalk is reduced when the EL display device is driven in an analog manner, and gray scale display defects are reduced when the EL display device is driven by a combination of digital driving and constant voltage driving.

However, in this embodiment, as in the first, second, and third embodiments,
Since one of the challenges to be overcome is to manufacture an EL display device at low cost, the device is manufactured by an EL display device manufacturing process using a droplet discharge method, which is one of the methods for manufacturing an EL display device that allows selective patterning.

As already mentioned, when wiring is formed by the droplet discharge method, there is a problem that the wiring resistance varies. By adopting this embodiment mode, the variation in the wiring resistance caused by the droplet discharge method can also be reduced.

This can be explained by considering that when power supply lines are arranged in a matrix, the resistance of the wiring is all connected in parallel. In other words, if they are connected in parallel, the resistance of the power supply line up to a certain pixel depends on the resistance value of all the power supply lines, and the position dependency of the resistance that exists when the power supply lines are not arranged in a matrix is reduced.

That is, according to this embodiment, not only is it possible to reduce the wiring resistance of the power supply line, but it is also possible to overcome the problem that the variation in wiring resistance must be minimized when a droplet discharge method is used.

In this embodiment, the wirings do not need to be parallel to each other and may be in any direction. Also, the number of power supply lines per pixel does not need to be one, and any number of lines may be used.
It is not necessary for the power supply lines to be arranged in a matrix form over the entire pixel section, but they may be arranged in only a part of the pixel section.

This embodiment mode can be freely combined with any of the first, second, and third embodiments.

(Embodiment 5)
This embodiment is a combination of the first embodiment and the second, third or fourth embodiment. The configuration will be described with reference to Figs.

Circuit diagrams of the entire pixel section in this embodiment are shown in Fig. 12 and Fig. 16. This embodiment is characterized in that it has a plurality of source signal lines for one vertical column of pixels.
An example will be described in which one vertical column of pixels has three source signal lines.

The number of source signal lines is not limited to three, but can be any number.

In Fig. 12, the circuit 1254 of each pixel will be described as being the circuit shown in Fig. 16. However, this is only an example, and the circuit of each pixel is not limited to that shown in Fig. 16.

The pixel in the first row and first column of the pixel section includes a gate signal line G1, one of three source signal lines S1a, a power supply line Vx1, a power supply line Vy1R, and a switching TFT 1
1001 , a driving TFT 1002 , an EL element 1003 , and a capacitance element 1004 .

The connection of the pixel to the circuit will be described. The gate signal line G1 is connected to the gate electrode of the switching TFT 1001, one of the three source signal lines S1a is connected to the source or drain electrode of the switching TFT 1001, and the power supply line Vx1 is connected to the driving TFT 1002.
The power supply line Vy1R is connected to the power supply line Vx1, the other electrode of the capacitance element 1004 is connected to the other source or drain electrode of the switching TFT 1001 and the gate electrode of the driving TFT 1002, and the other source or drain electrode of the driving TFT 1002 is connected to the EL element 1003.

The pixel in the second row and first column of the pixel section includes a gate signal line G2, one of the three source signal lines S1b, a power supply line Vx1, a power supply line Vy2R, and a switching T
A TFT 1001, a driving TFT 1002, an EL element 1003, and a capacitance element 1004,
It has the following features.

The pixel in the second row and first column of the pixel section is configured by changing G1 to G2 and S
It is characterized in that 1a is replaced by S1b and Vy1R is replaced by Vy2R.

The pixel in the third row and first column of the pixel section includes a gate signal line G3, one of the three source signal lines S1c, a power supply line Vx1, a power supply line Vy3R, and a switching TFT 1
1001 , a driving TFT 1002 , an EL element 1003 , and a capacitance element 1004 .

The pixel in the third row and first column of the pixel section is configured by changing G1 to G3 and S
It is characterized in that 1a is replaced by S1c and Vy1R is replaced by Vy3R.

In addition, in the above three rows of pixel columns, G1, G2, and G3 are electrically connected.

The first pixel row is also characterized by a repetition of the above configuration.

In addition, in the second pixel row, in the above configuration, Vx1 is changed to Vx2, S1a is changed to S2a, and S
1b to S2b, S1c to S2c, Vy1R to Vy1G, Vy2R to Vy2G, V
It is characterized in that y3R is replaced with Vy3G.

In addition, in the third pixel column, in the above configuration, Vx1 is changed to Vx3, S1a is changed to S3a, and S
1b to S3b, S1c to S3c, Vy1R to VynB, Vy2R to Vy2B, V
It is characterized in that y3R is replaced with Vy3B.

The third and subsequent pixel columns are characterized by a repeat of the configuration of the above three columns.

Furthermore, Vy1R to VymR are all electrically connected to each other.

Furthermore, Vy1G to VymG are all electrically connected to each other.

Furthermore, Vy1B to VymB are all electrically connected to each other.

According to this embodiment, it is possible to overcome the problem that the write time must be made as long as possible, as described in the first embodiment, and also the problem that the parasitic capacitance must be made as small as possible.

Moreover, according to this embodiment, it is possible to overcome the problem that the wiring resistance must be made as small as possible, as explained in the second, third, or fourth embodiment, and also to overcome the problem that the variation in wiring resistance must be made as small as possible.

Furthermore, according to this embodiment, since a droplet discharge method capable of selectively forming a pattern is used, the EL display device can be manufactured at low cost.

(Embodiment 6)
An embodiment of the present invention will be described with reference to Figures 18 to 19. In this embodiment, a channel-etch type thin film transistor is used as the thin film transistor in embodiment 1. Therefore, repeated description of the same parts or parts having similar functions will be omitted.

A base film 1201 having a function of improving adhesion is formed on a substrate 1200 (see FIG. 18A). Note that an insulating layer may be formed on the substrate 1200. This insulating layer is used as a base film and may not be formed, but has the effect of blocking contaminants from the substrate 1200. In the case of forming a base layer to prevent contamination from the glass substrate, the base film 1201 is formed as a pretreatment in the formation regions of the conductive layers 1202 and 1203 formed thereon by a droplet discharge method.
Form 1.

In this embodiment mode, a substance having a photocatalytic function is used as a base film having a function of improving adhesion.

In this embodiment, a case where TiO _x crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method will be described. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form an undercoat film 1201 made of a metal material such as molybdenum (O) or its oxide. The undercoat film may be formed to a thickness of 0.01 to 10 nm, but it does not necessarily have to have a layer structure because it is only required to be formed very thin. When a high melting point metal material is used as the undercoat film, it is preferable to treat the undercoat film exposed on the surface by carrying out one of the following two steps after forming the conductive layers 1202 and 1203 that will become the gate electrode layers.

The first method is a step of insulating the base film 1201 that does not overlap with the conductive layers 1202 and 1203 to form an insulating layer. That is, the base film 1201 that does not overlap with the conductive layers 1202 and 1203 is oxidized to insulate it. When the base film 1201 is oxidized to insulate it in this way, it is preferable to form the base film 1201 to a thickness of 0.01 to 10 nm, which allows it to be easily oxidized. Note that the oxidation method may be a method of exposing it to an oxygen atmosphere or a method of performing heat treatment.

The second method is a process of etching and removing the base film 1201 using the conductive layers 1202 and 1203 as masks. When this process is used, there is no restriction on the thickness of the base film 1201.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion between the pattern formed by the droplet discharge method and the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic), or a material having a skeletal structure formed by bonding silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent, may be used.

Next, a composition containing a conductive material is discharged to form a conductive layer 12 which will later function as a gate electrode.
The conductive layers 1202 and 1203 are formed by using a droplet discharge means. In this embodiment mode, silver is used as the conductive material, but a laminate of silver and copper or the like may be used. Alternatively, a copper single layer may be used.

In addition, as a pretreatment for the conductive layer formed by the droplet discharge method, the above-mentioned base film 120
However, this treatment step may be carried out after the conductive layer is formed.

Next, a gate insulating film is formed over the conductive layers 1202 and 1203 (see FIG. 18A).
The gate insulating film may be formed of a known material such as a silicon oxide material or a silicon nitride material, and may be a multilayer or a single layer.

Next, a composition containing a conductive material is selectively discharged onto the gate insulating film to form a conductive layer (also referred to as a first electrode) 1206 (see FIG. 18B). When light is emitted from the substrate 1200 side or when a transmissive EL display panel is manufactured, the conductive layer 1206 is
A predetermined pattern may be formed by forming a composition containing indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ₂ ), etc., and then baking the composition. Although not shown, a photocatalytic substance may be formed in the region where the conductive layer 1206 is to be formed, in the same manner as when the conductive layers 1202 and 1203 are formed. The photocatalytic substance improves adhesion, and the conductive layer 1206 can be formed by thinning the conductive layer 1206 into a desired pattern. This conductive layer 1206 becomes a first electrode that functions as a pixel electrode.

The semiconductor layer may be formed by known means (such as sputtering, LPCVD, or plasma CVD). The material of the semiconductor layer is not limited, but is preferably silicon or a silicon germanium (SiGe) alloy.

The semiconductor layer can be made of an amorphous semiconductor (typically hydrogenated amorphous silicon), a semi-amorphous semiconductor or a semiconductor containing a crystalline phase in a part of the semiconductor layer, a crystalline semiconductor (typically polysilicon), or an organic semiconductor.

In this embodiment mode, an amorphous semiconductor is used as the semiconductor. A semiconductor layer 1207 is formed, and a semiconductor layer having one conductivity type, for example, an N-type semiconductor layer 1208 is formed by a plasma CVD method or the like (see FIG. 12C). The semiconductor layer having one conductivity type may be formed as necessary.

Next, mask layers 1211 and 1212 made of an insulating material such as resist or polyimide are formed, and the semiconductor layer 1207 and the N-type semiconductor layer 1208 are formed using the mask layers 1211 and 1212.
are patterned at the same time.

Next, mask layers 1213 and 1214 made of an insulator such as resist or polyimide are formed by a droplet discharge method (see FIG. 18D). Using the mask layers 1213 and 1214, a through hole 1218 is formed in a part of the gate insulating layers 1205 and 1204 by etching, and a part of the conductive layer 1203 functioning as a gate electrode layer arranged on the lower side is exposed.

After removing the mask layers 1213 and 1214, a composition containing a conductive material is discharged to form conductive layers 1215, 1216, and 1217. The conductive layers 1215, 1216, and 1217 are used as masks to pattern the N-type semiconductor layer to form an N-type semiconductor layer (FIG. 19A).
Note that, although not shown, before forming the conductive layers 1215, 1216, and 1217, a photocatalytic substance may be selectively formed in a portion where the conductive layers 1215, 1216, and 1217 are in contact with the gate insulating layer 1205. In this case, the conductive layers can be formed with good adhesion.

The conductive layer 1217 functions as a source/drain wiring layer and is formed so as to be electrically connected to the conductive layer 1206 which is the first electrode formed previously.
In the through hole 1218 formed in the 5, a conductive layer 1216 which is a source or drain wiring layer is
and a conductive layer 1203 which is a gate electrode layer are electrically connected to each other.

The step of forming a through hole 1218 in a part of the gate insulating layers 1205 and 1204 is performed on the conductive layer 1
After forming 215, 1216, and 1217, conductive layers 1215, 1216, and 1217 that will become the wiring layers are
17 may be used as a mask to form a through hole 1218. Then, a conductive layer is formed in the through hole 1218 to electrically connect the conductive layer 1216, which is a wiring layer, and the conductive layer 1203, which is a gate electrode layer. In this case, there is an advantage that the process is simplified.

Next, an insulating layer 1220 that will become a partition is formed. The insulating layer 1220 is formed on the entire surface by a spin coating method or a dipping method, and then an opening is formed by etching as shown in Fig. 19(B). If the insulating layer 1220 is formed by a droplet discharge method, the etching is not necessarily required.

The insulating layer 1220 is formed with openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1206 which is the first electrode.

Through the above steps, a TFT substrate is completed in which a bottom-gate type (also called an inverted staggered type) channel-etch type TFT and a conductive layer 1206 which is a first electrode are connected over the substrate 1200 .

An electroluminescent layer 1221 and a conductive layer 1222 are stacked over the conductive layer 1206 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 19B).
.

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, it is possible to produce a highly reliable display device with improved adhesion and peel resistance.

(Seventh embodiment)
An embodiment of the present invention will be described with reference to Fig. 20 to Fig. 21. In this embodiment, a top-gate (also called staggered) thin film transistor is used as the thin film transistor in the embodiment 1. Therefore, repeated description of the same parts or parts having similar functions will be omitted.

A base film 1301 having a function of improving adhesion is formed on the substrate 1300 (see FIG. 20A). An insulating layer may be formed on the substrate 1300. This insulating layer is not necessarily formed, but has the effect of blocking contaminants from the substrate 1300. In particular, in the case of a staggered thin film transistor as in this embodiment mode, a base layer is necessary because the semiconductor layer is in direct contact with the substrate. When a base layer is formed to prevent contamination from the glass substrate, conductive layers 1315, 1316, and 1317 are formed thereon by a droplet discharge method.
A base film 1301 is formed in a formation region as a pretreatment.

In this embodiment mode, a substance having a photocatalytic function is used as the base film 1301 having a function of improving adhesion.

In this embodiment, a case where TiO _x crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method will be described. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 1301 made of a metal material such as molybdenum (O) or its oxide. The base film 1301 may be formed to a thickness of 0.01 to 10 nm.
Since it is sufficient to form the conductive layer 1315 and the conductive layer 1316 as a source/drain wiring layer, the conductive layer 1315 and the conductive layer 1316 function as a source/drain wiring layer.
After forming 16 and 1317, it is desirable to treat the underlying film exposed on the surface by carrying out one of the following two processes.

In the first method, conductive layers 1315 and 1316 functioning as source/drain wiring layers are formed.
This is a step of insulating the base film 1301 that does not overlap with the conductive layers 1315, 1316, and 1317 that function as source/drain wiring layers, thereby forming an insulating layer. That is, the base film 1301 that does not overlap with the conductive layers 1315, 1316, and 1317 that function as source/drain wiring layers is oxidized to be insulated. When the base film 1301 is oxidized to be insulated in this manner, it is preferable to form the base film 1301 to a thickness of 0.01 to 10 nm, which allows easy oxidation. Note that the oxidation method may be a method of exposing the base film to an oxygen atmosphere or a method of performing heat treatment.

In the second method, conductive layers 1315 and 1316 functioning as source/drain wiring layers are
, 1317 are used as a mask to etch and remove the base film 1301. When this process is used, there is no restriction on the thickness of the base film 1301.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material-based substance that functions as an adhesive may be formed to increase the adhesion between the pattern formed by the droplet discharge method and the region where it is formed. The skeletal structure is formed by the bond between an organic material (organic resin material) (polyimide, acrylic) or silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Next, a composition containing a conductive material is discharged to form conductive layers 1315, 1316, and 1317 that function as source/drain wiring layers.
The formation of the liquid droplets is carried out by using a liquid droplet ejection means.

Conductive materials for forming the conductive layers 1315, 1316, and 1317 include Ag (silver),
A composition mainly composed of metal particles such as Au (gold), Cu (copper), W (tungsten), and Al (aluminum) can be used. In particular, since it is preferable to reduce the resistance of the source or drain wiring layer, it is preferable to use a material in which any of gold, silver, and copper is dissolved or dispersed in a solvent in consideration of the resistivity value, and more preferably, low-resistance silver or copper is used. The solvent corresponds to esters such as butyl acetate, alcohols such as isopropyl alcohol, organic solvents such as acetone, and the like. The surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant, etc.

Next, a composition containing a conductive material is selectively discharged to form a conductive layer (also called a first electrode).
1306 is formed (see FIG. 20A). When light is emitted from the substrate 1300 side or when a transmissive EL display panel is manufactured, the conductive layer 1306 may be formed by forming a predetermined pattern using a composition containing indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like, and baking the pattern. Although not shown, conductive layers 1315 and 1316 are formed in the region where the conductive layer 1306 is to be formed.
, 1317, a photocatalytic substance may be formed.
The adhesiveness is improved, and the conductive layer 1306 can be thinned into a desired pattern to form the conductive layer 1306. This conductive layer 1306 becomes a first electrode that functions as a pixel electrode.

In addition, as a pretreatment for the conductive layer formed by the droplet discharge method, the above-mentioned base film 130
However, this treatment step may be performed after forming the conductive layers 1315, 1316, and 1317. For example, although not shown, if a titanium oxide film is formed and an N-type semiconductor layer is formed thereon, the adhesion between the conductive layer and the N-type semiconductor layer is improved.

After forming an N-type semiconductor layer on the entire surface of the conductive layers 1315, 1316, and 1317, the N-type semiconductor layers between the conductive layers 1315 and 1316 and between the conductive layers 1316 and 1317 are masked with mask layers 1311, 1312, and 1313 made of an insulator such as resist or polyimide.
9 and then etched away. A semiconductor layer having one conductivity type may be formed as necessary. Then, a semiconductor layer 1307 made of an amorphous semiconductor (hereinafter referred to as AS) or an SAS is formed by a vapor phase growth method or a sputtering method. When using a plasma CVD method, the AS is formed by using a semiconductor material gas, SiH ₄ or a mixed gas of SiH ₄ and H _2. The SAS is formed by diluting the SiH ₄ and H ₂ by 3 to 1000 times to form a mixed gas. When forming an SAS with this gas type, the crystallinity is better on the surface side of the semiconductor layer, and it is suitable for combination with a top-gate type TFT in which a gate electrode is formed on the upper layer of the semiconductor layer.

Next, a gate insulating layer 1305 is formed to have a single layer or a laminated structure by using a plasma CVD method or a sputtering method. In a particularly preferred embodiment, a three-layer laminate of an insulating layer made of silicon nitride, an insulating layer made of silicon oxide, and an insulating layer made of silicon nitride is formed as the gate insulating film.

Next, gate electrode layers 1302 and 1303 are formed by a droplet discharge method. Examples of conductive materials for forming these layers include Ag (silver), Au (gold), Cu (copper), W (tungsten), and Al (
Compositions based on particles of a metal such as aluminum can be used.

The semiconductor layer 1307 and the gate insulating layer 1305 are formed by a mask layer 1 formed by a droplet discharge method.
313, 1314 are used to form source or drain wiring layers (conductive layers 1315, 1316, 1317).
That is, the semiconductor layer is formed so as to straddle the conductive layer 1315 and the conductive layer 1316.

Next, conductive layers 1330 and 1331 are formed by a droplet discharging method, and the conductive layer 1316 and the gate electrode layer 1303, and the conductive layer 1317 and the conductive layer 1306 which is a first electrode are electrically connected to each other.

The drain or source wiring layer and the gate electrode layer may be directly connected by the gate electrode layer without using the conductive layer 1330. In that case, before forming the gate electrode layers 1302 and 1303, a through hole is formed in the gate insulating layer 1305 to expose parts of the conductive layers 1316 and 1317 which are source or drain wirings, and then the gate electrode layers 1302 and 1303 and the conductive layer 1331 are formed by a droplet discharge method. At this time, the gate electrode layer 1303 becomes a wiring which also serves as the conductive layer 1330 and is connected to the conductive layer 1316. The etching may be dry etching or wet etching, but plasma etching which is dry etching is preferable.

Next, an insulating layer 1320 that will become a partition wall is formed.
A protective layer of silicon nitride or silicon nitride oxide may be formed on the entire surface so as to cover the thin film transistor under the insulating layer 1320. After forming an insulating layer on the entire surface by a spin coating method or a dip method, an opening is formed by etching as shown in FIG. 21. If the insulating layer 1320 is formed by a droplet discharge method, etching is not necessarily required. When a wide area such as the insulating layer 1320 is formed by the droplet discharge method, throughput is improved by discharging a composition from multiple nozzle outlets of a droplet discharge device and drawing and forming multiple lines so that they overlap.

The insulating layer 1320 is formed with openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1306 which is the first electrode.

Through the above steps, a TFT substrate is completed in which a top-gate type (also called an inverted staggered type) TFT and a conductive layer 1306 which is a first electrode layer are connected over the substrate 1300 .

Before forming the electroluminescent layer 1321, a heat treatment at 200° C. is performed under atmospheric pressure to form the insulating layer 132
The moisture adsorbed in or on the surface of the 0 is removed.
Then, the electroluminescent layer 13 is heated at a temperature of preferably 250 to 350° C. without being exposed to the air.
It is preferable that the film 21 is formed by a vacuum deposition method or a droplet discharge method under reduced pressure.

An electroluminescent layer 1321 and a conductive layer 1322 are stacked over the conductive layer 1306 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 21).

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

It is also possible to produce a highly reliable display device with improved adhesion and peel resistance.

(Embodiment 8)
An embodiment of the present invention will be described with reference to Figures 22 and 23. This embodiment is different from the first embodiment in the connection structure between the thin film transistor and the first electrode.
Therefore, repeated description of identical parts or parts having similar functions will be omitted.

On a substrate 1400, a base film 1401 for improving adhesion is formed as a base pretreatment. In this embodiment, a case where _TiOx crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method is described. A metal titanium tube is used as a target,
Sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 1401 made of a metal material such as molybdenum (O) or its oxide. The base film 1401 may be formed to a thickness of 0.01 to 10 nm.
Since it is sufficient to form the base film extremely thinly, it does not necessarily have to have a layer structure. When a high melting point metal material is used as the base film, it is desirable to treat the base film exposed on the surface by performing one of the following two steps after forming the conductive layers 1402 and 1403 that will become the gate electrode layers.

The first method is a step of insulating the base film 1401 that does not overlap with the conductive layers 1402 and 1403 to form an insulating layer. That is, the base film 1401 that does not overlap with the conductive layers 1402 and 1403 is oxidized to be insulated. When the base film 1401 is oxidized to be insulated in this manner, it is preferable to form the base film 1401 to a thickness of 0.01 to 10 nm, which allows easy oxidation. Note that the oxidation method may be a method of exposing the base film to an oxygen atmosphere or a method of performing heat treatment.

The second method is a process of etching and removing the base film 1401 using the conductive layers 1402 and 1403 as masks. When this process is used, there is no restriction on the thickness of the base film 1401.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion between the pattern formed by the droplet discharge method and the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic), or a material having a skeletal structure formed by bonding silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent, may be used.

Next, a composition containing a conductive material is discharged to form a conductive layer 14 which will later function as a gate electrode.
The conductive layers 1402 and 1403 are formed by using a droplet discharge means. In this embodiment mode, silver is used as the conductive material, but a laminate of silver and copper or the like may be used. Alternatively, a copper single layer may be used.

In addition, as a pretreatment for the conductive layer formed by the droplet discharge method, the above-mentioned base film 140
However, this treatment step may be carried out after the conductive layer is formed.

Next, a gate insulating film is formed over the conductive layers 1402 and 1403 (see FIG. 22A).
The gate insulating film may be formed of a known material such as a silicon oxide material or a silicon nitride material, and may be a multilayer or a single layer.

The semiconductor layer may be formed by known means (such as sputtering, LPCVD, or plasma CVD). The material of the semiconductor layer is not limited, but is preferably silicon or a silicon germanium (SiGe) alloy.

The semiconductor layer can be made of an amorphous semiconductor (typically hydrogenated amorphous silicon), a semi-amorphous semiconductor or a semiconductor containing a crystalline phase in a part of the semiconductor layer, a crystalline semiconductor (typically polysilicon), or an organic semiconductor.

In this embodiment mode, an amorphous semiconductor is used as the semiconductor.
To form the channel protective films 1409 and 1410, for example, an insulating film is formed by plasma CVD and selectively etched to have a desired shape in a desired region. The channel protective film may be formed of polyimide, polyvinyl alcohol, or the like by using a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing).
Thereafter, a semiconductor layer having one conductivity type, for example, an N-type semiconductor layer 14, is formed by a plasma CVD method or the like.
08. The semiconductor layer having one conductivity type may be formed as necessary.

Next, mask layers 1411 and 1412 made of an insulating material such as resist or polyimide are formed, and the semiconductor layer 1407 and the N-type semiconductor layer 1408 are formed using the mask layers 1411 and 1412.
are patterned at the same time.

Next, mask layers 1413 and 1414 made of an insulator such as resist or polyimide are formed by a droplet discharge method (see FIG. 22C). Using the mask layers 1413 and 1414, a through hole 1418 is formed in a part of the gate insulating layers 1405 and 1404 by etching, and a part of the conductive layer 1403 functioning as a gate electrode layer arranged on the lower layer side is exposed. Either plasma etching (dry etching) or wet etching may be used for the etching, but plasma etching is suitable for processing a large-area substrate. In addition, if atmospheric discharge etching is applied, localized discharge processing is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

After removing the mask layers 1413 and 1414, a composition containing a conductive material is discharged to form conductive layers 1415, 1416, and 1417, and the N-type semiconductor layer is patterned using the conductive layers 1415, 1416, and 1417 as masks (see FIG. 22D).
The above-mentioned base pretreatment step may be performed to selectively form a photocatalytic substance or the like on a portion of the insulating layer 1417 that is in contact with the gate insulating layer 1405. In addition, a base pretreatment step may be performed on the surface after the formation of the insulating layer 1417. By this step, the conductive layer can be formed with good adhesion to the layers above and below it.

In addition, the conductive layers 1415, 1416, and 1417, which are wiring layers, are as shown in FIG.
The insulating layers 1441, 1442, and 1443 are formed to cover the N-type semiconductor layer and the semiconductor layer. Since the semiconductor layer is etched, there is a risk that the wiring layer will not be able to cover the semiconductor layer at the location where there is a sharp step, resulting in disconnection. Therefore, in order to reduce the step, insulating layers 1441, 1442, and 1443 may be formed to make the step gentler. The insulating layers 1441, 1442, and 1443 can be selectively formed without a mask or the like by using a droplet discharge method. The insulating layers 1441, 1442, and 1443 reduce the step, and the wiring layer covering them can be formed with good coverage without defects such as disconnection. The insulating layers 1441, 1442, and 1443 can be formed of silicon oxide, silicon nitride, silicon oxynitride,
Aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, or acrylic acid, methacrylic acid and their derivatives, or polyimide
), aromatic polyamide, polybenzimidazole
) or siloxane-based materials as starting materials.
Among compounds containing hydrogen, the insulating material can be an inorganic siloxane containing a Si--O--Si bond, or an organic siloxane-based insulating material in which hydrogen on silicon is replaced by an organic group such as methyl or phenyl.

Next, a conductive layer 1 serving as a source/drain wiring layer is selectively formed on the gate insulating film.
A conductive layer (also referred to as a first electrode) 1406 is formed by discharging a composition containing a conductive material so as to be in contact with the substrate 1400 (see FIG. 23A). When light is emitted from the substrate 1400 side or when a transmissive EL display panel is manufactured, the conductive layer 1406 is made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Alternatively, a predetermined pattern may be formed by forming a composition containing tin oxide (SnO2) or the like and firing the composition.
As in the case of forming 3, a base pretreatment such as the formation of a photocatalytic substance may be performed. The base pretreatment improves adhesion and allows the conductive layer 1406 to be thinned into a desired pattern. This conductive layer 1406 becomes a first electrode that functions as a pixel electrode.

In addition, a conductive layer 1416 which is a source or drain wiring layer and a conductive layer 1403 which is a gate electrode layer are electrically connected to each other through a through hole 1418 formed in the gate insulating layer 1405. Examples of conductive materials for forming this wiring layer include Ag (silver), Au (gold), Cu (copper),
A composition containing metal particles such as W (tungsten) and Al (aluminum) as a main component can be used. In addition, a combination of light-transmitting indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, etc. may be used.

After the conductive layers 1415, 1416, 1417, and 1406 are formed, the conductive layers 1415 and 1406 are
A through hole 1418 may be formed by using the conductive layers 1416, 1417, and 1406 as a mask. Then, a conductive layer is formed in the through hole 1418, and the conductive layer 140 which is a gate electrode layer is formed on the conductive layer 1416.
3 is electrically connected.

Next, an insulating layer 1420 that will become a partition wall is formed.
A protective layer of silicon nitride or silicon nitride oxide may be formed on the entire surface so as to cover the thin film transistor under the insulating layer 1420. After forming an insulating layer on the entire surface by a spin coating method or a dip method, an opening is formed by etching as shown in FIG. 23B. If the insulating layer 1420 is formed by a droplet discharge method, etching is not necessarily required. When a wide area such as the insulating layer 1420 is formed by the droplet discharge method, the throughput is improved by discharging a composition from multiple nozzle discharge ports of a droplet discharge device and drawing and forming multiple lines so as to overlap each other.

The insulating layer 1420 is formed with openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1406 which is the first electrode.

Through the above steps, a bottom gate type (also called an inverted staggered type) channel protective TFT and a conductive layer (first electrode layer) 1406 are connected to each other on the substrate 1400.
The FT substrate is completed.

An electroluminescent layer 1421 and a conductive layer 1422 are stacked over the conductive layer 1406 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 23B).

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, it is possible to produce a highly reliable display device with improved adhesion and peel resistance.

(Embodiment 9)
An embodiment of the present invention will be described with reference to Figures 24 to 25. This embodiment is different from the sixth embodiment in the connection structure between the thin film transistor and the first electrode.
Therefore, repeated description of identical parts or parts having similar functions will be omitted.

On the substrate 1500, a base film 1501 is formed as a base pretreatment to improve adhesion. In this embodiment, a case where TiO _x crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method will be described. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating a film formation chamber or a substrate on which a processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 1501 made of a metal material such as molybdenum (O) or its oxide. The base film 1501 may be formed to a thickness of 0.01 to 10 nm.
Since it is sufficient to form the base film extremely thinly, it does not necessarily have to have a layer structure. When a high melting point metal material is used as the base film, it is desirable to treat the base film exposed on the surface by performing one of the following two steps after forming the conductive layers 1502 and 1503 that will become the gate electrode layers.

The first method is a step of insulating the base film 1501 that does not overlap with the conductive layers 1502 and 1503 to form an insulating layer. That is, the base film 1501 that does not overlap with the conductive layers 1502 and 1503 is oxidized to insulate it. When the base film 1501 is oxidized to insulate it in this way, it is preferable to form the base layer 1501 to a thickness of 0.01 to 10 nm, which allows easy oxidation. Note that the oxidation method may involve exposure to an oxygen atmosphere or may involve heat treatment.

The second method is a process of etching and removing the base film 1501 using the conductive layers 1502 and 1503 as masks. When this process is used, there is no restriction on the thickness of the base film 1501.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion between the pattern formed by the droplet discharge method and the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic), or a material having a skeletal structure formed by bonding silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent, may be used.

Next, a composition containing a conductive material is discharged to form a conductive layer 15 which will later function as a gate electrode.
The conductive layers 1502 and 1503 are formed by using a droplet discharge means. In this embodiment mode, silver is used as the conductive material, but a laminate of silver and copper or the like may be used. Alternatively, a copper single layer may be used.

In addition, as a pretreatment for the conductive layer formed by the droplet discharge method, the above-mentioned base film 150
However, this treatment step may be carried out after the conductive layer is formed.

Next, a gate insulating film is formed over the conductive layers 1502 and 1503 (see FIG. 24A).
The gate insulating film may be formed of a known material such as a silicon oxide material or a silicon nitride material, and may be a multilayer or a single layer.

The semiconductor layer may be formed by known means (such as sputtering, LPCVD, or plasma CVD). The material of the semiconductor layer is not limited, but is preferably silicon or a silicon germanium (SiGe) alloy.

The semiconductor layer can be made of an amorphous semiconductor (typically hydrogenated amorphous silicon), a semi-amorphous semiconductor or a semiconductor containing a crystalline phase in a part of the semiconductor layer, a crystalline semiconductor (typically polysilicon), or an organic semiconductor.

In this embodiment mode, an amorphous semiconductor is used as the semiconductor.
A semiconductor layer having one conductivity type, for example, an N-type semiconductor layer 1508, is formed by plasma CVD or the like. The semiconductor layer having one conductivity type may be formed as necessary.

Next, mask layers 1511 and 1512 made of an insulating material such as resist or polyimide are formed, and the semiconductor layer 1507 and the N-type semiconductor layer 1508 are formed using the mask layers 1511 and 1512.
are simultaneously patterned (see FIG. 24(B)).

Next, mask layers 1513 and 1514 made of an insulator such as resist or polyimide are formed by a droplet discharge method (see FIG. 24C). Using the mask layers 1513 and 1514, a through hole 1518 is formed in a part of the gate insulating layers 1505 and 1504 by etching, and a part of the conductive layer 1503 functioning as a gate electrode layer arranged on the lower layer side is exposed. Either plasma etching (dry etching) or wet etching may be used for the etching, but plasma etching is suitable for processing a large-area substrate. Furthermore, if atmospheric discharge etching is applied, localized discharge processing is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

After removing the mask layers 1513 and 1514, a composition containing a conductive material is discharged to form conductive layers 1515, 1516, and 1517, and the N-type semiconductor layer is patterned using the conductive layers 1515, 1516, and 1517 as masks (see FIG. 24D).
The above-mentioned base pretreatment step may be performed to selectively form a photocatalytic substance or the like on a portion where the conductive layer 517 contacts the gate insulating layer 1505. In addition, a base pretreatment step may be performed on the surface after the formation. By this step, the conductive layer can be formed with good adhesion to the layers above and below it.

Next, a conductive layer 1 serving as a source/drain wiring layer is selectively formed on the gate insulating film.
A composition containing a conductive material is discharged so as to be in contact with the conductive layer 1507 to form a conductive layer (also referred to as a first electrode) 1506 (see FIG. 25A). When light is emitted from the substrate 1500 side or when a transmissive EL display panel is manufactured, the conductive layer 1506 may be made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Alternatively, a predetermined pattern may be formed by forming a composition containing tin oxide (SnO ₂ ) or the like and firing the composition.
As in the case of forming the conductive layer 1506, a pretreatment such as forming a photocatalytic substance may be performed. The pretreatment improves adhesion and allows the conductive layer 1506 to be thinned into a desired pattern. This conductive layer 1506 becomes a first electrode that functions as a pixel electrode.

In addition, a conductive layer 1516 which is a source or drain wiring layer and a conductive layer 1503 which is a gate electrode layer are electrically connected to each other in a through hole 1518 formed in the gate insulating layer 1505. Examples of conductive materials for forming this conductive layer include Ag (silver), Au (gold), Cu (copper),
A composition containing metal particles such as W (tungsten) and Al (aluminum) as a main component can be used. In addition, a combination of light-transmitting indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, etc. may be used.

After the conductive layers 1515, 1516, 1517, and 1506 are formed, the conductive layers 1515 and 1
A through hole 1518 may be formed by using the layers 1516, 1517, and 1506 as a mask. Then, a conductive layer is formed in the through hole 1518, and the conductive layer 1516 and the conductive layer 150 which is a gate electrode layer are formed.
3 is electrically connected.

Next, an insulating layer 1520 that will become a partition wall is formed.
A protective layer of silicon nitride or silicon nitride oxide may be formed on the entire surface so as to cover the thin film transistor under the insulating layer 1520. After forming an insulating layer on the entire surface by a spin coating method or a dip method, an opening is formed by etching as shown in FIG. 25B. If the insulating layer 1520 is formed by a droplet discharge method, etching is not necessarily required. When a wide area such as the insulating layer 1520 is formed by the droplet discharge method, the throughput is improved by discharging a composition from multiple nozzle outlets of a droplet discharge device and drawing and forming multiple lines so as to overlap each other.

The insulating layer 1520 is formed to have openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1506 which is the first electrode.

Through the above steps, a TFT substrate for an EL display panel is completed, in which a bottom-gate type (also called an inverted staggered type) channel-etched TFT and a first electrode (first electrode layer) 1506 are connected on a substrate 1500 .

An electroluminescent layer 1521 and a conductive layer 1522 are stacked over the conductive layer 1506 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 25B).
.

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, it is possible to produce a highly reliable display device with improved adhesion and peel resistance.

(Embodiment 10)
An embodiment of the present invention will be described with reference to Figures 26 to 27. This embodiment is different from the seventh embodiment in the connection structure between the thin film transistor and the first electrode.
Therefore, repeated description of identical parts or parts having similar functions will be omitted.

A base film 1601 having a function of improving adhesion is formed on the substrate 1600 (see FIG. 26A). Note that an insulating layer may be formed on the substrate 1600. This insulating layer is not necessarily formed, but has the effect of blocking contaminants from the substrate 1600. In particular, in the case of a staggered thin film transistor as in this embodiment mode, the semiconductor layer is in direct contact with the substrate, so that the base layer is effective. When a base layer is formed to prevent contamination from the glass substrate, the base film 1601 is formed as a pretreatment in the formation regions of the conductive layers 1615, 1616, and 1617 formed by a droplet discharge method.

In this embodiment mode, a substance having a photocatalytic function is used as the base film 1601 having a function of improving adhesion.

In this embodiment, a case where TiO _x crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method will be described. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 1601 made of a metal material such as molybdenum (O) or its oxide. The base film 1601 may be formed to a thickness of 0.01 to 10 nm.
Since it is sufficient to form the conductive layer 1615 and 1616 as a very thin layer, the conductive layer 1615 and 1616 function as a source/drain wiring layer.
After forming 16 and 1617, it is desirable to treat the underlying film exposed on the surface by carrying out one of the following two processes.

In the first method, conductive layers 1615 and 1616 functioning as source/drain wiring layers are formed.
This is a step of insulating the base film 1601 that does not overlap with the conductive layers 1615, 1616, and 1617 that function as source/drain wiring layers, thereby forming an insulating layer. That is, the base film 1601 that does not overlap with the conductive layers 1615, 1616, and 1617 that function as source/drain wiring layers is oxidized to be insulated. When the base film 1601 is oxidized to be insulated in this manner, it is preferable to form the base film 1601 to a thickness of 0.01 to 10 nm, which allows easy oxidation. Note that the oxidation method may be a method of exposing the base film to an oxygen atmosphere or a method of performing heat treatment.

In the second method, conductive layers 1615 and 1616 functioning as source/drain wiring layers are formed.
, 1617 are used as a mask to etch and remove the base film 1601. When this process is used, there is no restriction on the thickness of the base film 1601.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion of the pattern formed by the droplet discharge method to the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic), or a material having a skeletal structure formed by bonding silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent, may be used.

Next, a composition containing a conductive material is discharged to form conductive layers 1615, 1616, and 1617 that function as source/drain wiring layers.
The formation of the liquid droplets is carried out by using a liquid droplet ejection means.

Conductive materials for forming the conductive layers 1615, 1616, and 1617 include Ag (silver),
A composition containing metal particles such as Au (gold), Cu (copper), W (tungsten), and Al (aluminum) as the main component can be used. In particular, since it is preferable to reduce the resistance of the source or drain wiring layer, it is preferable to use a material in which any of gold, silver, and copper is dissolved or dispersed in a solvent in consideration of the resistivity value, and more preferably, low-resistance silver or copper is used. In addition, particles in which another conductive material is coated around a conductive material to form multiple layers may be used. For example, particles having a three-layer structure in which nickel boron (NiB) is coated around copper and silver is coated around it may be used. The solvent corresponds to esters such as butyl acetate, alcohols such as isopropyl alcohol, organic solvents such as acetone, etc. The surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant, etc.

In addition, as a pretreatment for the conductive layer formed by the droplet discharge method, the above-mentioned base film 160
However, this treatment step may be performed after forming the conductive layers 1615, 1616, and 1617. For example, although not shown, if a titanium oxide film is formed and an N-type semiconductor layer is formed thereon, the adhesion between the conductive layer and the N-type semiconductor layer is improved.

After an N-type semiconductor layer is formed over the entire surface of the conductive layers 1615, 1616, and 1617, the N-type semiconductor layer between the conductive layers 1615 and 1616 and between the conductive layers 1616 and 1617 is removed by etching using mask layers 1611, 1612, and 1619 made of an insulator such as resist or polyimide. A semiconductor layer having one conductivity type may be formed as necessary. Then, a semiconductor layer 1607 made of AS or SAS is formed by vapor phase growth or sputtering. When using plasma CVD, AS is formed using a semiconductor material gas, _SiH4 or a mixed gas of _SiH4 and _H2 . SAS is formed by mixing _SiH4 with _H2 to 3 times the concentration of H2.
It is formed with a mixed gas diluted 1000 times. When forming a SAS with this gas type, the crystallinity is better on the surface side of the semiconductor layer, and it is suitable for combination with a top-gate type TFT in which the gate electrode is formed on the upper layer of the semiconductor layer.

Next, a gate insulating layer 1605 is formed to have a single layer or a stacked structure by using a plasma CVD method or a sputtering method (see FIG. 26B). In a particularly preferred embodiment, a stacked structure of three layers, an insulating layer made of silicon nitride, an insulating layer made of silicon oxide, and an insulating layer made of silicon nitride, is formed as the gate insulating film.

Next, conductive layers 1602 and 1603 which are gate electrode layers are formed by a droplet discharge method (FIG. 26
(C)). The conductive material for forming this layer is Ag (silver), Au (gold), Cu (
A composition containing particles of a metal such as copper (Cu), W (tungsten), or Al (aluminum) as a main component can be used.

The semiconductor layer 1607 and the gate insulating layer 1605 are formed by a mask layer 1
613 and 1614 are used to form source or drain wiring layers (conductive layers 1615, 1616,
That is, the semiconductor layer is formed so as to straddle the conductive layers 1615 and 1616 which are source and drain wiring layers.

Next, conductive layers 1630 and 1631 are formed by a droplet discharge method.
03.

Subsequently, a conductive layer (also referred to as a first electrode) 1606 is formed by selectively discharging a composition containing a conductive material so as to be in contact with the conductive layer 1631. The conductive layer 1606 may have a structure in which it is in direct contact with the conductive layer 1617. When light is emitted from the substrate 1600 side or when a transmissive EL display panel is manufactured, the conductive layer 1606 is formed of indium tin oxide (I
Alternatively, a predetermined pattern may be formed by forming a composition containing, for example, indium tin oxide (ITSO), zinc oxide (ZnO), or tin oxide (SnO ₂ ), and then baking the composition.
A photocatalytic substance may be formed in the same manner as when forming 617. The photocatalytic substance improves adhesion and allows the conductive layer 1606 to be thinned into a desired pattern. This conductive layer 1606 becomes a first electrode that functions as a pixel electrode.

The drain or source wiring layer and the gate electrode layer may be directly connected to each other by the gate electrode layer without using the conductive layer 1630. In that case, the conductive layers 1602 and 1603 which are the gate electrode layers may be directly connected to each other.
Before forming the gate insulating layer 1603, a through hole is formed in the gate insulating layer 1605 to expose a part of the conductive layers 1616 and 1617 which are source and drain wirings.
The conductive layers 602 and 1603 and the conductive layer 1631 are formed by a droplet discharge method. At this time, the conductive layer 1603 becomes a wiring that also serves as the conductive layer 1630, and is connected to the conductive layer 1616. Although the etching may be dry etching or wet etching, plasma etching, which is dry etching, is preferable.

Next, an insulating layer 1620 that will become a partition wall is formed.
A protective layer of silicon nitride or silicon nitride oxide may be formed on the entire surface so as to cover the thin film transistor under the insulating layer 1620. After forming an insulating layer on the entire surface by a spin coating method or a dip method, an opening is formed by etching as shown in FIG. 27. If the insulating layer 1620 is formed by a droplet discharge method, etching is not necessarily required. When a wide area such as the insulating layer 1620 is formed by the droplet discharge method, throughput is improved by discharging a composition from multiple nozzle discharge ports of a droplet discharge device and drawing and forming multiple lines so as to overlap each other.

The insulating layer 1620 is formed with openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1606 which is the first electrode.

By the above steps, a top-gate type (also called a staggered type) TFT is formed on the substrate 1600.
A TFT substrate is completed in which the conductive layer (first electrode layer) 1606 is connected.

Before forming the electroluminescent layer 1621, a heat treatment at 200° C. is performed under atmospheric pressure to form the insulating layer 162
The moisture adsorbed in or on the surface of the 0 is removed.
Then, the electroluminescent layer 16 is heated at a temperature of preferably 250 to 350° C. without being exposed to the air.
It is preferable that the film 21 is formed by a vacuum deposition method or a droplet discharge method under reduced pressure.

An electroluminescent layer 1621 and a conductive layer 1622 are stacked over the conductive layer 1606 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 27).

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, it is possible to produce a highly reliable display device with improved adhesion and peel resistance.

(Embodiment 11)
An embodiment of the present invention will be described with reference to Fig. 28 and Fig. 29. This embodiment differs from the first embodiment in that a conductive layer 816, which is a wiring layer, is connected to a conductive layer 803, which is a gate electrode layer, through a gate insulating layer 805. Therefore, repeated description of the same parts or parts having similar functions will be omitted.

A base film 1701 for improving adhesion is formed over a substrate 1700 (see FIG. 28A). Note that an insulating layer may be formed over the substrate 1700.

In this embodiment mode, a substance having a photocatalytic function is used as the base film 1701 having a function of improving adhesion.

In this embodiment, a case where TiO _x crystals having a predetermined crystal structure are formed as a photocatalytic substance by a sputtering method will be described. A metal titanium tube is used as a target, and sputtering is performed using argon gas and oxygen. He gas may also be introduced. In order to form TiO _x with high photocatalytic activity, an atmosphere containing a large amount of oxygen is used, and the formation pressure is increased. Furthermore, it is preferable to form TiO _x while heating the film formation chamber or the substrate on which the processing object is provided.

Even if the TiO _x film thus formed is very thin, it has a photocatalytic function.

As another pretreatment for the substrate, Ti (titanium), W (tungsten), Cr (chromium), Ta (tantalum), Ni (nickel), M are deposited by sputtering or vapor deposition.
It is preferable to form a base film 1701 made of a metal material such as molybdenum (O) or its oxide. The base film 1701 may be formed to a thickness of 0.01 to 10 nm.
Since it is sufficient to form the base film extremely thinly, it does not necessarily have to have a layer structure. When a high melting point metal material is used as the base film, it is desirable to treat the base film exposed on the surface by performing one of the following two steps after forming the conductive layers 1702 and 1703 that will become the gate electrode layers.

In the first step, the base film 1701 that does not overlap the conductive layers 1702 and 1703 is insulated.
This is a step of forming an insulating layer.
In this way, when the base film 1701 is oxidized to be insulating, it is preferable to form the base film 1701 to a thickness of 0.01 to 10 nm.
In this way, oxidation can be easily achieved. As a method for oxidation, a method of exposing the material to an oxygen atmosphere or a method of carrying out a heat treatment can be used.

The second step is a step of etching and removing the base film 1701 using the conductive layers 1702 and 1703 as masks. When this step is used, there is no restriction on the thickness of the base film 1701.

Another method for pre-treatment of the substrate is to perform plasma treatment on the formation region (surface to be formed). The conditions for the plasma treatment are to use air, oxygen or nitrogen as the treatment gas and to set the pressure to several tens of Torr to 1000 Torr (133000 Pa), preferably 100 (1330
0 Pa) to 1000 Torr (133,000 Pa), more preferably 700 Torr (9
A pulse voltage is applied at a pressure of 1×10 ¹⁰ to 800 Torr (106,400 Pa), i.e., atmospheric pressure or a pressure close to atmospheric pressure.
^The plasma treatment is carried out using ^a treatment gas of air, oxygen or nitrogen, so that the surface can be modified regardless of the material. As a result, the surface can be modified on any material.

As another method, an organic material that functions as an adhesive may be formed to increase the adhesion of the pattern formed by the droplet discharge method to the region where the pattern is formed. An organic material (organic resin material) (polyimide, acrylic), or a material having a skeletal structure formed by bonding silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent, may be used.

Next, a composition containing a conductive material is discharged to form a conductive layer 17 which will later function as a gate electrode.
The conductive layers 1702 and 1703 are formed by using a droplet discharge means.

After the conductive layer 1703 is formed, a composition containing a conductive material is locally discharged to form a conductor 1704 that functions as a pillar. The conductor 1704 is formed by depositing the discharged composition, and is preferably formed in a cylindrical shape to facilitate contact between a lower pattern and an upper pattern. The conductor 1704 may be formed using the same material as the conductive layer 1703 or a different material, and may be formed by discharging the composition in layers.

In addition, after forming the conductive layer 1703, in order to further increase adhesion, the above-mentioned base pretreatment may be performed on the conductive layer 1703. In addition, it is preferable to perform a base film treatment similarly after forming the conductor 1704 that will become a pillar. By performing a base pretreatment such as forming a photocatalytic substance such as TiO _{2 X} , film layers can be formed with good adhesion.

Next, a gate insulating film is formed over the conductive layers 1702 and 1703 (see FIG. 28A).
.

Next, a conductive layer (also referred to as a first electrode) 1706 is formed by selectively discharging a composition containing a conductive material onto the gate insulating film (see FIG. 28B).
A photocatalytic substance may be formed in the region where the conductive layer 1706 is to be formed, in the same manner as when the conductive layers 1702 and 1703 are formed. The photocatalytic substance improves adhesion, and the conductive layer 1706 can be formed by thinning it into a desired pattern. The conductive layer 1706 is a first layer that functions as a pixel electrode.
This becomes the electrode.

In this embodiment, an amorphous semiconductor is used as the semiconductor. In order to form the semiconductor layer 1707, which is an amorphous semiconductor layer, and to form the channel protective films 1709 and 1710, an insulating film is formed by, for example, a plasma CVD method, and selectively etched to have a desired shape in a desired region. At this time, the channel protective films 1709 and 1710 can be formed by exposing the back surface of the substrate using the gate electrode as a mask. In addition, polyimide or polyvinyl alcohol may be dropped by a droplet discharge method to form the channel protective film. As a result, the exposure step can be omitted. After that, a semiconductor layer having one conductivity type, for example, an N-type semiconductor layer 1708 is formed by using an N-type amorphous semiconductor layer by a plasma CVD method or the like. (
(See FIG. 28C.) The semiconductor layer having one conductivity type may be formed as necessary.

Next, mask layers 1711 and 1712 made of an insulating material such as resist or polyimide are formed, and the semiconductor layer 1707 and the N-type semiconductor layer 1708 are formed using the mask layers 1711 and 1712.
are patterned at the same time.

In this embodiment mode, a conductor connected to the conductive layer 1703, which is a gate electrode layer, by a conductor 1704 functioning as a pillar penetrates the gate insulating layer 1705 and is present on the gate insulating layer 1705. Therefore, a step of opening a through hole in the gate insulating layer can be omitted.

A composition containing a conductive material is discharged to form conductive layers 1715, 1716, and 1717.
The N-type semiconductor layer is patterned using the conductive layers 1715, 1716, and 1717 as masks. Although not shown, before forming the conductive layers 1715, 1716, and 1717, a photocatalytic substance may be selectively formed in the portions where the conductive layers 1715, 1716, and 1717 are in contact with the gate insulating layer 1705. In this case, the conductive layers can be formed with good adhesion.

The conductive layer 1717 functions as a source/drain wiring layer and is formed so as to be electrically connected to the first electrode formed previously.
The conductor 1704 can be electrically connected to the conductive layer 1703 which is a gate electrode layer through the conductor 1704 (see FIG. 29A). If an insulating layer or the like remains on the conductor 1704 which functions as a pillar, it may be removed by etching or the like.

Next, an insulating layer 1720 is formed to serve as a partition wall.

The insulating layer 1720 is formed to have openings of through holes aligned with the positions where pixels are to be formed corresponding to the conductive layer 1706 which is the first electrode.

Through the above steps, a TFT substrate for an EL display panel in which a bottom-gate type (also called an inverted staggered type) channel protective TFT and a first electrode (first electrode layer) are connected on the substrate 1700 is completed.

An electroluminescent layer 1721 and a conductive layer 1722 are stacked over the conductive layer 1706 which is a first electrode, to complete a display device having a display function using a light-emitting element (see FIG. 29B).
.

As described above, in this embodiment, the light exposure process using a photomask is not used, so that the process can be omitted. Also, by forming various patterns directly on the substrate using the droplet discharge method, even if a fifth generation or later glass substrate with a side length of more than 1000 mm is used, an EL display panel can be easily manufactured.

In addition, a display device with improved adhesion and peel resistance and high reliability can be manufactured. The connection method using pillars in the through holes of this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 12)
The present invention can be applied to form a thin film transistor and a display device can be formed using the thin film transistor, but when a light emitting element is used as a display element and an N-type transistor is used as a transistor for driving the light emitting element, the light emitted from the light emitting element is either bottom emission, top emission, or dual emission. Here, the stacked structure of the light emitting element according to each case will be described with reference to FIG.

In this embodiment mode, the present invention is applied, and the transistor 1851 which is a channel protective thin film transistor formed in Embodiment Mode 1 is used.

First, in the case where light is emitted toward the substrate 1850 side, that is, in the case where light is emitted from the bottom surface, FIG.
In this case, the source or drain wirings 1852 and 1853, the first electrode 1854, and the electroluminescent layer 185 are electrically connected to the transistor 1851.
30B, a case where light is emitted to the side opposite to the substrate 1850, that is, a case where top emission is performed will be described. A source or drain wiring 1861 and 1862 electrically connected to a transistor 1851, a first electrode 1863, an electroluminescent layer 1864, and a second electrode 1865 are laminated in this order. With the above structure, even if light is transmitted through the first electrode 1863, the light is reflected by the wiring and is reflected by the substrate 1850.
In this structure, it is not necessary to use a light-transmitting material for the first electrode 1863. Finally, a case where light is emitted to both the substrate 1850 side and the opposite side, that is, a case where dual emission is performed, will be described with reference to FIG.
Source or drain wirings 1870 and 1871 electrically connected to the first electrode 18
A first electrode 1872, an electroluminescent layer 1873, and a second electrode 1874 are laminated in this order. At this time, if both the first electrode 1872 and the second electrode 1874 are formed from a material having light-transmitting properties or with a thickness that allows light to pass therethrough, dual-side emission is realized.

The light-emitting element has a structure in which an electroluminescent layer is sandwiched between a first electrode and a second electrode. The materials of the first electrode and the second electrode need to be selected in consideration of the work function, and the first electrode and the second electrode can be either an anode or a cathode depending on the pixel configuration. In this embodiment, since the polarity of the driving TFT is an N-channel type, it is preferable to use the first electrode as a cathode and the second electrode as an anode. Furthermore, when the polarity of the driving TFT is a P-channel type, it is preferable to use the first electrode as an anode and the second electrode as a cathode.

When the first electrode is an anode, the electroluminescent layer is preferably laminated in the order of HIL (hole injection layer), HTL (hole transport layer), EML (light emitting layer), ETL (electron transport layer), and EIL (electron injection layer) from the anode side. When the first electrode is a cathode, the order is reversed, and the EIL (electron injection layer), ETL (electron transport layer), EML (light emitting layer), and HIL (electron transport layer) are laminated in the order of EIL (electron injection layer), ETL (electron transport layer), EML (light emitting layer), and HIL (electron injection layer) from the cathode side.
It is preferable to laminate the TL (hole transport layer), the HIL (hole injection layer), and the anode as the second electrode in this order. The electroluminescent layer can have a single layer structure or a mixed structure in addition to the laminated structure.

In addition, as the electroluminescent layer, materials exhibiting red (R), green (G), and blue (B) light emission are
The red (R), green (G) and red (R) are selectively formed by a deposition method using a deposition mask.
), the material that emits blue (B) light can be formed by a droplet discharge method (such as a low molecular or polymer material) like the color filter. In this case, it is preferable because RGB can be separately painted without using a mask.

Specifically, CuPc or PEDOT is used as the HIL, α-NPD as the HTL, BCP or _Alq3 as the ETL, and BCP:Li or _CaF2 as the EIL. For example, the EML may be made of _Alq3 doped with a dopant corresponding to each of the R, G, and B emission colors (DCM, etc. for R, DMQD, etc. for G).

The electroluminescent layer is not limited to the above-mentioned materials. For example, instead of CuPc or PEDOT, an oxide such as molybdenum oxide (MoO _x : x=2 to 3) and α-NPD or rubrene can be co-deposited to improve hole injection properties. The material of the electroluminescent layer can be an organic material (including a low molecular weight or a high molecular weight material) or a composite material of an organic material and an inorganic material.

Although not shown in FIG. 30, a color filter may be formed on the opposing substrate of the substrate 1850. The color filter can be formed by a droplet discharge method, and in this case, optical plasma treatment or the like can be applied as the above-mentioned base pretreatment. The base film of the present invention allows a color filter to be formed with good adhesion to a desired pattern. The use of a color filter also allows for high-definition display. The color filter allows each RG to be formed with a desired pattern.
This is because the broad peak in the emission spectrum of B can be corrected to become sharper.

Although the case of forming a material that emits RGB light has been described above, a full-color display can be achieved by forming a material that emits a single color of light and combining it with a color filter or a color conversion layer. For example, when forming an electroluminescent layer that emits white or orange light, a full-color display can be achieved by separately providing a color filter or a combination of a color filter and a color conversion layer. The color filter or color conversion layer may be formed on, for example, a second substrate (sealing substrate) and bonded to the substrate. As described above, the material that emits a single color of light, the color filter, and the color conversion layer can all be formed by a droplet discharge method.

Of course, a single-color display may be used. For example, an area color type display device may be formed using single-color emission. A passive matrix type display unit is suitable for the area color type, and it can mainly display characters and symbols.

In the above structure, a material having a small work function can be used as the cathode, and for example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The electroluminescent layer may be any of a single layer type, a laminate type, and a mixed type without a layer interface, and may be any of a singlet material, a triplet material, or a combination of these, an organic material including a low molecular weight material, a high molecular weight material, and a medium molecular weight material, an inorganic material represented by molybdenum oxide having excellent electron injection properties, and a composite material of an organic material and an inorganic material. The first electrodes 1854, 1863, and 1872 are formed using a transparent conductive film that transmits light, and for example, a transparent conductive film formed using a target in which indium oxide is further mixed with 2 to 20% by weight of zinc oxide (ZnO) in addition to ITO and ITSO is used. Note that, before forming the first electrodes 1854, 1863, and 1872, it is preferable to perform a plasma treatment in an oxygen atmosphere or a heat treatment in a vacuum atmosphere. The partition wall is formed using a material containing silicon, an organic material, or a compound material. A porous film may also be used. However, if the partition wall is formed using a photosensitive or non-photosensitive material such as acrylic or polyimide, the side surface has a shape in which the radius of curvature changes continuously, and the thin film on the upper layer is formed without being broken. This embodiment mode can be freely combined with the above-mentioned embodiment modes.

(Embodiment 13)
The appearance of a panel, which is one mode of a display device to which the present invention is applied, will be described with reference to FIG.

The panel shown in FIG. 31 is mounted with a driver IC in which a driving circuit is formed around a pixel section 1951 by the COG (Chip On Glass) method.
It may also be implemented using the AB (Tape Automated Bonding) method.

The substrate 1950 is fixed to an opposing substrate 1953 by a sealant 1952. The pixel portion 1951 may use an EL element as a display medium.
The driver ICs 1955a, 1955b and the driver ICs 1957a, 1957b, and 1957c may be formed of similar TFTs using polycrystalline semiconductors in addition to integrated circuits formed using single crystal semiconductors.
957b, 1957c include FPC1954a, 1954b, 1954c or FPC1
Signals and power are supplied via 956a and 1956b.

(Embodiment 14)
An EL television receiver can be completed by using the display device formed by the present invention. Fig. 32 shows a block diagram showing the main configuration of an EL television receiver. There are various types of EL display panels, such as a pixel section 1951 and a scanning line side driver circuit and a signal line side driver circuit mounted around the pixel section 1951 by the COG method as shown in Fig. 31, a pixel section only is formed and a scanning line side driver circuit and a signal line side driver circuit are mounted by the TAB method, and a TFT is formed by SAS, a pixel section and a scanning line side driver circuit are integrally formed on a substrate and a signal line side driver circuit is mounted as a separate driver IC. Any type of configuration is acceptable.

Other external circuit configurations include a video signal input side including a video signal amplifier circuit 2005 that amplifies the video signal among the signals received by the tuner 2004, a video signal processing circuit 2006 that converts the output signal from the video signal amplifier circuit 2005 into color signals corresponding to the respective colors of red, green, and blue, and a control circuit 2007 that converts the video signal into the input specifications of the driver IC. The control circuit 2007 outputs signals to the scanning line side and the signal line side.
In the case of digital driving, a signal dividing circuit 2008 may be provided on the signal line side, and an input digital signal may be divided into m parts and supplied.

Of the signals received by tuner 2004, an audio signal is sent to an audio signal amplifier circuit 2009, and the output is supplied to a speaker 2013 via an audio signal processing circuit 2010. A control circuit 2011 receives control information on the receiving station (receiving frequency) and volume from an input unit 2012, and sends signals to the tuner 2004 and the audio signal processing circuit 2010.

With such an external circuit incorporated, the EL module is mounted in a housing 21 as shown in FIG.
01 to complete a television receiver. The display screen 2021 is formed by the EL display module, and other auxiliary equipment includes a speaker 2022 and an operation switch 2024. In this way, a television receiver can be completed according to the present invention.

Also, a wave plate or a polarizing plate may be used to block reflected light of light incident from the outside. Wave plates of λ/4 and λ/2 may be used, and the device may be designed to control light. The device may be configured with a TFT element substrate, a light emitting element, a sealing substrate (sealing material), a wave plate (λ/4, λ/2),
), which acts as a polarizing plate, and the light emitted from the light-emitting element passes through them and is emitted to the outside from the polarizing plate side. This wave plate and polarizing plate only need to be installed on the side where the light is emitted, and in the case of a dual-sided emission type display device, they can be installed on both sides. In addition, an anti-reflection film may be provided on the outside of the polarizing plate. This makes it possible to display a more sensitive and precise image.

A display panel 2102 using an EL element is incorporated in a housing 2101, and a receiver 210
The television receiver can receive general television broadcasts using the TV receiver 2105, and can also perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication by connecting to a wired or wireless communication network via a modem 2104. The television receiver can be operated using a switch built into the housing or a separate remote control device 2106, and this remote control device may also be provided with a display unit 2107 for displaying information to be output.

Also, in addition to the main screen 2103, the television receiver may be provided with a sub-screen 2108 formed of a second display panel, and configured to display channels, volume, etc.
Alternatively, in this configuration, the main screen 2103 may be formed of an EL display panel having a good viewing angle, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption.
The main screen 2103 may be formed of a liquid crystal display panel, and the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be capable of blinking. By using the present invention, a highly reliable display device can be obtained even if such a large substrate is used and many TFTs and electronic components are used.

Of course, the present invention is not limited to television receivers, but can be applied to a variety of uses, particularly as a large-area display medium, such as personal computer monitors, information display boards at railway stations and airports, and advertising display boards on the street.

(Embodiment 15)
The present invention can be applied to manufacture various display devices, that is, the present invention can be applied to various electronic devices in which the display devices are incorporated in the display portion.

Such electronic devices include cameras such as video cameras and digital cameras, projectors, head-mounted displays (goggle-type displays), car navigation systems, car stereos, personal computers, game devices, portable information terminals (mobile computers, mobile phones, e-books, etc.), image playback devices equipped with recording media (specifically, Digi
Examples of such devices include a display device that can play back a recording medium such as a digital versatile disc (DVD) and display the image. Examples of such devices are shown in FIG.

FIG. 34A shows a notebook personal computer, which includes a main body 2201 and a housing 220
2, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, etc. The present invention is applied to the manufacture of the display portion 2203. By using the present invention, a notebook type personal computer having a display portion with high display quality can be manufactured at low cost.

FIG. 34B shows a storage medium reproducing device (specifically, a DVD reproducing device) equipped with an image display unit, which includes a main body 2301, a housing 2302, a display unit A 2303, a display unit B 2304, a storage medium (
It includes a reading section 2305 (DVD, etc.), operation keys 2306, and a speaker section 2307. The display section A 2303 mainly displays image information, and the display section B 2304 mainly displays character information. The present invention is applied to the production of the display section A 2303 and the display section B 2304.
By using the present invention, a storage medium reproducing device equipped with an image display section with high display quality can be manufactured at low cost.

FIG. 34C shows a mobile phone, which includes a main body 2401, a voice output unit 2402, and a voice input unit 2403.
2403, a display portion 2404, an operation switch 2405, an antenna 2406, etc. By applying a display device manufactured according to the present invention to the display portion 2404, a mobile phone having a display portion with high display quality can be manufactured at low cost.

FIG. 35A shows a video camera, which includes a main body 2501, a display portion 2502, a housing 2503,
External connection port 2504, remote control receiver 2505, image receiver 2506, battery 250
35B and 35C, the display unit 2502 includes a voice input unit 2508, an operation key 2509, and an eyepiece unit 2510. The present invention can be applied to the display unit 2502, which is a dual-side emission type display device.
35 shows an image displayed by the display portion 2502. FIG. 35(B) shows the captured image, and FIG. 35(C) shows the image seen from the vehicle being captured. The display device of the present invention is a transmissive type and can display images on both sides, so that the captured image can be seen from the subject side as well. This is convenient for taking a picture of yourself. The present invention can also be applied to digital video cameras and the like in addition to video cameras, and similar effects can be obtained. By applying the display device manufactured according to the present invention to the display portion 2502, video cameras, digital video cameras, and the like having display portions with high display quality can be manufactured at low cost. In this embodiment,
The above-mentioned embodiment and the embodiment can be freely combined.

605 Gate insulating layer 606 Insulating layer 615 Source signal line 616 Source signal line 617 Source signal line 800 Substrate 801 Base film 802 Conductive layer 803 Conductive layer 804 Insulating layer 805 Gate insulating layer 806 Conductive layer 807 Semiconductor layer 808 N-type semiconductor layer 809 Channel protective film 811 Mask layer 813 Mask layer 815 Conductive layer 816 Conductive layer 817 Conductive layer 818 Through hole 820 Insulating layer 821 Electroluminescent layer 822 Conductive layer 850 Sealing substrate 851 Sealing material 854 Circuit of each pixel 855 Line segment

Claims (2)

A plurality of pixels arranged in a matrix form,
The pixel is electrically connected to a gate signal line, a source signal line, and a power supply line,
the power supply line has a first wiring arranged parallel to the source signal line, and a second wiring arranged perpendicular or substantially perpendicular to the first wiring, and the second wiring is connected to the first wiring for each pixel;
one of the pixels is a display device including a first transistor, one of a source and a drain of which is electrically connected to the source signal line, a second transistor, one of a source and a drain of which is electrically connected to the power supply line , and a capacitance element , one electrode of which is electrically connected to a gate of the second transistor and the other electrode of which is electrically connected to the power supply line;
a first conductive layer having a region extending in a first direction and functioning as the source signal line;
a second conductive layer having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor;
a third conductive layer having a function as the power supply line and a function as the other electrode of the capacitance element;
a semiconductor layer having a channel formation region of the second transistor;
the second conductive layer has a first region overlapping the third conductive layer, a second region not overlapping the third conductive layer and not overlapping the semiconductor layer, and a third region overlapping the semiconductor layer;
In one plan view of the pixel, the first region, the second region, and the third region have portions that are arranged in this order along the first direction,
a channel formation region of the second transistor having an area larger than an area of the channel formation region of the first transistor. A plurality of pixels arranged in a matrix form,
The pixel is electrically connected to a gate signal line, a source signal line, and a power supply line,
the power supply line has a first wiring arranged parallel to the source signal line, and a second wiring arranged perpendicular or substantially perpendicular to the first wiring, and the second wiring is connected to the first wiring for each pixel;
one of the pixels is a display device including a first transistor, one of a source and a drain of which is electrically connected to the source signal line, a second transistor, one of a source and a drain of which is electrically connected to the power supply line , and a capacitance element , one electrode of which is electrically connected to a gate of the second transistor and the other electrode of which is electrically connected to the power supply line;
a first conductive layer having a region extending in a first direction and functioning as the source signal line;
a second conductive layer having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor;
a third conductive layer having a function as the power supply line and a function as the other electrode of the capacitance element;
a semiconductor layer having a channel formation region of the second transistor;
the second conductive layer has a first region overlapping the third conductive layer, a second region not overlapping the third conductive layer and not overlapping the semiconductor layer, and a third region overlapping the semiconductor layer;
A display device, wherein, in a planar view of the pixel, the first region, the second region, and the third region have a portion arranged side by side in this order along the first direction.

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