JP7529628B2 - Printed wiring board and information processing device - Google Patents

Description

The present invention relates to a printed wiring board and an information processing device.

The memory device installed in the information processing device includes, for example, multiple SDRAMs (Synchronous Dynamic Random Access Memories) and a memory controller (for example, a controller LSI: Large Scale Integration) that controls writing and reading of the SDRAMs. The SDRAMs are also referred to as "memory elements" in the following explanation. It is common to use DDR SDRAMs (Double-Data-Rate SDRAMs) as SDRAMs.

The printed wiring board comprises multiple memory elements and a memory controller attached to the printed circuit board. Address (Add), command (Cmd), and control (Ctrl) signals are sent from the memory controller to each memory element using a wiring pattern formed on the printed circuit board called multi-drop wiring. In this multi-drop wiring, the memory controller is the signal sending end, and the multiple memory elements are the signal receiving ends.

When connecting a memory controller and multiple memory elements with multi-drop wiring, it is necessary to select the wiring pitch and length appropriately. If the wiring length is not appropriate, negative reflections will occur in the transmitted signal due to the capacitance of the memory elements and crosstalk between VIAs. Crosstalk is a phenomenon in which a change in the signal of one wiring affects the signal of another wiring. Crosstalk between VIAs is crosstalk that occurs near multiple VIAs formed for each of the multiple wirings for the same device.

Here, VIAs enable signals to be conducted to a wiring layer different from the surface on which the devices are mounted, in order to reduce the mounting area of various devices on the printed circuit board. VIAs are plated components that penetrate all or some of the layers of the printed circuit board, and are provided to connect wiring on different layers. A certain device (for example, memory element 111 shown in FIG. 1, which will be described later) may have many wirings formed, and a VIA may be formed for each of these many wirings. If the wirings are close to each other, crosstalk is more likely to occur.

When a negative reflection component that occurs in the transmission signal sent from the memory controller is superimposed on the received waveform of the memory element and causes a ring back, it becomes difficult to properly maintain the threshold of the digital signal. This leads to a decrease in the voltage margin, and the memory element is unable to transmit signals correctly. Furthermore, it becomes difficult for the memory element to perform stable operation due to fluctuations in the power supply voltage and temperature. Therefore, this technology requires a method that makes it possible to reduce capacitive reflection and crosstalk noise from nearby signals.

Patent document 1 states, "Various embodiments reduce electromagnetic reflections through the use of electronic bandgap (EBG) structures placed between memory modules. EBG structures can be used to attenuate electromagnetic reflections and improve performance at least in memory modules closer to a computer processor."

Special table 2019-525472 publication

Information processing devices (computers) equipped with printed circuit boards equipped with memory elements control various facilities such as power plants, substations, and ironworks, so there is a strong demand for stable operation of the information processing devices. Furthermore, in order for these information processing devices to respond to the recent trend toward IoT (Internet of Things), it is essential to improve the performance of the information processing devices by increasing the speed and capacity of the memory elements.

In particular, memory elements with a multi-drop wiring structure are used for address, command, and control signals among the signals used in memory elements. This wiring structure involves multiple branches and loads, and is therefore prone to waveform distortion due to unwanted reflections. In addition, since the wiring length of the data line is longer than that of the data wiring, crosstalk noise (FEXT: Far-End Crosstalk) superimposed from nearby signals becomes apparent. Here, the data line refers to, for example, the multi-drop wiring 102 from the memory controller 110 to the termination resistor 104 shown in FIG. 3, which will be described later. In addition, the data wiring refers to wiring that connects devices one-to-one, such as the wiring TL1 between the memory elements 111 and 112 and the wiring TL2 between the memory elements 112 and 113, which will be described later, shown in FIG. 3.

When variables such as power supply voltage fluctuations, temperature changes, and LSI manufacturing variations are added to information processing devices, the memory elements are unable to receive digital signals correctly. Therefore, the stable operation of information processing devices that are resistant to the various variables mentioned above is an issue, and there is a demand for improved waveform quality in signal transmission.

As mentioned above, devices such as memory controllers and memory elements are known to suffer from degradation of waveform quality due to crosstalk, which occurs when signals transmitted through adjacent wiring and VIAs affect each other. In addition, as LSIs in these devices become smaller and denser, the spacing between signal pins becomes narrower, and signals transmitted within the VIAs affect each other, causing crosstalk noise to be superimposed on the signals. When this crosstalk noise propagates to the memory element at the receiving end, the quality of the signal waveform deteriorates. However, because the device structure places restrictions on the placement of VIAs, it has been difficult to completely eliminate crosstalk noise.

Patent Document 1 describes an example of multi-drop wiring using a DIMM (Dual Inline Memory Module), but does not mention any solution for wiring between memory elements. For this reason, even if the technology described in Patent Document 1 is used, it is not possible to suppress the deterioration of signal waveform quality that occurs in a memory-down structure in which memory elements are mounted on the same printed circuit board as the memory controller, or in a DIMM wiring structure in which signals are received from the memory controller and distributed to each memory element.

The present invention was made in consideration of these circumstances, and aims to suppress deterioration in the quality of the signal received by the receiving circuit.

The printed wiring board according to the present invention comprises a printed circuit board formed of a plurality of layers , a transmitting circuit formed on the printed circuit board, a plurality of receiving circuits formed on the printed circuit board, a multi-drop wiring for signal transmission to which the transmitting circuit and the plurality of receiving circuits are connected, and a filter section formed on the multi-drop wiring for filtering noise superimposed on a signal transmitted from the transmitting circuit to the receiving circuit, wherein wiring branching from a plurality of branch points formed on the multi-drop wiring, one end of which is connected to the transmitting circuit, is respectively connected to the plurality of receiving circuits , and the filter section is a filtering VIA formed for the multi-drop wiring of a layer in which the multi-drop wiring is formed among the plurality of layers, and is not connected to wiring of a different layer or to the receiving circuit, and is formed between a transmitting circuit generating crosstalk noise and a receiving circuit affected by the crosstalk noise, between a receiving circuit among the plurality of receiving circuits that is closest to the transmitting circuit and the multi-drop wiring to which the transmitting circuit is connected, and between the receiving circuit that is closest to the transmitting circuit and the multi-drop wiring to which the transmitting circuit is connected, a VIA connecting the transmitting circuit and the multi-drop wiring and a filtering VIA are formed in that order from the transmitting circuit .

According to the present invention, it is possible to remove noise superimposed on a signal received by a receiving circuit, and suppress deterioration of the signal quality.
Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments.

1 is a configuration diagram of an information processing device to which multi-drop wiring according to an embodiment of the present invention is applied; 1 is another configuration diagram of an information processing device to which multi-drop wiring according to an embodiment of the present invention is applied; FIG. 1 is a diagram showing an example of the configuration of a conventional multi-drop wiring formed on a printed wiring board. FIG. 1 is a diagram showing another example of the configuration of conventional multi-drop wiring formed on a printed wiring board. 1 is a diagram showing an example of the configuration of a multi-drop wiring according to an embodiment of the present invention formed on a printed wiring board; 11 is a diagram showing another example of the configuration of the multi-drop wiring of this embodiment formed on a printed wiring board. FIG. 1 is a cross-sectional view of a printed wiring board according to an embodiment of the present invention. 1 shows an example of scattering parameters (S parameters) that indicate insertion loss from one memory element to another memory element. 4 shows an example of a scattering parameter that describes crosstalk from one memory element to another. FIG. 13 is a diagram showing an example of an eye pattern waveform observed in a memory element of an information processing device having a conventional multi-drop wiring configuration example. 11 is a diagram showing an example of an eye pattern waveform observed in a memory element of an information processing device having a multi-drop wiring configuration example of this embodiment. FIG.

Below, an embodiment of the present invention (hereinafter, referred to as "this embodiment") will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and duplicate descriptions will be omitted.

[Configuration of information processing device]
1 and 2 show an outline of an information processing device to which the multi-drop wiring of this embodiment is applied.
FIG. 1 is a diagram showing the configuration of an information processing device to which the multi-drop wiring of this embodiment is applied.
The information processing device 100 shown in FIG.
The printed wiring board 10 includes a printed circuit board 101, one memory controller 110, and multiple memory elements 111 to 115. The printed circuit board 101 has the one memory controller 110 and the multiple memory elements 111 to 115 directly mounted on its surface.

The printed circuit board 101 includes a multi-drop wiring 102. The multi-drop wiring 102 connects the memory controller 110 and each of the memory elements 111-115.
Each of the memory elements 111 to 115 is, for example, a DDR SDRAM. Writing and reading of data in each of the memory elements 111 to 115 is controlled by a memory controller 110. To perform this control, address, command, and control signals are transmitted from the memory controller 110 to each of the memory elements 111 to 115 via the multi-drop wiring 102.

FIG. 2 is a diagram showing another configuration of an information processing device to which the multi-drop wiring of this embodiment is applied.
The information processing device 100A shown in FIG. 2 includes a printed wiring board 10A.
A connector 103 is attached to a printed circuit board 101 of the printed wiring board 10A. A plurality of memory elements 111 to 115 mounted on a sub-board 106 are connected to the connector 103. The sub-board 106 on which the plurality of memory elements 111 to 115 are mounted in this manner is called a DIMM card or the like.
The memory controller 110 is directly mounted on the printed circuit board 101 .

In the information processing device 100A shown in FIG. 2, similar to the information processing device 100 shown in FIG. 1, multiple memory elements 111-115 are mounted on the surface of a printed circuit board 101. Address, command, and control signals are also transmitted from the memory controller 110 to each of the memory elements 111-115 via the multi-drop wiring 102 in the printed circuit board 101 shown in FIG. 2.

[Conventional configuration]
Next, an example of a conventional multi-drop wiring configuration will be described with reference to FIGS.

<Example of conventional multi-drop wiring configuration>
Fig. 3 is a diagram showing an example of the configuration of a conventional multi-drop wiring 102 formed on a printed circuit board 101. Note that the multi-drop wiring 102 of this example may be applied to either the case in which memory elements 111 to 115 are directly mounted on the printed circuit board 101 as shown in Fig. 1, or the case in which memory elements 111 to 115 are mounted on the printed circuit board 101 via a connector 103 as shown in Fig. 2.

The start end (one end) 102x of the multi-drop wiring 102 is connected to the memory controller 110, which is a transmission circuit for address, command, and control signals. This multi-drop wiring 102 has branch points 102a, 102b, 102c, 102d, and 102e at multiple locations, and a termination resistor 104 is connected to the end (other end). The memory controller 110 in the figure is given the symbol "Tx", which indicates the transmission end of the signal. The memory controller 110 is also assigned the alias "IC1". The symbols and aliases assigned to the memory controller 110 are the same in the subsequent figures.

The wiring branched at each of the branch points 102a-102e is connected to the connection points 111a-115a of each of the memory elements 111-115. As already explained, each of the memory elements 111-115 is arranged on the surface of the printed circuit board 101. Therefore, at each of the branch points 102a, 102b, 102c, 102d, and 102e, branches to the memory elements 111, 112, 113, 114, and 115 are formed. Each of the memory elements 111-115 in the figure is assigned the symbols "Rx1" to "Rx5" which represent the receiving end of the signal. Also, each of the memory elements 111-115 is assigned the aliases "IC2" to "IC6". The symbols and aliases assigned to each of the memory elements 111-115 are the same in the subsequent figures.

In addition, VIA120 to VIA126 are formed on the printed circuit board 101 in accordance with the multi-drop wiring 102. VIA120 is formed between the starting point 102x and the branch point 102a. In the figure, "VIA0" to "VIA6" are assigned as aliases to VIA120 to VIA126. The symbols and aliases assigned to each of VIA120 to VIA126 are the same in the subsequent figures.

The wiring from the start point 102x of the multi-drop wiring 102 to the VIA 120 is called wiring TL0, and the wiring from the VIA 120 (VIA0) to the branch point 102a is assigned the symbol "TL1". In this way, wiring TL0 represents a signal line from the memory controller 110 to VIA0 for connecting to the inner layer wiring or back surface wiring of the printed circuit board 101.

Then, the wiring between branch points 102a and 102b is assigned the code "TL2". Similarly, the wiring between branch points 102b and 102c, between branch points 102c and 102d, and between branch points 102d and 102e are assigned the codes "TL3", "TL4", and "TL5".

And, VIA 121 is formed at branch point 102a. Similarly, VIAs 122, 123, 124, and 125 are formed at branch points 102b, 102c, 102d, and 102e, respectively. Wires TL1 to TL5 are wires that connect the memory controller 110 to each of the memory elements 111 to 115, and to the terminal. And, wires TL1 to TL5 are connected to each of branch points 102A to 102e via VIAs 1 to 5, respectively.

Note that FIG. 3 shows a configuration in which wiring TL0 and TL1 are provided between the memory controller 110 and the memory element 111. When this memory controller 110 is mounted on the printed circuit board 101, a Pad on VIA structure is used in which the pins of the memory controller 110 are connected to the pads of the printed circuit board 101. For this reason, if a configuration is used in which VIA0 is formed directly on the pads of the memory controller 110, wiring TL0 may not be present.

<Another example of a conventional multi-drop wiring configuration>
FIG. 4 is a diagram showing another example of the configuration of a conventional multi-drop wiring 102 formed on a printed circuit board 101. In FIG.
4, memory controller 110 and memory elements 111 to 115 are connected via multi-drop wiring 102. A start end (one end) 102x of multi-drop wiring 102 is connected to memory controller 110. A termination resistor 104 is connected to an end (the other end) of multi-drop wiring 102.

In addition, VIAs 120 to 126 are formed on the printed circuit board 101 in accordance with the multi-drop wiring 102. VIA 120 is formed between the starting point 102x and the branch point 102a.

Here, memory elements 111 to 115 are directly connected to multidrop wiring 102. Therefore, in another configuration of multidrop wiring 102, there is no branch point for connecting multidrop wiring 102 to memory elements 111 to 115. However, VIAs 121 to 125 are formed at the points where memory elements 111 to 115 are connected to multidrop wiring 102, respectively. Note that the names of wiring TL0 to TL5 are the same as in the example configuration of conventional multidrop wiring 102 shown in Figure 3.

[Configuration of this Example]
Next, a configuration example of the multi-drop wiring 102 according to an embodiment of the present invention will be described with reference to FIGS.

<Example of multi-drop wiring configuration>
FIG. 5 shows an example of the configuration of the multi-drop wiring 102 of this embodiment formed on the printed circuit board 101.
The configuration example of the multi-drop wiring 102 shown in Fig. 5 is similar to the configuration example of the conventional multi-drop wiring 102 shown in Fig. 3, but differs in that a filtering VIA 131 is provided in the middle of the wiring TL1 between VIA0 and VIA1. This multi-drop wiring 102 is a wiring that transmits addresses, commands, and control signals from the memory controller 110 to the memory elements 111 to 115. The multi-drop wiring 102 may be configured to be directly connected to the memory elements 111 to 115 without going through the connector 103 as shown in Fig. 1, or may be configured to be connected to the memory elements 111 to 115 via the connector 103 as shown in Fig. 2.

The printed wiring board 10 includes a printed circuit board 101, a memory controller 110 (an example of a transmission circuit) formed on the printed circuit board 101, memory elements 111 to 115 (an example of multiple reception circuits) formed on the printed circuit board 101, a multi-drop wiring 102 for high-speed signal transmission to which the memory controller 110 and the memory elements 111 to 115 are connected, and a filter unit formed on the multi-drop wiring 102 to filter noise superimposed on a signal transmitted from the memory controller 110 to the memory elements. One end of the multi-drop wiring 102 is connected to the memory controller 110, and wiring branches from multiple branch points formed on the multi-drop wiring 102 are connected to the memory elements 111 to 115. Here, the filter unit is a filtering VIA 131 that is not connected to wiring in a different layer or a memory element, which is formed for the multi-drop wiring 102 of the layer in which the multi-drop wiring 102 is formed among the multiple layers formed on the printed circuit board 101.

The filtering VIA 131 is provided for the purpose of attenuating crosstalk noise observed as the waveform of the signal received by each memory element 111 to 115, which is the signal receiving end (Rx). At least one filtering VIA 131 is required. For this reason, multiple filtering VIAs 131 may be formed in the multi-drop wiring 102.

The filtering VIA 131 is formed in the wiring (the wiring TL1 in FIG. 5) from the memory controller 110 to the memory element 111 .

However, if multiple filtering VIAs 131 are provided, the wiring connected to other devices must be designed to avoid the filtering VIAs 131, which increases the mounting area of various devices on the printed circuit board 101. For this reason, filtering VIAs 131 do not need to be placed along with all of the wiring TL1 to TL5, but are selectively used for signal lines where waveform quality degradation due to crosstalk is significant. Also, filtering VIAs 131 may be placed along any of the wiring TL2 to TL5 depending on where the problematic crosstalk noise occurs. Therefore, the designer of the information processing device should perform simulations and design the system so that filtering VIAs 131 are provided only on wiring that is likely to generate crosstalk noise.

For example, crosstalk noise occurring in the signal received by memory element 112 is superimposed on the signal received by memory elements 111 and 113 through wiring TL1 and TL2. For this reason, when simulating signal transmission, the waveforms of the signals received by memory elements 111 and 113 are observed. If there is no problem with the waveforms of the signals received by memory elements 111 and 113, there is no need to provide filtering VIA 131.

However, if there is a problem with the waveform of the signal received by either memory element 111 or 113, a filtering VIA 131 is provided in the wiring from VIA 2 to either memory element 111 or 113. For example, if it is desired to remove a waveform of a specific frequency, the possibility of installing a filtering VIA 131 and its installation location are determined by referring to the change in the waveform depending on whether or not a filtering VIA 131 is present. For this reason, if the impact of crosstalk noise superimposed on the signal received by memory element 111 is large, a filtering VIA 131 is provided in wiring TL2 between memory element 112 and memory element 111. In this way, the filtering VIA 131 is provided between the transmitting end where crosstalk noise occurs and the receiving end affected by the crosstalk noise.

<Another example of the multi-drop wiring configuration of this example>
FIG. 6 shows another example of the configuration of the multi-drop wiring 102 of this embodiment formed on the printed circuit board 101.
Another example of the configuration of the multi-drop wiring 102 shown in FIG. 6 is similar to the example of the configuration of the conventional multi-drop wiring 102 shown in FIG. 4, but differs in that a filtering VIA 131 is provided on the wiring TL1 between VIA0 and VIA1.

<Example of Filtering VIA Configuration>
Here, a configuration example of the filtering VIA 131 will be described with reference to FIG.
Fig. 7 is a cross-sectional view of the printed circuit board 101. The cross-sectional view of Fig. 7 shows the multi-drop wiring 102 shown in Fig. 5, but in another configuration example of the multi-drop wiring 102 shown in Fig. 6, each VIA and filtering VIA are shown in a cross-sectional view similar to that of Fig. 7.

The printed circuit board 101 is composed of multiple layers stacked from the first layer to the sixth layer. In FIG. 7, the layers that are actually stacked are omitted. The first layer is formed with the start end 102x of the multi-drop wiring 102, memory elements 111 to 115, and a termination resistor 104. The start end 102x is connected to one end of the wiring TL0 formed on the first layer, and the other end of the wiring TL0 is connected to the wiring TL1 formed on the third layer via VIA0. The wiring TL2 to TL5 are also formed on the same third layer. As described above, VIA1 to VIA6 are formed in the multi-drop wiring 102. And VIA0 to VIA6 are used to connect the wiring of the device (memory element, etc.) formed on the first layer to the wiring of the third layer, which is different from the first layer.

Here, the filtering VIA 131 formed in the wiring TL1 is configured to penetrate from the first layer to the sixth layer. Moreover, the filtering VIA 131 is not connected to any device such as the memory elements 111 to 115. Even if the filtering VIA 131 is provided in any of the wirings TL2 to TL5, no device is connected to the filtering VIA 131. The filtering VIA 131 is not limited to the wiring TL1, and may be added to any location where it is desired to suppress crosstalk superimposed on the signals received by each of the memory elements 111 to 115.

Here, the filtering VIA 131 is either a through VIA formed by penetrating multiple layers, or a non-through VIA formed by penetrating some of the multiple layers. A non-through VIA is a VIA that does not penetrate all layers of the printed circuit board 101. The configuration of the filtering VIA 131 is not limited to the through-hole structure shown in FIG. 7. For example, the filtering VIA 131 may be configured by at least one of a non-through VIA structure including a laser VIA and a stack structure in which non-through VIAs are stacked. For example, a VIA that penetrates only the third and fourth layers is a non-through VIA. A stack structure is a structure in which multiple VIAs formed in multiple layers constituting the printed circuit board 101 are stacked. The stack structure is also called an any-layer structure.

The effect of providing the filtering VIA 131 in this manner will be described.
A filtering VIA 131 that does not involve a layer change between the memory controller 110 and the memory element 111 is disposed in the wiring TL1. The filtering VIA 131 has a function of attenuating high-frequency crosstalk noise superimposed on a signal (Victim signal) received by the receiving end. By attenuating the crosstalk noise from the signal, the receiving end can receive the signal well. Here, a signal received by the memory element that is affected by the signal transmitted by the memory controller 110 is called a Victim signal. The occurrence or non-occurrence of a Victim signal can be grasped by an operation simulation performed when the multi-drop wiring 102 is designed.

Next, the difference in insertion loss between a configuration example of a conventional multi-drop wiring 102 and a configuration example of the multi-drop wiring 102 of this example will be described. Hereinafter, the wiring configured with the topology shown in FIG. 3 or FIG. 4 will be referred to as the "conventional multi-drop wiring 102," and the wiring configured with the topology shown in FIG. 5 or FIG. 6 will be referred to as the "multi-drop wiring 102 of this example."

Figure 8 shows an example of scattering parameters (S parameters) that represent the insertion loss of a signal transmitted from memory element 111 to memory element 112. The graph in Figure 8 shows, for example, the extent to which the energy of a signal transmitted from memory controller 110 to memory element 111 is attenuated by a specific wiring for each frequency.

The dashed line in the figure represents the scattering parameters of a conventional multi-drop wiring 102 configured without a filtering VIA 131. The solid line in the figure represents the scattering parameters of the multi-drop wiring 102 of this example configured with a filtering VIA 131. From FIG. 8, it can be seen that the insertion loss is large in the frequency band of 3 GHz or more.

Figure 8 shows that in the frequency band of approximately 3 GHz or higher, the insertion loss is large for both the conventional and present multi-drop wiring 102, and that the configuration with the filtering VIA 131 has a larger amplitude drop than the configuration without the filtering VIA 131. For example, at frequencies of 3.5 GHz, 6 to 7 GHz, and 9 to 10 GHz, the insertion loss is large for the multi-drop wiring 102 with the filtering VIA 131 shown by the solid line.

This indicates that there are frequencies where energy is less easily transmitted to the receiving end than before. In other words, if the amplitude drop of the noise frequency superimposed on the signal is large, the noise in the signal received at the receiving end is suppressed.

Next, a difference in crosstalk between an example of the configuration of the multi-drop wiring 102 of the prior art and an example of the configuration of the multi-drop wiring 102 of this embodiment will be described.
FIG. 9 shows an example of scattering parameters representing crosstalk from memory element 111 to memory element 112.

The dashed lines in the figure represent the scattering parameters of a conventional multi-drop wiring 102 that is configured without a filtering VIA 131. The solid lines in the figure represent the scattering parameters of the multi-drop wiring 102 of this example that is configured with a filtering VIA 131.

Figure 9 shows that in the frequency band of approximately 6 GHz or higher, the loss of scattering parameters is large, and that the configuration with filtering VIA 131 has a larger amplitude drop than the configuration without filtering VIA 131. For example, at frequencies of around 6.1 GHz, 7 GHz, and 8 to 9 GHz, the crosstalk of the multi-drop wiring 102 with the configuration with filtering VIA 131 shown by the solid line is reduced.

From this point of view, if the frequency of the crosstalk noise superimposed on the signal is one that causes a large drop in amplitude, the signal received at the receiving end will have crosstalk noise suppressed.

<Relationship between threshold and waveform>
Next, the relationship between the threshold and the waveform observed at the interface of a memory element will be described with reference to Figures 10 and 11. Here, the DDR memory interface defined by the Joint Electron Device Engineering Council (JEDEC) standard is referred to as the "interface of a memory element".

FIG. 10 shows an example of an eye pattern waveform observed in a memory element 111 (IC2) of an information processing device 100 having a conventional multi-drop wiring 102 configuration.
FIG. 11 shows an example of an eye pattern waveform observed in the memory element 111 (IC2) of the information processing device 100 which is an example of the configuration of the multi-drop wiring 102 of this embodiment.

In the interface of a memory element, threshold voltages Vih(dc) and Vil(dc) are used during hold time, and threshold voltages Vih(ac) and Vil(ac) are used during setup time. The threshold voltage Vih(dc) used during hold time is lower than the threshold voltage Vih(ac) used during setup time. On the other hand, the threshold voltage Vil(dc) used during hold time is higher than the threshold voltage Vil(ac) used during setup time.

For example, when the signal waveform rises at a time of 0.3 ns and exceeds the threshold voltage Vih(ac), or falls and falls below the threshold voltage Vil(ac), the signal switches to "1" or "0". After that, when the signal waveform falls at a time of 0.9 ns and falls below the threshold voltage Vih(dc), or rises and exceeds the threshold voltage Vih(dc), the signal switches to "0" or "1".

The eye mask is represented by a trapezoid with the upper edge at the threshold voltages Vih(dc) and Vil(dc) and the lower edge at the threshold voltages Vih(ac) and Vil(ac). Here, the lower edge of the eye mask corresponds to the point where the waveform intrudes into either the threshold voltages Vih(ac) or Vil(ac) used in the setup time. In FIG. 10, it is shown that the waveform intrudes into the threshold voltage Vih(ac) at the intrusion point 130. In the eye pattern obtained from a general multi-drop wiring 102, the signal waveform is distorted because ringback due to crosstalk intrudes into the digital threshold. As a result, it can be seen that the eye mask is small and the waveform quality is low.

On the other hand, in FIG. 11, there is no point where the waveform penetrates either the threshold voltage Vih(ac) or Vil(ac). Therefore, there is no risk that the receiving end will mistakenly recognize an ON state signal as an OFF state.

The distances M1 and M2 between the trapezoidal eye mask and the waveform shown in Figures 10 and 11 are the voltage margins. Distance M1 is the distance between the threshold voltage Vih (dc) and the waveform where the signal becomes "1", or between the threshold voltage Vil (dc) and the waveform where the signal becomes "0", and is called the voltage margin. The voltage margin contributes to stable operation and improved reliability of the information processing device 100 shown in Figure 1. In order for the receiving end to receive data properly, it is preferable for the voltage margin of this eye mask to be large. Conversely, if the voltage margin of the eye mask is small, there is a high possibility that the receiving end will not be able to receive data correctly.

Comparing the eye patterns shown in Figures 10 and 11, the distance M2 to the eye mask of this example shown in Figure 11 is greater than the distance M1 to the eye mask shown in Figure 10. Therefore, the memory element of the information processing device 100 having the example configuration of the multi-drop wiring 102 of this example can receive signals more correctly than the memory element of the information processing device 100 having the example configuration of the conventional multi-drop wiring 102.

The expansion of the voltage margin for the eye mask represented by the eye pattern waveform shown in FIG. 11 is achieved by mitigating the simultaneous superposition of the ringback component and the capacitive reflection component that appear in the eye pattern, and by avoiding the intrusion of the waveform into the threshold voltages Vih(ac) and Vil(ac). Therefore, according to the printed circuit board 101 having the multi-drop wiring 102 of this example, the transmission of address, command, and control signals from the memory controller 110 to each of the memory elements 111 to 115 can be stably performed without errors. Therefore, the reliability of the information processing device 100, 100A equipped with the memory controller 110 and the memory elements 111 to 115 is improved.

<Method of Manufacturing Information Processing Device>
The manufacturing method of the filtering via 131 in this example may be the same as the manufacturing method of the vias 121 to 126. There is also a method of reducing the effect of crosstalk of parallel wiring by tabbed routing. However, when trying to realize the designed tab shape in the manufacturing process, it is necessary to correct the etching mask shape considering the circulation of the etching solution in etching by a general and inexpensive subtractive method. However, in tabbed routing, there are many places with narrow conductor spacing as areas where the circulation of the etching solution is deteriorated. This leads to an increase in the difficulty of manufacturing.
Therefore, the above-mentioned etching correction can be avoided by using an additive method or a semi-additive method, but these methods are more expensive than the subtractive method.

For this reason, it is advisable to create the multi-drop wiring 102 and filtering VIA 131 by etching using a common and inexpensive subtractive method. Then, by using the subtractive method to add a manufacturing process for the filtering VIA 131 to the manufacturing process for normally used VIAs, it is possible to realize the filtering VIA 131. The use of the subtractive etching method does not increase the difficulty of manufacturing the printed circuit board 101.

In the information processing devices 100 and 100A according to the embodiments described above, when wiring to the high-speed memory elements 111 to 115 with small voltage margins, it is necessary to ensure a voltage margin against external noise, including crosstalk. Therefore, by providing a filtering VIA 131 in the multi-drop wiring 102, crosstalk noise can be suppressed. As a result, it is possible to ensure the voltage margin of the eye pattern and improve the waveform quality of the received signal.

For example, the information processing device 100, 100A is resistant to variables such as power supply voltage fluctuations in the information processing device 100, 100A that controls various equipment, changes in the characteristics of the memory controller 110 due to changes in the ambient temperature, manufacturing variations between lots of memory elements mounted on a printed wiring board, and manufacturing variations between lots of LSIs and the like that make up the memory controller 110.

Conventionally, VIAs such as the filtering VIA 131 have not been formed in the multi-drop wiring 102. The reasons for this include, for example, that the effect of the filtering VIA 131 was not known, and that the implementation area of various devices increases when the filtering VIA 131 is configured. In addition, in the middle of the conventional wiring for low-speed signal transmission, a VIA that is not connected to any device was sometimes formed. This VIA was provided to check the signal quality by applying a probe to the wiring and extracting a signal from the wiring. However, even if a VIA is formed in the wiring for transmitting high-speed signals as in this example, even if a probe is applied to the VIA to extract a signal, the signal waveform is distorted and the signal waveform cannot be observed correctly. On the other hand, the filtering VIA 131 in this example is used to suppress noise superimposed on the signal transmitted through the wiring. This makes it possible for the receiving end to receive the signal correctly.

[Modification]
The present invention is not limited to the above-described embodiment, but includes various modifications.

In the above embodiment, an example has been described in which memory elements 111 to 115 are mounted on the front surface of the printed circuit board 101. However, a configuration in which the multi-drop wiring 102 branches and connects to the memory elements mounted on the front and back surfaces of the printed circuit board 101 may also be used. In this case, too, by forming a filtering VIA 131 in the multi-drop wiring 102, the voltage margin for the eye mask observed at the receiving end can be expanded.

In the above embodiment, it has been described that the multi-drop wiring 102 is configured within one printed circuit board 101. However, it is also possible to configure the multi-drop wiring 102 by mounting a memory element such as a DIMM card on the printed circuit board 101, separate from the printed circuit board 101 on which the memory controller 110 is mounted, and connecting the memory element to the printed circuit board 101.

The printed circuit board 101 according to the embodiment described above is configured with VIAs 0 to 6 and a filtering VIA 131 for wiring on an inner layer (third layer shown in FIG. 7). If wiring is configured on the outer layer (third layer shown in FIG. 7) of the printed circuit board 101, a filter section may be configured for this wiring by combining a capacitor and a resistor that can suppress the frequency components of crosstalk noise. Even with a filter section configured in this way, it is possible to filter out noise superimposed on the signals transmitted from the memory controller 110 to the memory elements 111 to 115, and therefore crosstalk noise can be sufficiently suppressed.

In addition, in the above-described embodiment, as a specific example, an information processing device that controls production equipment in a factory is given as an example of the implementation, but the same effect can be obtained not only in applications for controlling industrial equipment, but also in various consumer devices, in-vehicle devices, and various other information processing devices equipped with memory elements.

Incidentally, the present invention is not limited to the above-described embodiments, and it goes without saying that various other applications and modifications are possible without departing from the gist of the present invention as set forth in the claims.
For example, the above-mentioned embodiments have described the configuration of the device and system in detail and specifically in order to explain the present invention in an easily understandable manner, and are not necessarily limited to those including all of the configurations described. In addition, it is possible to replace part of the configuration of the embodiments described here with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.
In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other.

10, 10A... Printed wiring board, 100, 100A... Information processing device, 101... Printed circuit board, 102... Multi-drop wiring, 103... Connector, 104... Termination resistor, 106... Sub-board, 110... Memory controller, 111-115... Memory element, 131... Filtering VIA

Claims (4)

A printed circuit board formed of multiple layers;
A transmission circuit formed on the printed circuit board;
A plurality of receiving circuits formed on the printed circuit board;
a multi-drop wiring for signal transmission to which the transmitting circuit and a plurality of the receiving circuits are connected;
a filter unit formed in the multi-drop wiring and configured to filter out noise superimposed on a signal transmitted from the transmitting circuit to the receiving circuit,
a plurality of branching points formed in the multi-drop wiring, one end of which is connected to the transmission circuit, are connected to the plurality of reception circuits,
The filter section is a wiring of a different layer formed for the multi-drop wiring of a layer in which the multi-drop wiring is formed among the plurality of layers, or a filtering VIA that is not connected to the receiving circuit, and is formed between the transmitting circuit in which crosstalk noise occurs and the receiving circuit affected by the crosstalk noise, between the receiving circuit that is closest to the transmitting circuit among the plurality of receiving circuits and the multi-drop wiring to which the transmitting circuit is connected,
A printed wiring board in which a VIA connecting the transmitting circuit to the multi-drop wiring and a filtering VIA are formed in this order from the transmitting circuit between the receiving circuit that is closest to the transmitting circuit and the multi-drop wiring to which the transmitting circuit is connected. The printed wiring board according to claim 1 , wherein the filtering via is either a through via formed through the plurality of layers or a non-through via formed through some of the plurality of layers. the transmitting circuit is a memory controller and the receiving circuit is a memory device;
2. The printed wiring board according to claim 1, wherein the multi-drop wiring is wiring for transmitting address, command and control signals from the memory controller to the memory elements. An information processing device including a printed wiring board having a printed circuit board formed of multiple layers, in which a transmitting circuit and multiple receiving circuits are connected by multi-drop wiring for signal transmission,
a filter section is formed in the multi-drop wiring to filter out noise superimposed on a signal transmitted from the transmitting circuit to the receiving circuit;
a plurality of branching points formed in the multi-drop wiring, one end of which is connected to the transmission circuit, are connected to the plurality of reception circuits,
The filter section is a wiring of a different layer formed for the multi-drop wiring of a layer in which the multi-drop wiring is formed among the plurality of layers, or a filtering VIA that is not connected to the receiving circuit, and is formed between the transmitting circuit in which crosstalk noise occurs and the receiving circuit affected by the crosstalk noise, between the receiving circuit that is closest to the transmitting circuit among the plurality of receiving circuits and the multi-drop wiring to which the transmitting circuit is connected,
An information processing device, wherein a VIA connecting the transmitting circuit and the multi-drop wiring, and a filtering VIA are formed in this order from the transmitting circuit between the receiving circuit that is closest to the transmitting circuit and the multi-drop wiring to which the transmitting circuit is connected.

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