JP7525484B2 - Analog-digital conversion device, control method for analog-digital conversion device, and audio device - Google Patents

Description

The present disclosure relates to an analog-to-digital conversion device, a control method for an analog-to-digital conversion device, and an audio device.

In various audio devices, an analog-digital conversion device is used to convert an analog audio signal input from a microphone or the like into a digital signal. In order to maximize the S/N ratio and dynamic range, a conventional analog-digital conversion device used in an audio device adjusts the level at a stage before the input of the analog-digital converter with a static gain according to the microphone output characteristics, and adjusts the output level of a decimation filter arranged at a stage after the analog-digital converter (see, for example, Patent Document 1). Patent Document 1 also discloses a technology for purely improving characteristics by improving the feedback of a delta-sigma modulator in the analog-digital conversion device.
Furthermore, in a conventional analog-to-digital conversion device used in an audio device, the output level of a decimation filter arranged downstream of the analog-to-digital converter is detected, and the detected level is fed back to a variable gain amplifier arranged upstream of the analog-to-digital converter to control the gain of the variable gain amplifier (see, for example, Patent Document 2).

JP 2009-303157 A Japanese Patent Application Publication No. 8-18457

The analog-to-digital conversion device according to the conventional technology described in Patent Document 1 improves the feedback section of the delta-sigma modulator to improve distortion characteristics and raise the allowable input level, but there is a problem in that it is difficult to change the characteristics of the delta-sigma modulator.
The analog-to-digital conversion device according to the conventional technology described in Patent Document 2 uses feedback control, and therefore the response of the control loop that controls the gain of the variable gain amplifier according to the signal level is slow. Specifically, the response of the control loop is slow due to the processing delay of the analog-to-digital converter, the processing delay of the decimation filter, and the processing delay of the level detection circuit. Thus, the conventional technology described in Patent Document 2 has a problem in that the response of the control loop is slow and the response required for noise cancellation cannot be guaranteed.

The present disclosure aims to provide an analog-to-digital conversion device with excellent responsiveness of a control loop that controls the gain of a variable gain amplifier in accordance with a signal level, a control method for an analog-to-digital conversion device, and an audio device.

In order to achieve the above object, the analog-to-digital conversion device of the present disclosure comprises:
A variable gain amplifier that amplifies the input analog signal;
an analog-to-digital converter that converts the analog signal passed through the variable gain amplifier into a digital signal;
an attenuator for attenuating the digital signal output from the analog-to-digital converter;
a level detection unit for detecting a level of an input analog signal; and
The control unit controls the gain of the variable gain amplifier and the attenuation of the attenuator based on the detection level of the level detection unit.

In order to achieve the above object, a control method for an analog-to-digital conversion device according to the present disclosure includes:
A variable gain amplifier that amplifies the input analog signal;
an analog-to-digital converter that converts the analog signal passed through the variable gain amplifier into a digital signal; and
1. An analog-to-digital conversion device including an attenuator for attenuating a digital signal output from an analog-to-digital converter,
Detects the level of the input analog signal,
Based on the detected level, the gain of the variable gain amplifier and the attenuation of the attenuator are controlled.

In addition, to achieve the above objective, the audio device of the present disclosure has an analog-to-digital conversion device of the above configuration.

FIG. 1 is a block diagram showing an outline of a system configuration of an analog-to-digital conversion device according to an embodiment of the present disclosure. FIG. 2 is a block diagram showing a specific example circuit of an analog-to-digital conversion device according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram showing changes in input/output signals and control signals at each point in the system of an analog-to-digital conversion device according to an embodiment of the present disclosure. FIG. 4 is a level diagram in which a gain of 0 dB of the variable gain amplifier is appropriate for the maximum allowable input of the analog-to-digital converter. FIG. 5 is a level diagram where a gain of the variable gain amplifier >0 dB is appropriate for the maximum allowable input of the analog-to-digital converter. FIG. 6 is a timing diagram for explaining the reasons for selecting the clock frequencies of the timing generation section and the control value generation section of the ARC circuit. FIG. 7 is a timing diagram showing the output signal of the energy comparator relative to the output signal of the preamplifier. FIG. 8 is a block diagram showing the path from the variable gain amplifier to the digital attenuator. 9A and 9B are timing diagrams showing an example of the operation of the gain setting of a variable gain amplifier. 10A and 10B are timing diagrams showing an example of the operation of three timer counters that manage the processing intervals for setting the gain of the variable gain amplifier and the attenuation amount setting of the digital attenuator. FIG. 11 is a diagram for explaining the delay time from the output of the audio signal from the preamplifier to the gain setting of the variable gain amplifier. FIG. 12 is an explanatory diagram of an implementation example of a 512f _s operation block. 13A and 13B are timing diagrams illustrating an implementation example 1 of a _128fs operation block. FIG. 14 is an explanatory diagram of implementation example 2 of a _128fs operation block. FIG. 15A is an explanatory diagram of implementation example 3 of a _128fs operation block, and FIG. 15B is a timing diagram for explaining implementation example 3. FIG. 16 is a timing diagram showing an example of the operation of the delay timer in implementation example 4 of the 128f _s operation block. FIG. 17 is a block diagram showing an outline of the system configuration of an audio device according to an embodiment of the present disclosure.

Hereinafter, a form for carrying out the technology of the present disclosure (hereinafter, referred to as "embodiment") will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiment, and various numerical values in the embodiment are merely examples. In the following description, the same reference numerals will be used for the same elements or elements having the same functions, and duplicated descriptions will be omitted. The description will be given in the following order.
1. Description of the analog-digital conversion device, control method for the analog-digital conversion device, and audio device according to the present disclosure 2. Analog-digital conversion device according to an embodiment of the present disclosure 2-1. Overview of system configuration 2-2. Specific circuit examples 2-2-1. Regarding the digital attenuator 2-2-2. Regarding the energy comparator 2-2-3. Regarding the control unit 2-2-4. Regarding input/output signals and control signals at each point in the system 2-2-5. Regarding the operation clock 2-2-6. Regarding the delay time caused by the analog-digital converter 2-2-7. Regarding delay in gain setting operation of the variable gain amplifier 2-2-8. Regarding setting the control timing difference between gain and attenuation 2-2-9. Regarding implementation of delay in reflecting settings 2-2-10. Regarding level interrupt and gain setting of the variable gain amplifier 2-2-11. Regarding attenuation setting 2-3. Control method, action, and effect according to the embodiment 2-4. Implementation example 2-4-1. Implementation example of _512fs operation block 2-4-2. Implementation example 1 of _128fs operation block
2-4-3. _128fs operation block implementation example 2
2-4-4. Implementation example 3 of 128f _s operation block
2-4-5. Implementation example 4 of 128f _s operation block
3. Audio device according to an embodiment of the present disclosure 4. Modifications 5. Configurations that the present disclosure can adopt

<General Description of Analog-Digital Conversion Device, Control Method for Analog-Digital Conversion Device, and Audio Device of the Present Disclosure>
The analog-digital conversion device, the control method thereof, and the audio device of the present disclosure may be configured to have a preamplifier that takes in an input analog signal and supplies it to a variable gain amplifier. The level detection unit may be configured to detect the level of the analog signal after passing through the preamplifier. The level detection unit may also be configured to have a plurality of comparators having mutually different thresholds.

In the analog-digital conversion device, control method thereof, and audio device of the present disclosure including the preferred configuration described above, the level detection section may be configured to have a first comparator having a first threshold higher than the bias of the output signal of the preamplifier, and a second comparator having a second threshold lower than the bias of the output signal of the preamplifier. The first comparator may be configured to output a true logic when the level of the analog signal is higher than the first threshold, and the second comparator may be configured to output a true logic when the level of the analog signal is lower than the second threshold. The level detection section may be configured to output the logical sum of the output of the first comparator and the output of the second comparator as the detection level of the analog signal.

Furthermore, in the analog-to-digital conversion device, control method thereof, and audio device of the present disclosure, which include the preferred configuration described above, the preamplifier can be configured to have the role of keeping the output impedance constant in response to changes in the operation of the variable gain amplifier and the level detector.

In the analog-to-digital conversion device, control method thereof, and audio device of the present disclosure including the above-mentioned preferred configuration, the control unit can be configured to control the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier. Also, the control unit can be configured to control the attenuation amount of the attenuator while maintaining a constant timing difference with respect to the control timing of the variable gain amplifier.

Furthermore, in the analog-to-digital conversion device, control method thereof, and audio device of the present disclosure, which include the preferred configuration described above, the analog-to-digital converter can be configured to include a delta-sigma modulator that oversamples the analog signal that has passed through the variable gain amplifier and converts it into a pulse train signal that corresponds to the amplitude of the analog signal.

Furthermore, the analog-to-digital conversion device, control method thereof, and audio device disclosed herein, which include the preferred configuration described above, can be configured to have a decimation filter that converts the pulse train signal output from the delta-sigma modulator and passed through an attenuator into a digital signal with a sampling frequency that can obtain the required signal information without being affected by aliasing noise.

Analog-to-Digital Conversion Device According to an Embodiment of the Present Disclosure
1 is a block diagram showing an outline of a system configuration of an analog-digital conversion device according to an embodiment of the present disclosure. To an analog-digital conversion device 10 according to this embodiment, n systems (n=1 in FIG. 1) of analog audio signals are input from an external microphone (not shown in the drawings) (hereinafter, may be simply referred to as a "microphone") (microphone input).

[System configuration overview]
The analog-to-digital conversion device 10 according to this embodiment has a configuration including a preamplifier 11, a variable gain amplifier 12, an analog-to-digital converter (ADC) 13, a digital attenuator 14, a decimation filter 15 which is an example of a digital filter, a level detection unit 16, and a control unit 17.

Under the control of the control unit 17, the analog-to-digital conversion device 10 outputs an analog audio signal input through the preamplifier 11 as an audio PCM (Pulse Code Modulation) signal via the variable gain amplifier 12, analog-to-digital converter 13, digital attenuator 14, and decimation filter 15.

In the analog-to-digital conversion device 10 configured as described above, the preamplifier 11 has a variable gain and serves to keep the output impedance constant in response to operational changes in the microphone in the preceding stage and the variable gain amplifier 12 and level detection section 16 in the succeeding stage. The preamplifier 11 further sets an appropriate gain depending on the microphone (not shown) connected to the input side.

The variable gain amplifier 12 is, for example, a programmable gain amplifier (PGA), and amplifies the analog audio signal input through the preamplifier 11 with a gain (amount of amplification) determined according to the detection level of the level detection unit 16 under the control of the control unit 17. The variable gain amplifier 12 then supplies the amplified analog audio signal to the next-stage analog-to-digital converter 13, which operates in oversampling mode.

Under the control of the control unit 17, the variable gain amplifier 12 operates so that when the microphone input level is low, the gain is high, and when the microphone input level is high, the gain is low. When the microphone input level changes from high to low, the gain increases slowly (for example, in 0.2 dB steps) with a gentle slope. Then, the steps change in a cycle that results in a low frequency outside the audible range. When the microphone input level changes from low to high, the gain decreases instantly with a steep slope. This makes it possible to prevent incidental noise across the entire frequency range that would occur even if the allowable input of the analog-to-digital converter 13 or the allowable output of the variable gain amplifier 12 were to be exceeded only momentarily.

The analog-to-digital converter 13 is, for example, composed of a 1-bit delta-sigma modulator (hereinafter referred to as a "ΔΣ modulator") that oversamples the analog signal (audio signal) amplified and input by the variable gain amplifier 12 and converts it into a pulse train signal (i.e., a digital signal) corresponding to the amplitude of the analog signal.

Digital attenuator 14 performs a process of attenuating the output of analog-digital converter 13, which is operating in oversampling mode, before it is decimated by the next-stage digital filter. Specifically, under the control of control unit 17, digital attenuator 14 converts the digital audio signal output from analog-digital converter 13 into a value that takes into account an attenuation amount that offsets the amount of amplification by variable gain amplifier 12. When the number of bits of the output of analog-digital converter 13 is 1 bit, a simple value mapping is performed.

Decimation filter 15, which is an example of a digital filter, is composed of, for example, a Cascaded Integrator Comb (CIC) filter. This decimation filter 15 converts the pulse train signal output from analog-to-digital converter 13 and passed through digital attenuator 14 into a digital signal with a sampling frequency that can obtain the necessary signal information without being affected by aliasing noise, and outputs it as an audio PCM signal.

The decimation filter 15 performs decimation in accordance with the sampling frequency required by the downstream circuit and outputs an audio PCM signal.Typical sampling frequencies are _4fs ( _fs : fundamental sampling frequency), _8fs , and _16fs .

The input terminal of the level detection unit 16 is connected to the output terminal of the preamplifier 11 so as not to be affected by impedance or the gain set in the preamplifier 11. The level detection unit 16 has x systems (two systems in this example) of energy comparators _{16_1} , _{16_2} for n systems of analog input. The two systems of energy comparators _{16_1} , _{16_2} have different thresholds and detect the level of the analog audio signal after passing through the preamplifier 11. Hereinafter, for convenience, the energy comparator _{16_1} may be described as _{CMP_1} , and the energy comparator _{16_2} may be described as _{CMP_2} .

The control unit 17 is composed of, for example, an ARC (Adaptive Range Control) circuit, and controls the gain of the variable gain amplifier 12 and the attenuation of the digital attenuator 14 based on the detection level of the level detection unit 16. The control unit 17 then accurately sets the control timing of the variable gain amplifier 12 and the control timing of the digital attenuator 14. This accurate control timing can be set from a fixed delay amount that can be determined by the topology of the analog-digital converter 13, and the input/output delay characteristics of the variable gain amplifier 12, which have a small fluctuation range even when variations are taken into account.

As described above, the analog-to-digital conversion device 10 of this embodiment is configured as a feedforward control in which the level of the input analog signal is detected by the level detection unit 16, and the gain of the variable gain amplifier 12 and the attenuation amount of the digital attenuator 14 are controlled based on the detected level.

[Specific circuit example]
2 is a block diagram showing a specific example of a circuit of an analog-to-digital conversion device according to an embodiment of the present disclosure. Here, a circuit configuration is illustrated in which, for example, two-channel analog audio signals are input to the analog-to-digital conversion device 10 as MIC1 and MIC2.

Therefore, the analog-to-digital conversion device 10 of this circuit example is configured to have preamplifiers _{11_1} , _{11_2} , variable gain amplifiers _{12_1} , _{12_2} , analog-to-digital converters _{13_1} , _{13_2} , digital attenuators _{14_1} , _{14_2} , decimation filter 15, energy comparators _{16_11} , _{16_12} , energy comparators _{16_21} , _{16_22} , and a control unit 17.

In the analog-to-digital conversion device 10 according to the above circuit example, the gain of the variable gain amplifier 12 consisting of a PGA is set according to a digital value under the control of the control unit 17. In this circuit example, the gain is controlled from 0 dB to 6 dB, for example in 0.2 dB steps. The larger the variable range of the gain that can be set, the greater the dynamic range can be expected to be, but since the occurrence of pop noise becomes noticeable, a practical variable range of around 3 dB to 6 dB is preferable.

The optimum gains of the variable gain amplifiers _{12_1} and 12_2 are obtained according to the connected microphones, the gains of the preamplifiers _{11_1} and _{11_2} , and the maximum allowable inputs of the analog-digital converters _{13_1} and _{13_2} . This is for _the purpose of bringing the outputs of the preamplifiers _{11_1} and _{11_2} closer to the maximum allowable inputs of the analog-digital converters _{13_1} and _{13_2} . The control unit 17 controls the gains of the variable gain amplifiers _{12_1} and _{12_2} so that when the microphone input level is small, the gains of the variable gain amplifiers 12_1 and 12_2 are large, and when the microphone input level is large, the gains of the variable gain amplifiers _{12_1} and _{12_2} are small.

In the analog-digital conversion device 10 according to this embodiment, the gain of the preamplifiers _{11_1} and _{11_2} is configured so that it can be set to a range wider than the variable width of the dynamic range. The step width should be as small as possible. A typical example is 0.2 dB.

The control unit 17 is provided with two ARC circuits _{171_1} and _{171_2} corresponding to the two channels. The two ARC circuits _{171_1} and _{171_2} have timing generation units _{171_11} and _{171_21} and control value generation units _{171_12} and _{171_22} , respectively. The timing generation unit _{171_11} of the ARC circuit 171_1 generates a timing signal _{T_1} that determines the timing for controlling the gain of the variable gain amplifier _{12_1} . The timing generation unit _{171_21} of the _ARC circuit _{171_2} generates a timing signal _{T_2} that determines the timing for controlling the gain of the variable gain amplifier _{12_2} .

A control value generating unit _{171_12} of the ARC circuit _{171_1} generates a control value _{N_p1} that controls the gain of the variable gain amplifier _{12_1} and a control value _{N_a1} that controls the attenuation amount of the digital attenuator _{14_1} . A control value generating unit _{171_22} of the ARC circuit _{171_2} generates a control value _{N_p2} that controls the gain of the variable gain amplifier _{12_2} and a control value _{N_a2} that controls the attenuation amount of the digital attenuator _{14_2} .

The gains of the variable gain amplifiers _{12_1} and _{12_2} are set by the control values (setting values) _{N_p1} and _{N_p2} generated by the control value generating units _{171_12} and _{171_22} of the two ARC circuits _{171_1} and _{171_2} under the control of the control unit 17 configured as above. Furthermore, the gain during the transition period is set to an intermediate gain before and after the setting. Furthermore, the attenuation amounts of the digital attenuators _{14_1} and _{14_2} are set by the control values N_a1 and _{N_a2} generated by the control value generating units _{171_12} and 171_22 of the two ARC circuits _{171_1} and _{171_2} under the control of the control unit ₁₇ configured as _above .

Here, a typical operating speed and bit width of the analog-digital converters _{13_1} and _{13_2} will be described. The analog-digital converters _{13_1} and _{13_2} are 1 bit at _128fs ( _fs : fundamental sampling frequency, 44.1kHz/48kHz). The dither circuits _{172_1} and _{172_2} provided in the control unit 17 are also 1 bit.

In the analog-to-digital conversion device 10 having the above configuration, the preamplifiers _{11_1} , _{11_2} , the variable gain amplifiers _{12_1} , _{12_2} , the energy comparators _{16_11} , _{16_12} , and the energy comparators _{16_21} , _{16_22} constitute an analog block, and the analog-to-digital converters _{13_1} , _{13_2} , the digital attenuators _{14_1} , _{14_2} , the decimation filter 15, and the control unit 17 constitute a digital block.

When different semiconductor processes are used for the analog block side and the digital block side, the analog-digital converters _{13_1} , _{13_2} and the dither circuits _{172_1} , _{172_2} having a digital configuration are made to use the process for the analog block side.

Here, the operation speed and bit width of the analog-digital converters _{13_1} and _{13_2} are exemplified as 1 bit at 128 _fs , but are not limited to this. For example, 3 bits at 64 _fs or 128 _fs , 2 bits for the dither circuits _{172_1} and _{172_2} , etc. may be used, and there are no particular restrictions on the analog-digital converters _{13_1} and _{13_2} .

(About digital attenuators)
Next, the circuit configuration of the digital attenuator 14 ( _{14_1} , _{14_2} ) will be described. In the case of a 1-bit analog-digital converter, this can be realized by mapping to a fixed value according to the amount of attenuation. In this circuit example, mapping is performed to 16 bits. In the case of a multi-bit analog-digital converter such as a 3-bit analog-digital converter, the attenuation process can be realized by multiplication using a multiplier, or by long division multiplication such as adding the number of bits of the mapped value.

The attenuation step achieves the same step amount as the gain step of the variable gain amplifier 12. When the gain step of the variable gain amplifier 12 is 0.2 dB, the maximum allowable attenuation step is 0.2 dB. To simplify implementation, the step amount of the digital attenuator 14 is defined as the same as the step amount of the variable gain amplifier 12, or as 1/2 factorial, 0.1 dB, 0.05 dB, 0.025 dB, ...

Finer step settings have the advantage of being able to accurately define the 0 dBFS output of the decimation filter 15. Usually, the output of the decimation filter 15 is operated at a wider dynamic range, such as 24-bit or 32-bit, which is a wider bit width of the PCM signal, but this is effective when matching the reference of the microphone input of multiple channels with the 0 dBFS (FS: Full Scale) output of the analog-to-digital converter 13. This eliminates the need to perform multiplication processing at multiple locations to match the levels between multiple channels. However, this is determined in consideration of the circuit size.

(About the energy comparator)
Next, the energy comparators _{16_1} ( _{16_11} , _{16_12} ) and the energy comparators _{16_2} ( _{16_21} , _{16_22} ) constituting the level comparison unit 16 will be described.

The energy comparators _{16_1} and _{16_2} output the true or false result of the comparison with the comparison value depending on the energy. For one energy, the input signal is detected by the energy comparator _{16_1} having a high threshold (first _threshold ) and the energy comparator _{16_2} having a low threshold (second threshold) in comparison with the bias of the output signal of the preamplifier 11 ( _{11_1} , 11_2).

The energy comparator _{16_1} , whose threshold is higher than the bias, outputs true logic when the input is higher than the threshold. The energy comparator _{16_2} , whose threshold is lower than the bias, outputs true logic when the input is lower than the threshold. The logical sum of the outputs of these two energy comparators _{16_1} and _{16_2} becomes the energy comparison result. The system is configured so that at least two energy thresholds can be set.

An example of setting the energy thresholds is as follows. That is, the input level to the analog-digital converter 13 at which the analog-digital converter 13 can output without distortion is set to 0 dB, and the gain of the variable gain amplifier 12 is set to the lower limit of the control variable width, and the preamplifier 11 output levels are set to provide input levels to the analog-digital converter 13 of -6 dB and -9 dB. The larger threshold is set to be equal to the reciprocal of the maximum gain set in the variable gain amplifier 12, and the next threshold is set to a value 3 dB smaller than that.

(Regarding the control unit)
Next, the control unit 17 consisting of an ARC circuit will be described. The control unit 17 handles the output signals of the two-level energy comparators _{16_1} and _{16_2} as prioritized asynchronous level interrupt signals, and controls the gain of the variable gain amplifier 12 in response to the level interrupt signal. The control unit 17 further sets the attenuation amount of the digital attenuator 14 in response to the level interrupt signal.

The control unit 17 controls the attenuation amount of the digital attenuator 14 to a value that offsets the gain of the variable gain amplifier 12 while always maintaining a constant timing difference with respect to the control timing of the variable gain amplifier 12. The control timing of the digital attenuator 14 is generated by adding a theoretical delay clock cycle due to the configuration of the analog-digital converter 13 and a clock cycle for a time period that takes into account the difference in delay between the input and output of the energy comparators _{16_1} , _{16_2} and the variable gain amplifier 12 to the control timing of the variable gain amplifier 12.

When the current gain setting value of the variable gain amplifier 12 is higher than the target gain setting value of the variable gain amplifier 12 determined in response to the level interrupt signal, the control unit 17 immediately controls the variable gain amplifier 12 to a lower target gain. When the current gain setting value of the variable gain amplifier 12 is lower than the target gain setting value of the variable gain amplifier 12, the control unit 17 controls the slope so that it does not change temporarily depending on the interrupt timing.

The control unit 17 controls the gain of the variable gain amplifier 12 in steps while maintaining a constant slope of the gain change. The timing of the step control is set to be longer than the period of frequencies lower than the audible band. However, if the step period is set to a long interval such as one second, you may notice a phenomenon in which noise generated by spurious components due to quantization of the analog-digital converter 13 becomes colored, which is unavoidable depending on the number of bits of the analog-digital converter 13 and the configuration of the dither circuit. In that case, the step period is set to a period of a higher frequency outside the audible band, such as 300 ms.

(Input/output signals and control signals at each point in the system)
Next, input/output signals and control signals at each point (A) to (E) in the system of the analog-digital conversion device 10 shown in FIG. 1 will be described.

Figure 3 is a schematic diagram showing the changes in input/output signals and control signals at each point in the system. The horizontal axis in Figure 3 is time. The microphone input is an analog signal, but in Figure 3, a step signal is given to make it easier to understand. (A) to (E) in Figure 3 represent the waveforms at each of points (A) to (E) in Figure 1.

3, the first row is the output signal of the preamplifier 11, and represents the waveform of the input signal _PGAin of the variable gain amplifier 12. The second row is the target gain of the variable gain amplifier 12 set by the energy comparators _{16_1} and _{16_2} . The third row is the gain set in the variable gain amplifier 12 by the control unit 17 consisting of an ARC circuit. The fourth row is the attenuation amount set in the digital attenuator 14 by the control unit 17.

The fifth row shows the output signal PGA _{out of the variable gain amplifier 12 in which the gain of the third-stage variable gain amplifier 12 is reflected in the input signal PGA in of} the first-stage variable gain amplifier 12, and also shows the waveform of the input signal ADC _in of the analog-digital converter 13. The sixth row shows the waveform of the signal ADC _out after being converted into a PDM (Pulse Density Modulation) signal by the 1-bit analog-digital converter 13.

The seventh row shows the waveform of the input signal CIC _in to the decimation filter 15, which is the signal after the output signal ADC _out of the analog-digital converter 13 has been attenuated by the attenuation amount in the fourth row. The eighth row shows the waveform of the signal MIC (CIC) _out after it has been PCM-converted by the decimation filter 15.

Level diagrams of each stage in the steady state are shown in Figures 4 and 5. Figure 4 is a level diagram in the case where the gain of the variable gain amplifier 12 is 0 dB, which is appropriate for the maximum allowable input of the analog-to-digital converter 13. In Figures 4 and 5, points (A) to (D) correspond to points (A) to (D) in Figure 1. Typically, the threshold of the energy comparator _{16_1} ( _{CMP_1} ) in Figures 4 and 5 is set to a level of -6 dB, which is the maximum allowable input level, and the threshold of the energy comparator _{16_2} ( _{CMP_2} ) is set to a level of -9 dB, which is the maximum allowable input level.

5 is a level diagram for the case where a gain of the variable gain amplifier 12 > 0 dB is appropriate for the maximum allowable input of the analog-digital converter 13, in other words, when the gain of the variable gain amplifier 12 is 0 dB, the input range of the analog-digital converter 13 cannot be effectively used even if the external input is at its maximum. The gain of the variable gain amplifier 12 is set to the minimum gain p _min , not 0 dB. 0 dBFS is set to the maximum value of the external input. This is a response when the bit width of the audio PCM signal after PCM conversion by the decimation filter 15 cannot be secured to about 24 bits and is not truncated.

(Regarding the operating clock)
In the block diagram of Figure 2, the preamplifiers _{11_1} , _{11_2} , the variable gain amplifiers _{12_1} , _{12_2} , the energy comparators _{16_11} , _{16_12} , and the energy comparators _{16_21} , _{16_22} are configured with analog circuits. The other components are configured with digital circuits that require a clock supply during operation, and require real-time performance without delay. Therefore, the source oscillation of the operating clock is common to all components. The components are configured with an interface that does not require asynchronous transfer for control other than interrupt detection.

Define the basic sampling frequency _fs . For audio, the sampling frequency _fs is typically 44.1 kHz or 48 kHz. In this case, the oscillation frequency of the crystal oscillator of the source is 512 _fs , that is, 22.5792 MHz or 24.576 MHz. The output side to which the digital-to-analog converter or digital amplifier is connected requires a crystal oscillator because it is affected by clock jitter.

Although this system does not directly require a crystal oscillator, when an analog-digital converter and a digital-analog converter are used simultaneously, the frequency depends on the crystal oscillator used on the digital-analog converter side. Therefore, when incorporated into a system where phase noise is a concern, such as a wireless system, it is desirable from the viewpoint of BOM (Bill of Materials) to share the X crystal oscillator between the digital-analog converter and the wireless section, and the sampling frequency f _s is a slightly higher frequency. 26 MHz and 32 MHz are often used in wireless systems. These are treated as 512 f _s , and the sampling frequency f _s is treated as 50.78125 kHz or 62.5 kHz.

When the analog-to-digital converter 13 is operated at 128 _fs , the operating frequency of the digital block in FIG.
1. Blocks of the control unit 17 ARC circuits _{171_1} , _{171_2} timing generation units _{171_11} , _{171_21} : _128fs x 4 = _512fs
2. Blocks of the control unit 17 ARC circuits _{171_1} , _{171_2} control value generation units _{171_12} , _{171_22} : _128fs
3. Blocks of the control unit 17 Dither circuit: _256fs RZ signal generation, 128fs _NRZ signal generation 4. Digital attenuator 14 and decimation filter 15: _128fs x N (N: 2 or more when computing unit is shared)

Here, the reason for selecting the clock frequencies of the timing generation units _{171_11} and _{171_21} of the ARC circuits _{171_1} and _{171_2} and the control value generation units _{171_12} and _{171_22} will be described with reference to the timing diagram of FIG.

When setting the control values of the variable gain amplifiers _{12_1} and _{12_2} at the same frequency as the operating clock of the analog-digital converters _{13_1} and _{13_2} , only when the control value changes, a timing signal CHG for setting the control value in the variable gain amplifier 12 is issued. The timing signal CHG corresponds to the timing signals _{T_1} and _{T_2} in FIG. 2, and is generated by the timing generation units _{171_11} and _{171_21} .
When a change in the control value is detected, the timing signal CHG transitions to a high level and always goes to a low level in the next cycle.
The pulse width of the control value of the variable gain amplifier 12 is half the minimum change width, and the change points of the timing signal CHG are generated so as not to overlap with the change points of the control value of the variable gain amplifier 12. A frequency four times the sampling frequency of the analog-digital converters _{13_1} and _{13_2} is appropriate.
The energy comparators _{16_1} and _{16_2} take in the signal as a level signal. Because the input signal is asynchronous, a maximum delay of two cycles of the synchronous clock occurs. For the synchronous clock, a frequency four times the sampling frequency of the analog-digital converters _{13_1} and _{13_2} is appropriate.

FIG. 7 _shows a timing diagram of the output signals AIN _{x _CMP — 1} and AIN x _CMP _{— 2} of the energy comparators 16 _{— 1} and 16 — 2 with respect to the output signals of the preamplifiers 11 _{— 1} and 11 _{— 2} , which are the input signals PGA in of the variable gain amplifiers 12 — _{1 and} 12 _{— 2} .

When _the power of the output signal of the preamplifiers _{11_1} and _{11_2} exceeds _{the specified values CMPxH_1_VTH, CMPxL_1_VTH / CMPxH_2_VTH , CMPxL_2_VTH ,} this is an interrupt source that asserts high (Hi) active. One interrupt is generated by _a pair of comparison outputs _{AINx_CMP_1} and _{AINx_CMP_2 ,} one for the positive and negative sides of the bias. Two or more interrupts are prepared, and when the interrupts assert simultaneously, the one with the larger power threshold is given priority. When _the energy comparator _{16_1} is operated under the assumption that a larger value is set for _{CMP_1} , the energy comparator _{16_1} has priority as an interrupt.

Here, the control of the attenuation amounts of the digital attenuators _{14_1} and _{14_2} by the ARC circuits _{171_1} and _{171_2} of the control unit 17 will be described.

After the gains of the variable gain amplifiers _{12_1} , _{12_2} are set, the control value generators _{171_12} , _{171_22} in the ARC circuits _{171_1} , _{171_2} output the attenuation amount for correction as the control value _{MICx_VOL} in accordance with the inherent delays of the variable gain amplifiers _{12_1} , _{12_2} and the analog-to-digital converters _{13_1} , _{13_2} . The control value MICx_VOL corresponds to the control values _{N_a1} , _{N_a2} in FIG. 2.

The digital attenuators _{14_1} , _{14_2} interpret the set value of _{CMP_1_VOL} as the minimum gain p _min and control the control value _{MIC_VOL} to 0 dB when the gains of the variable gain amplifiers _{12_1} , _{12_2} are set to the minimum gain p _min . The interface between the ARC circuits _{171_1} , _{171_2} and the digital attenuators _{14_1} , _{14_2} is not an attenuation amount but a volume value in which a negative gain is mapped in 0.05 dB steps.
MIC _x _VOL+PGA_VOL=CMP _{_1} _VOL
This is the relationship.

(Delay time caused by analog-to-digital converter)
The control unit 17 controls the gains of the variable gain amplifiers _{12_1} and _{12_2} and the attenuation amounts of the digital attenuators _{14_1} and _{14_2} at appropriate time intervals. Fig. 8 shows a path from the variable gain amplifiers 12 ( _{12_1} and _{12_2} ) to the digital attenuators 14 ( _{14_1} and _{14_2} ).

The delay time caused by the analog-digital converters 13 ( _{13_1} , _{13_2} ) is uniquely determined by the topology. The STF(f) (STF: Signal Transfer Function) is found from the circuit, and the delay time Δt can be calculated by arg(STF(f))/2πf. f is calculated as 20 kHz. _fs = 48 kHz, 44.1 kHz, and varies depending on the crystal oscillator and reference clock used, but the number of cycles is constant depending on the topology, regardless of the sampling _fs or operating clock.

The fraction after the decimal point is determined together with the delay of the variable gain amplifiers _{12_1} and _{12_2} . The operating clock of the control unit 17 is _512fs , so it may be converted into the number of cycles of the _512fs clock, but since there is variation in the analog part, the precision is not pursued to _512fs , and the main body of the control unit 17 including the timing adjustment is operated at _128fs , which is the same frequency as the analog-digital converter 13.
As an example, for a third order ΔΣ modulator, it is 8.4 cycles at 128 _fs .

(Regarding delay in gain setting operation of variable gain amplifier)
The variable gain amplifiers 12 ( _{12_1} , _{12_2} ) are analog blocks and therefore have delay variations, but in an actual design, it is possible to keep the delay within about one cycle of the _128fs clock. Although it depends on the gain of the variable gain amplifier 12, when the gain range of the variable gain amplifier 12 is about 0 to 6 dB, it is possible to keep the delay within a range of two to four cycles of the _128fs clock, so the delay variations are corrected by a fixed number of cycles.

The delay setting cycle is variable because the delay time changes depending on the set gain. A change from large to small gain occurs immediately in large steps, so correction is made with the delay value for the small gain. A change from small to large gain occurs very slowly in small steps such as 0.2 dB, so correction is made with an appropriate delay value for the current control value of the variable gain amplifier 12.

In an actual example, the difference in the number of correction steps between 0 dB and 6 dB is approximately 1.5, so it is possible to operate with only two correction step values: one when the gain changes from small to large, and one when the gain changes from large to small.

Because of the analog delay, the number of cycles changes depending on the frequency of _fs by the reference clock. Table 1 shows the relationship between the gain (PGA gain) of the variable gain amplifier 12 and the minimum delay time (Min.ns), normal delay time (Typ.ns), and maximum delay time (Max.ns) (delay of the variable gain amplifier 12 with an input capacitance (5 pF) equivalent to that of the ΔΣ modulator). Table 2 shows the relationship between the gain (PGA gain) of the variable gain amplifier 12 and the _fs frequency, minimum cycle (Min.cycle), normal cycle (Typ.cycle), and maximum cycle (Typ.cycle) (128 _fs cycle for the delay of the variable gain amplifier 12). Since there is a change depending on the operating clock frequency, the number of cycles of the correction value can be changed by referring to the register value that defines _fs for the entire system.

(Regarding setting the control timing difference between gain and attenuation)
Next, setting of the timing difference between the timing of the gain control of the variable gain amplifier 12 and the timing of the attenuation amount control of the digital attenuator 14 will be described.

In one example, the sum of the delay of the ΔΣ modulator constituting the analog-to-digital converter 13 and the delay of the variable gain amplifier 12 is about 11 or 12 cycles when the operating clock frequency of the analog-to-digital converter 13 is 128 _s . As shown below, a common delay cycle of 8 of the ΔΣ modulator is subtracted and made separately configurable.
When the attenuation setting is changed from small to large, 3 cycles occur due to factors other than the delay of the ΔΣ modulator. When the attenuation setting is changed from large to small, 4 cycles occur due to factors other than the delay of the ΔΣ modulator.

After setting the gain of the variable gain amplifier 12, a delay is applied for the sum of 8 cycles of the delay of the ΔΣ modulator and the delay of the variable gain amplifier 12 described above, and then the attenuation amount of the digital attenuator 14 is set. If a pipeline is inserted for implementation reasons, the recommended register setting value is reduced by the number of cycles of the pipeline.

(About the implementation of delay in reflecting settings)
If a shift register is used for delay, the number of flip-flops will be 100, which is 1k gates in scale. If a low-pass filter time constant is used, the gate clock cannot be inferred, and unless a HALT function and HALT clock configuration are used, the multiplication and addition circuit will operate constantly, wasting power.

When the external input in Figure 8 changes from small to large, it is necessary to immediately set the gain of the variable gain amplifier 12 and the attenuation of the digital attenuator 14. Therefore, if two interrupts are input consecutively from the energy comparators _{16_1} and _{16_2} , the processing intervals for the gain setting and the attenuation setting must be measured separately for each interrupt and each setting must be performed.

On the other hand, when the external input changes from large to small, the gain of the variable gain amplifier 12 and the attenuation of the digital attenuator 14 are set with a difference of about 0.025 seconds, so there is a margin in the number of cycles even if the operating clock frequency is 128 _fs . The transition interval of the FSM (Finite State Machine) can be made slower than the processing interval for setting the gain of the variable gain amplifier 12 and the attenuation of the digital attenuator 14.

Therefore, from the standpoint of ease of implementation and verification, and power consumption, three timer counters are prepared to manage the processing intervals for the gain setting of the variable gain amplifier 12 and the attenuation setting of the digital attenuator 14, and are implemented using an FSM.

9A and 9B show timing diagrams of an example of the operation of setting the gain of the variable gain amplifier 12. In FIG. 9A and 9B, the output signal of the energy comparator _{16_1} ( _{CMP_1} ), the output signal of the energy comparator _{16_2} ( _{CMP_2} ), the target gain of the variable gain amplifier 12, and the gain PVOL of the variable gain amplifier 12 are shown.

10A and 10B show timing diagrams of an example of the operation of three timer counters that manage the processing intervals for setting the gain of the variable gain amplifier 12 and the attenuation amount setting of the digital attenuator 14. In Fig. 10A and 10B, the output signal of _{CMP_1} , the output signal of _{CMP_2} , the target gain of the variable gain amplifier 12, the gain PVOL of the variable gain amplifier 12, and the attenuation amount MVOL of the digital attenuator 14 are shown.

The timing for lowering the gain PVOL of the variable gain amplifier 12 is instantaneous. The timing interval for increasing the gain PVOL of the variable gain amplifier 12 is controlled to always be constant. The delay in setting the gain PVOL of the variable gain amplifier 12 and the setting of the attenuation amount MVOL of the digital attenuator 14 is also controlled so that it does not occur at a timing other than the settings, in other words, so that the time difference is constant.

(Level interrupt and variable gain amplifier gain settings)
The output signal of the energy comparator _{16_1} ( _{CMP_1} ) and the output signal of the energy comparator _{16_2} ( _{CMP_2} ) are treated as level interrupts. After the two interrupts are asynchronously switched at the _512fs clock, it is determined whether or not to use the interrupt by the enable register. When both are enabled, _{CMP_1} is processed preferentially as a prioritized interrupt.

Therefore, a large power is set in the threshold setting register CMP _n H _x _VTH of _{CMP_1} , and a small gain is set in the gain setting register CMP _{x _VOL} of the variable gain amplifier 12, which is set when processing an interrupt request. Registers of setting values are prepared for each analog input system n and energy comparator system x.

If there is no interrupt with a higher priority, the gain PVOL of the variable gain amplifier 12 is set to the target gain setting value corresponding to the interrupt system. The operation differs depending on the magnitude relationship between the currently set gain PVOL of the variable gain amplifier 12 and the target gain setting value corresponding to the interrupt.

1. When the current gain setting value is higher than the target gain setting value corresponding to the interrupt, the gain of the variable gain amplifier 12 is immediately set to the value in the setting register.
2. When the current gain setting is lower than the target gain setting corresponding to the interrupt, the gain of the variable gain amplifier 12 is gradually made to approach the target value at intervals set in a specified register. The gain step of the variable gain amplifier 12 that transitions at one time is usually 0.2 dB. The setting value is variable.

The actual gain of the variable gain amplifier 12 is the integer value of the register value multiplied by 0.2. The upper and lower limits of the gain setting of the variable gain amplifier 12 can be set.

The lower limit of the gain setting is set assuming that the input range of the analog-to-digital converter 13 cannot be fully used even when the maximum input of the external microphone passes through the preamplifier 11. It is possible to use a gain of +3 dB even with the maximum input, instead of a gain of +6 dB. This value is set as the minimum gain p _min .

The upper limit of the gain setting is set on the assumption that the noise figure of the variable gain amplifier 12 is poor when the gain is high, and this may actually worsen the S/N ratio during normal operation of the entire system. This corresponds to a case where it is better to use +4 dB rather than +6 dB. This value is set as the maximum gain p _max .

Figure 11 shows an explanatory diagram of the delay time from the output of the audio signal from the preamplifier 11 to the gain setting of the variable gain amplifier 12.

An example of the delay amount of the energy comparators _{16_1} and _{16_2} is 0.4 μs. The level interrupt is asynchronously switched with the fastest clock in the system that is synchronous with the operation clock of the control unit 17. The fastest frequency is 512 _fs , and when _fs = 44.1 kHz, the delay is 0.089 μs. This interrupt signal is used to operate the FSM and manipulate the control register value, so even at the fastest, a delay of one cycle of the operation clock of the control unit 17 occurs.

Due to the delay caused by the asynchronous transfer and the operation of the control unit 17, the delay from the comparison and judgment of the input levels of the ARC circuits _{171_1} and _{171_2} of the control unit 17 to the gain setting of the variable gain amplifier 12 is the sum of these. If the operating clock _128fs of the control unit 17 is set to 1/4 the speed of the source oscillation, a delay of 6 to 10 cycles of the _512fs clock occurs from the output of _{16_1} and _{16_2} . In terms of time, this is 0.666μs to 0.834μs, so the system will ignore the delay of this part.

(About attenuation setting)
The attenuation amount of the digital attenuators _{14_1} and _{14_2} is determined by two factors: the minimum gain p _min and the gain setting value p _vol of the variable gain amplifiers _{12_1} and _{12_2} . The gain setting value p _vol corresponds to the control values _{N_p1} and _{N_p2} in Fig. 2. Here, if the attenuation amount is m _att and the volume expression of a negative number is m _vol , the volume expression of a negative number m _vol is expressed as follows:
_mvol = _pmin - _pvol
The attenuation amount m _att is
m _att = p _vol - p _min
The magnitude relationship between the minimum gain p _min , the gain setting value p _vol , and the maximum gain p _max is as follows:
p _min ≦p _vol ≦p _max
It is.

Table 3 shows an example of the setting specifications of the register MIC_VOL that controls the digital attenuators _{14_1} and _{14_2} . The register MIC_VOL is provided in the control value generating units _{171_12} and _{171_22} in FIG. 2. The mute and 0 dB settings are irregular. A regular calculation using the gain setting value _pvol of the variable gain amplifiers _{12_1} and _{12_2} outputs a negative volume expression _mvol to the digital attenuators _{14_1} and _{14_2} . If we consider an 8-bit invisible sign bit and consider that it is deleted and interfaced, it can be expressed in two's complement. Since specifying mute causes problems, the negative side is processed for overflow with 0x82. The positive side is processed with 0x00.

If 0.2 or 0.05 is expressed as a binary fixed-point number, it becomes an irrational number, so it is converted to an integer before handling. The minimum unit of the step of the gain setting value p _vol is 0.2 dB, which is four times the step of the negative volume expression m _vol . Therefore, the result of the calculation using integer values P _VOL , P _MIN , and P _MAX , which are p _vol , p _min , and p _max multiplied by 5, is further multiplied by 4 to obtain M _VOL , which becomes the signal level supplied to the digital attenuators _{14_1} and _{14_2} . The most significant bit of M _VOL is excluded from the sign bit. The integer values P _VOL , P _MIN , and P _MAX are the same as the output signal and the register setting value.

The digital attenuators _{14_1} and _{14_2} can set the attenuation amount finer than 0.2 dB in order to adjust the amount on a channel-by-channel basis. Since the attenuation amounts of the digital attenuators _{14_1} and _{14_2} are fixed amounts, offsets can be applied independently.

[Control method, operation, and effect according to the embodiment]
The analog-to-digital conversion device 10 according to this embodiment configured as described above is configured for feedforward control, which detects the level of an input analog signal and controls the gain of the variable gain amplifier 12 and the attenuation of the digital attenuator 14 based on the detected level. Furthermore, the feedforward control makes it possible to provide an analog-to-digital conversion device with superior control loop responsiveness compared to feedback control.

Furthermore, the analog-to-digital conversion device 10 according to this embodiment can provide the following actions and effects.
In audio applications, it is possible to obtain a dynamic range during operation that is wider than the input dynamic range of the analog-to-digital converters 13 ( _{13_1} , _{13_2} ).
The occurrence of pop noise, which is a problem in audio, can be sufficiently suppressed when a sudden strong input change occurs.
When an audible band signal with a constant signal strength is input, the input signal is not affected by the system and constant static characteristics can be obtained.
- The dynamic range can be expanded without any discomfort when changing from strong input to weak input.
The analog block requires the addition of an energy comparator consisting of a comparator and a logical OR to enable fine gain setting, but this can be achieved with a small-scale circuit configuration.
The digital block does not require calculations using a DSP (Digital Signal Processor) or the like, and can be realized with a small-scale configuration mainly consisting of an FSM.

[Implementation example]
Next, an implementation example of the analog-to-digital conversion device 10 according to the present embodiment shown in FIG. 2 will be described.

(Example of implementation of _512fs operation block)
FIG. 12 is a diagram for explaining an implementation example of a _512fs operation block. The _{inputs A_W_AINn_CMPx} of the energy comparators _{16_1} and _{16_2} are synchronized by a simple synchronous circuit and output as _a level interrupt signal _{AINn_CMPx} . There is a large difference in the time required for response processing corresponding to assertion and negation of an interrupt. When asserting, it is immediate, but when negating, data transition is promoted at an interval of at least 32 cycles by an FSM operating on a _128fs clock. Therefore, chattering removal of the level interrupt signal can be controlled by the FSM, and is not performed because it is not necessary for the input stage to respond. As a result, a synchronized signal is asserted at the fastest speed even when an interrupt is asserted.

The gain setting of the variable gain amplifiers _{12_1} and _{12_2} is realized by asserting the setting signal _{A_W_PGAx_CHG} after giving the gain setting value _{A_W_PGAx_VOL} . In the _512fs operation block, an FSM dedicated to generating the setting signal _{A_W_PGAx_CHG} is configured. The gain setting value of the variable gain amplifiers _{12_1} and _{12_2} generated by the FSM operating at a clock of _128fs is observed. The state is configured with an IDLE(1) state waiting for detection of a change, a CHG(2) state to which a transition occurs when a change is detected, a HOLD(3) state to which a transition occurs unconditionally in one cycle _{of 512fs} from the CHG state, and a RESET(0) state to which a transition occurs upon an asynchronous reset. After the asynchronous reset is released from the RESET state, the state transitions unconditionally to the IDLE state. With this configuration, the most significant bit of the 2-bit register that holds the state value is output as a signal for setting the gain values of the variable gain amplifiers _{12_1} and _{12_2} .

( _128fs operation block implementation example 1)
13A and 13B are timing diagrams for explaining implementation example 1 of a 128 _fs operating block. In implementation example 1, an overview will be given of generating a gain setting value PVOL (A_W_PGA _x _VOL) and an attenuation setting signal MVOL (A_M_MIC _x _VOL) from an FSM that operates on a 128 _fs clock and a block that operates on a control signal generated by the FSM.

It is also shown that the target gain setting value is set according to the priority interrupt signal and interrupts used at the input of the FSM. The target gain setting value is used to generate the gain PVOL of the variable gain amplifiers _{12_1} and _{12_2} . The gain PVOL is managed within the FSM and outputs the value to be set.

In order to realize a small circuit scale, the delay control of the gain setting timing and the attenuation setting timing is configured by three delay timers. Each delay timer starts operation with a start signal, and generates an attenuation setting signal from the gain setting value when a predetermined setting threshold is reached. The three delay timers are delay timer 1, which starts operation when the energy comparator CMP ₁ asserts, delay timer 2, which starts operation when only the energy comparator CMP ₂ asserts, and delay timer 3, which starts operation at the timing when the target gain setting value, which is determined by the assertion state of the energy comparators CMP ₁ and CMP _2, is set lower than the current gain setting value.

The gain setting value that is set when the energy comparators _CMP1 and _CMP2 assert is constant. It is made variable by a register. In the figure, the target gain setting value _PVOL1 that is set when the energy comparator _CMP1 referenced by the delay timer 1 asserts is the minimum gain p _min . The setting value is stored in the AIN _{x CMP1} VOL register and supplied as a signal named CSYN_AIN _{x CMP1} VOL.

The target gain setting value _PVOL2 , which is set when the energy comparator _CMP2 referenced by the delay timer 2 is asserted, is an intermediate gain, and the setting value is stored in the _{AINx_CMP2_VOL register} and supplied as _{CSYN_AINxCMP2_VOL} . The target gain setting value referenced by the delay timer 3 becomes _the currently set gain value PVOL.

An attenuation setting value MVOL is generated as a signal named A_M_MIC _x _VOL from the end timings of the three delay timers and the supplied gain setting value. The attenuation setting value MVOL determines the amplitude of the input signal to the digitalization filter 15.

( _128fs operation block implementation example 2)
14 is a diagram for explaining implementation example 2 of the _128fs operation block. Implementation example 2 is an implementation example in which the gain setting value PVOL (A_W_PGA _x _VOL) is forcibly set to a fixed value. Normally, the setting value is controlled by the FSM, but the value of the fixed setting register PGA _x _VOL and signal name CSYN_PGA _x _VOL is reflected when enable is asserted.

( _128fs operation block implementation example 3)
Fig. 15A is an explanatory diagram of implementation example 3 of a _128fs operation block, and Fig. 15B is a timing diagram for explaining implementation example 3. Implementation example 3 is an implementation example of an FSM.

There is one counter that controls the FSM. It is implemented to increment when the value is other than 0. This counter controls the FSM operation that changes the gain of the variable gain amplifiers _{12_1} and _{12_2} at regular intervals when the target gain setting value is greater than the current gain setting value PVOL.

The FSM operates when the CSYN_ARC _x _EN signal is asserted. When it is negated, it is in the RESET (0) state. When the CSYN_ARC _x _EN signal is asserted, it transitions from the RESET (0) state to the EQUAL (1) state.

In the EQUAL(1) state, the state remains in the EQUAL(1) state when the gain setting value PVOL is equal to the target gain setting value. The target gain setting value is updated by an interrupt, and when the target gain setting value is higher than the current gain setting value, the state transitions to a state for increasing the gain of the variable gain amplifiers _{12_1} and _{12_2} by 0.2 dB steps at regular intervals, using the setting value register ARC _x PGA_STEP and signal name CSYN_ARC _x PGA_STEP.

The state transitions to the LESS_THAN(2) state, and at the same time, the FSM control counter is set to 1 and begins incrementing. When the FSM control counter reaches 32, the state transitions to the INTERVAL(3) state. In the INTERVAL(3) state, the time interval for stepping up the gain setting value in units set in the ARC _x PGA_STEP register, usually equivalent to 0.2 dB, is created by observing the FSM control counter.

Since this corresponds to one period of a low frequency outside the audible range, the lower bits of the counter, which operates on the FSM operating clock _{of 128fs} , can be ignored and timing can be created by comparing only the upper bits. The threshold for comparison with the upper bits of the counter is set by the ARC _n TIMER_TH register, signal name CSYN_ARC _n TIMER_TH. When the counter reaches the threshold, it transitions to the LESS_THAN (2) state and resets the FSM control counter to 1 to create the next interval.

When transitioning from the INTERVAL (3) state to the LESS_THAN (2) state, the gain setting value PVOL is updated to a stepped-up value. At the same time, the increment operation of delay timer 3, which operates the attenuation setting value MVOL with a delay difference, is started, and the PVOL3 register, which notifies the circuit that generates the attenuation setting value MVOL of the updated value, is set to the same value as the gain setting value PVOL. In order to start operation of delay timer 3 at the transition, a start 3 signal is generated that is asserted only in the cycle in which the transition is determined.

When the target gain setting value updated by the interrupt is lower than the current gain setting value, regardless of the state, the gains of the variable gain amplifiers _{12_1} and _{12_2} are set to the target value in the next cycle and the state transitions to the EQUAL(1) state. At the same time, in response to the interrupt that occurs, the increment operation of the delay timer 1 or delay timer 2 for controlling the digital attenuators _{14_1} and _{14_2} is started. A start signal is generated to start the increment operation of the delay timer 1/delay timer 2.

This logic can be realized by saying that the current gain setting is greater than the target gain setting. This is because in the next cycle the current gain setting will always be equal to the target gain setting. The counter for FSM control is also set to 0 to stop operation.

Each delay timer is configured with logic that increments by a non-zero value, sets it to 1 the next cycle when the start signal is asserted, and sets it to 0 when the threshold is reached.

( _128fs operation block implementation example 4)
Implementation example 4 is an example of the operation of the delay timer. An example of a timing diagram of the operation of the delay timer is shown in Fig. 16. Here, it is specified on the assumption that the threshold value of the delay timer will not exceed 31.

The timing diagram in Fig. 16 shows the case when the delay timer threshold is at its maximum setting of 31. The delay timer threshold is a maximum of 12 cycles for a 128 _fs ΔΣ modulator prepared as specified in the section above (Setting the control timing difference between gain and attenuation), and even if a ΔΣ modulator of the same topology is operated at 64 _fs , the delay cycles due to the ΔΣ modulator is 16, so the maximum is 20 cycles. Therefore, a setting of 31 is sufficient for the delay timer threshold.

The delay timer is a circuit for creating change points of the digital attenuators 14_1 and 14_2 with a small-scale circuit operation from three different gain setting change points due to an event with a different timing from the FSM that occurs to transition the two gain setting values to lower values and _an event due to one FSM that transitions the gain setting value to higher _values .

Since the timing occurs independently, an appropriate attenuation setting value is generated when any of the delay timers reaches the threshold. Since the attenuation setting value is calculated from the gain setting value, the appropriate gain setting value _PVOL1 , _PVOL2 , _PVOL3 is referenced for each timing, in addition to the current gain setting value. Each occurs independently, and the definition of the delay time is not defined by gain, but by the delay cycle defined by the change direction of the gain setting, as described above (Regarding the delay of the gain setting operation of the variable gain amplifier). This makes the number of delay cycles for delay timer 1 and delay timer 2 the same, and guarantees that the time to reach the threshold will never be different.

Since the setting delay is in units of 128 _fs , the perception of error can be ignored, and this is a restriction imposed on the premise of making the implementation easier. Since a gain setting value change caused by an interrupt from the energy comparators _{16_1} and _{16_2} may occur while the delay timer 3 is operating, the condition for stopping the delay timer 3 includes the timing when the delay timer 1 or delay timer 2 reaches the threshold. Therefore, if the delay timer 3 reaches the threshold at the same time as the delay timer 1 or delay timer 2 reaches the threshold, the delay timer 1 or delay timer 2 has priority, so that the immediately effective operation of changing the gain of the variable gain amplifiers _{12_1} and _{12_2} can also be preferentially executed by the control of the digital attenuators _{14_1} and _{14_2} .

In this way, the operation of the delay timer also determines the priority of the setting timing of the attenuation setting values to be set in the digital attenuators _{14_1} and _{14_2} , so the register that holds the attenuation setting values can be configured as a circuit that determines the values by referring to the gain setting values _PVOL1 , _PVOL2 , and _PVOL3 corresponding to the delay timers when the respective delay timers reach their respective timings, without taking the priority into consideration.

The generation of the attenuation setting value MVOL is determined by the formula defined in the above section (Regarding attenuation setting), and overflow processing is also performed. The timing at which the delay timer reaches the threshold is notified one cycle earlier, and the selection of the gain setting values _PVOL1 , _PVOL2 , and _PVOL3 for generating the attenuation setting value MVOL is determined one cycle earlier and held in the pipeline. Therefore, as defined in the above section (Regarding setting the control timing difference between gain and attenuation), a value one cycle smaller is given to the setting register that controls the delay timer threshold.

<Audio device according to an embodiment of the present disclosure>
The analog-to-digital conversion device 10 according to the embodiment of the present disclosure described above can be used as the analog-to-digital conversion device in various audio devices equipped with the analog-to-digital conversion device.

Figure 17 is a block diagram showing an outline of the system configuration of an audio device according to an embodiment of the present disclosure, using an analog-to-digital conversion device 10 according to an embodiment of the present disclosure. The audio device 100 according to this embodiment is configured to include, for example, a microphone 110, an analog-to-digital conversion device 120, a signal processing unit 130, a digital-to-analog conversion device 140, and a speaker 150.

In the audio device 100 configured as above, the analog-to-digital conversion device 10 according to the embodiment described above can be used as the analog-to-digital conversion device 120 that converts the analog audio signal input from the microphone 110 into an audio PCM signal. This analog-to-digital conversion device 10 is a feedforward control that detects the level of the input analog audio signal and performs gain control based on the detected level, so that the analog-to-digital conversion device 120 can be an analog-to-digital conversion device with excellent control loop responsiveness.

<Modification>
Although the technology of the present disclosure has been described above based on preferred embodiments, the technology of the present disclosure is not limited to these embodiments. The configurations and structures of the analog-to-digital conversion device and audio device described in the above embodiments are merely examples and can be modified as appropriate.

For example, in the above embodiment, the analog-digital conversion device 10 is applied to an audio device 100, but the application is not limited to audio devices. Also, in the above embodiment, an analog-digital converter consisting of a ΔΣ modulator (a delta-sigma modulation type analog-digital converter) is used as the analog-digital converter 13 in the analog-digital conversion device 10, but this is not limited to this, and other types of analog-digital converters, such as a successive approximation type analog-digital converter, can be used.

<Configurations that the present disclosure can take>
The present disclosure may also be configured as follows.

<A. Analog-to-digital conversion device>
[A-1] A variable gain amplifier that amplifies an input analog signal;
an analog-to-digital converter that converts the analog signal passed through the variable gain amplifier into a digital signal;
an attenuator for attenuating the digital signal output from the analog-to-digital converter;
a level detection unit for detecting a level of an analog signal; and
a control unit that controls a gain of the variable gain amplifier and an attenuation amount of the attenuator based on a detection level of the level detection unit;
Analog-to-digital conversion device.
[A-2] A preamplifier that takes in an input analog signal and supplies it to a variable gain amplifier,
The level detection unit detects the level of the analog signal after passing through the preamplifier.
The analog-to-digital conversion device described in [A-1] above.
[A-3] The level detection unit has a plurality of comparators having different thresholds;
The analog-to-digital conversion device according to [A-2] above.
[A-4] The level detection unit has a first comparator having a first threshold higher than the bias of the output signal of the preamplifier, and a second comparator having a second threshold lower than the bias of the output signal of the preamplifier;
The analog-to-digital conversion device described in [A-3] above.
[A-5] The first comparator outputs a true logic when the level of the analog signal is higher than a first threshold value;
The second comparator outputs a true logic when the level of the analog signal is lower than a second threshold.
The analog-to-digital conversion device described in [A-4] above.
[A-6] The level detection unit outputs the logical sum of the output of the first comparator and the output of the second comparator as the detection level of the analog signal.
The analog-to-digital conversion device described in [A-5] above.
[A-7] The preamplifier has the role of keeping the output impedance constant against operational changes of the variable gain amplifier and the level detector.
An analog-to-digital conversion device according to any one of [A-1] to [A-6] above.
[A-8] The control unit controls the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier.
An analog-to-digital conversion device according to any one of [A-1] to [A-7] above.
[A-9] The control unit controls the attenuation amount of the attenuator while maintaining a constant timing difference with respect to the control timing of the variable gain amplifier.
The analog-to-digital conversion device according to [A-8].
[A-10] The analog-to-digital converter is composed of a delta-sigma modulator that oversamples the analog signal that has passed through the variable gain amplifier and converts it into a pulse train signal according to the amplitude of the analog signal.
An analog-to-digital conversion device according to any one of [A-1] to [A-9] above.
[A-11] A decimation filter is provided for converting the pulse train signal output from the delta-sigma modulator and passed through the attenuator into a digital signal having a sampling frequency that can obtain the necessary signal information without being affected by aliasing noise.
The analog-to-digital conversion device according to [A-10] above.

B. Control method of analog-digital conversion device
[B-1] A variable gain amplifier that amplifies an input analog signal;
an analog-to-digital converter that converts the analog signal passed through the variable gain amplifier into a digital signal; and
In controlling an analog-to-digital conversion device having an attenuator that attenuates a digital signal output from an analog-to-digital converter,
Detects the level of the analog signal,
Based on the detection level, the gain of the variable gain amplifier and the attenuation of the attenuator are controlled.
A method for controlling an analog-to-digital conversion device.
[B-2] The pulse train signal output from the delta-sigma modulator and passed through the attenuator is converted into a digital signal with a sampling frequency that can obtain the necessary signal information without being affected by aliasing noise.
A method for controlling the analog-to-digital conversion device described in [B-1] above.

C. Audio Equipment
[C-1] A variable gain amplifier that amplifies an input analog signal;
an analog-to-digital converter that converts the analog signal passed through the variable gain amplifier into a digital signal;
an attenuator for attenuating the digital signal output from the analog-to-digital converter;
a level detection unit for detecting a level of an analog signal; and
a control unit that controls a gain of the variable gain amplifier and an attenuation amount of the attenuator based on a detection level of the level detection unit;
An audio device having an analog-to-digital conversion device.
[C-2] A preamplifier that takes in an input analog signal and supplies it to a variable gain amplifier,
The level detection unit detects the level of the analog signal after passing through the preamplifier.
The audio device described in [C-1] above.
[C-3] The level detection unit has a plurality of comparators having different thresholds;
The audio device described in [C-2] above.
[C-4] The level detection unit has a first comparator having a first threshold higher than the bias of the output signal of the preamplifier, and a second comparator having a second threshold lower than the bias of the output signal of the preamplifier;
The audio device described in [C-3] above.
[C-5] The first comparator outputs a true logic when the level of the analog signal is higher than a first threshold;
The second comparator outputs a true logic when the level of the analog signal is lower than a second threshold.
The audio device described in [C-4] above.
[C-6] The level detection unit outputs the logical sum of the output of the first comparator and the output of the second comparator as a detection level of the analog signal.
The audio device described in [C-5] above.
[C-7] The preamplifier has the role of keeping the output impedance constant against operational changes of the variable gain amplifier and the level detector.
An audio device according to any one of [C-1] to [C-6] above.
[C-8] The control unit controls the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier.
An audio device according to any one of [C-1] to [C-7] above.
[C-9] The control unit controls the attenuation amount of the attenuator while maintaining a constant timing difference with respect to the control timing of the variable gain amplifier.
The audio device described in [C-8].
[C-10] The analog-to-digital converter is composed of a delta-sigma modulator that oversamples the analog signal that has passed through the variable gain amplifier and converts it into a pulse train signal according to the amplitude of the analog signal.
An audio device according to any one of [C-1] to [C-9] above.
[C-11] A decimation filter is provided to convert the pulse train signal output from the delta-sigma modulator and passed through the attenuator into a digital signal having a sampling frequency that can obtain the necessary signal information without being affected by aliasing noise.
The audio device described in [C-10] above.

REFERENCE SIGNS LIST 10...Analog-to-digital conversion device, 11 ( _{11_1} , _{11_2} )...Preamplifier, 12 ( _{12_1} , _{12_2} )...Variable gain amplifier, 13 ( _{13_1} , _{13_2} )...Analog-to-digital converter (ADC), 14 ( _{14_1} , _{14_2} )...Digital attenuator, 15...Decimation filter, 16...Level detection unit, _{16_1} ( _{16_11} , _{16_12} ), _{16_2} ( _{16_21} , _{16_22} )...Energy comparator, 17...Control unit

Claims (10)

a variable gain amplifier that amplifies the input first analog signal ;
an analog-to-digital converter that converts the second analog signal output from the variable gain amplifier into a digital signal;
an attenuator for attenuating the digital signal output from the analog-to-digital converter;
a level detection unit that detects a level of the first analog signal; and
a control unit that controls a gain of the variable gain amplifier and an attenuation amount of the attenuator based on the detection level of the level detection unit,
the control unit controls the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier, at a timing obtained by adding a delay time due to the topology of the analog-to-digital converter and a time based on a delay difference between input and output between the level detection unit and the variable gain amplifier to a control timing of the variable gain amplifier.
Analog-to-digital conversion device. a preamplifier that receives a third analog signal and supplies the first analog signal to the variable gain amplifier;
the level detection unit detects the level of the first analog signal after passing through the preamplifier.
2. The analog-to-digital conversion device according to claim 1. The level detection unit has a plurality of comparators having different threshold values.
3. An analog-to-digital conversion device according to claim 2. the level detection unit includes a first comparator having a first threshold higher than a bias of the output signal of the preamplifier, and a second comparator having a second threshold lower than the bias of the output signal of the preamplifier;
4. An analog-to-digital conversion device according to claim 3. the first comparator outputs a true logic when a level of the first analog signal is higher than the first threshold;
the second comparator outputs a true logic when the level of the first analog signal is lower than the second threshold.
5. An analog-to-digital conversion device according to claim 4. the level detection unit outputs a logical sum of the output of the first comparator and the output of the second comparator as a detection level of the first analog signal.
6. An analog-to-digital conversion device according to claim 5. the analog-to-digital converter comprises a delta-sigma modulator that oversamples the second analog signal that has passed through the variable gain amplifier and converts it into a pulse train signal corresponding to the amplitude of the second analog signal;
7. An analog-to-digital conversion device according to claim 1. a decimation filter that converts the pulse train signal output from the delta-sigma modulator and passed through the attenuator into a digital signal having a sampling frequency that allows necessary signal information to be obtained without being affected by aliasing noise;
8. An analog-to-digital conversion device according to claim 7. a variable gain amplifier that amplifies a first analog signal that is an input signal;
an analog-to-digital converter that converts the second analog signal output from the variable gain amplifier into a digital signal; and
In controlling an analog-to-digital conversion device including an attenuator that attenuates the digital signal output from the analog-to-digital converter,
Detecting the level of the first analog signal using a level detection unit;
The control unit
based on the detection level, controlling the gain of the variable gain amplifier and the attenuation of the attenuator;
controlling the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier, at a timing obtained by adding a delay time due to the topology of the analog-digital converter and a time based on a delay difference between input and output between the level detection unit and the variable gain amplifier to a control timing of the variable gain amplifier;
A method for controlling an analog-to-digital conversion device. a variable gain amplifier that amplifies a first analog signal that is an input signal;
an analog-to-digital converter that converts the second analog signal output from the variable gain amplifier into a digital signal;
an attenuator for attenuating the digital signal output from the analog-to-digital converter;
a level detection unit that detects a level of the first analog signal; and
a control unit that controls a gain of the variable gain amplifier and an attenuation amount of the attenuator based on the detection level of the level detection unit,
the control unit controls the attenuation amount of the attenuator to a value that offsets the gain of the variable gain amplifier, at a timing obtained by adding a delay time due to the topology of the analog-to-digital converter and a time based on a delay difference between input and output between the level detection unit and the variable gain amplifier to a control timing of the variable gain amplifier.
An audio device having an analog-to-digital conversion device.

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