JP7524745B2 - Electro-optical devices and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device.

Electronic devices such as projectors use electro-optical devices such as liquid crystal displays that can change the optical characteristics of each pixel.

The electro-optical device described in Patent Document 1 includes a substrate, a pixel electrode provided for each pixel, a transistor having an LDD (Lightly Doped Drain) structure as a switching element for the pixel electrode, and a light-shielding film disposed between the substrate and the transistor. The transistor has a semiconductor layer having a channel region, a source region, a drain region, a low-concentration source region, and a low-concentration drain region, and a gate electrode overlapping the channel region in a planar view. The light-shielding film is disposed in a lattice shape surrounding the pixel electrode in a planar view, and overlaps with the transistor in a planar view. The light-shielding film is also used as a scanning line that supplies a gate potential to the gate electrode.

JP 2008-225034 A

It is known that the closer the light-shielding film is to the semiconductor layer of the transistor, the better the light-shielding properties. However, the light-shielding film that can function as a scanning line described in Patent Document 1 overlaps the entire area of the transistor in a planar view, so there is a risk of an increase in off-leak current if the light-shielding film approaches areas other than the channel region of the transistor. As a result, there is a risk of a decrease in display quality due to the occurrence of black spots, etc.

One aspect of the electro-optical device of the present invention comprises a substrate, a pixel electrode, a transistor arranged in a layer between the substrate and the pixel electrode, a first light-shielding film arranged in a layer between the substrate and the transistor, and a second light-shielding film arranged in a layer between the substrate and the transistor, wherein the first light-shielding film overlaps with a gate electrode of the transistor in a planar view of the substrate but is arranged so as not to overlap with a low-concentration drain region of the transistor, and the second light-shielding film overlaps with everything except the channel region of the transistor in the planar view and has a fixed potential applied to it.

One aspect of the electronic device of the present invention has the electro-optical device described above and a control unit that controls the operation of the electro-optical device.

1 is a plan view of an electro-optical device according to an embodiment. 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along line AA. 2 is an equivalent circuit diagram showing an electrical configuration of the element substrate of FIG. 1. FIG. 3 is a diagram showing a part of the element substrate of FIG. 2 . FIG. 3 is a diagram showing a part of the element substrate of FIG. 2 . FIG. 5 is a diagram showing a part of the element substrate shown in FIG. 4 . FIG. 5 is a diagram showing a part of the element substrate shown in FIG. 4 . 5 is a diagram showing a planar arrangement of a first light-shielding film, a second light-shielding film, and a semiconductor layer shown in FIG. 4. 5 is a cross-sectional view showing the contact portion shown in FIG. 4. This is a cross section taken along line BB in FIG. 5A to 5C are diagrams illustrating a flow of a method for manufacturing a part of an element substrate of an electro-optical device. 11A to 11C are cross-sectional views for explaining a recess forming step. 11A to 11C are cross-sectional views for explaining first and second light-shielding film forming steps. 11A to 11C are cross-sectional views for explaining first and second light-shielding film forming steps. 1A to 1C are cross-sectional views for explaining a transistor forming step. 11A to 11C are cross-sectional views for explaining a stopper portion forming step. FIG. 11 is a plan view for explaining a stopper portion forming step. 11 is a cross-sectional view for explaining a scanning line forming step. FIG. 11 is a cross-sectional view for explaining a scanning line forming step. FIG. FIG. 11 is a plan view for explaining a scanning line forming step. 11 is a cross-sectional view for explaining a scanning line forming step. FIG. FIG. 11 is a cross-sectional view for explaining a first constant potential line forming step. FIG. 11 is a cross-sectional view for explaining a first constant potential line forming step. FIG. 11 is a plan view for explaining a first constant potential line forming step. FIG. 11 is a cross-sectional view for explaining a first constant potential line forming step. 13 is a cross-sectional view showing a first light-shielding film and a second light-shielding film of a modified example. FIG. FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. FIG. 1 is a plan view showing a smartphone as an example of an electronic device. FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device.

Below, preferred embodiments of the present invention will be described with reference to the attached drawings. Note that the dimensions or scale of each part in the drawings may differ from the actual dimensions, and some parts are shown diagrammatically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these forms unless otherwise specified in the following description to the effect that the present invention is limited thereto.

1. Electro-optical device 1A. Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to a first embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 shown in FIG. 1 taken along line A-A. In FIG. 1, the opposing substrate 3 is omitted. In addition, for convenience of explanation, the following description will be given using the mutually orthogonal X-axis, Y-axis, and Z-axis as appropriate. In addition, one direction along the X-axis is denoted as the X1 direction, and the opposite direction to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the opposite direction to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the opposite direction to the Z1 direction is denoted as the Z2 direction. In addition, in the following description, viewing in the Z1 or Z2 direction is referred to as a "planar view," and viewing from a direction perpendicular to a cross section including the Z-axis is referred to as a "cross-sectional view."

The electro-optical device 100 shown in Figures 1 and 2 is a transmissive liquid crystal device of an active matrix driving system. As shown in Figure 2, the electro-optical device 100 has a light-transmitting element substrate 2, a light-transmitting opposing substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. Note that "light-transmitting" means transparency to visible light, and preferably means that the transmittance of visible light is 50% or more. The element substrate 2, liquid crystal layer 5, and opposing substrate 3 are arranged in this order in the Z1 direction. Note that the shape of the electro-optical device 100 shown in Figure 1 in a plan view is rectangular, but it may be, for example, circular.

As shown in FIG. 2, the element substrate 2 is a substrate having a plurality of TFTs (Thin Film Transistors) described below. The element substrate 2 has a first substrate 21, a laminate 22, a plurality of pixel electrodes 25, and a first alignment film 29. The first substrate 21 is an example of a "substrate." The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are arranged in this order in the Z1 direction. In addition, although not shown, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in a planar view.

The first substrate 21 is a flat plate having translucency and insulating properties. The first substrate 21 includes, for example, a glass substrate or a quartz substrate. The laminate 22 will be described later. Each pixel electrode 25 has translucency. Each pixel electrode 25 includes a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), and FTO (fluorine-doped tin oxide). The pixel electrode 25 applies an electric field to the liquid crystal layer 5. The first alignment film 29 has translucency and insulating properties. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. Examples of materials for the first alignment film 29 include silicon oxide and polyimide.

The opposing substrate 3 is a substrate disposed opposite the element substrate 2. The opposing substrate 3 has a second substrate 31, an insulating film 32, a common electrode 33, and a second alignment film 34. The second substrate 31, the insulating film 32, the common electrode 33, and the second alignment film 34 are arranged in this order in the Z2 direction. Although not shown, the opposing substrate 3 has a light-shielding partition surrounding the multiple pixel electrodes 25 in a planar view. "Light-shielding" means light-shielding properties against visible light, and preferably means that the transmittance of visible light is less than 50%, and more preferably 10% or less.

The second substrate 31 is a flat plate having translucency and insulating properties. The second substrate 31 includes, for example, a glass substrate or a quartz substrate. The insulating film 32 has translucency and insulating properties. The material of the insulating film 32 is, for example, an inorganic material such as silicon oxide. The common electrode 33 is an opposing electrode disposed with respect to the plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 includes, for example, a transparent conductive material such as ITO, IZO, and FTO. The common electrode 33 applies an electric field to the liquid crystal layer 5. The second alignment film 34 has translucency and insulating properties. The second alignment film 34 aligns the liquid crystal molecules of the liquid crystal layer 5. Examples of the material of the second alignment film 34 include silicon oxide or polyimide.

The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass. The sealing member 4 is fixed to each of the element substrate 2 and the opposing substrate 3.

The liquid crystal layer 5 is disposed within the region surrounded by the element substrate 2, the opposing substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

As shown in FIG. 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Some of the plurality of external terminals 13 are connected to wiring routed from the scanning line driving circuit 11 or the signal line driving circuit 12, although not shown. The plurality of external terminals 13 also include a terminal that is electrically connected to a common electrode 33 via wiring and conductive material, not shown.

The electro-optical device 100 has a display area A10 that displays an image, and a peripheral area A20 that is located outside the display area A10 in a planar view. A plurality of pixels P arranged in a matrix are provided in the display area A10. A plurality of pixel electrodes 25 are arranged in a one-to-one relationship for the plurality of pixels P. The aforementioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a planar view. A scanning line driving circuit 11 and a signal line driving circuit 12 are arranged in the peripheral area A20.

In this embodiment, the electro-optical device 100 is a transmissive type, and an image is displayed by modulating the light incident on the element substrate 2 while it is being emitted from the opposing substrate 3. Note that an image may also be displayed by modulating the light incident on the opposing substrate 3 while it is being emitted from the element substrate 2. The electro-optical device 100 may also be a reflective type. In this case, for example, the common electrode 33 is translucent, and the pixel electrode 25 is reflective. In the case of the reflective type, an image is displayed by modulating the light incident on the opposing substrate 3 while it is being reflected by the pixel electrode 25 and then emitted again from the opposing substrate 3.

The electro-optical device 100 is also applied to display devices that perform color display, such as personal computers and smartphones, which will be described later. When applied to such display devices, color filters are appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filters are omitted for the electro-optical device 100.

1B. Electrical Configuration of the Element Substrate 2 FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n first constant potential lines 243. The first constant potential lines 243 are an example of a "constant potential line". As will be described later in detail, the transistors 23, the scanning lines 241, the signal lines 242, and the first constant potential lines 243 are disposed in a layer between the first substrate 21 and the pixel electrodes 25. n and m are each an integer of 2 or more. The transistors 23 are disposed in correspondence with each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y2 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1 to n scanning lines 241 from the scanning line driving circuit 11.

Each of the m signal lines 242 shown in FIG. 3 extends in the Y2 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in FIG. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m signal lines 242 from the signal line drive circuit 12.

The n scanning lines 241 and m signal lines 242 shown in FIG. 3 are electrically insulated from each other and are arranged in a grid pattern in a plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to a pixel P. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

Each of the n first constant potential lines 243 extends in the X1 direction, and the n first constant potential lines 243 are arranged at equal intervals in the Y2 direction. The n first constant potential lines 243 are electrically insulated from the m signal lines 242 and the n scanning lines 241, and are arranged at intervals from these. A fixed potential that is the same potential as that of the opposing substrate is applied to each of the first constant potential lines 243. Each of the n first constant potential lines 243 is electrically connected to a corresponding plurality of capacitance elements 240. Each capacitance element 240 is a storage capacitance for storing the potential of the pixel electrode 25. The plurality of capacitance elements 240 are electrically connected to the plurality of pixel electrodes 25 in a one-to-one relationship. The plurality of capacitance elements 240 are electrically connected to the drains of the plurality of transistors 23 in a one-to-one relationship.

When the scanning signals G1, G2, ..., and Gn are successively activated and the n scanning lines 241 are successively selected, the transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a size corresponding to the gradation to be displayed are taken into the pixel P corresponding to the selected scanning line 241 via the m signal lines 242 and applied to the pixel electrode 25. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. The applied voltage is also held by the capacitance element 240. This change in the orientation of the liquid crystal molecules modulates the light, making it possible to display gradations.

1C. Configuration of the Element Substrate 2 Fig. 4 and Fig. 5 are diagrams each showing a part of the element substrate 2 shown in Fig. 2. Note that Fig. 4 and Fig. 5 are diagrams focusing on one pixel P.

As shown in Figures 4 and 5, the first substrate 21, which serves as a "substrate," has a recess 210. A first light-shielding film 61 and a second light-shielding film 62 are disposed in the recess 210. The recess 210, the first light-shielding film 61, and the second light-shielding film 62 will be described in detail later.

The laminate 22 is disposed on the first substrate 21. The laminate 22 is transparent and insulating. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, 229, and 220 that are stacked in order from the first substrate 21 toward the plurality of pixel electrodes 25. The material of each layer of the laminate 22 is an inorganic material such as silicon oxynitride and silicon oxide.

A plurality of transistors 23 and wiring are arranged between the layers of the laminate 22. Specifically, as shown in FIG. 4, the laminate 22 includes the transistor 23, the scanning line 241, the signal line 242, the first constant potential line 243, the second constant potential line 244, the capacitance element 240, the drain relay electrode 247, and the source relay electrode 248. As shown in FIG. 5, the laminate 22 includes the relay electrode 249. The transistor 23 includes a semiconductor layer 231 having an LDD (Lightly Doped Drain) structure, a gate electrode 232, and a gate insulating film 233. The capacitance element 240 includes a first capacitance 245 and a second capacitance 246. As shown in FIG. 4, a stopper portion 282 that functions as an etching stopper during the manufacture of the element substrate 2 is arranged between the layers of the laminate 22.

Specifically, the semiconductor layer 231 of the transistor 23 is disposed between the insulating layer 221 and the insulating layer 222. The gate electrode 232 of the transistor 23 is disposed between the insulating layer 222 and the insulating layer 223. The stopper portion 282 is disposed between the insulating layer 223 and the insulating layer 224. The scanning line 241, the drain relay electrode 247, and the source relay electrode 248 are disposed between the insulating layer 224 and the insulating layer 225. The first constant potential line 243 is disposed between the insulating layer 225 and the insulating layer 226. The first capacitance 245 of the capacitance element 240 is disposed between the insulating layer 226 and the insulating layer 227. The second capacitance 246 of the capacitance element 240 is disposed between the insulating layer 227 and the insulating layer 228. The signal line 242 and the relay electrode 249 are disposed between the insulating layer 228 and the insulating layer 229. A second constant potential line 244 is disposed between the insulating layer 229 and the insulating layer 220.

The semiconductor layer 231 of the transistor 23 has a channel region 231a, a drain region 231b, a source region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231a is located between the drain region 231b and the source region 231c. The low-concentration drain region 231d is located between the channel region 231a and the drain region 231b. The low-concentration source region 231e is located between the channel region 231a and the source region 231c. The semiconductor layer 231 is formed by depositing, for example, polysilicon, and the region other than the channel region 231a is doped with an impurity that increases conductivity. The impurity concentration in the low-concentration drain region 231d and the low-concentration source region 231e is lower than the impurity concentration in the drain region 231b and the source region 231c. The low-concentration source region 231e may be omitted.

Although a plan view is omitted, the gate electrode 232 overlaps the channel region 231a of the semiconductor layer 231 in a plan view. The gate electrode 232 is formed, for example, by doping polysilicon with impurities that increase the conductivity. The gate electrode 232 may be formed using a material having conductivity such as metal, metal silicide, and metal compound. In addition, a gate insulating film 233 is interposed between the gate electrode 232 and the channel region 231a. The gate insulating film 233 is composed of silicon oxide formed, for example, by thermal oxidation or a CVD (chemical vapor deposition) method.

The first capacitance 245 has a pair of electrodes 2451 and 2452, and a dielectric layer 2253 disposed between the electrodes 2451 and 2452. The second capacitance 246 has a pair of electrodes 2461 and 2462, and a dielectric layer 2263 disposed between the electrodes 2461 and 2462.

In addition, conductive parts 271, 272, 273, 274, 275, 276, 277, 278, 279, and 280 are arranged in the laminate 22 as contacts that electrically connect two wirings or electrodes. In addition, a contact part 281 is arranged in the laminate 22. Each of the conductive parts 271 to 280 and the contact part 281 is a through electrode having conductivity, and is composed of, for example, a substantially columnar plug.

4 and 5, the conductive portion 271 penetrates the insulating layers 223 and 224, and connects the gate electrode 232, the scanning line 241, and the first light-shielding film 61. As shown in FIG. 4, the conductive portion 272 penetrates the insulating layers 222 to 224, and connects the drain region 231b of the semiconductor layer 231 and the drain relay electrode 247. Note that the conductive portion 272 and the drain relay electrode 247 are formed integrally, for example. The conductive portion 273 penetrates the insulating layers 222 to 224, and connects the source region 231c of the semiconductor layer 231 and the source relay electrode 248. Note that the conductive portion 273 and the source relay electrode 248 are formed integrally, for example.
As will be described later with reference to FIG. 9, the contact portion 281 penetrates the insulating layers 221 to 225 and connects the first constant potential line 243 and the second light-shielding film 62 .

4, the conductive portion 274 penetrates the insulating layers 225-227 and connects the drain relay electrode 247 and the electrode 2461 of the second capacitance 246. The conductive portion 275 penetrates the insulating layers 225-228 and connects the source relay electrode 248 and the signal line 242. The conductive portion 276 penetrates the insulating layer 226 and connects the first constant potential line 243 and the electrode 2451 of the first capacitance 245. The conductive portion 277 penetrates the insulating layer 227 and connects the electrode 2452 of the first capacitance 245 and the electrode 2461 of the second capacitance 246. As shown in FIG. 5, the conductive portion 278 penetrates the insulating layers 226 and 227 and connects the first constant potential line 243 and the electrode 2462 of the second capacitance 246. The conductive portion 279 penetrates the insulating layers 227 and 228, and connects the electrode 2452 of the first capacitor 245 to the relay electrode 249. The conductive portion 280 penetrates the insulating layers 229 and 220, and connects the relay electrode 249 to the pixel electrode 25.

Materials for the wiring such as the scanning line 241 arranged in the laminate 22 include, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), metal nitrides, and metal oxides. Specifically, for example, the wiring includes an aluminum film and a titanium nitride film. By including an aluminum film, it is possible to achieve lower resistance compared to a case where the wiring is composed only of a titanium nitride film. Also, materials for the conductive portions 271 to 280 and the contact portion 281 include, for example, metals such as tungsten, cobalt (Co), and copper (Cu), metal nitrides such as titanium nitride, and metal oxides such as tungsten silicide.

Note that the arrangement of wiring, etc. shown in Figures 4 and 5 is merely an example, and the arrangement of wiring, etc. is not limited to the example shown in Figures 4 and 5.

1D. Configuration of the first light-shielding film 61, the second light-shielding film 62 and the vicinity thereof FIGS. 6 and 7 are diagrams showing a part of the element substrate 2 shown in FIG. 4. FIG. 8 is a diagram showing the planar arrangement of the first light-shielding film 61, the second light-shielding film 62 and the semiconductor layer 231 shown in FIG. 4. FIG. 9 is a cross-sectional view showing the contact portion 281 shown in FIG. 4. FIG. 10 is a cross-section taken along line B-B in FIG. 6. Note that FIG. 7 corresponds to the cross-section taken along line C-C in FIG. 10. FIG. 9 corresponds to the cross-section taken along line D-D in FIG. 10.

As shown in Figures 6 and 7, the first light-shielding film 61 and the second light-shielding film 62 are each disposed between the first substrate 21 and the transistor 23. The first light-shielding film 61 and the second light-shielding film 62 are disposed in the recess 210 of the first substrate 21. In addition, the first adhesive layer 610, the second adhesive layer 620, and the insulating layer 63 are disposed in the recess 210.

The recess 210 has a first portion 211 that is a first depth, and a second portion 212 that is a second depth that is shallower than the first depth. From another perspective, the recess 210 has a first recess and a second recess formed on the bottom surface of the first recess. Thus, the bottom surface of the recess 210 has a step.

As shown in FIG. 8, the first portion 211 is disposed inside the second portion 212 in a planar view. The first portion 211 overlaps the gate electrode 232 and the channel region 231a of the semiconductor layer 231 in a planar view. In particular, in this embodiment, the first portion 211 does not overlap with any portion of the semiconductor layer 231 other than the channel region 231a in a planar view.

The second portion 212 overlaps with the semiconductor layer 231 in a planar view. In addition, the area of the second portion 212 in a planar view is larger than the area of the semiconductor layer 231 in a planar view. The second portion 212 also has a wide portion 212a that is wider in the X1 direction, and a narrow portion 212b that is narrower in the X1 direction than the wide portion 212a. The wide portion 212a overlaps with the channel region 231a and the low-concentration drain region 231d of the semiconductor layer 231 in a planar view. The narrow portion 212b overlaps with the low-concentration source region 231e, the drain region 231b, and the source region 231c in a planar view.

As shown in Figures 6 and 7, the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610 and the first light-shielding film 61 are stacked in this order from the bottom of the recess 210. The first light-shielding film 61, the first adhesive layer 610 and the insulating layer 63 are disposed in the first portion 211 of the recess 210. The second light-shielding film 62 and the second adhesive layer 620 are disposed in the first portion 211 and the second portion 212 of the recess 210.

The first light-shielding film 61 and the second light-shielding film 62 have light-shielding properties and electrical conductivity. The first light-shielding film 61 and the second light-shielding film 62 are provided to block light from entering the transistor 23. The insulating layer 63 has insulating properties. The insulating layer 63 is disposed between the first light-shielding film 61 and the second light-shielding film 62 to insulate them. The first adhesive layer 610 is disposed between the insulating layer 63 and the first light-shielding film 61 to bond the insulating layer 63 and the first light-shielding film 61. The second adhesive layer 620 is disposed between the first substrate 21 and the second light-shielding film 62 to bond the first substrate 21 and the second light-shielding film 62.

The second adhesive layer 620 and the second light-shielding film 62 are disposed along the bottom surface of the recess 210, which has a step. Therefore, the second adhesive layer 620 and the second light-shielding film 62 have a step that follows the bottom surface of the recess 210. In addition, the top surfaces of the first substrate 21, the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the first light-shielding film 61 form a continuous surface without steps. In other words, the top surfaces of the first substrate 21, the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the first light-shielding film 61 form an approximately flat surface.

As shown in FIG. 8, the first light-shielding film 61 overlaps the gate electrode 232 and the channel region 231a of the semiconductor layer 231 in a planar view. In particular, in this embodiment, the first light-shielding film 61 does not overlap any portion of the semiconductor layer 231 other than the channel region 231a in a planar view.

The second light-shielding film 62 is formed along the semiconductor layer 231 in a planar view, and overlaps with the semiconductor layer 231 in a planar view. In addition, the area of the second light-shielding film 62 in a planar view is larger than the area of the semiconductor layer 231 in a planar view. Therefore, the second light-shielding film 62 overlaps both the channel region 231a and the region below the channel region 231a of the semiconductor layer 231 in a planar view. The second light-shielding film 62 also overlaps with the gate electrode 232 in a planar view. As shown in FIG. 10, the semiconductor layer 231 and the scanning line 241 intersect in a planar view, so the second light-shielding film 62 intersects with the scanning line 241 in a planar view.

The material of each of the first light-shielding film 61 and the second light-shielding film 62 is, for example, a metal material containing tungsten, titanium, chromium, etc. The material of each of the first adhesive layer 610 and the second adhesive layer 620 is, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and a metal oxide such as a metal silicide such as tungsten silicide (WSi). The material of the insulating layer 63 is, for example, an inorganic material containing silicon such as silicon oxide and silicon oxynitride. Note that each of the first light-shielding film 61, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the second adhesive layer 620 may be a single layer or multiple layers.

7, the first light-shielding film 61 is connected to the scanning line 241 via the conductive portion 271. The conductive portion 271 contacts the first light-shielding film 61, the scanning line 241, and the gate electrode 232, and electrically connects them. Therefore, the first light-shielding film 61 functions as a back gate in addition to preventing light from entering the transistor 23. The conductive portion 271 is arranged to sandwich the transistor 23 in a cross-sectional view seen in the Y1 direction. Therefore, the conductive portion 271 is arranged to sandwich the gate electrode 232 and the semiconductor layer 231 in a cross-sectional view seen in the Y1 direction. In addition, as shown in FIG. 10, the conductive portion 271 overlaps with the gate electrode 232 and the channel region 231a in a plan view. Therefore, the conductive portion 271 can particularly suppress the incidence of light into the channel region 231a.

9, the second light-shielding film 62 is connected to the first constant potential line 243 via the contact portion 281. Since a fixed potential is applied to the first constant potential line 243, a fixed potential is applied to the second light-shielding film 62 via the contact portion 281. The contact portion 281 contacts each of the second light-shielding film 62, the stopper portion 282, and the second constant potential line 244. The contact portion 281 is disposed so as to sandwich the stopper portion 282 and the semiconductor layer 231 in a cross-sectional view seen in the Y1 direction. As shown in FIG. 10, the contact portion 281 overlaps with the low-concentration drain region 231d in a plan view. Therefore, the contact portion 281 can particularly suppress the incidence of light into the low-concentration drain region 231d.

The first light-shielding film 61 described above overlaps the gate electrode 232 and the channel region 231a of the semiconductor layer 231 in a planar view of the first substrate 21. On the other hand, as described above, the second light-shielding film 62 overlaps with the region other than the channel region 231a in a planar view, and a fixed potential is applied to the second light-shielding film 62. Therefore, even if the second light-shielding film 62 approaches the region other than the channel region 231a, the risk of an increase in off-leak current due to the influence of the potential of the second light-shielding film 62 can be suppressed. Therefore, the first light-shielding film 61 and the second light-shielding film 62 can be brought closer to the transistor 23 while suppressing an increase in the off-leak current between the source and drain when the transistor 23 is in an off state. In particular, by the second light-shielding film 62 overlapping with the low concentration drain region 231d in a planar view, it is possible to improve the light-shielding property of the transistor 23 while suppressing an increase in the off-leak current. Therefore, it is possible to improve the light-shielding property without the trade-off between the suppression of an increase in the off-leak current. This makes it possible to prevent degradation of display quality due to the occurrence of black spots, burn-in, etc. In addition, by having the transistor 23 have an LDD structure, it is possible to prevent an increase in off-leak current compared to a case where the transistor does not have an LDD structure.

As described above, the first light-shielding film 61 is electrically connected to the gate electrode 232. Therefore, a gate potential is applied to the first light-shielding film 61. Therefore, potentials different from each other are applied to the first light-shielding film 61 and the second light-shielding film 62. By electrically connecting the first light-shielding film 61 to the gate electrode 232, it is possible to suppress a decrease in the on-current.

In addition, since the first light-shielding film 61 overlaps the gate electrode 232, it does not overlap with any region other than the channel region 231a of the semiconductor layer 231. As in this embodiment, it is preferable that the first light-shielding film 61 does not overlap with any region other than the channel region 231a, particularly the low-concentration drain region 231d, in a planar view. This makes it possible to particularly effectively suppress the risk of an increase in off-leak current due to the influence of the first light-shielding film 61, even if the first light-shielding film 61 is brought closer to the channel region 231a.

6, by using the first light-shielding film 61 and the second light-shielding film 62, the distance D1 between the semiconductor layer 231 and the first light-shielding film 61 and the distance D2 between the semiconductor layer 231 and the second light-shielding film 62 can be made shorter than in the past. Specifically, for example, the distance D1 between the semiconductor layer 231 and the first light-shielding film 61 and the distance D2 between the semiconductor layer 231 and the second light-shielding film 62 are preferably 500 Å or more and 3000 Å or less. By being in such a range, it is possible to sufficiently improve the light-shielding properties while suppressing the occurrence of film formation defects of the insulating layer 221.

As described above, the contact portion 281 overlaps with the low-concentration drain region 231d in a planar view. Furthermore, as shown in FIG. 9, the contact portion 281 is arranged to sandwich the low-concentration drain region 231d. Therefore, the low-concentration drain region 231d is almost surrounded by the contact portion 281 and the second light-shielding film 62. Therefore, the light-shielding property against light incident on the low-concentration drain region 231d can be particularly improved compared to a case where the contact portion 281 is not arranged to sandwich the low-concentration drain region 231d. Note that the contact portion 281 does not have to be arranged to sandwich the low-concentration drain region 231d.

The second light-shielding film 62 overlaps the low-concentration drain region 231d, the source region 231c, and the drain region 231b in a planar view. In this embodiment, the second light-shielding film 62 overlaps the entire region of the semiconductor layer 231 below the channel region 231a in a planar view. Therefore, the light-shielding property for the semiconductor layer 321 can be improved compared to when the second light-shielding film 62 does not overlap these regions. In particular, in this embodiment, the entire semiconductor layer 231 and the second light-shielding film 62 overlap. Therefore, the light-shielding property can be improved to the maximum. Note that the second light-shielding film 62 may overlap at least a part of the semiconductor layer 231 below the channel region 231a in a planar view.

As described above, the second light-shielding film 62 is disposed in the first portion 211 and the second portion 212 of the recess 210. On the other hand, the first light-shielding film 61 is disposed in the first portion 211 and is located between the second light-shielding film 62 and the gate electrode 232. By disposing the first light-shielding film 61 and the second light-shielding film 62 in the recess 210, the first light-shielding film 61 and the second light-shielding film 62 are prevented from peeling off from the first substrate 21, compared to when they are disposed on a flat surface, for example. Thus, the decrease in light-shielding property due to peeling is suppressed. In addition, by interposing the first light-shielding film 61 between the gate electrode 232 and the second light-shielding film 62, a configuration can be easily realized that can suppress an increase in off-leakage current while ensuring the light-shielding property of the first light-shielding film 61 and the second light-shielding film 62.

Furthermore, an insulating layer 63 is disposed between the first light-shielding film 61 and the second light-shielding film 62. This allows the first light-shielding film 61 and the second light-shielding film 62 to be electrically insulated from each other. Therefore, when the first light-shielding film 61 and the second light-shielding film 62 are disposed so as to overlap each other in a planar view, the first light-shielding film 61 and the second light-shielding film 62 can be brought closer to the transistor 23 without compromising the suppression of an increase in the off-leak current and the suppression of a decrease in the on-current.

As described above, the first adhesive layer 610 is disposed between the insulating layer 63 and the first light-shielding film 61 to bond them together. By providing the first adhesive layer 610, the adhesion between the insulating layer 63 and the first light-shielding film 61 can be increased compared to when the first adhesive layer 610 is not provided. Similarly, the second adhesive layer 620 is disposed between the first substrate 21 and the second light-shielding film 62 to bond them together. By providing the second adhesive layer 620, the adhesion between the first substrate 21 and the second light-shielding film 62 can be increased compared to when the second adhesive layer 620 is not provided. Therefore, peeling of the first light-shielding film 61 and the second light-shielding film 62 can be suppressed. Note that the first adhesive layer 610 and the second adhesive layer 620 may each be omitted.

In addition, the electro-optical device 100 having the first light-shielding film 61 and the second light-shielding film 62 can effectively suppress the incidence of light from the first substrate 21 toward the semiconductor layer 231 by the first light-shielding film 61 and the second light-shielding film 62. Therefore, the light-shielding effect can be particularly exhibited in the electro-optical device 100 in which light is incident from the first substrate 21 toward the pixel electrode 25.

11 is a diagram showing the flow of a manufacturing method for a part of the element substrate 2 of the electro-optical device 100. The manufacturing method for the element substrate 2 includes a recess forming step S11, a first and second light-shielding film forming step S12, a transistor forming step S13, a stopper portion forming step S14, a scanning line forming step S15, and a first constant potential line forming step S16.

Figure 12 is a cross-sectional view for explaining the recess formation process S11. As shown in Figure 12, a recess 210 having a first portion 211 and a second portion 212 is formed by etching a first substrate 21 made of, for example, a glass plate or a quartz plate. Specifically, after forming a first recess, the bottom surface of the first recess is further etched to form a second recess. In other words, the recess 210 is formed by a modified dual damascene method.

13 and 14 are cross-sectional views for explaining the first and second light-shielding film formation steps S12. As shown in FIG. 13, the second adhesive layer 620x, the second light-shielding film 62x, the insulating layer 63x, the first adhesive layer 610x, and the first light-shielding film 61x are laminated in this order in the recess 210. Each layer is formed by a deposition method such as a CVD method or a PVD (physical vapor deposition) method. Next, the second adhesive layer 620x, the second light-shielding film 62x, the insulating layer 63x, the first adhesive layer 610x, and the first light-shielding film 61x are subjected to a polishing process such as a CMP method, so that the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the first light-shielding film 61 are formed as shown in FIG. 14. The polishing process flattens the upper surfaces of the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the first light-shielding film 61.

By using the dual damascene method, after forming the recess 210, the second adhesive layer 620x, the second light-shielding film 62x, the insulating layer 63x, the first adhesive layer 610x, and the first light-shielding film 61x are laminated in this order, so that the second adhesive layer 620, the second light-shielding film 62, the insulating layer 63, the first adhesive layer 610, and the first light-shielding film 61 can be formed simply and reliably. Therefore, the number of steps can be significantly reduced compared to, for example, forming the first light-shielding film 61 and the second light-shielding film 62 in different recesses. This can increase productivity.

Figure 15 is a cross-sectional view for explaining the transistor formation process S13. As shown in Figure 15, first, an insulating layer 221 is formed on the first light-shielding film 61 and the second light-shielding film 62 by, for example, thermal oxidation or CVD. The insulating layer 221 is appropriately planarized by CMP. Due to the presence of the first light-shielding film 61 and the second light-shielding film 62, the insulating layer 221 is formed to a thickness in the range of, for example, 500 Å to 3000 Å.

Next, a semiconductor layer 231, a gate insulating film 233, and a gate electrode 232 are formed on the insulating layer 221. As described above, the semiconductor layer 231 is formed, for example, by depositing polysilicon, and the region other than the channel region 231a is doped with impurities that increase conductivity. The gate insulating film 233 is formed, for example, by thermal oxidation or a CVD method. The gate electrode 232 is formed, for example, by doping polysilicon with impurities that increase conductivity.

Figure 16 is a cross-sectional view for explaining the stopper portion forming process S14. Figure 17 is a plan view for explaining the stopper portion forming process S14.

As shown in FIG. 16, first, an insulating layer 223 is formed on the gate electrode 232 by, for example, a CVD method. The insulating layer 223 is then planarized by a CMP method as appropriate. Next, a stopper portion 282 is formed on the insulating layer 223. The stopper portion 282 is formed using, for example, a metal material such as metals such as tungsten, titanium, and aluminum, metal nitrides, and metal silicides. The stopper portion 282 is formed, for example, by patterning a metal material film formed by a CVD method or a PVD method, by etching. The stopper portion 282 may be made of silicon nitride, etc.

As shown in FIG. 17, the stopper portion 282 is formed to overlap the low concentration drain region 231d of the semiconductor layer 231. The stopper portion 282 is used in the formation of the contact hole H4 in which the contact portion 281 formed in the first constant potential line formation process S16 is disposed.

Figures 18, 19, and 21 are cross-sectional views for explaining the scanning line formation process S15. Figure 20 is a plan view for explaining the scanning line formation process S15.

An insulating layer 224 is formed on the stopper portion 282 by, for example, a CVD method. The insulating layer 224 is then planarized by a CMP method as appropriate. Next, as shown in FIGS. 18 and 19, three contact holes H1, H2, and H3 are formed in the insulating layer 224. The contact holes H1, H2, and H3 are formed by the same process, for example, by etching using a fluorine-based etching agent. As shown in FIG. 20, the contact hole H1 is formed so as to overlap the gate electrode 232. The contact hole H2 is formed so as to overlap the drain region 231b. The contact hole H3 is formed so as to overlap the source region 231c.

18 and 19, when the contact hole H1 is formed, the gate electrode 232 and the first light-shielding film 61 function as an etching stopper. When the contact hole H1 is formed, each part of the gate electrode 232 and the first light-shielding film 61 is exposed. In addition, the contact hole H1 has two depths. Specifically, as shown in FIG. 19, the contact hole H1 has a depth from the upper surface of the insulating layer 224 to the gate electrode 232 and a depth from the upper surface of the insulating layer 224 to the first light-shielding film 61. In addition, as shown in FIG. 18, when the contact holes H2 and H3 are formed, the semiconductor layer 231 functions as an etching stopper. Therefore, when the contact holes H2 and H3 are formed, each part of the drain region 231b and the source region 231c of the semiconductor layer 231 is exposed.

Next, a conductive film is formed on the insulating layer 224 to fill the contact holes H1, H2, and H3, and then the conductive film is patterned by etching. As a result, as shown in FIG. 21, a conductive portion 271 that fills the contact hole H1, a conductive portion 272 that fills the contact hole H2, and a conductive portion 273 that fills the contact hole H3 are formed. In addition, the conductive portion 271 and the scanning line 241 are integrally formed, the conductive portion 272 and the drain relay electrode 247 are integrally formed, and the conductive portion 273 and the source relay electrode 248 are integrally formed.

Figures 22, 23, and 25 are cross-sectional views for explaining the first constant potential line forming process S16. Figure 24 is a plan view for explaining the first constant potential line forming process S16.

An insulating layer 225 is formed on the scanning line 241, for example, by a CVD method. The insulating layer 225 is then planarized by a CMP method as appropriate. Then, as shown in FIGS. 22 and 23, a contact hole H4 is formed in the insulating layer 225. The contact hole H4 is formed, for example, by etching using a fluorine-based etching agent. Furthermore, as shown in FIG. 24, the contact hole H4 is formed so as to overlap the stopper portion 282.

22 and 23, when the contact hole H4 is formed, the stopper portion 282 and the second light-shielding film 62 function as an etching stopper. When the contact hole H4 is formed, a portion of each of the stopper portion 282 and the second light-shielding film 62 is exposed. Also, as shown in FIG. 23, the contact hole H4 has two depths. Specifically, the contact hole H4 has a depth from the upper surface of the insulating layer 225 to the stopper portion 282, and a depth from the upper surface of the insulating layer 225 to the second light-shielding film 62.

Next, a conductive film is formed on the insulating layer 225 to fill the contact hole H4, and then the conductive film is patterned by etching. As a result, as shown in FIG. 25, a contact portion 281 that fills the contact hole H4 is formed.

In this manner, layers up to the first constant potential line 243 of the element substrate 2 are formed. Other components of the element substrate 2 are formed, for example, by using a known method.
2. Modifications The above-described embodiment may be modified in various ways. Specific modifications that may be applied to the above-described embodiment are illustrated below. Two or more aspects selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

In the above embodiment, the first substrate 21 has a recess 210, but the recess 210 may not be present. In that case, the first light-shielding film 61 and the second light-shielding film 62 may be disposed on the flat upper surface of the first substrate 21.

In the above embodiment, the first light-shielding film 61 overlaps the second light-shielding film 62 in a planar view, but they do not have to overlap.

26 is a cross-sectional view showing the first light-shielding film 61A and the second light-shielding film 62B of the modified example. The first light-shielding film 61A shown in FIG. 26 is disposed in the recess 215 of the first substrate 21. On the other hand, the second light-shielding film 62B is disposed in the recess 216 of the first substrate 21. Therefore, the first light-shielding film 61A does not overlap the second light-shielding film 62A in a planar view. However, as in the above-mentioned embodiment, by forming one recess 210 having a step and forming the first light-shielding film 61 and the second light-shielding film 62 in the recess 210, the number of manufacturing steps can be significantly reduced compared to the case where two recesses 215 and 216 are formed and the first light-shielding film 61A and the second light-shielding film 62A are formed. In addition, the first light-shielding film 61A and the second light-shielding film 62A can be disposed under the semiconductor layer 231 without any gaps when viewed from the first substrate 21, thereby improving the light-shielding performance of the transistor 23.

In the above embodiment, the semiconductor layer 231 intersects with the scanning line 241 in a planar view, but may be arranged along the scanning line 241 in a planar view. Therefore, in the above embodiment, the semiconductor layer 231 extends along the Y2 direction, but may be arranged along the X1 direction in which the scanning line 241 extends. Also, in the above embodiment, the second light-shielding film 62 intersects with the scanning line 241 in a planar view, but may be arranged along the scanning line 241 in a planar view. Therefore, in the above embodiment, the second light-shielding film 62 extends along the Y2 direction, but may be arranged along the X1 direction in which the scanning line 241 extends.

In the above embodiment, an active matrix electro-optical device 100 is exemplified, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix method.

The driving method of the "electro-optical device" is not limited to the vertical electric field method, and may be a horizontal electric field method. In the first embodiment, the pixel electrodes 25 are provided on the element substrate 2, and the common electrode 33 is provided on the counter substrate 3, but an electrode for applying an electric field to the liquid crystal layer 5 may be provided on only one of the element substrate 2 or the counter substrate 3. Note that, for example, an IPS (In Plane Switching) mode is an example of the horizontal electric field method. Also, examples of the vertical electric field method include a TN (Twisted Nematic) mode, a VA (Vertical Alignment), a PVA mode, and an OCB (Optically Compensated Bend) mode.

3. Electronic Devices The electro-optical device 100 can be used in various electronic devices.

Figure 27 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

Figure 28 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

Figure 29 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. The electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. In other words, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is a light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to the display image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

The above electronic devices include the electro-optical device 100 described above and the control unit 2003, 3002, or 4005. By including the electro-optical device 100, which has excellent light blocking properties and suppresses an increase in off-leak current, it is possible to improve the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000.

The electronic devices to which the electro-optical device of the present invention can be applied are not limited to the devices exemplified above, and include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

The present invention has been described above based on a preferred embodiment, but the present invention is not limited to the above-mentioned embodiment. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-mentioned embodiment, and any configuration can be added.

In the above description, a liquid crystal device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. In addition, the present invention can be applied to a display panel using light-emitting elements such as organic electroluminescence (EL), inorganic electroluminescence, or light-emitting polymers, in the same manner as in the above-mentioned embodiment. In addition, the present invention can be applied to an electrophoretic display panel using microcapsules containing a colored liquid and white particles dispersed in the liquid, in the same manner as in the above-mentioned embodiment. In addition, the present invention can be applied to a display panel (DMD (Digital Mirror Device)) using a large number of movable micromirrors.

2...element substrate, 3...opposing substrate, 4...sealing member, 5...liquid crystal layer, 11...scanning line driving circuit, 12...signal line driving circuit, 13...external terminal, 21...first substrate, 22...laminated body, 23...transistor, 25...pixel electrode, 29...first alignment film, 31...second substrate, 32...insulating film, 33...common electrode, 34...second alignment film, 61...first light-shielding film, 62...second light-shielding film, 63...insulating layer, 100... Electro-optical device, 210... recess, 211... first portion, 212... second portion, 212a... wide portion, 212b... narrow portion, 220 to 229... insulating layer, 231... semiconductor layer, 231a... channel region, 231b... drain region, 231c... source region, 231d... low-concentration drain region, 231e... low-concentration source region, 232... gate electrode, 233... gate insulating film, 240... capacitance element Electrode, 241...scanning line, 242...signal line, 243...first constant potential line, 244...second constant potential line, 245...first capacitance, 246...second capacitance, 247...drain relay electrode, 248...source relay electrode, 249...relay electrode, 271-180...conductive portion, 281...contact portion, 282...stopper portion, 610...first adhesive layer, 610x...first adhesive layer, 620...second adhesive layer, 620x... Second adhesive layer, 2253...dielectric layer, 2263...dielectric layer, 2451...electrode, 2452...electrode, 2461...electrode, 2462...electrode, A10...display area, A20...peripheral area, D1...distance, D2...distance, H1...contact hole, H2...contact hole, H3...contact hole, H4...contact hole, P...pixel, b...blue component, g...green component, r...red component.

Claims (10)

A substrate;
A pixel electrode;
a transistor disposed in a layer between the substrate and the pixel electrode;
a first light-shielding film disposed in a layer between the substrate and the transistor;
a second light-shielding film disposed in a layer between the substrate and the transistor;
the first light-shielding film is disposed so as to overlap a gate electrode of the transistor in a plan view of the substrate, but not to overlap a lightly doped drain region of the transistor;
The electro-optical device, wherein the second light-shielding film overlaps with the transistor other than its channel region in the plan view, and a fixed potential is applied to the second light-shielding film. The electro-optical device according to claim 1, wherein the first light-shielding film is electrically connected to the gate electrode. The electro-optical device according to claim 1 , wherein the second light-shielding film overlaps a source region and a drain region of the transistor. The substrate has a recess,
the recess has a first portion having a first depth and a second portion having a second depth that is shallower than the first depth;
the second light-shielding film is disposed in the first portion and the second portion,
The electro-optical device according to claim 1 , wherein the first light-shielding film is disposed in the first portion and is located between the second light-shielding film and the gate electrode. The electro-optical device according to claim 4 , further comprising an insulating layer disposed between the first light-shielding film and the second light-shielding film. a first adhesive layer disposed between the insulating layer and the first light-shielding film and adhering the insulating layer and the first light-shielding film;
The electro-optical device according to claim 5 , further comprising a second adhesive layer disposed between the substrate and the second light-shielding film, the second adhesive layer bonding the substrate and the second light-shielding film. a distance between the semiconductor layer of the transistor and the first light-shielding film is 500 Å or more and 3000 Å or less;
7. The electro-optical device according to claim 1, wherein the distance between the semiconductor layer of the transistor and the second light-shielding film is 500 Å or more and 3000 Å or less. A substrate;
A pixel electrode;
a transistor disposed in a layer between the substrate and the pixel electrode;
a first light-shielding film disposed in a layer between the substrate and the transistor;
a second light-shielding film disposed in a layer between the substrate and the transistor and to which a fixed potential is applied;
a constant potential line to which the fixed potential is applied;
a contact portion electrically connecting the constant potential line and the second light-shielding film ,
the first light-shielding film overlaps with a gate electrode of the transistor in a plan view of the substrate,
the second light-shielding film overlaps an area other than a channel region of the transistor in the plan view,
The contact portion overlaps with the lightly doped drain region of the transistor in the plan view, and is disposed so as to sandwich the lightly doped drain region. The electro-optical device according to claim 1 , wherein light is incident from the substrate toward the pixel electrodes. The electro-optical device according to claim 1 ,
and a control unit for controlling an operation of the electro-optical device.

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