JP7510906B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device having an oscillator circuit.

Conventionally, microcomputers having an oscillator circuit such as a high-speed on-chip oscillator (HOCO) are known. A microcomputer having an oscillator circuit is disclosed, for example, in JP 2013-65190 A (Patent Document 1). An oscillator circuit such as a HOCO has a current mirror circuit. A current mirror circuit is a circuit that copies a current like a mirror, and is basically composed of two transistors.

JP 2013-65190 A

In an oscillator circuit like the one above, the oscillation characteristics fluctuate if there is variation in the characteristics of the two transistors that make up the current mirror circuit in the oscillator circuit.

Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

According to one embodiment, the oscillator circuit includes a first element and a second element having the same configuration. The overlap between the first element and the layout of the top conductive layer in a planar view and the overlap between the second element and the layout of the top conductive layer in a planar view are the same as or symmetrical to each other.

According to the embodiment, it is possible to suppress the variation in characteristics between a first element and a second element having the same configuration included in an oscillator circuit.

1 is a plan view showing a configuration of a semiconductor device according to an embodiment in a chip state; FIG. 2 is a circuit diagram illustrating an example of an oscillator circuit. 2 is a plan view showing a region in which transistors constituting a current mirror circuit in an oscillator circuit are formed. FIG. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 4 is a schematic cross-sectional view taken along line VV in FIG. 3. 4 is a plan view showing an example of overlap between a transistor formation region and a top conductive layer in FIG. 3 in a plan view. 7A is a schematic cross-sectional view taken along line VIIA-VIIA in FIG. 6, and FIG. 7B is a schematic cross-sectional view taken along line VIIB-VIIB in FIG. 11A and 11B are diagrams for explaining that stress acting on the lower layer differs when the uppermost conductive layer is arranged non-uniformly. 4 is a plan view showing a first modification of the overlap between the transistor formation region and the uppermost conductive layer in FIG. 3 in a plan view. FIG. 4 is a plan view showing a second modification of the overlap between the transistor formation region and the uppermost conductive layer in FIG. 3 in a plan view. FIG. 4 is a plan view showing a third modification of the overlap between the transistor formation region and the uppermost conductive layer in FIG. 3 in a plan view. FIG. 7 is a plan view showing a fourth modified example of an overlap between a transistor formation region and an uppermost conductive layer in a plan view in FIG. 3 . 5 is a plan view showing a fifth modified example of an overlap between a transistor formation region and an uppermost conductive layer in FIG. 3 in a plan view. FIG. 7 is a plan view showing a sixth modified example of an overlap between the transistor formation region and the uppermost conductive layer in FIG. 3 in a plan view. FIG. 7 is a plan view showing a seventh modification of the overlap between the transistor formation region and the uppermost conductive layer in FIG. 3 in a plan view. FIG. 11 is a cross-sectional view showing a configuration in which an overlap between a first transistor and an uppermost conductive layer in a plan view and an overlap between a second transistor and an uppermost conductive layer in a plan view are symmetrical to each other. FIG. 10 is a plan view showing an example of overlap between a resistor and a top conductive layer in an oscillator circuit in a plan view. FIG. 18A is a schematic cross-sectional view taken along line XVIIIA-XVIIIA in FIG. 17, and FIG. 18B is a schematic cross-sectional view taken along line XVIIIB-XVIIIB in FIG.

The embodiments of the present disclosure will be described in detail below with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant explanations will not be repeated. In the drawings, configurations may be omitted or simplified for the sake of convenience. Furthermore, at least a portion of the embodiments and each modified example may be combined with each other in any desired manner.

<Overall Configuration of Semiconductor Device in Plan View>
An overall configuration of a semiconductor device in a plan view according to an embodiment will be described with reference to FIG.

As shown in FIG. 1, the semiconductor device SD in this embodiment is, for example, a microcomputer. The semiconductor device SD is, for example, in a chip state, and has a semiconductor substrate. On the surface of the semiconductor substrate, formation regions for flash memory circuits FM1, FM2, an SRAM circuit SM, a logic circuit LC, an oscillator circuit HC, and the like are arranged.

The oscillator circuit HC generates, for example, an operating clock. The oscillator circuit HC is, for example, a HOCO circuit, but may also be a LOCO (Low-speed On-Chip Oscillator) circuit, or may include both a HOCO circuit and a LOCO circuit.

The semiconductor device SD in this embodiment is not limited to a semiconductor chip, but may be in a wafer state before being divided into semiconductor chips, or may be in a package state in which the semiconductor chip is sealed with sealing resin. In this specification, a plan view means a viewpoint seen from a direction perpendicular to the surface of the semiconductor substrate SB (Figures 4 and 5).

<Circuit configuration of oscillator circuit HC>
Next, an example of the circuit configuration of the oscillator circuit HC used in FIG. 1 will be described with reference to FIG.

As shown in FIG. 2, the oscillator circuit HC has, for example, a constant current circuit CC and a reference voltage circuit SV. The constant current circuit CC has n-channel MOS (Metal Oxide Semiconductor) transistors (nMOS transistors) TR1, TR2, and TR7, p-channel MOS transistors (pMOS transistors) TR3, TR4, TR5, and TR6, and a resistor R1.

The nMOS transistors TR1 and TR2 form a current mirror circuit. The pMOS transistor TR6 and the nMOS transistor TR7 form the charge/discharge switching section CDS.

The reference voltage circuit SV has a capacitor CD, a comparator CP, resistors R2, R3, and R4, and an nMOS transistor TR8. The capacitor CD sets the oscillation period. The comparator CP controls the charging and discharging of the capacitor CD.

In the oscillator circuit HC, when the pMOS transistor TR6 is on and the nMOS transistor TR7 is off due to the output state of the comparator CP, the capacitor CD is charged by the constant current generated by the constant current circuit CC.

When the potential VA at point P1 exceeds the reference voltage VR at point P2, which is the input terminal of the comparator CP, due to the charging of the capacitor CD, the comparator CP inverts. The inverted output of the comparator CP turns on the nMOS transistor TR8. This causes the reference voltage VR to drop to VRA. At the same time, the nMOS transistor TR7 turns on and the pMOS transistor TR6 turns off. This starts the discharging of the capacitor CD.

When the potential VA at point P1 falls below the decreasing potential of the reference voltage VRA due to the discharge of the capacitor CD, the comparator CP inverts and returns to its initial state. By repeating this operation, an oscillation output is output to the output OUT of the oscillation circuit.

<Current mirror circuit configuration>
Next, the configuration of the current mirror circuit included in the oscillator circuit HC of Fig. 2 will be described with reference to Fig. 3 to Fig. 7. Note that, although the case where the current mirror circuit is configured with nMOS transistors TR1 and TR2 has been described in Fig. 2, the current mirror circuit may be configured with pMOS transistors TR1 and TR2. In the following, the case where the current mirror circuit is configured with a plurality of pMOS transistors TR1 and a plurality of pMOS transistors TR2 will be described.

As shown in FIG. 3, the current mirror circuit is composed of multiple pMOS transistors TR1 (first elements) and multiple pMOS transistors TR2 (second elements). The multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 have the same configuration. Here, having the same configuration means having the same configuration in terms of design, and includes differences due to manufacturing errors in actual manufacturing (errors in impurity concentration distribution due to ion implantation, errors in patterning shape due to photolithography and etching, etc.).

The multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 are elements that make up a current mirror circuit, and are elements that need to be formed with precision so that they have the same structure. In other words, the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 are elements that require relative precision.

The multiple pMOS transistors TR1 are formed in the active region AR1. The multiple pMOS transistors TR2 are formed in the active region AR2. The multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 have the same planar shape.

Active region AR1 and active region AR2 are isolated from each other on the surface of semiconductor substrate SB by element isolation region SR. Active region AR1 and active region AR2 have the same planar shape. Each of active regions AR1 and AR2 has, for example, a rectangular shape in plan view.

The formation region FR1 of the multiple pMOS transistors TR1 in plan view is defined by the planar shape of the active region AR1. The formation region FR2 of the multiple pMOS transistors TR2 in plan view is defined by the planar shape of the active region AR2.

The multiple pMOS transistors TR1 are arranged in the active region AR1. The multiple pMOS transistors TR1 are arranged so as to be aligned in the channel length direction of the pMOS transistor TR1. Each of the multiple pMOS transistors TR1 has a pair of impurity regions IR1 and a gate electrode GE1. Adjacent pMOS transistors TR1 share one of the pair of impurity regions IR1. The gate electrodes GE1 of the multiple pMOS transistors TR1 extend parallel to each other.

The multiple pMOS transistors TR2 are arranged in the active region AR2. The multiple pMOS transistors TR2 are arranged so as to be aligned in the channel length direction of the pMOS transistor TR2. Each of the multiple pMOS transistors TR2 has a pair of impurity regions IR2 and a gate electrode GE2. Adjacent pMOS transistors TR2 share one of the pair of impurity regions IR2. The gate electrodes GE2 of the multiple pMOS transistors TR2 extend parallel to each other.

As shown in Figures 4 and 5, an element isolation region SR is disposed on the surface of the semiconductor substrate SB. The element isolation region SR is, for example, STI (Shallow Trench Isolation), but may also be LOCOS (LOCal Oxidation of Silicon). The element isolation region SR made of STI has a trench TRE and a filling insulating layer BI. The trench TRE extends in the depth direction (thickness direction of the semiconductor substrate SB) from the surface of the semiconductor substrate SB. The filling insulating layer BI is embedded in the trench TRE.

As shown in FIG. 4, the pMOS transistors TR1 are arranged on the surface of the semiconductor substrate SB surrounded by the element isolation region SR. Each of the pMOS transistors TR1 has a pair of impurity regions IR1, a gate insulating layer GI1, and a gate electrode GE1.

The pair of impurity regions IR1 are disposed on the surface of the semiconductor substrate SB. One of the pair of impurity regions IR1 serves as a source SO1, and the other serves as a drain DR1. The gate electrode GE1 is disposed on the surface of the semiconductor substrate SB between the pair of impurity regions IR1, with a gate insulating layer GI1 interposed therebetween. The sidewalls of the gate electrode GE1 are covered with a sidewall insulating layer SW1.

The impurity regions IR1 that become the multiple sources SO1 are electrically connected to each other via a first conductive layer CL1. The impurity regions IR1 that become the multiple drains DR1 are electrically connected to each other via a second conductive layer CL2. The first conductive layer CL1 is, for example, a wiring layer above the gate electrode GE1. The second conductive layer CL2 is a wiring layer above the first conductive layer CL1. Each of the first conductive layer CL1 and the second conductive layer CL2 is made of, for example, a metal material. The second conductive layer CL2 is a wiring layer above the first conductive layer CL1.

As shown in FIG. 5, the pMOS transistors TR2 are arranged on the surface of the semiconductor substrate SB surrounded by the element isolation region SR. Each of the pMOS transistors TR2 has a pair of impurity regions IR2, a gate insulating layer GI2, and a gate electrode GE2.

The pair of impurity regions IR2 are disposed on the surface of the semiconductor substrate SB. One of the pair of impurity regions IR2 serves as the source SO2, and the other serves as the drain DR2. The gate electrode GE2 is disposed on the surface of the semiconductor substrate SB between the pair of impurity regions IR2, with a gate insulating layer GI2 interposed therebetween. The sidewalls of the gate electrode GE2 are covered with a sidewall insulating layer SW2.

The impurity regions IR2 that become the multiple sources SO2 are electrically connected to each other via a third conductive layer CL3. The impurity regions IR2 that become the multiple drains DR2 are electrically connected to each other via a fourth conductive layer CL4. The third conductive layer CL3 is, for example, a wiring layer above the gate electrode GE1, and is a layer formed separately from the same layer as the first conductive layer CL1. The fourth conductive layer CL4 is a wiring layer above the third conductive layer CL3, and is a layer formed separately from the same layer as the second conductive layer CL2. Each of the third conductive layer CL3 and the fourth conductive layer CL4 is made of, for example, a metal material.

In this embodiment, the second conductive layer CL2 is a wiring layer above the first conductive layer CL1, and the fourth conductive layer CL4 is a wiring layer above the third conductive layer CL3. However, conversely, the second conductive layer CL2 may be a wiring layer below the first conductive layer CL1, and the fourth conductive layer CL4 may be a wiring layer below the third conductive layer CL3.

As shown in FIG. 6, in this embodiment, the overlap between the layout of the multiple pMOS transistors TR1 and the top conductive layer UC in a planar view is the same as the overlap between the layout of the multiple pMOS transistors TR2 and the top conductive layer UC in a planar view.

In plan view, the top conductive layer UC has a repeating pattern in which the same shape is repeated in the region directly above the current mirror circuit. The repeating pattern of the top conductive layer UC is, for example, a remaining pattern in plan view. A remaining pattern means a pattern in which, in plan view, the pattern-free portion of the top conductive layer UC is not surrounded by the pattern of the top conductive layer UC. Note that a cut-out pattern, which will be described later, means a pattern in which, in plan view, the pattern-free portion of the top conductive layer UC is surrounded by the pattern of the top conductive layer UC.

The top conductive layer UC has a repeating pattern that forms a slit shape in a planar view in the region directly above each of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. In other words, the top conductive layer UC repeats the same shape as a rectangular residual pattern that extends linearly in a planar view in the region directly above each of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. The rectangular residual pattern of the top conductive layer UC extends in the channel width direction of each of the pMOS transistors TR1 and TR2.

As shown in FIG. 7, the uppermost conductive layer UC refers to the conductive layer located in the resin-sealed semiconductor package, which is the uppermost layer (the layer farthest away) from the surface of the semiconductor substrate SB. The uppermost conductive layer UC may be a wiring layer that transmits electrical signals, or may be a dummy wiring layer having a floating potential.

The uppermost conductive layer UC is made of, for example, aluminum (Al). The uppermost conductive layer UC may be made of aluminum-copper (AlCu) containing aluminum, or may be made of copper (Cu).

Between the top conductive layer UC and the plurality of pMOS transistors TR1, for example, an intermediate conductive layer MI may be arranged. Also, between the top conductive layer UC and the plurality of pMOS transistors TR2, for example, an intermediate conductive layer MI may be arranged.

The intermediate conductive layer MI may be a single layer conductor or a multi-layer conductor. When the intermediate conductive layer MI is a multi-layer conductor, the intermediate conductive layer MI may include, for example, a first intermediate conductor MI1 and a second intermediate conductor MI2. Furthermore, the intermediate conductive layer MI is not limited to two layers of conductors MI1 and MI2, and may have three or more layers of conductors.

The first intermediate conductor MI1 is disposed on an interlayer insulating layer IL1 that covers the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. The first intermediate conductor MI1 is made of, for example, a metal material, and may include a first conductive layer CL1 shown in FIG. 4 and a third conductive layer CL3 shown in FIG. 5.

The second intermediate conductor MI2 is disposed on an interlayer insulating layer IL2 that covers the first intermediate conductor MI1. The second intermediate conductor MI2 is made of, for example, a metal material and may include a second conductive layer CL2 shown in FIG. 4 and a fourth conductive layer CL4 shown in FIG. 5. The top conductive layer UC is disposed on an interlayer insulating layer IL3 that covers the second intermediate conductor MI2.

It is preferable that the overlap between the layout of the intermediate conductive layer MI and the multiple pMOS transistors TR1 in a planar view and the overlap between the layout of the intermediate conductive layer MI and the multiple pMOS transistors TR2 in a planar view are the same. Specifically, it is preferable that the overlap between the layout of the first intermediate conductor MI1 and the multiple pMOS transistors TR1 in a planar view and the overlap between the layout of the first intermediate conductor MI1 and the multiple pMOS transistors TR2 in a planar view are the same. It is also preferable that the overlap between the layout of the second intermediate conductor MI2 and the multiple pMOS transistors TR1 in a planar view and the overlap between the layout of the second intermediate conductor MI2 and the multiple pMOS transistors TR2 in a planar view are the same.

The uppermost conductive layer UC may be covered with an interlayer insulating layer IL4. A passivation film PV is disposed on the interlayer insulating layer IL4. No protective film made of an organic material such as polyimide is disposed on the passivation film PV. Therefore, the sealing resin ER is in direct contact with the upper surface of the passivation film PV. In other words, the semiconductor package of this embodiment has a polyimide-less configuration (a configuration without a protective film made of an organic material).

Although a polyimide-less configuration has been described above, a protective film made of an organic material such as polyimide may be disposed between the passivation film PV and the sealing resin ER. In this case, the protective film made of an organic material such as polyimide contacts the upper surface of the passivation film PV and the lower surface of the sealing resin ER.

The thickness of the top conductive layer UC is, for example, 1.5 μm or more. The distance between the bottom surface of the top conductive layer UC and the top surfaces of the gate electrodes GE1 and GE2 is, for example, 3.5 μm or more and 4.0 μm or less. The width of each of the gate electrodes GE1 and GE2 is, for example, 0.17 μm or more.

＜Effects＞
Next, the effects of this embodiment will be described in comparison with a comparative example shown in FIG.

As shown in FIG. 8, in a semiconductor package, when sealing is performed with the sealing resin ER, stress occurs due to the difference in the thermal expansion coefficient between the sealing resin ER and the semiconductor chip, and this stress acts on the semiconductor substrate SB. At this time, if a top-layer conductive layer UC is disposed between the sealing resin ER and the semiconductor substrate SB, the top-layer conductive layer UC functions as a buffer to relieve the stress. For this reason, the above-mentioned stress is unlikely to act on the portion of the semiconductor substrate SB directly above which the top-layer conductive layer UC is disposed. On the other hand, the above-mentioned stress is likely to act on the portion of the semiconductor substrate SB above which the top-layer conductive layer UC is not disposed.

In the comparative example shown in FIG. 8, the top conductive layer UC is arranged non-uniformly on the multiple pMOS transistors TR1 and on the multiple pMOS transistors TR2. Specifically, the top conductive layer UC is not arranged on the multiple pMOS transistors TR1, but is arranged on the multiple pMOS transistors TR2.

As a result, a large stress acts on the portion of the semiconductor substrate SB where the multiple pMOS transistors TR1 are arranged, and a small stress acts on the portion of the semiconductor substrate SB where the multiple pMOS transistors TR2 are arranged.

In this way, the stress acting on the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 is different. This causes the characteristics of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2, which should essentially have the same characteristics, to vary. As a result, it becomes difficult to obtain an appropriate oscillation frequency in an oscillator circuit having multiple pMOS transistors TR1 and multiple pMOS transistors TR2.

In contrast to this, in this embodiment, as shown in FIG. 6, the overlap in plan view between the layout of the multiple pMOS transistors TR1 and the uppermost conductive layer UC is the same as the overlap in plan view between the layout of the multiple pMOS transistors TR2 and the uppermost conductive layer UC. Therefore, when sealing with the sealing resin ER, the stress difference acting on the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 is small. This makes it possible to suppress the variation in the characteristics of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. This makes it easy to obtain an appropriate oscillation frequency in an oscillator circuit having multiple pMOS transistors TR1 and multiple pMOS transistors TR2.

In this embodiment, as shown in Figures 2 and 3, the oscillator circuit HC includes a current mirror circuit composed of transistors TR1 and TR2. Since the variation in the characteristics of the transistors TR1 and TR2 can be suppressed, the current can be accurately copied by the current mirror circuit.

If a protective film made of an organic material such as polyimide is placed between the passivation film PV and the sealing resin ER, the polyimide functions as a buffer to relieve the stress generated during sealing with the sealing resin ER. Therefore, as in the comparative example shown in Figure 8, if the top conductive layer UC is unevenly placed in a polyimide-less configuration, the difference in stress acting on each of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 becomes significant.

In contrast, in this embodiment, as shown in FIG. 7, the top conductive layer UC is uniformly disposed on each of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. In other words, the overlap in plan view between the layout of the multiple pMOS transistors TR1 and the top conductive layer UC is the same as the overlap in plan view between the layout of the multiple pMOS transistors TR2 and the top conductive layer UC. Therefore, even in a polyimide-less configuration, the stress difference acting on the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2 is small. Therefore, it is possible to suppress the variation in characteristics between the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2.

In addition, since the semiconductor device SD of this embodiment can be constructed without polyimide, it is advantageous in terms of cost.

In addition, in this embodiment, as shown in FIG. 7, an intermediate conductive layer MI is disposed below the uppermost conductive layer UC. The overlap in plan view between the layout of the multiple pMOS transistors TR1 and the intermediate conductive layer MI is the same as the overlap in plan view between the layout of the multiple pMOS transistors TR2 and the intermediate conductive layer MI. This further reduces the difference in stress acting on the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. This further reduces the variation in characteristics between the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2.

<Modification>
Next, modifications of this embodiment will be described with reference to FIGS.

As in the first modification shown in FIG. 9, the top conductive layer UC may cover the entire region directly above the current mirror circuit. In other words, the top conductive layer UC may cover the entire region directly above each of the pMOS transistors TR1 and TR2 that make up the current mirror circuit. In this case, the top conductive layer UC may cover the entire region directly above the element isolation region SR between the pMOS transistors TR1 and TR2.

As shown in FIG. 10, in the second modification, the top conductive layer UC may be a rectangular residual pattern that extends linearly in the channel length direction of each of the pMOS transistors TR1 and TR2 in a plan view. The repeated pattern of the top conductive layer UC forms a slit shape in a plan view in the region directly above each of the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. The top conductive layer UC has a first portion UC1 located directly above the multiple pMOS transistors TR1 and a second portion UC2 located directly above the multiple pMOS transistors TR2. The first portion UC1 and the second portion UC2 are separated from each other in the region directly above the current mirror circuit and extend in parallel in the channel width direction.

As in the third modification shown in FIG. 11, the uppermost conductive layer UC may be a cutout pattern in plan view. The cutout pattern of the uppermost conductive layer UC may be a pattern in which at least one of rectangular and circular shapes is cut out. The uppermost conductive layer UC may have a plurality of rectangular cutout patterns arranged to form a lattice shape in plan view.

As shown in FIG. 12, in variant 4, the uppermost conductive layer UC may have multiple circular cutout patterns arranged in a lattice shape in a plan view.

As in variant 5 shown in FIG. 13, the top conductive layer UC may be a residual pattern in plan view. The residual pattern may be a pattern in which at least one of rectangular and circular shapes is repeated. The top conductive layer UC may be composed of a plurality of rectangular residual patterns arranged in a matrix in plan view.

As shown in FIG. 14, the uppermost conductive layer UC may be composed of a plurality of circular residual patterns arranged in a matrix in a plan view.

As in the seventh modification shown in FIG. 15, the top conductive layer UC may be arranged so as not to cover the area directly above the current mirror circuit in a plan view. In this case, for example, the top conductive layer UC may be a cut-out pattern in which the entire area directly above the current mirror circuit in a plan view is cut out.

In addition, the repeating pattern of the top conductive layer UC may be a checkerboard pattern other than the grid pattern described above.

In the first to seventh modifications shown in Figures 9 to 15, the overlap in plan view between the layout of the multiple pMOS transistors TR1 and the uppermost conductive layer UC is the same as the overlap in plan view between the layout of the multiple pMOS transistors TR2 and the uppermost conductive layer UC. Therefore, as in the above embodiment, it is possible to suppress the variation in characteristics between the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2. This makes it easy to obtain an appropriate oscillation frequency in an oscillator circuit having multiple pMOS transistors TR1 and multiple pMOS transistors TR2.

Also, as shown in FIG. 16, the overlap between the layout of the multiple pMOS transistors TR1 and the uppermost conductive layer UC in a planar view and the overlap between the layout of the multiple pMOS transistors TR2 and the uppermost conductive layer UC in a planar view may be symmetrical with each other. The symmetry may be linear symmetry in a planar view, or may be point symmetry. If it is linear symmetry, it is preferable that it is also linearly symmetrical in a cross-sectional view with respect to a virtual line SL that passes through the midpoint between the multiple pMOS transistors TR1 and the multiple pMOS transistors TR2.

In addition, the above describes the overlap between each of the pMOS transistors TR1 and TR2 included in the oscillator circuit HC and the top conductive layer UC in a planar view, but the same applies to the overlap between the top conductive layer UC and the resistors included in the oscillator circuit HC in a planar view.

In other words, as shown in FIG. 17, the overlap between the resistor RA and the layout of the top conductive layer UC in a planar view and the overlap between the resistor RB and the layout of the top conductive layer UC in a planar view may be the same as or symmetrical to each other.

For example, when a resistor RA is formed in a wiring CLA made of polycrystalline silicon doped with impurities, the resistor RA (hatched area in FIG. 17) is set to have a lower impurity concentration than the portion of the wiring in the wiring CLA. Also, when a resistor RB is formed in a wiring CLB made of polycrystalline silicon doped with impurities, the resistor RB (hatched area in FIG. 17) is set to have a lower impurity concentration than the portion of the wiring in the wiring CLUB.

The resistor RA may be set to have a smaller width or thickness than the portion of the wiring CLA that will become the wiring. The resistor RB may be set to have a smaller width or thickness than the portion of the wiring CLB that will become the wiring.

Resistors RA and RB have the same configuration. Here, "having the same configuration" means having the same configuration in terms of design, and includes differences due to manufacturing errors in actual manufacturing (errors in impurity concentration distribution due to ion implantation, errors in patterning shape due to photoengraving and etching, etc.).

In addition, resistors RA and RB are elements that need to be formed with precision so that they have the same structure, and are elements that require relative precision.

As shown in FIG. 18, each of the resistors RA and RB is located, for example, directly above the element isolation region SR. The element isolation region SR may be STI or LOCOS.

By using the configurations of Figures 17 and 18, the difference between the stress acting on resistor RA and the stress acting on resistor RB is reduced. This makes it possible to suppress the variation in the characteristics of resistors RA and RB. This makes it easier to obtain an appropriate oscillation frequency in an oscillator circuit having resistors RA and RB.

Each of the pMOS transistors TR1 and TR2 in the above embodiment and modified examples may be an nMOS transistor or a MIS (Metal Insulator Semiconductor) transistor.

The invention made by the inventor has been specifically described above based on the embodiment, but it goes without saying that the invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

AR1, AR2 active region, BI filled insulating layer, CD capacitor, CDS charge/discharge switching section, CL1 first conductive layer, CL2 second conductive layer, CL3 third conductive layer, CL4 fourth conductive layer, CLA, CLUB wiring, CO, CP comparator, DR1, DR2 drain, ER sealing resin, FM1, FM2 flash memory circuit, FR1, FR2 formation region, GE1, GE2 gate electrode, GI1, GI2 gate insulating layer, HC oscillation circuit, IL1 to IL4 interlayer insulating layer, IR1, IR2 impurity region, LC logic circuit, MI intermediate conductive layer, MI1 first intermediate conductor, MI2 second intermediate conductor, PV passivation film, R1 to R4, RA, RB resistor, SB semiconductor substrate, SD semiconductor device, SM SRAM circuit, SO1, SO2 source, SR element isolation region, SV reference voltage circuit, SW1, SW2 sidewall insulating layer, TR1 to TR8 transistors, TRE trench, UC top conductive layer, UC1 first part, UC2 second part.

Claims (15)

A first element included in the oscillation circuit;
a second element included in the oscillator circuit and having the same configuration as the first element;
a top conductive layer disposed over the first element and the second element;
a semiconductor device in which an overlap between the first element and the layout of the uppermost conductive layer in a plan view and an overlap between the second element and the layout of the uppermost conductive layer in a plan view are the same as or symmetrical to each other. The semiconductor device according to claim 1, wherein the oscillator circuit includes a current mirror circuit formed by the first element and the second element. The semiconductor device according to claim 2, wherein the top conductive layer covers the entire area directly above the current mirror circuit. The semiconductor device according to claim 2, wherein the uppermost conductive layer has a repeating pattern in which the same shape is repeated in a plan view in the region directly above the current mirror circuit. The semiconductor device according to claim 4, wherein the repeating pattern of the uppermost conductive layer is a residual pattern in a plan view. The semiconductor device according to claim 5, wherein the remaining pattern of the uppermost conductive layer is a pattern in which at least one of rectangular and circular shapes is repeated. The semiconductor device according to claim 4, wherein the repeating pattern of the uppermost conductive layer is a cutout pattern in a plan view. The semiconductor device according to claim 7, wherein the cutout pattern of the uppermost conductive layer is a pattern cut out in at least one of a rectangular shape and a circular shape. The semiconductor device according to claim 4, wherein the repeating pattern of the top conductive layer is a slit shape, a lattice shape, or a checkerboard shape. The semiconductor device according to claim 2, wherein the top conductive layer is arranged so as not to cover the area directly above the current mirror circuit. The semiconductor device according to claim 1, wherein the thickness of the uppermost conductive layer is 1.5 μm or more. The semiconductor device according to claim 1, wherein the distance between the bottom surface of the top conductive layer and the top surface of the first element and the distance between the bottom surface of the top conductive layer and the top surface of the second element are each 3.5 μm or more and 4.0 μm or less. Further comprising a semiconductor substrate;
each of the first element and the second element has a conductive layer disposed on the semiconductor substrate;
2. The semiconductor device according to claim 1, wherein the conductive layer has a width of 0.17 [mu]m or more. a passivation film disposed on the uppermost conductive layer;
The semiconductor device according to claim 1 , further comprising a sealing resin arranged so as to be in contact with an upper surface of the passivation film. an intermediate conductive layer disposed above the first element and the second element and below the uppermost conductive layer;
2. The semiconductor device according to claim 1, wherein an overlap in a planar view between the first element and a layout of the intermediate conductive layer directly above the first element and an overlap in a planar view between the second element and a layout of the intermediate conductive layer directly above the second element are the same as or symmetrical to each other.

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