JP7510139B2 - Method for producing Ge single crystal film - Google Patents

Description

The present invention relates to a method for producing a Ge single crystal film and an optical device using the same.

In recent years, the development of optical devices that use Ge (germanium) as an optical semiconductor device has progressed. The basic optical components of silicon photonics are Si-based optical waveguides and Ge photodetectors, and small optical modules that monolithically integrate these on the same substrate are expected to be applied to communication systems.

Regarding a method for manufacturing a Ge single crystal film, which is a basic material for a Ge photodetector, for example, Patent Document 1 describes a method of epitaxially growing Ge on the surface of a Si substrate on which a submicron-wide SiO ₂ mask is repeated. As shown in FIG. 8, when Ge epitaxially grows on the surface of a Si substrate 30 on which a SiO ₂ mask 31 is repeated, Ge selectively grows from the exposed surface of the Si substrate 30. When the crystal growth continues, Ge grows laterally leaving a cavity 33 on the SiO ₂ mask 31, and is integrated with the adjacent Ge selective growth layer to form a continuous film. By using this method, a Ge single crystal thin film 32 with reduced threading dislocation density can be formed on a Si substrate 30 without heat treatment.

JP 2017-98493 A

However, in the conventional method, a film thickness of about 1.5 μm is required to make Ge a continuous film and to flatten the surface. In addition, since the film thickness is thinner than that of Ge grown on a normal Si substrate without a _SiO2 mask, a Ge film of 2 μm or more is required in terms of normal growth. Since the typical crystal growth rate of Ge is 10 nm/min, a crystal growth time of 4 hours or more is required to form a Ge film of 2 μm or more.

In addition, the _SiO2 mask must be a thin film of about 10 nm. If the _SiO2 mask is too thick, the lateral growth of the Ge crystals is hindered, and a longer growth time is required to obtain a continuous film. The thickness of the _SiO2 mask can be reduced by treating it with an aqueous hydrofluoric acid solution before the Ge crystal growth, but the concentration of hydrofluoric acid and the treatment time must be precisely controlled.

In order to increase the response speed of optical devices to 10 GHz or more, it is necessary to reduce the thickness of the Ge single crystal film used in the photoreceiver and optical intensity modulator of optical integrated circuits to 1 μm or less. However, thick Ge single crystal films manufactured by conventional methods cannot be applied to such high-speed optical devices. It is possible to thin the _SiO2 mask to submicron or less, but this requires high-precision processing technology.

Therefore, the object of the present invention is to provide a method for producing a Ge single crystal film that can produce a thin continuous film of Ge single crystal in a shorter time than conventional methods, and an optical device using the same.

To solve the above problems, the method for manufacturing a Ge single crystal film according to the present invention is characterized in that the surface layer of a silicon wafer is processed to form a submicron-wide Si nanowire array, and a Ge single crystal film is formed on the Si nanowire array by chemical vapor deposition.

According to the present invention, a continuous Ge film can be obtained with a shorter growth time and smaller grown film thickness than the conventional method for manufacturing a Ge single crystal film using a _SiO2 mask. Also, as with the conventional method, the threading dislocation density generated in the Ge single crystal due to the 4% lattice mismatch between Si and Ge can be reduced without heat treatment, and a high-quality Ge epitaxial film can be formed.

In the present invention, the line width of the Si nanowire array is preferably 0.1 to 1.5 μm. Also, the space width of the Si nanowire array is preferably 0.1 to 1.0 μm. If the line width of the Si nanowire array is 0.1 to 1.5 μm, a continuous film of Ge single crystal with a low threading dislocation density and a flat surface can be formed. In addition, the Si nanowire array can be used as a Si optical waveguide, which can improve the manufacturing efficiency of small optical modules.

In the present invention, the thickness of the Ge single crystal film is preferably 1 μm or less. This makes it possible to provide a Ge single crystal film suitable for fabricating optical devices with a response speed of 10 GHz or more.

In the present invention, the silicon wafer is preferably an SOI wafer in which an upper Si layer is formed on a Si support substrate via an insulating layer, and the surface layer is preferably the upper Si layer. In this case, the thickness of the upper Si layer is preferably 0.1 to 1.5 μm. When an SOI wafer is used, it is easy to process a Si nanowire array. Furthermore, SOI wafers are suitable as substrate materials for optical integrated circuits using silicon photonics, and enable high-density integration of various optical devices such as light sources, optical waveguides, optical intensity modulators, photodetectors, and optical couplers.

In forming the Si nanowire array, the upper Si layer may be selectively etched so that no Si remains in the separation grooves between the Si nanowire patterns, or the upper Si layer may be selectively etched so that Si remains in the separation grooves between the Si nanowire patterns. In the former case, a Ge single crystal film having cavities formed in the separation grooves between the Si nanowire patterns can be obtained. In the latter case, Ge growth also occurs in the separation grooves between the Si nanowire patterns, so that a Ge single crystal film without cavities between the Si nanowire patterns can be obtained.

In the present invention, the silicon wafer may be a bulk silicon wafer. In this case, Ge growth also occurs in the isolation grooves between the Si nanowire patterns, so that a Ge single crystal film without cavities between the Si nanowire patterns can be obtained.

The optical device according to the present invention is characterized in that it comprises an optical waveguide array consisting of a submicron-width Si nanowire array formed on the surface layer of a Si substrate, and a Ge single crystal film formed on the Si nanowire array, the Ge single crystal film including a pn junction or a pin junction.

According to the present invention, the thickness of the Ge single crystal film can be reduced to 1 μm or less. Therefore, it is possible to realize an optical device capable of high-speed operation of 10 GHz or more.

The present invention provides a method for producing a Ge single crystal film that can produce a thin continuous film of Ge single crystal in a shorter time than conventional methods, and an optical device using the same.

1A to 1C are schematic diagrams showing a method for producing a Ge single crystal film according to a first embodiment of the present invention. 2(a) and (b) are schematic diagrams showing a method for producing a Ge single crystal film according to a second embodiment of the present invention. 3A and 3B are diagrams showing the structure of an optical device according to an embodiment of the present invention, where (a) is a schematic cross-sectional view and (b) is a schematic plan view. FIG. 4 is a SEM image of a cross section of the Ge single crystal film according to Example 1. FIG. 5 is a TEM image of a cross section of the Ge single crystal film according to Example 1. FIG. 6 is a TEM image of a cross section of the Ge single crystal film according to Example 2. FIG. 7 is an SEM image of a cross section of a Ge single crystal film according to a comparative example. FIG. 8 is a schematic diagram showing a conventional method for producing a Ge single crystal film.

The following describes in detail a preferred embodiment of the present invention with reference to the attached drawings.

Figure 1 is a schematic diagram showing a method for manufacturing a Ge single crystal film according to a first embodiment of the present invention.

In the manufacture of a Ge single crystal film, first prepare an SOI (Silicon On Insulator) wafer 10 (Figure 1(a)). The SOI wafer 10 is a type of silicon wafer in which an upper Si layer 13 (Si active layer) is formed on a Si support substrate 11 via an insulating layer 12 called a BOX (Buried Oxide) layer. The thickness of the upper Si layer 13 is preferably 0.1 to 1.5 μm. The thickness of the insulating layer 12 is not particularly limited, but is preferably 1 to 20 μm.

Next, the upper Si layer 13 of the SOI wafer 10 is processed to form a submicron-wide Si nanowire array 14 (FIG. 1(b)). The Si nanowire array 14 can be formed by photolithography and dry etching of the upper Si layer 13. The Si nanowire array 14 is periodically arranged along the <011> direction of the upper Si layer 13, which has a (100) plane orientation.

The line width _W1 of the Si fine wire array 14 is preferably 0.1 to 1.5 μm, and more preferably 0.1 to 1.0 μm. This is because if the line width _W1 of the Si fine wire pattern 14a is smaller than 0.1 μm, the effect of reducing the threading dislocation density of the Ge single crystal film is very small, and if it is larger than 1.5 μm, it is difficult to form a Ge single crystal film with a flat surface. The space width _W2 of the Si fine wire array 14 is preferably 0.1 to 1.0 μm, and particularly preferably equal to or smaller than _the line width _W1 .

Next, a Ge single crystal film 15 is formed by chemical vapor deposition on the main surface of the SOI wafer 10 on which the Si nanowire array 14 is formed (FIG. 1(c)). The Ge single crystal film 15 is preferably formed by UHV-CVD (Ultra-High Vacuum Chemical Vapor Deposition), and the crystal growth temperature (substrate temperature) is preferably 600 to 700°C.

Epitaxial growth of Ge proceeds vertically (film thickness) from the surface of the Si fine-line pattern 14a, and also horizontally, so that when adjacent Ge layers come into contact, they form a continuous film. Since crystal growth of Ge from the sidewall surface of the Si fine-line pattern 14a is suppressed, a cavity 16 is formed between adjacent Si fine-line patterns 14a, 14a, but if the crystal growth of Ge continues, a continuous film with a flat surface is obtained by epitaxial growth in the horizontal direction.

In the conventional method using a SiO ₂ mask, a film thickness of about 1.5 μm is required to obtain a continuous Ge film with a flat surface, and a film thickness of about 2.0 μm is required in the area not covered by the SiO ₂ mask. However, according to the present invention, a continuous Ge film with a flat surface can be obtained with a shorter growth time and smaller growth film thickness than the conventional method. This is due to the effect that the position where the cavity is formed is lowered compared to the conventional method in which a cavity is formed in the Ge _single crystal film on the SiO 2 mask. Note that if the line width W ₁ of the Si fine line pattern 14a is too wide, the surface of the continuous Ge film will not be flat. This is because a (311) facet surface with a slow crystal growth rate is formed widely during Ge growth, and this facet surface stabilizes the surface in an inclined state.

Figures 2(a) and (b) are schematic diagrams showing a method for manufacturing a Ge single crystal film according to a second embodiment of the present invention.

The method for manufacturing a Ge single crystal film according to this embodiment is such that when the upper Si layer 13 of the SOI wafer 10 is selectively etched to form the Si nanowire array 14, the upper surface of the insulating layer 12 that constitutes the bottom surface of the isolation groove 14b (Si trench) between adjacent Si nanowire patterns 14a, 14a is not completely exposed, but a part of the upper Si layer 13 remains on the upper surface of the insulating layer 12 (Figure 2(a)).

Then, when the Ge single crystal film 15 is formed, epitaxial growth of Ge proceeds not only from the top surface of the Si fine line pattern 14a but also from the bottom surface of the separation groove 14b, so that the separation groove 14b is filled with Ge and no cavity 16 is formed (FIG. 2(b)). However, as in the first embodiment, a continuous Ge film with a flat surface can be obtained with a shorter growth time and smaller grown film thickness than in the conventional method. In addition, dislocations in the Ge single crystal film progress laterally along with the lateral epitaxial growth of Ge, so that the effect of reducing the threading dislocation density can be obtained as in the first embodiment.

When optical devices are manufactured using a silicon wafer on which the Ge single crystal film is formed, the Si nanowire pattern functions as an optical waveguide, and the Ge single crystal film is processed into optical devices such as a light source, optical modulator, and photoreceiver connected to the optical waveguide. For example, a Ge photoreceiver can be realized by patterning the Ge single crystal film, then implanting ions into part of the upper surface of the Ge single crystal film to form a pn junction.

Figures 3(a) and (b) show the structure of an optical device according to an embodiment of the present invention, where (a) is a schematic cross-sectional view and (b) is a schematic plan view.

As shown in Figures 3(a) and (b), this optical device 20 is formed by processing the Ge single crystal film 15 shown in Figure 1(c) to form a Ge photodetector 21 on the Si fine-line pattern 14a. As described above, the Si fine-line array 14 is formed on the Si support substrate 11 (Si substrate) via the insulating layer 12, and the Si fine-line array 14 constitutes an optical waveguide array. Each of the multiple Si fine-line patterns 14a that constitute the Si fine-line array 14 functions as a Si optical waveguide. In this way, the Si fine-line array 14 is not simply used for Ge crystal growth, but actually functions as part of the optical device.

The patterned Ge single crystal film 15 also constitutes a Ge photodetector 21 connected to a Si optical waveguide. A p-type impurity region 15p and an n-type impurity region 15n are provided in the Ge single crystal film 15, thereby forming a pin junction in the lateral direction. The p-type impurity region 15p and the n-type impurity region 15n can be formed by ion implantation of p-type dopants and n-type dopants, respectively, into predetermined regions of the Ge single crystal film 15. The Ge photodetector 21 is not limited to the structure shown in the figure, and various structures can be adopted.

As described above, the method for manufacturing a Ge single crystal film according to this embodiment epitaxially grows the Ge single crystal film 15 on the submicron-wide Si nanowire array 14 by chemical vapor deposition, so that a thin continuous film of Ge single crystal can be formed in a shorter time than in the past. Also, as in the past, a high-quality Ge single crystal thin film with reduced threading dislocation density can be obtained.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these are also included within the scope of the present invention.

For example, in the above embodiment, a Ge single crystal film is formed on an SOI wafer, but the present invention is not limited to the use of an SOI wafer, and it is also possible to use, for example, a bulk silicon wafer. In this case, the surface layer of the bulk silicon wafer is processed into a fine line array with a submicron width, and Ge is epitaxially grown on the array, thereby forming a continuous Ge film without voids, as in the second embodiment.

The optical device 20 shown in Figure 3 is an example in which the Ge single crystal film 15 is processed into a Ge optical receiver, but the Ge single crystal film can also be used as an optical modulator, and is not limited to being a Ge optical receiver.

Example 1
The upper Si layer of the SOI wafer with a (100) surface orientation was processed into a fine line shape to form a Si fine line array (line and space pattern) extending in the <011> direction. The thickness of the upper Si layer of the SOI wafer was 0.22 μm, and the thickness of the insulating layer was 3 μm. The Si fine line array was formed by photolithography and dry etching, the line width and space width of the Si fine line array were 0.5 μm, and the upper Si layer did not remain in the separation groove between the Si fine line patterns, and the upper surface of the SiO ₂ insulating layer was exposed.

Next, Ge was formed by UHV-CVD on the SOI wafer with the Si nanowire array formed on it. _GeH4 was used as the source gas, and Ge epitaxial growth was performed at a substrate temperature of 700°C. The Ge crystal growth was performed under conditions that allowed a Ge single crystal film of 1.0 μm to be obtained on the flat area without the Si nanowire array.

The cross section of the Ge single crystal film thus obtained was observed by SEM. As a result, as shown in Figure 4, a Ge continuous film with a thickness of 0.8 μm was formed, and the surface of the Ge continuous film was flat. In addition, cavities were formed between the Si nanowires.

The cross section of the Ge single crystal film of Example 1 was observed by TEM. As a result, as shown in Figure 5, it was confirmed that dislocations tend to be drawn into the side walls and cavities of the Si nanowires.

Next, the density of dislocations penetrating the Ge single crystal film was evaluated. The surface of the Ge single crystal film was etched with a mixed solution of HF/HNO ₃ /CH ₃ COOH/I ₂ , and the threading dislocation density was obtained from the density of etch pits formed on the surface. As a result, the threading dislocation density of the Ge single crystal film according to Example 1 was 1.2×10 ⁸ cm ⁻² . This was about half the threading dislocation density (2.4×10 ⁸ cm ⁻² ) of the Ge single crystal film formed on a Si plane without a fine line pattern. From this result, it was found that the present invention can reduce the threading dislocation density caused by the 4% lattice mismatch between Si and Ge, as in the conventional method, and a high-quality Ge single crystal film can be obtained without heat treatment.

Example 2
The upper Si layer of the SOI wafer was processed to form a Si nanowire array in the same manner as in Example 1, except that the dry etching time was slightly shortened so that a very thin portion of the upper Si layer remained in the isolation grooves between the Si nanowire patterns. Then, a Ge continuous film was formed under the same conditions as in Example 1.

The cross section of the Ge single crystal film thus obtained was observed by SEM. As a result, as in Example 1, a Ge continuous film with a thickness of approximately 0.8 μm was formed, and the surface of the Ge continuous film was flat. Furthermore, no cavities were formed between the Si nanowires, and Ge was embedded between the Si nanowires.

The cross section of the Ge single crystal film of Example 2 was observed by TEM. As a result, as shown in FIG. 6, it was found that the tendency for dislocations to be drawn into the side walls of the Si fine wires was maintained. In other words, when a Si fine wire array was formed, the effect of reducing threading dislocations was confirmed regardless of the presence or absence of cavities in the separation grooves. Furthermore, from these results, it was confirmed that the effect of reducing threading dislocation density was not limited to SOI wafers, but also in bulk silicon wafers in which the Si surface appears between the Si fine wire patterns.

Comparative Example
A Ge single crystal film was formed under the same conditions as in Example 1, except that the line width of the Si fine-wire array was set to 1.5 μm. As a result, as shown in FIG. 7, a Ge continuous film with a thickness of about 1.0 μm and cavities between the Si fine-wire patterns could be formed. However, the surface of the Ge continuous film was not flat, but was uneven. The thickness of the Ge continuous film was maximum at the center of the Si fine-wire pattern and minimum at the separation grooves between the Si fine wires.

In the comparative example, the crystal growth conditions were the same as in Example 1 except that the line width of the Si nanowire array was 1.5 μm, so the surface of the Ge single crystal film could not be made flat. However, if the line width of the Si nanowire array is about 1.5 μm, it is believed that flattening can be achieved by adjusting the crystal growth conditions, such as the crystal growth temperature and furnace pressure.

REFERENCE SIGNS LIST 10 SOI wafer 11 Si support substrate 12 Insulating layer 13 Upper Si layer 14 Si fine-wire array 14a Si fine-wire pattern 14b Isolation groove 15 Ge single crystal film 15n n-type impurity region 15p p-type impurity region 16 Cavity 20 Optical device 21 Photodetector 30 Si substrate 31 _SiO2 mask 32 Ge single crystal thin film 33 Cavity

Claims (4)

A surface layer of a silicon wafer is processed to form a silicon nanowire array ;
forming a Ge single crystal film on the Si nanowire array by chemical vapor deposition;
The silicon wafer is an SOI wafer in which an upper Si layer is formed on a Si support substrate via an insulating layer,
the surface layer portion is the upper Si layer,
The line width of the Si nanowire array is 0.1 to 1.5 μm,
In forming the Si nanowire array, the upper Si layer is selectively etched so that Si remains in the isolation grooves between the Si nanowire patterns. 2. The method for producing a Ge single crystal film according to claim 1 , wherein the space width of said Si nanowire array is 0.1 to 1.0 μm. 3. The method for producing a Ge single crystal film according to claim 1 , wherein the Ge single crystal film has a thickness of 1 [mu]m or less. 4. The method for producing a Ge single crystal film according to claim 1 , wherein the upper Si layer has a thickness of 0.1 to 1.5 μm.