JP7505612B2 - Electro-optical device and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device.

In recent years, various electro-optical devices have been proposed that display images using light-emitting elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs"). In these electro-optical devices, pixel circuits including light-emitting elements and transistors are provided in correspondence with the pixels of the image to be displayed. Specifically, a common configuration is one in which a plurality of pixel circuits corresponding to the pixels of the image to be displayed are arranged in a matrix, and control lines such as scanning lines are provided in each row to drive the plurality of pixel circuits. (See, for example, Patent Document 1).

JP 2007-316462 A

In recent years, there has been a growing demand for electro-optical devices with smaller display sizes and higher display definition, which requires narrower pitches of control lines in order to arrange pixel circuits at high density.
The present invention has been made in consideration of the above-mentioned circumstances, and one of its objectives is to realize high-density wiring of a plurality of control lines, including a plurality of scanning lines, thereby achieving a high-definition display or a smaller display size.

In order to achieve the above-mentioned object, an electro-optical device according to the present invention comprises a scanning line, a data line intersecting the scanning line, and a pixel circuit provided corresponding to the intersection of the scanning line and the data line, wherein the pixel circuit comprises a drive transistor, a write transistor whose gate is electrically connected to the scanning line, a first storage capacitor that stores a charge corresponding to a data signal supplied via the data line and the write transistor, and a light-emitting element that emits light with a luminance corresponding to the magnitude of a current supplied via the drive transistor, and is characterized in that when viewed from a direction perpendicular to a surface of a substrate on which the pixel circuit is formed, the scanning line and the gate of the drive transistor overlap.
According to this invention, since the scanning lines are wired on the gates of the driving transistors, the spatial constraints in providing the scanning lines are alleviated compared to the case where the scanning lines are wired so as not to intersect with the gates of the driving transistors. This allows the scanning lines to be arranged at a narrower pitch and with a higher wiring density. That is, according to the invention, a plurality of pixel circuits can be arranged at a higher density, enabling a higher resolution display and a smaller display size. In the invention, the write transistor may be electrically connected between the gate of the driving transistor and the data line, for example.

Moreover, an electro-optical device according to the present invention comprises one or more control lines including a scanning line, a data line intersecting the scanning line, and a pixel circuit provided corresponding to the intersection of the scanning line and the data line, the pixel circuit having a drive transistor, a write transistor having a gate electrically connected to the scanning line, a first storage capacitor that stores a charge corresponding to a data signal supplied via the data line and the write transistor, and a light-emitting element that emits light with a luminance corresponding to the magnitude of a current supplied via the drive transistor, and the one or more control lines include a control line that overlaps with the gate of the drive transistor when viewed from a direction perpendicular to a surface of a substrate on which the pixel circuit is formed.
According to this invention, since the control lines are wired on the gates of the drive transistors, spatial constraints when providing the control lines are alleviated compared to when the control lines are wired so as not to intersect with the gates of the drive transistors. This makes it possible to narrow the pitch of the control lines and increase the wiring density. In other words, according to the invention, multiple pixel circuits can be arranged at a higher density, enabling higher resolution display and smaller display size.

The electro-optical device described above further includes a scanning line drive circuit that controls the operation of the pixel circuit, and the write transistor is turned on when the scanning line drive circuit supplies a first potential to the scanning line and turned off when the scanning line drive circuit supplies a second potential to the scanning line, and when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the scanning line and the gate of the drive transistor overlap, and when a first switching period is defined as a period during which the scanning line drive circuit switches the potential supplied to the scanning line from the second potential to the first potential, and a second switching period is defined as a period during which the scanning line drive circuit switches the potential supplied to the scanning line from the first potential to the second potential, the duration of the second switching period is preferably longer than the duration of the first switching period.

When the gate of the driving transistor and the scanning line intersect in a plan view, a parasitic capacitance occurs between the gate of the driving transistor and the scanning line. When the potential of the scanning line fluctuates suddenly, the potential fluctuation affects the gate of the driving transistor, causing a change in the potential of the gate of the driving transistor.
The drive transistor supplies a current to the light-emitting element, the magnitude of which corresponds to the gate-source voltage determined when the write transistor is turned off, and the light-emitting element emits light at a luminance corresponding to the magnitude of the current. Therefore, if the gate potential of the drive transistor changes when the write transistor is turned off (i.e., after the luminance of the light-emitting element is set to a voltage that determines the luminance of the light-emitting element), the light-emitting element emits light at a luminance different from the determined luminance, thereby degrading the display quality of the electro-optical device.
In contrast, the scanning line driving circuit of the present invention changes the potential of the scanning line more slowly when the write transistor is turned off than when it is turned on. This prevents the potential fluctuation of the scanning line when the write transistor is turned off from propagating to the gate of the driving transistor, allowing the light-emitting element to emit light at a specified brightness. In other words, the electro-optical device of the present invention can achieve a narrower pitch of the control lines without degrading the display quality.

The pixel circuit may also include a first switching transistor electrically connected between the gate and drain of the drive transistor, and the one or more control lines may include a first control line electrically connected to the gate of the first switching transistor.
In this case, it is preferable that the first switching transistor is turned on when the scanning line drive circuit supplies a first potential to the first control line and is turned off when the scanning line drive circuit supplies a second potential to the first control line, the first control line and the gate of the drive transistor overlap when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuits are formed, and when a period during which the scanning line drive circuit switches the potential supplied to the first control line from the second potential to the first potential is defined as a third switching period and a period during which the scanning line drive circuit switches the potential supplied to the first control line from the first potential to the second potential is defined as a fourth switching period, the duration of the fourth switching period is longer than the duration of the third switching period.

When the gate of the drive transistor and the first switching transistor intersect in a plan view, a parasitic capacitance occurs between the gate of the drive transistor and the first control line, and when the potential of the first control line fluctuates suddenly, the potential fluctuation affects the gate of the drive transistor, causing a change in the potential of the gate of the drive transistor.
When the first switching transistor is turned on, the gate and source of the drive transistor are electrically connected, and the voltage between the gate and source of the drive transistor is set to a value that compensates for the variation in the threshold voltage of each pixel circuit. Therefore, if the potential of the gate of the drive transistor changes when the first switching transistor is turned off (i.e., after the threshold compensation is performed), the variation in the threshold voltage of the drive transistor for each pixel circuit cannot be compensated for, and the uniformity of the display is impaired.
In contrast, the scanning line driving circuit according to this embodiment changes the potential of the first control line more slowly when the first switching transistor is turned off than when the first switching transistor is turned on. This prevents the potential fluctuation of the first control line when the first switching transistor is turned off from propagating to the gate of the driving transistor, and prevents the potential of the gate of the driving transistor from changing from the threshold-compensated potential. In other words, according to the electro-optical device according to the present invention, even if the first control line is disposed above the gate of the driving transistor, it is possible to prevent the occurrence of display unevenness that impairs the uniformity of the display, and therefore it is possible to achieve both miniaturization of the electro-optical device, high resolution display, and high quality display.

The pixel circuit may also include a second switching transistor electrically connected between the driving transistor and the light-emitting element, and the one or more control lines may include a second control line electrically connected to a gate of the second switching transistor.
In this case, it is preferable that the second switching transistor is turned on when the scanning line drive circuit supplies a first potential to the second control line and is turned off when the scanning line drive circuit supplies a second potential to the second control line, the second control line and the gate of the drive transistor overlap when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuits are formed, and when a period during which the scanning line drive circuit switches the potential supplied to the second control line from the second potential to the first potential is defined as a fifth switching period and a period during which the scanning line drive circuit switches the potential supplied to the second control line from the first potential to the second potential is defined as a sixth switching period, the duration of the fifth switching period is longer than the duration of the sixth switching period.
According to this aspect, it is possible to prevent the potential fluctuation occurring in the second control line when the second switching transistor is turned on from propagating to the gate of the drive transistor, thereby realizing a narrower pitch of the control lines without deteriorating the display quality.

The pixel circuit may also include a third switching transistor electrically connected between a power supply line to which a predetermined reset potential is supplied and the light-emitting element, and the one or more control lines may include a third control line electrically connected to a gate of the third switching transistor.
In this case, it is preferable that the third switching transistor is turned on when the scanning line drive circuit supplies a first potential to the third control line and is turned off when the scanning line drive circuit supplies a second potential to the third control line, the third control line and the gate of the drive transistor overlap when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuits are formed, and when a period during which the scanning line drive circuit switches the potential supplied to the third control line from the second potential to the first potential is defined as a seventh switching period and a period during which the scanning line drive circuit switches the potential supplied to the third control line from the first potential to the second potential is defined as an eighth switching period, the duration of the eighth switching period is longer than the duration of the seventh switching period.
According to this aspect, it is possible to prevent the potential fluctuation occurring in the third control line when the third switching transistor is turned off from propagating to the gate of the drive transistor, thereby realizing a narrower pitch of the control lines without deteriorating the display quality.

The electro-optical device described above includes a data line driving circuit electrically connected to the data line, a control circuit for controlling the operation of the scanning line driving circuit and the data line driving circuit, and a second holding capacitance provided corresponding to the data line and holding the potential of the data line, the data line driving circuit including a first potential line to which a predetermined initial potential is supplied from the control circuit, a second potential line to which a reference potential is supplied from the control circuit, and a level shift circuit provided corresponding to the data line, the level shift circuit including a third holding capacitance having one electrode electrically connected to the data line, a first transistor electrically connected between one electrode of the third holding capacitance and the first potential line, and a second holding capacitance provided corresponding to the data line and holding the potential of the data line. and a second transistor electrically connected to the first transistor, and during a first period, the control circuit maintains the first transistor in an on state, and during a second period that starts after the first period ends, the scanning line driving circuit maintains the write transistor in an on state, and the control circuit maintains the first transistor in an off state and the second transistor in an on state, and during a third period that starts after the second period ends, the scanning line driving circuit maintains the write transistor in an on state, and the control circuit maintains the first transistor and the second transistor in an off state, and the other electrode of the third holding capacitance is preferably supplied with a potential based on an image signal that specifies the luminance of the light-emitting element.

According to this invention, the data line is connected to the second storage capacitor and the third storage capacitor, and the other electrode of the third storage capacitor is supplied with a potential based on an image signal that determines the luminance of the light-emitting element. Therefore, the fluctuation range of the potential of the data line is a range obtained by compressing the fluctuation range of the potential supplied to the other electrode of the third storage capacitor according to the capacitance ratio of the second storage capacitor and the third storage capacitor. In other words, the fluctuation range of the potential of the data line is narrower than the fluctuation range of the potential based on the image signal. This makes it possible to set the potential of the gate of the drive transistor with high precision without having to record the image signal with high precision. Therefore, it is possible to supply a current to the light-emitting element with high precision, and a high-quality display is possible. In addition, since the fluctuation range of the potential of the data line can be kept small, it is possible to prevent the occurrence of crosstalk, unevenness, etc. caused by the potential fluctuation of the data line.

In addition, the electro-optical device according to the present invention determines the gate potential of the driving transistor by supplying charges to the first and second storage capacitors from one electrode of the third storage capacitor via the data line. Specifically, the gate potential of the driving transistor is determined by the capacitance value of the first storage capacitor, the capacitance value of the second storage capacitor, and the amount of charge supplied by the third storage capacitor to the first and second storage capacitors. If the electro-optical device does not include the second storage capacitor, the gate potential of the driving transistor is determined by the capacitance value of the first storage capacitor and the charge supplied by the third storage capacitor. Therefore, if the capacitance value of the first storage capacitor has a relative variation for each pixel circuit due to an error in the semiconductor process, the gate potential of the driving transistor also varies for each pixel circuit. In this case, display unevenness occurs and the display quality is reduced.
In contrast, the present invention includes a second storage capacitor that stores the potential of the data line. The second storage capacitor is provided corresponding to each data line, and therefore can be configured to have an electrode with a larger area than the first storage capacitor provided in the pixel circuit. Therefore, the second storage capacitor has a smaller relative variation in capacitance value due to semiconductor process errors than the first storage capacitor. This makes it possible to prevent the potential of the gate of the drive transistor from varying for each pixel circuit, and enables a high-quality display that prevents the occurrence of display unevenness.

It is also preferable that the level shift circuit includes a fourth holding capacitance, and during at least a portion of the period from the start of the first period to the start of the third period, a potential indicated by the image signal is supplied to one electrode of the fourth holding capacitance, and during the third period, one electrode of the fourth holding capacitance is electrically connected to the other electrode of the third holding capacitance.

According to this invention, during the first and second periods, an image signal is supplied to one electrode of the fourth retention capacitor, temporarily held therein, and then during the third period, supplied to the gate of the driving transistor via the third retention capacitor.
If the electro-optical device does not include a fourth storage capacitor, all operations for supplying the potential indicated by the image signal to the gate of the driving transistor must be performed during the third period, and the third period must be set to be sufficiently long.
In contrast, in the present invention, the image signal supply operation and the data line initialization operation are performed in parallel during the first and second periods, and therefore the time constraints on the operations to be performed during one horizontal scanning period can be alleviated, making it possible to slow down the image signal supply operation and ensure a sufficient period for initializing the data lines, etc.
Furthermore, according to the present invention, the magnitude of the fluctuation in potential based on the image signal is compressed using a fourth holding capacitance in addition to the first holding capacitance, the second holding capacitance, and the third holding capacitance, making it possible to supply current to the light-emitting element with high precision.

It is also preferable that the scanning line driving circuit maintains the first switching transistor in an ON state during the second period, maintains the first switching transistor in an OFF state during periods other than the second period, and maintains the third switching transistor in an ON state and the second switching transistor in an OFF state during the first period, the second period, and the third period.

According to this invention, by turning on the first switching transistor in the second period, the potential of the gate of the drive transistor can be set to a potential corresponding to the threshold voltage of the drive transistor, making it possible to compensate for variations in the threshold voltage of the drive transistor for each pixel circuit.
Also, according to the present invention, by turning on the third switching transistor in the first to third periods, it is possible to suppress the influence of the holding voltage of the capacitance parasitic to the light emitting element.

In addition to the electro-optical device, the present invention can also be conceptualized as an electronic device having the electro-optical device. Typical examples of electronic devices include display devices such as head-mounted displays (HMDs) and electronic viewfinders.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a diagram showing a configuration of the electro-optical device. FIG. FIG. 2 is a diagram showing a data line driving circuit in the electro-optical device. FIG. 2 is a diagram showing a pixel circuit in the electro-optical device. 2 is a plan view showing a configuration of a pixel circuit in the electro-optical device. FIG. 2 is a partial cross-sectional view showing a configuration of a pixel circuit in the electro-optical device. 4 is a timing chart showing the operation of the electro-optical device. 5A to 5C are diagrams illustrating the operation of the electro-optical device. 4A to 4C are diagrams illustrating potential changes at the gate node of the electro-optical device. 5A to 5C are explanatory diagrams showing amplitude compression of a data signal in the electro-optical device. 3 is an explanatory diagram showing characteristics of a transistor in the electro-optical device. FIG. 10 is a plan view showing a configuration of a pixel circuit in an electro-optical device according to Modification 1. FIG. 4 is a timing chart showing the operation of the electro-optical device. 11 is a plan view showing a configuration of a pixel circuit in an electro-optical device according to Modification 2. FIG. 4 is a timing chart showing the operation of the electro-optical device. 1 is a perspective view showing an HMD using an electro-optical device according to an embodiment and the like. FIG. 2 is a diagram showing the optical configuration of an HMD.

Below, the embodiment of the present invention will be described with reference to the drawings.

<Embodiment>
1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is, for example, a micro display that displays an image in a head-mounted display.
1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In this embodiment, the plurality of pixel circuits and the drive circuit included in the display panel 2 are formed on a silicon substrate, and the pixel circuits use OLEDs, which are an example of light-emitting elements. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens at the display section, and one end of a flexible printed circuit (FPC) board 84 is connected to the display panel 2.
The FPC board 84 has the control circuit 3, which is a semiconductor chip, mounted thereon by COF (Chip On Film) technology, and is provided with a plurality of terminals 86 for connection to a higher-level circuit (not shown).

2 is a block diagram showing the configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Video is supplied to the control circuit 3 from a higher-level circuit (not shown) in synchronization with a synchronization signal. Here, the image data Video is data that specifies the gradation level of pixels of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later) in, for example, 8 bits. The synchronization signal is a signal that includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a control signal Ctr, a negative logic control signal /Gini, a positive logic control signal Gref, a positive logic control signal Gcpl, a negative logic control signal /Gcpl that is in a logical inversion relationship with the control signal Gcpl, control signals Sel(1), Sel(2), Sel(3), and control signals /Sel(1), /Sel(2), /Sel(3) that are in a logical inversion relationship with these signals. Here, the control signal Ctr is a signal including multiple signals such as a pulse signal, a clock signal, and an enable signal. Note that the control signals Sel(1), Sel(2), Sel(3) may be collectively referred to as the control signal Sel, and the control signals /Sel(1), /Sel(2), /Sel(3) may be collectively referred to as the control signal /Sel.
Furthermore, the control circuit 3 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies to the display panel 2 a predetermined reset potential Vorst, a predetermined initial potential Vini, a predetermined reference potential Vref, and the like.
Furthermore, the control circuit 3 generates an analog image signal Vid based on the image data Video.
Specifically, the control circuit 3 is provided with a look-up table that stores a correspondence between the potential indicated by the image signal Vid and the luminance of a light-emitting element (an OLED 130 described later) included in the display panel 2. Then, by referring to the look-up table, the control circuit 3 generates an image signal Vid indicating a potential corresponding to the luminance of the light-emitting element defined in the image data Video, and supplies this to the display panel 2.

As shown in FIG. 2, the display panel 2 includes a display section 100 and driving circuits (a data line driving circuit 10 and a scanning line driving circuit 20) for driving the display section 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. In detail, in the display unit 100, m rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the figure, and (3n) columns of data lines 14, which are grouped into three columns, extend in the vertical direction (Y direction) in the figure, and are provided while maintaining electrical insulation from each of the scanning lines 12. Then, pixel circuits 110 are provided corresponding to the intersections of the m rows of scanning lines 12 and the (3n) columns of data lines 14. Therefore, in this embodiment, the pixel circuits 110 are arranged in a matrix of m vertical rows by (3n) horizontal columns.

Here, m and n are both natural numbers. In order to distinguish the rows of the matrix of the scanning lines 12 and pixel circuits 110, they may be called 1, 2, 3, ..., (m-1), m rows from the top in the figure. Similarly, in order to distinguish the columns of the matrix of the data lines 14 and pixel circuits 110, they may be called 1, 2, 3, ..., (3n-1), (3n) columns from the left in the figure. In addition, if an integer j between 1 and n is used to generalize the groups of the data lines 14, the j-th group counting from the left includes the data lines 14 in the (3j-2)th, (3j-1)th, and (3j)th columns.
The three pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the data lines 14 in three columns belonging to the same group correspond to R (red), G (green), and B (blue) pixels, respectively, and these three pixels express one dot of a color image to be displayed. That is, in this embodiment, the color of one dot is expressed by additive color mixing by the emission of OLEDs corresponding to RGB.

2, in the display unit 100, (3n) columns of power supply lines 16 are provided to extend in the vertical direction and to be electrically insulated from each of the scanning lines 12. A predetermined reset potential Vorst is commonly supplied to each of the power supply lines 16. In order to distinguish the columns of the power supply lines 16, they may be referred to as the 1st, 2nd, 3rd, ..., (3n), (3n+1)th power supply lines 16 from the left in the figure. Each of the 1st to (3n)th power supply lines 16 is provided corresponding to each of the 1st to (3n)th data lines 14.
The display panel 2 is provided with (3n) storage capacitors 50 corresponding to the first to (3n)th data lines 14, respectively. Each storage capacitor 50 has two electrodes. One electrode of the storage capacitor 50 is connected to the data line 14, and the other electrode is connected to the power supply line 16. That is, the storage capacitor 50 functions as a second storage capacitor that stores the potential of the data line 14. The storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the power supply line 16 and the data line 14 adjacent to each other. In this case, the distance between the power supply line 16 and the data line 14 adjacent to each other is determined so as to obtain a required capacitance. In the following, the capacitance value of the storage capacitor 50 is denoted as Cdt.
2, the storage capacitor 50 is provided outside the display unit 100, but this is merely an equivalent circuit, and the storage capacitor 50 may be provided inside the display unit 100. Moreover, the storage capacitor 50 may be provided from the inside to the outside of the display unit 100.

The scanning line driving circuit 20 generates a scanning signal Gwr for scanning the scanning lines 12 in sequence, row by row, over a frame period, in accordance with a control signal Ctr. Here, the scanning signals Gwr supplied to the 1st, 2nd, 3rd, ..., mth scanning lines 12 are denoted as Gwr(1), Gwr(2), Gwr(3), ..., Gwr(m-1), and Gwr(m), respectively.
In addition to the scanning signals Gwr(1) to Gwr(m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100, but these are not shown in Fig. 2. The frame period refers to the period required for the electro-optical device 1 to display one cut (frame) of image, and for example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, then the frame period is one cycle of the vertical synchronization signal, that is, 8.3 milliseconds.

The data line driving circuit 10 includes (3n) level shift circuits LS provided in one-to-one correspondence with each of the (3n) columns of data lines 14, n demultiplexers DM provided for each of the three columns of data lines 14 that make up each group, and a data signal supply circuit 70.
The data signal supply circuit 70 generates data signals Vd(1), Vd(2), ..., Vd(n) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 generates data signals Vd(1), Vd(2), ..., Vd(n) based on the image signal Vid obtained by time-division multiplexing the data signals Vd(1), Vd(2), ..., Vd(n). Then, the data signal supply circuit 70 supplies the data signals Vd(1), Vd(2), ..., Vd(n) to the demultiplexers DM corresponding to the 1st, 2nd, ..., nth groups, respectively. Also, the maximum value of the electric potential that the data signals Vd(1) to Vd(n) can take is defined as Vmax, and the minimum value is defined as Vmin.

Figure 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the level shift circuit LS. Note that Figure 3 representatively shows a demultiplexer DM belonging to the jth group and three level shift circuits LS connected to the demultiplexer DM. Note that hereinafter, the demultiplexer DM belonging to the jth group may be written as DM(j).

The configurations of the demultiplexer DM and the level shift circuit LS will be described below with reference to FIG. 3 in addition to FIG.
As shown in Fig. 3, the demultiplexer DM is a group of transmission gates 34 arranged for each column, and sequentially supplies data signals to the three columns constituting each group. Here, the input terminals of the transmission gates 34 corresponding to columns (3j-2), (3j-1), and (3j) belonging to the jth group are commonly connected to each other, and the data signal Vd(j) is supplied to each of the common terminals. The transmission gate 34 arranged in the leftmost column (3j-2) in the jth group is turned on (conductive) when the control signal Sel(1) is at H level (when the control signal /Sel(1) is at L level). Similarly, the transmission gate 34 provided in column (3j-1), which is the center column in the jth group, turns on when the control signal Sel(2) is at H level (when the control signal /Sel(2) is at L level), and the transmission gate 34 provided in column (3j), which is the rightmost column in the jth group, turns on when the control signal Sel(3) is at H level (when the control signal /Sel(3) is at L level).

The level shift circuit LS has a set of a holding capacitance 41, a holding capacitance 44, a P-channel MOS transistor 45 (first transistor), an N-channel MOS transistor 43 (second transistor), and a transmission gate 42 for each column, and shifts the potential of the data signal output from the output terminal of the transmission gate 34 of each column.
Here, the storage capacitor 44 has two electrodes. One electrode of the storage capacitor 44 is electrically connected to the data line 14 of the corresponding column and one of the source or drain of the transistor 45. The other electrode of the storage capacitor 44 is electrically connected to the output terminal of the transmission gate 42 and one of the source or drain of the transistor 43 via a node h1. That is, the storage capacitor 44 functions as a third storage capacitor having one electrode electrically connected to the data line 14. The capacitance value of the storage capacitor 44 is denoted as Crf1.

The other of the source or drain of the transistor 45 in each column is electrically connected to a power supply line 61 (first potential line). The control circuit 3 also supplies a control signal /Gini to the gates of the transistors 45 in each column in common. Therefore, the transistor 45 electrically connects one electrode of the storage capacitor 44 (and the data line 14) to the power supply line 61 when the control signal /Gini is at L level, and electrically disconnects the electrode from the power supply line 61 when the control signal /Gini is at H level. A predetermined initial potential Vini is supplied to the power supply line 61 from the control circuit 3.
The other of the source or drain of the transistor 43 in each column is electrically connected to a power supply line 62 (second potential line). The control circuit 3 also supplies a control signal Gref to the gates of the transistors 43 in each column in common. Therefore, the transistor 43 electrically connects the other electrode of the storage capacitor 44 and the node h1 to the power supply line 62 when the control signal Gref is at H level, and electrically disconnects them from the power supply line 62 when the control signal Gref is at L level. The control circuit 3 supplies the reference potential Vref to the power supply line 62.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to an input terminal of a transmission gate 42 via a node h2. The output terminal of the transmission gate 42 is electrically connected to the other electrode of the storage capacitor 44 via a node h1.
The control circuit 3 commonly supplies a control signal Gcpl and a control signal /Gcpl to the transmission gates 42 of each column. Therefore, the transmission gates 42 of each column are simultaneously turned on when the control signal Gcpl is at H level (when the control signal /Gcpl is at L level).
One electrode of the storage capacitor 41 of each column is electrically connected to the output terminal of the transmission gate 34 and the input terminal of the transmission gate 42 via the node h2. When the transmission gate 34 is turned on, the data signal Vd(j) is supplied to one electrode of the storage capacitor 41 via the output terminal of the transmission gate 34. That is, the storage capacitor 41 functions as a fourth storage capacitor having one electrode to which the data signal Vd(j) is supplied. The other electrode of the storage capacitor 41 of each column is commonly connected to a power supply line 63 to which a potential Vss, which is a fixed potential, is supplied. Here, the potential Vss may correspond to the L level of a scanning signal or a control signal, which is a logic signal. The capacitance value of the storage capacitor 41 is denoted as Crf2.

The pixel circuit 110 will be described with reference to FIG. 4. Since each pixel circuit 110 has the same configuration from an electrical perspective, the pixel circuit 110 in the i-th row and (3j-2)-th column, which is the leftmost column (3j-2) of the j-th group, will be described as an example. Note that i is a symbol that generally indicates the row in which the pixel circuits 110 are arranged, and is an integer between 1 and m.

4, the pixel circuit 110 includes P-channel MOS transistors 121 to 125, an OLED 130, and a storage capacitor 132. A scanning signal Gwr(i), control signals Gcmp(i), Gel(i), and Gorst(i) are supplied to this pixel circuit 110. Here, the scanning signal Gwr(i), and control signals Gcmp(i), Gel(i), and Gorst(i) are supplied by the scanning line driving circuit 20 in correspondence with the i-th row.
Although not shown in FIG. 2, the display panel 2 (display unit 100) is provided with m rows of control lines 143 (first control lines) extending horizontally (X direction) in FIG. 2, m rows of control lines 144 (second control lines) extending horizontally, and m rows of control lines 145 (third control lines) extending horizontally. The scanning line driving circuit 20 supplies control signals Gcmp(1), Gcmp(2), Gcmp(3), ..., Gcmp(m) to the control lines 143 in the first, second, third ..., mth rows, respectively, supplies control signals Gel(1), Gel(2), Gel(3), ..., Gel(m) to the control lines 144 in the first, second, third ..., mth rows, respectively, and supplies control signals Gorst(1), Gorst(2), Gorst(3), ..., Gorst(m) to the control lines 145 in the first, second, third ..., mth rows, respectively. That is, the scanning line driving circuit 20 commonly supplies the scanning signal Gwr(i) and the control signals Gel(i), Gcmp(i), and Gorst(i) to the (3n) pixel circuits located in the i-th row via the scanning line 12 and the control lines 143, 144, and 145 in the i-th row, respectively. Hereinafter, the scanning line 12, the control line 143, the control line 144, and the control line 145 may be collectively referred to as the "control line." That is, in the display panel 2 according to this embodiment, four control lines including the scanning line 12 are provided in each row.

The gate of the transistor 122 is electrically connected to the scanning line 12 in the i-th row, and one of the source and drain is electrically connected to the data line 14 in the (3j-2)th column. The storage capacitor 132 has two electrodes. The other of the source and drain of the transistor 122 is electrically connected to the gate of the transistor 121, one electrode of the storage capacitor 132, and one of the source and drain of the transistor 123, respectively. That is, the transistor 122 is electrically connected between the gate of the transistor 121 and the data line 14, and functions as a write transistor that controls the electrical connection between the gate of the transistor 121 and the data line 14. In the following, a wiring that electrically connects the gate of the transistor 121, the other of the source and drain of the transistor 122, one of the source and drain of the transistor 123, and one electrode of the storage capacitor 132 may be referred to as a gate node g (of the transistor 121).
The source of the transistor 121 is electrically connected to the power supply line 116, and the drain is electrically connected to the other of the source or the drain of the transistor 123 and the source of the transistor 124. A potential Vel which is the high side of the power supply in the pixel circuit 110 is supplied to the power supply line 116. The transistor 121 functions as a drive transistor which passes a current according to the voltage between the gate and source of the transistor 121.
The transistor 123 has a gate electrically connected to a control line 143 and is supplied with a control signal Gcmp(i). The transistor 123 functions as a first switching transistor that controls the electrical connection between the gate and drain of the transistor 121.
The transistor 124 has a gate electrically connected to a control line 144, and is supplied with a control signal Gel(i). The transistor 124 has a drain electrically connected to the source of the transistor 125 and the anode 130a of the OLED 130. The transistor 124 functions as a second switching transistor that controls the electrical connection between the drain of the transistor 121 and the anode of the OLED 130.
The transistor 125 has a gate electrically connected to the control line 145 and is supplied with a control signal Gorst(i). The drain of the transistor 125 is electrically connected to the power supply line 16 in the (3j-2)th column and is kept at a reset potential Vorst. This transistor 125 functions as a third switching transistor that controls the electrical connection between the power supply line 16 and the anode 130a of the OLED 130.
In this embodiment, since the display panel 2 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to potential Vel.
The sources and drains of the transistors 121 to 125 may be interchanged depending on the channel types and potential relationships of the transistors 121 to 125. The transistors may be thin film transistors or field effect transistors.

One electrode of the storage capacitor 132 is electrically connected to the gate of the transistor 121, and the other electrode is electrically connected to the power supply line 116. Therefore, the storage capacitor 132 functions as a first storage capacitor that stores the voltage between the gate and source of the transistor 121. The capacitance value of the storage capacitor 132 is represented as Cpix. At this time, the capacitance value Cdt of the storage capacitor 50, the capacitance value Crf1 of the storage capacitor 44, and the capacitance value Cpix of the storage capacitor 132 are expressed as follows:
Cdt>Crf1>>Cpix
That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1. Note that, as the storage capacitor 132, a capacitance parasitic on the gate node g of the transistor 121 may be used, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate may be used.

The anode 130a of the OLED 130 is a pixel electrode provided for each pixel circuit 110. In contrast, the cathode of the OLED 130 is a common electrode 118 provided in common to all pixel circuits 110, and is maintained at a potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between the anode 130a and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any of RGB is overlaid on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode recombine in the organic EL layer to generate excitons, which then generate white light. The white light generated at this time passes through the cathode on the opposite side to the silicon substrate (anode 130a), is colored by a color filter, and is then visible to the observer.

Next, the structure of the pixel circuit 110 will be described with reference to FIGS.
FIG. 5 is a plan view showing the configuration of the pixel circuit 110 in row i (3j-2) column. FIG. 5 shows the wiring structure when the pixel circuit 110 with a top emission structure is viewed in plan from the observation side, but for simplification, structures formed after the anode 130a of the OLED 130 are omitted. FIG. 6 is a partial cross-sectional view taken along line E-e in FIG. 5. In FIG. 6, up to the anode 130a of the OLED 130 is shown, and structures thereafter are omitted. Note that in FIG. 5 and FIG. 6, the scales may be different in order to make each layer, each member, each region, and the like recognizable.

As shown in Fig. 6, each element constituting the pixel circuit 110 is formed on a silicon substrate 150. In this embodiment, a P-type semiconductor substrate is used as the silicon substrate 150. An N-well 160 is formed over almost the entire surface of the silicon substrate 150. Note that in Fig. 5, in order to easily grasp the region in which the transistors 121 to 125 are provided when viewed in a plan view, only the region in the N-well 160 in which the transistors 121 to 125 are provided and the vicinity thereof are shown with hatching.
A potential Vel is supplied to the N-well 160 via an N-type diffusion layer (not shown), so that the substrate potential of the transistors 121 to 125 is the potential Vel.

As shown in Figures 5 and 6, multiple P-type diffusion layers are formed by doping ions on the surface of the N-well 160. Specifically, nine P-type diffusion layers P1 to P9 are formed on the surface of the N-well 160 for each pixel circuit 110. These P-type diffusion layers P1 to P9 function as the sources or drains of the transistors 121 to 125. In addition, a gate insulating layer L0 is formed on the surfaces of the N-well 160 and the P-type diffusion layers P1 to P9, and gate electrodes G1 to G5 are formed on the surface of the gate insulating layer L0 by patterning. These gate electrodes G1 to G5 function as the gates of the transistors 121 to 125, respectively.

5, the transistor 121 has a gate electrode G1, a P-type diffusion layer P1, and a P-type diffusion layer P2. Of these, the P-type diffusion layer P1 functions as the source of the transistor 121, and the P-type diffusion layer P2 functions as the drain of the transistor 121.
The transistor 122 also has a gate electrode G2, a P-type diffusion layer P3, and a P-type diffusion layer P4. Of these, the P-type diffusion layer P3 functions as one of the source and drain of the transistor 122, and the P-type diffusion layer P4 functions as the other of the source and drain of the transistor 122.
The transistor 123 has a gate electrode G3, a P-type diffusion layer P4, and a P-type diffusion layer P5. Of these, the P-type diffusion layer P4 functions as one of the source and drain of the transistor 123, and the P-type diffusion layer P5 functions as the other of the source and drain of the transistor 123. In other words, the P-type diffusion layer P4 functions as the other of the source and drain of the transistor 122, and also functions as one of the source and drain of the transistor 123.
The transistor 124 has a gate electrode G4, a P-type diffusion layer P6, and a P-type diffusion layer P7. Of these, the P-type diffusion layer P6 functions as the source of the transistor 124, and the P-type diffusion layer P7 functions as the drain of the transistor 124.
In this embodiment, the drain of the transistor 121, the source or the other of the drain of the transistor 123, and the source of the transistor 124 are respectively configured with separate P-type diffusion layers P2, P5, and P6, but may be configured with a single P-type diffusion layer. In this case, it is not necessary to provide a relay node N13 described later.
The transistor 125 has a gate electrode G5, a P-type diffusion layer P8, and a P-type diffusion layer P9. Of these, the P-type diffusion layer P8 functions as the source of the transistor 125, and the P-type diffusion layer P9 functions as the drain of the transistor 125.

As shown in FIG. 6, a first interlayer insulating layer L1 is formed so as to cover the gate electrodes G1 to G5 and the gate insulating layer L0.
On the surface of the first interlayer insulating layer L1, a conductive wiring layer made of aluminum or the like is patterned to form the scanning lines 12, the power supply lines 116, and the control lines 143 to 145 for each row, and also form the relay nodes N11 to N16 and the branching portion 116a for each pixel circuit 110. Note that these wiring layers formed on the surface of the first interlayer insulating layer L1 may be collectively referred to as the first wiring layer.

5, the power supply line 116 extends in the X direction intersecting with the Y axis direction, and has a portion (branch portion 116a) branched in the Y direction for each pixel circuit 110. When viewed in a plan view (i.e., when the pixel circuit 110 is viewed from a direction perpendicular to the surface of the silicon substrate 150 on which the pixel circuit 110 is arranged), the branch portion 116a is provided so that a part of the branch portion 116a overlaps with the P-type diffusion layer P1. Also, as shown in FIG. 5 and FIG. 6, the branch portion 116a is electrically connected to the P-type diffusion layer P1 through a contact hole Ha1 penetrating the first interlayer insulating layer L1. Note that in FIG. 5, the contact hole is shown as a part where different wiring layers overlap with a "□" with a "X" mark.

5, the scanning line 12 extends in the X direction and is provided so as to intersect with the gate electrodes G1 and G2 in a plan view. That is, in a plan view, at least a part of the scanning line 12 overlaps with at least a part of the gate electrode G1. The scanning line 12 is electrically connected to the gate electrode G2 through a contact hole Ha5.
The control line 143 extends in the X direction and is provided so as to intersect with the gate electrode G1 and the gate electrode G3 in a plan view. The control line 143 is electrically connected to the gate electrode G3 through a contact hole Ha7.
The control line 144 extends in the X direction, is provided so as to intersect with the gate electrode G4 in a plan view, and is electrically connected to the gate electrode G4 through a contact hole Ha10. The control line 145 extends in the X direction, is provided so as to intersect with the gate electrode G5 in a plan view, and is electrically connected to the gate electrode G5 through a contact hole Ha14.

5 and 6, the relay node N11 is electrically connected to the gate electrode G1 through the contact hole Ha2, and is also electrically connected to the P-type diffusion layer P4 through the contact hole Ha6. That is, the relay node N11 corresponds to a gate node g that electrically connects the gate of the transistor 121, the other of the source or drain of the transistor 122, and one of the source or drain of the transistor 123.
The relay node N16 is provided such that a portion of the relay node N16 and the gate electrode G1 overlap each other in a plan view. The relay node N16 and the gate electrode G1 sandwich the first interlayer insulating layer L1 to form a storage capacitor 132. That is, the gate electrode G1 corresponds to one electrode of the storage capacitor 132, and the relay node N16 corresponds to the other electrode of the storage capacitor 132.
The relay node N12 is electrically connected to the P-type diffusion layer P3 via a contact hole Ha4. The relay node N13 is electrically connected to the P-type diffusion layer P2 via a contact hole Ha3, electrically connected to the P-type diffusion layer P5 via a contact hole Ha8, and electrically connected to the P-type diffusion layer P6 via a contact hole Ha9. The relay node N14 is electrically connected to the P-type diffusion layer P7 via a contact hole Ha11, and electrically connected to the P-type diffusion layer P8 via a contact hole Ha12. The relay node N15 is electrically connected to the P-type diffusion layer P9 via a contact hole Ha13.

As shown in FIG. 6, a second interlayer insulating layer L2 is formed so as to cover the first wiring layer and the first interlayer insulating layer L1.
On the surface of the second interlayer insulating layer L2, a conductive wiring layer made of aluminum or the like is patterned to form data lines 14 and power supply lines 16 for each column, and also form relay nodes N21, N22 for each pixel circuit 110. Note that these wiring layers formed on the surface of the second interlayer insulating layer L2 may be collectively referred to as a second wiring layer.
5, the data line 14 is electrically connected to the relay node N12 through the contact hole Hb2. As a result, the P-type diffusion layer P3 is electrically connected to the data line 14 through the relay node N12. The power supply line 16 is electrically connected to the relay node N15 through the contact hole Hb3. As a result, the P-type diffusion layer P9 is electrically connected to the power supply line 16 through the relay node N15. The relay node N21 is electrically connected to the power supply line 116 through the contact hole Hb1, and is electrically connected to the relay node N16 (the other electrode of the storage capacitor 132) through the contact hole Hb4. As a result, the relay node N16 is electrically connected to the power supply line 116 through the relay node N21 and is maintained at the potential Vel.
As shown in FIG. 6, the relay node N22 is electrically connected to the relay node N14 via a contact hole Hb5.

As shown in FIG. 6, a third interlayer insulating layer L3 is formed so as to cover the second wiring layer and the second interlayer insulating layer L2.
On the surface of the third interlayer insulating layer L3, a conductive wiring layer such as aluminum or ITO (Indium Tin Oxide) is patterned to form the anode 130a of the OLED 130. The anode 130a of the OLED 130 is an individual pixel electrode for each pixel circuit 110, and is connected to the relay node N22 via a contact hole Hc1 that penetrates the third interlayer insulating layer L3. That is, the anode 130a of the OLED 130 is electrically connected to the P-type diffusion layer P7 (i.e., the drain of the transistor 124) and the P-type diffusion layer P8 (i.e., the source of the transistor 125) via the relay node N22 and the relay node N14.
Although not shown, a light-emitting layer made of an organic EL material is laminated on the anode 130a of the OLED 130, which is divided for each pixel circuit 110. A cathode (common electrode 118) that is a transparent electrode common to all of the pixel circuits 110 is provided on the light-emitting layer. That is, the OLED 130 sandwiches the light-emitting layer between the anode and cathode facing each other, and emits light with a luminance according to the current flowing from the anode to the common electrode 118. Of the light emitted by the OLED 130, the light that travels in the opposite direction to the silicon substrate 150 (i.e., upward in FIG. 6) is visually recognized by the observer as an image (top emission structure). In addition, a sealant or the like is provided to shield the light-emitting layer from the atmosphere, but the description thereof is omitted.

<Operation of the embodiment>
The operation of the electro-optical device 1 will be described with reference to FIG. 7. FIG. 7 is a timing chart for explaining the operation of each part of the electro-optical device 1. As shown in this figure, the scanning line driving circuit 20 sequentially switches the scanning signals Gwr(1) to Gwr(m) to the L level, and sequentially scans the 1st to mth scanning lines 12 for each horizontal scanning period (H) during one frame period. The operation during one horizontal scanning period (H) is common to the pixel circuits 110 of each row. Therefore, the following description will focus on the operation of the pixel circuit 110 in the i-th row (3j-2) column during the scanning period in which the i-th row is horizontally scanned.

In this embodiment, the scanning period of the i-th row is roughly divided into an initialization period shown in FIG. 7 (b), a compensation period shown in FIG. 7 (c), and a writing period shown in FIG. 7 (d). After the writing period shown in FIG. 7 (d), the light emission period shown in FIG. 7 (a) begins, and after one frame period has elapsed, the scanning period of the i-th row begins again. Therefore, in terms of time, the cycle is repeated as follows: (light emission period) → initialization period → compensation period → writing period → (light emission period).
In addition, in FIG. 7, the scanning signal Gwr(i-1), control signal Gel(i-1), Gcmp(i-1), and Gorst(i-1) corresponding to the (i-1) row immediately preceding the i-th row each have a waveform that temporally precedes the scanning signal Gwr(i), control signal Gel(i), Gcmp(i), and Gorst(i) corresponding to the i-th row by one horizontal scanning period (H).

<Light Emitting Period>
For convenience of explanation, the light emission period, which is a premise of the initialization period, will be described first. In the light emission period of the i-th row, the scanning line driving circuit 20 supplies a predetermined second potential V2 to the i-th scanning line 12, supplies a predetermined first potential V1 to the i-th control line 144, supplies a second potential V2 to the i-th control line 143, and supplies a second potential V2 to the i-th control line 145. In this embodiment, the first potential V1 is set lower than the second potential V2. For example, the first potential V1 may be equivalent to the L level of the control signal (control signal Gref, etc.) supplied by the control circuit 3, and the second potential VH may be equivalent to the H level of the control signal supplied by the control circuit 3. That is, as shown in FIG. 7, in the light emission period of the i-th row, the scanning signal Gwr(i) is set to the H level, the control signal Gel(i) is set to the L level, the control signal Gcmp(i) is set to the H level, and the control signal Gorst(i) is set to the H level.
8, in the pixel circuit 110 in row i (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies the OLED 130 with a current Ids according to the gate-source voltage Vgs. As will be described later, in this embodiment, the voltage Vgs during the light emission period is a value obtained by level-shifting the potential of the data signal. Therefore, the OLED 130 is supplied with a current according to the grayscale level with the threshold voltage of the transistor 121 compensated for.

Note that the light emission period of the i-th row is a period during which rows other than the i-th row are horizontally scanned, so the potential of the data line 14 fluctuates appropriately. However, in the i-th row pixel circuit 110, the transistor 122 is off, so the potential fluctuation of the data line 14 is not taken into consideration here. Also, in Figure 8, paths that are important in explaining the operation during the light emission period are shown in bold.

<Initialization period>
Next, when the scanning period for the i-th row is reached, the initialization period (b) starts as the first period.
7, in the initialization period of the i-th row, the scanning line driving circuit 20 supplies the second potential V2 to the i-th scanning line 12 to set the scanning signal Gwr(i) to the H level, supplies the second potential V2 to the i-th control line 144 to set the control signal Gel(i) to the H level, supplies the second potential V2 to the i-th control line 143 to set the control signal Gcmp(i) to the H level, and supplies the first potential V1 to the i-th control line 145 to set the control signal Gorst(i) to the L level. Therefore, in the pixel circuit 110 of the i-th row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode 130a of the OLED 130 is set to the reset potential Vorst.
As described above, the OLED 130 has a configuration in which an organic EL layer is sandwiched between the anode 130a and the cathode, and therefore a capacitance is parasitic in parallel between the anode and the cathode. When a current flows through the OLED 130 during a light emission period, the voltage across the anode and the cathode of the OLED 130 is held by the capacitance parasitic in parallel between the anode and the cathode, but this held voltage is reset by turning on the transistor 125. Therefore, in this embodiment, when a current flows again through the OLED 130 during a later light emission period, the OLED 130 is less susceptible to the influence of the voltage held by the capacitance parasitic in parallel between the anode and the cathode.

In detail, for example, if the configuration is not reset when switching from a high-luminance display state to a low-luminance display state, the high voltage when the luminance is high (a large current flows) is maintained, so that even if a small current is next attempted to flow, an excessive current flows, making it impossible to switch to a low-luminance display state. In contrast, in this embodiment, the potential of the anode 130a of the OLED 130 is reset by turning on the transistor 125, so that the reproducibility of the low-luminance side is improved. In this embodiment, the reset potential Vorst is set so that the difference between the reset potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, during the initialization period (the compensation period and writing period described next), the OLED 130 is in an off (non-light-emitting) state.

On the other hand, in the initialization period of the i-th row, the control circuit 3 sets the control signal /Gini to the L level, the control signal Gref to the H level, and the control signal Gcpl to the L level, as shown in Fig. 7. Therefore, the transistors 43 and 45 are turned on. As a result, one electrode of the storage capacitor 44 is electrically connected to the power supply line 61, and one electrode of the storage capacitor 44 (and the data line 14) is initialized to the initial potential Vini. In addition, the other electrode of the storage capacitor 44 is electrically connected to the power supply line 62, and the other electrode of the storage capacitor 44 (and the node h1) is initialized to the reference potential Vref.
In this embodiment, the initial potential Vini is set so that (Vel-Vini) is greater than the threshold voltage |Vth| of the transistor 121. Since the transistor 121 is a P-channel type, the threshold voltage Vth based on the source potential is negative. Therefore, in order to prevent confusion in explaining the high-low relationship, the threshold voltage is expressed as an absolute value |Vth| and is specified in terms of the large-small relationship.

7, during the period from the start of the scanning period for the i-th row until the start of the writing period, the data signal supply circuit 70 supplies data signals Vd(1), Vd(2), ..., Vd(n) to each of the demultiplexers DM(1), DM(2), ..., DM(n), respectively. That is, the data signal supply circuit 70 switches the data signal Vd(j) in the j-th group to potentials corresponding to the gradation levels of the pixels in the i-th row (3j-2) column, the i-th row (3j-1) column, and the i-th row (3j) column, in that order.
Meanwhile, the control circuit 3 sequentially and exclusively sets the control signals Sel(1), Sel(2), and Sel(3) to H level in accordance with the switching of the potential of the data signal, thereby turning on the three transmission gates 34 provided in each demultiplexer DM in the order of the leftmost column, the center column, and the rightmost column.
Here, during the initialization period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel(1), the data signal Vd(j) is supplied to one electrode of the storage capacitor 41, and the data signal Vd(j) is stored in the storage capacitor 41.

<Coverage period>
In the scanning period of the i-th row, the second period is the compensation period (c). In the compensation period of the i-th row, the control circuit 3 sets the control signal /Gini to H level, the control signal Gref to H level, and the control signal Gcpl to L level, as shown in FIG. 7. Therefore, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other electrode of the storage capacitor 44 and the power supply line 62 are electrically connected, and the node h1 is set to the reference potential Vref.

Furthermore, during the compensation period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel( 1 ), the data signal Vd(j) is supplied to one electrode of the storage capacitor 41 .
It should be noted that if the transmission gate 34 in the leftmost column belonging to the jth group has already been turned on by the control signal Sel(1) during the initialization period, then the transmission gate 34 will not be turned on during the compensation period. However, the data signal Vd(j) supplied when the transmission gate 34 in the leftmost column was turned on is held by the holding capacitance 41.

7, the scanning line driving circuit 20 supplies the first potential V1 to the scanning line 12 of the i-th row to set the scanning signal Gwr(i) to the L level, supplies the second potential V2 to the control line 144 of the i-th row to set the control signal Gel(i) to the H level, supplies the first potential V1 to the control line 143 of the i-th row to set the control signal Gcmp(i) to the L level, and supplies the first potential V1 to the control line 145 of the i-th row to set the control signal Gorst(i) to the L level. Therefore, the transistor 123 is turned on, and the transistor 121 is diode-connected. As a result, a drain current flows through the transistor 121 to charge the gate node g and the data line 14. In detail, the current flows through the power supply line 116 → transistor 121 → transistor 123 → transistor 122 → data line 14 of the (3j-2)th column. Therefore, the data line 14 and the gate node g, which are connected to each other by turning on the transistor 121, rise from the initial potential Vini. However, since the current flowing through the above path becomes more difficult as the gate node g approaches the potential (Vel-|Vth|), the data line 14 and the gate node g are saturated at the potential (Vel-|Vth|) by the time the compensation period ends.
Therefore, at the end of the compensation period, the storage capacitor 132 holds the threshold voltage |Vth| of the transistor 121. Note that, hereinafter, the potential (Vel-|Vth|) of the gate node g at the end of the compensation period may be expressed as potential Vp.

When the compensation period ends, the scanning line driving circuit 20 switches the potential supplied to the control line 143 from the first potential V1 to the second potential V2, thereby changing the control signal Gcmp(i) from the L level to the H level. This releases the diode connection of the transistor 121.
The scanning line driving circuit 20 switches the potential supplied to the control line 143 so that the waveform of the control signal Gcmp(i) when it changes from an L level to an H level becomes gentler than the waveform when it changes from an H level to an L level. That is, as shown in Fig. 7, a period during which the scanning line driving circuit 20 switches the potential supplied to the control line 143 from the second potential V2 to the first potential V1 is defined as a third switching period T3, and a period during which the scanning line driving circuit 20 switches the potential from the first potential V1 to the second potential V2 is defined as a fourth switching period T4. At this time, the scanning line driving circuit 20 changes the potential supplied to the control line 143 so that the time length of the fourth switching period T4 is sufficiently longer than the time length of the third switching period T3.

As described above, the control line 143 and the gate electrode G1 (the gate of the transistor 121) intersect in a plan view. Therefore, a parasitic capacitance exists between the control line 143 and the gate electrode G1. Therefore, if the time length of the fourth switching period T4 is shortened to the same extent as the time length of the third switching period T3 and the control signal Gcmp(i) is suddenly raised from an L level to an H level, the potential of the gate electrode G1 changes due to the influence of the high-frequency component of the control signal Gcmp(i) in the control line 143.
Although details will be described later, at the end of the compensation period, the potential of the gate node g (the potential of the gate electrode G1) is set to a potential that compensates for the variation in the threshold voltage of the transistor 121 for each pixel circuit 110. However, if the potential of the gate node g changes after the end of the compensation period, it becomes impossible to compensate for the variation in the threshold voltage for each pixel circuit 110, and the problem of display unevenness that impairs the uniformity of the display screen becomes prominent.
In contrast, in this embodiment, the time length of the fourth switching period T4 is made sufficiently longer than the time length of the third switching period T3, and the waveform of the control signal Gcmp(i) when it changes from L level to H level is made gentle, thereby preventing the potential fluctuation of the control line 143 from propagating to the gate node g (gate electrode G1). This compensates for the variation in threshold voltage for each pixel circuit 110, and enables a high-quality display that ensures display uniformity.

In practice, the duration of the third switching period T3 is sufficiently short that it can be considered to be "0". In other words, the waveform of the control signal Gcmp(i) when it falls from H level to L level may be equal to the waveform of the control signal Gref when it falls from H level to L level, for example. However, in FIG. 7, for the sake of convenience, the falling waveform of the control signal Gcmp(i) is depicted as a more gradual waveform than the actual waveform in order to illustrate the third switching period T3.

When the compensation period ends, the control circuit 3 changes the control signal Gref from H level to L level, turning off the transistor 43. As a result, the path from the data line 14 in the (3j-2)th column to the gate node g in the pixel circuit 110 in the i-th row and (3j-2)th column becomes floating, but the potential of the path is maintained at (Vel-|Vth|) by the storage capacitors 50 and 132.

<Writing period>
After the initialization period, the third period is the writing period (d). In the writing period of the i-th row, the scanning line driving circuit 20 supplies the first potential V1 to the i-th scanning line 12 to set the scanning signal Gwr(i) to the L level, supplies the second potential V2 to the i-th control line 144 to set the control signal Gel(i) to the H level, supplies the second potential V2 to the i-th control line 143 to set the control signal Gcmp(i) to the H level, and supplies the first potential V1 to the i-th control line 145 to set the control signal Gorst(i) to the L level, as shown in FIG. 7. This releases the diode connection of the transistor 121.

7, in the writing period of the i-th row, the control circuit 3 sets the control signal /Gini to H level, the control signal Gref to L level, and the control signal Gcpl to H level. Therefore, the transmission gate 42 is turned on, and the data signal Vd(j) held in the holding capacitance 41 is supplied to the other electrode of the holding capacitance 44 via the node h1. As a result, the node h1 and the other electrode of the holding capacitance 44 change from the reference potential Vref in the compensation period. The amount of change in potential of the node h1 at this time is represented as ΔVh. The potential of the node h1 in the writing period (Vref+ΔVh) may be represented as potential Vh.
When the potential of the node h1 changes by ΔVh from the reference potential Vref to the potential Vh, the potentials of the gate node g and the data line 14 also change from the potential Vp = (Vel - |Vth|) set during the compensation period. The amount of change in the potential of the gate node g at this time is represented as ΔVg. The potential of the gate node g during the writing period (Vp + ΔVg) may be represented as the potential Vgate.

In the following, the changes in the potentials of the gate node g and the node h1 before and after the start of the writing period will be described in detail with reference to FIG.
9A is an explanatory diagram for explaining the potential changes of the node h1 and the gate node g before and after the start of the write period. In this figure, (A-1) shows the potentials of the node h1 and the gate node g before the start of the write period, and (A-2) shows the potentials of the node h1 and the gate node g after the start of the write period (i.e., after the transmission gate 42 is turned on). Note that, since the storage capacitor 50 and the storage capacitor 132 are electrically connected in parallel during the compensation period and the write period, the capacitance value C0 of the combined capacitance 501 of the storage capacitor 50 and the storage capacitor 132 is expressed by the following formula (1).
C0 = Cpix + Cdt ... (1)

If the charge stored in the combined capacitance 501 before the start of the write period is Q0a and the charge stored in the combined capacitance 501 after the start of the write period is Q0b, the charge (Q0a-Q0b) flowing out of the combined capacitance 501 before and after the start of the write period is expressed by the following formula (2). Similarly, if the charge stored in the holding capacitance 44 before the start of the write period is Q1a and the charge stored in the holding capacitance 44 after the start of the write period is Q1b, the charge (Q1b-Q1a) flowing into the holding capacitance 44 before and after the start of the write period is expressed by the following formula (3). Before and after the start of the write period, the charge flowing out of the combined capacitance 501 and the charge flowing into the holding capacitance 44 are equal, so the following formula (4) holds.
Q0a-Q0b = C0*(Vp-Vgate) ... (2)
Q1b-Q1a=Crf1*{(Vgate-Vh)-(Vp-Vref)} ... (3)
Q0a-Q0b = Q1b-Q1a ... (4)

The potential Vgate of the gate node g during the writing period can be calculated from the formulas (2) to (4). Specifically, the potential Vgate is expressed by the following formula (5).
Vgate = {Crf1/(Crf1+C0)} * {Vh-Vref} + Vp ... (5)

Here, a capacitance ratio k1 shown in the following formula (6) is introduced. At this time, the potential Vgate of the gate node g during the writing period can be expressed by the following formula (7) using the capacitance ratio k1, and the potential change amount ΔVg of the gate node g before and after the start of the writing period can be expressed by the following formula (8) using the capacitance ratio k1.
k1 = Crf1 / (Crf1 + Cdt + Cpix) ... (6)
Vgate = k1 * (Vh - Vref) + Vp
= k1 * ΔVh + Vp … (7)
ΔVg = Vgate - Vp
= k1 * ΔVh … (8)

In this way, during the write period, the potential of the gate node g changes from the potential Vp=(Vel-|Vth|) during the compensation period to a potential Vgate=(Vel-|Vth|+k1·ΔVh) which is shifted upward by the value (k1*ΔVh) obtained by multiplying the amount of potential change ΔVh of the node h1 by the capacitance ratio k1. At this time, the absolute value |Vgs| of the voltage Vgs of the transistor 121 is a value obtained by subtracting the amount of potential rise of the gate node g from the threshold voltage |Vth|, as shown in the following equation (9).
|Vgs| = |Vth| -k1 * ΔVh ... (9)

9B is an explanatory diagram for explaining the potential changes of the nodes h1 and h2 before and after the start of the write period. In this figure, (B-1) shows the potentials of the nodes h1 and h2 before the start of the write period, and (B-2) shows the potentials of the nodes h1 and h2 after the start of the write period (i.e., after the transmission gate 42 is turned on). Note that during the compensation period and the write period, the combined capacitance 501 of the storage capacitance 50 and the storage capacitance 132 and the storage capacitance 41 are electrically connected in series, so that the capacitance value C1 of the combined capacitance 502 of the storage capacitance 50, the storage capacitance 132, and the storage capacitance 44 is expressed by the following formula (10).
C1 = (C0 * Crf1) / (C0 + Crf1) ... (10)

If the charge stored in the combined capacitance 502 before the start of the write period is Q1c and the charge stored in the combined capacitance 502 after the start of the write period is Q1d, the charge (Q1c-Q1d) flowing out of the combined capacitance 502 before and after the start of the write period is expressed by the following formula (11). Similarly, if the charge stored in the holding capacitance 41 before the start of the write period is Q2c and the charge stored in the holding capacitance 41 after the start of the write period is Q2d, the charge (Q2d-Q2c) flowing into the holding capacitance 41 before and after the start of the write period is expressed by the following formula (12). Before and after the start of the write period, the charge flowing out of the combined capacitance 502 and the charge flowing into the holding capacitance 41 are equal, so the following formula (13) holds.
Q1c-Q1d = C1*{Vref-Vh} ... (11)
Q2d-Q2c = Crf2*{Vh-Vd(j)} ... (12)
Q1c-Q1d = Q2d-Q2c … (13)

Therefore, the potential Vh of the node h1 during the writing period can be calculated from equations (11) to (13). Specifically, the potential Vh is expressed by the following equation (14). Moreover, the amount of potential change ΔVh at the node h1 is expressed by the following equation (15).
Vh = {C1/(C1+Crf2)}*(Vref)
+ {Crf2/(C1+Crf2)}*{Vd(j)} ... (14)
ΔVh = Vh - Vref
= {Crf2/(C1+Crf2)}*{Vd(j)-Vref} ... (15)

Here, when the capacitance ratio k2 shown in the following equation (16) is introduced, the amount of potential change ΔVh can also be expressed by the following equation (17).
k2 = Crf2 / (C1 + Crf2) ... (16)
ΔVh = k2 * {Vd(j) - Vref} ... (17)

The potential Vgate of the gate node g during the writing period can be expressed by the following formula (18) by substituting formula (17) into formula (7). Therefore, the potential change amount ΔVg of the gate electrode G before and after the start of the writing period can be expressed by the following formula (19).
Vgate = k1 * k2 * {Vd(j) - Vref} + Vp ... (18)
ΔVg = k1 * k2 * {Vd(j) - Vref} ... (19)

In this way, the potential of node h1 changes by a value ΔVh obtained by shifting the potential indicated by data signal Vd(j) by reference potential Vref and compressing it by capacitance ratio k2. As a result, the potential Vgate of gate node g changes by a value obtained by further compressing the amount of potential change ΔVh of node h1 by capacitance ratio k1. That is, as shown in equation (18), the potential Vgate of gate node g during the write period is supplied with a compressed potential by shifting data signal Vd(j) by reference potential Vref and multiplying the shifted potential by capacitance ratio k3 = k1 * k2 determined based on capacitance values Cdt, Crf1, Crf2, and Cpix.

10 is a diagram showing the relationship between the potential of the data signal Vd(j) and the potential Vgate of the gate node g during the writing period. The data signal Vd(j) generated based on the image signal Vid supplied from the control circuit 3 can have a potential range from a minimum value Vmin to a maximum value Vmax according to the gradation level of the pixel as described above. Then, as described above, the data signal Vd(j) is shifted by the reference potential Vref and the potential Vgate compressed by the capacitance ratio k3 is written to the gate node g. At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (=Vmax-Vmin) of the data signal by the capacitance ratio k3 as shown in the following formula (20).
ΔVgate = k3 * ΔVdata ... (20)

Furthermore, as is clear from equation (18), the direction and amount by which the potential range ΔVgate of the gate node g is shifted relative to the potential range ΔVdata of the data signal can be determined based on the potential Vp (=Vel-|Vth|) and the reference potential Vref.

After the writing period ends, the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2, thereby changing the scanning signal Gwr(i) from the L level to the H level. This turns off the transistor 122, so that the potential of the gate node g is maintained at the potential Vgate = [{Vel - |Vth|} + k3 · {Vd(j) - Vref}].
The scanning line driving circuit 20 switches the potential supplied to the scanning line 12 so that the waveform of the scanning signal Gwr(i) when it changes from an L level to an H level becomes gentler than the waveform when it changes from an H level to an L level. That is, as shown in Fig. 7, a period during which the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the second potential V2 to the first potential V1 is defined as a first switching period T1, and a period during which the scanning line driving circuit 20 switches the potential from the first potential V1 to the second potential V2 is defined as a second switching period T2. At this time, the scanning line driving circuit 20 changes the potential supplied to the scanning line 12 so that the time length of the second switching period T2 is sufficiently longer than the time length of the first switching period T1.

As described above, the scanning line 12 and the gate electrode G1 (the gate of the transistor 121) intersect in a plan view. Therefore, a parasitic capacitance exists between the scanning line 12 and the gate electrode G1. Therefore, if the time length of the second switching period T2 is shortened to the same extent as the time length of the first switching period T1 and the scanning signal Gwr(i) is suddenly raised from the L level to the H level, the potential of the gate electrode G1 changes due to the influence of the high-frequency component of the scanning signal Gwr(i) in the scanning line 12.
As described above, at the end of the writing period, the potential of the gate node g (the potential of the gate electrode G1) is determined to be the potential Vgate based on the data signal Vd(j) (image signal Vid) that defines the luminance of the OLED 130. However, if the potential of the gate node g changes after the end of the writing period, the potential of the gate node g becomes a potential different from the potential Vgate that is determined based on the data signal Vd(j). In this case, each pixel displays a gradation different from the gradation defined by the image signal Vid, and the display quality is degraded.
In contrast, in this embodiment, the time length of the second switching period T2 is made sufficiently longer than the time length of the first switching period T1, and the waveform of the scanning signal Gwr(i) when it changes from L level to H level is made to be a gentle waveform, thereby preventing the potential fluctuation of the scanning line 12 from propagating to the gate node g (gate electrode G1). This enables each pixel to accurately display the gradation defined by the image signal Vid, enabling high-quality display.

In reality, the duration of the first switching period T1 is short enough to be considered to be "0". In other words, the waveform of the scanning signal Gwr(i) when it falls from H level to L level may be equal to the waveform of the control signal Gref when it falls from H level to L level, for example. However, in FIG. 7, for the sake of convenience, the falling waveform of the scanning signal Gwr(i) is depicted to be sufficiently gentler than in reality in order to illustrate the first switching period T1.

<Light Emitting Period>
After the writing period of the i-th row is completed, the light emission period is started. In this embodiment, after the writing period of the i-th row is completed, the light emission period is started after one horizontal scanning period. During the light emission period, the scanning line driving circuit 20 sets the scanning signal Gwr(i) to the H level as described above, so that the transistor 122 is turned off and the gate node g is maintained at the potential Vgate = [{Vel - |Vth|} + k3 · {Vd(j) - Vref}]. Also, during the light emission period, the scanning line driving circuit 20 sets the control signal Gel(i) to the L level, so that the transistor 124 is turned on in the pixel circuit 110 of the i-th row (3j-2) column. Since the gate-source voltage Vgs is [|Vth| - k3 · {Vd(j) - Vref}], the OLED 130 is supplied with a current according to the grayscale level while compensating for the threshold voltage of the transistor 121, as shown in FIG. 8 above.
Such an operation is executed in parallel in time in the other pixel circuits 110 in the i-th row other than the (3j-2)th column pixel circuit 110 during the scanning period of the i-th row. Furthermore, such an operation in the i-th row is actually executed in the order of the 1st, 2nd, 3rd, ..., (m-1) and mth rows during one frame period, and is repeated for each frame.

Effects of the embodiment
According to this embodiment, the scanning line 12 and the control line 143 are provided at positions intersecting with the gate (gate electrode G1) of the transistor 121 in plan view. Therefore, compared to a case where the scanning line 12 and the control line 143 are provided so as not to intersect with the gate of the transistor 121, the multiple control lines (scanning line 12, control lines 143, 144, 145) extending in the X direction can be wired at a high density, and the pitch of the control lines can be narrowed. That is, according to this embodiment, by wiring the control lines at a high density, the pitch of the pixel circuits 110 can be narrowed, and thus the electro-optical device 1 (display unit 100) can be made smaller and the display can be made more precise.

According to this embodiment, the scanning line driving circuit 20 changes the potential supplied to the scanning line 12 so that the waveform of the scanning signal Gwr(i) when it changes from an L level to an H level is gentler than the waveform when it changes from an H level to an L level. This prevents the potential fluctuation of the scanning signal Gwr(i) from propagating to the gate of the transistor 121 even when the scanning line 12 and the gate of the transistor 121 intersect in a planar view, so that each pixel can accurately display the gradation defined by the image signal Vid.

According to this embodiment, the scanning line driving circuit 20 changes the potential supplied to the control line 143 so that the waveform of the control signal Gcmp(i) when it changes from an L level to an H level is gentler than the waveform when it changes from an H level to an L level. This makes it possible to prevent the potential fluctuation of the control signal Gcmp(i) from propagating to the gate of the transistor 121 even when the control line 143 and the gate of the transistor 121 intersect in a plan view, thereby enabling a high-quality display that ensures uniformity in the display.

According to this embodiment, the potential range ΔVgate at the gate node g is narrowed relative to the potential range ΔVdata of the data signal, so a voltage reflecting the gradation level can be applied between the gate and source of the transistor 121 without the need to precisely divide the data signal. Therefore, even if the minute current flowing through the OLED 130 changes relatively greatly in response to a change in the gate-source voltage Vgs of the transistor 121 in the pixel circuit 110, it becomes possible to precisely control the current supplied to the OLED 130.

4, a capacitance Cprs may be parasitic between the data line 14 and the gate node g of the pixel circuit 110. In this case, if the potential change width of the data line 14 is large, it propagates to the gate node g via the capacitance Cprs, causing so-called crosstalk and unevenness, thereby degrading the display quality. The effect of the capacitance Cprs becomes more noticeable when the pixel circuit 110 is miniaturized.
In contrast to this, in this embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitance Cprs can be suppressed.

In addition, according to this embodiment, the influence of the threshold voltage is offset for the current Ids supplied to the OLED 130 by the transistor 121. Therefore, according to this embodiment, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 130, so that the occurrence of display unevenness that impairs the uniformity of the display screen is suppressed, enabling a high-quality display.

This cancellation will be explained with reference to Fig. 11. As shown in this figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control the minute current supplied to the OLED 130.
In the figure, A shows the relationship between the gate potential of a transistor with a large threshold voltage |Vth| and the current supplied by the transistor, and B shows the relationship between the gate potential of a transistor with a small threshold voltage |Vth| and the current supplied by the transistor. In Fig. 11, the gate-source voltage Vgs is the difference between the solid line and the potential Vel. In Fig. 11, the current on the vertical scale is shown in logarithm with the direction from source to drain being negative (downward).
During the compensation period, the gate node g changes from the initial potential Vini to a potential (Vel-|Vth|). Therefore, the operating point of a transistor with a large threshold voltage |Vth| represented by the solid line A moves from S to Aa, while the operating point of a transistor with a small threshold voltage |Vth| represented by the solid line B moves from S to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is specified, the amount of potential shift from the operating points Aa and Ba during the writing period is the same k1·ΔVh. Therefore, the operating point of the transistor represented by the solid line A moves from Aa to Ab, and the operating point of the transistor represented by the solid line B moves from Ba to Bb, but the current at the operating point after the potential shift is approximately the same Ids for both of the two transistors.

According to this embodiment, the operation of storing the data signal supplied from the control circuit 3 via the demultiplexer DM in the storage capacitor 41 is executed from the initialization period to the compensation period. That is, according to this embodiment, during the initialization period, the operation of initializing the potential of the anode 130a to the reset potential Vorst and the operation of storing the data signal in the storage capacitor 41 are executed in parallel, and during the compensation period, the operation of compensating for the variation in the threshold voltage of the transistor 121 and the operation of storing the data signal in the storage capacitor 41 are executed in parallel. Therefore, it is possible to relax the time constraints on the operations to be executed during one horizontal scanning period, and to slow down the data signal supply operation in the data signal supply circuit 70.

<Modification>
The present invention is not limited to the above-described embodiment, and various modifications are possible, for example, as described below. In addition, one or more of the modified aspects described below may be arbitrarily selected and appropriately combined.

<Modification 1>
In the above-described embodiment, each pixel circuit 110 is configured such that, when viewed in a planar view, the scanning line 12 and the control line 143 intersect with the gate electrode G1, but in addition to the scanning line 12 and the control line 143, the control line 144 may also intersect with the gate electrode G1.
Fig. 12 is a plan view showing a configuration of a pixel circuit 110 according to Modification 1. The pixel circuit 110 according to Modification 1 is configured similarly to the pixel circuit 110 according to the embodiment shown in Fig. 5, except that the control line 144 and the gate electrode G1 intersect when viewed in plan, and the control line 144 has a branch portion 142a branched in the Y direction for each pixel circuit 110.
According to this configuration, the multiple control lines (scanning line 12, control lines 143, 144, 145) extending in the X direction can be wired at a higher density and the pitch of the control lines can be narrowed, compared to a case where the control line 144 is provided so as not to intersect with the gate of the transistor 121. This enables the electro-optical device (display unit) to be made smaller and the display to have a higher resolution.

In addition, when the control line 144 and the gate electrode G1 intersect, the scanning line driving circuit 20 may switch the potential supplied to the control line 144 so that the waveform of the control signal Gel(i) when it changes from an H level to an L level is gentler than the waveform when it changes from an L level to an H level.
Fig. 13 is a timing chart for explaining the operation of the electro-optical device according to Modification 1. As shown in Fig. 13, the scanning line driving circuit 20 according to Modification 1 changes the potential supplied to the control line 144 so that the time length of a fifth switching period T5 during which the potential supplied to the control line 144 is switched from the second potential V2 to the first potential V1 is sufficiently longer than the time length of a sixth switching period T6 during which the potential is switched from the first potential V1 to the second potential V2.
As described above, the potential of the gate electrode G1 (gate node g of the transistor 121) is set to the potential Vgate that determines the luminance of the OLED 130 in the writing period preceding the fifth switching period T5. Therefore, if the potential of the control line 144 changes suddenly in the fifth switching period T5 and the potential fluctuation is propagated to the gate electrode G1, each pixel cannot accurately display the gradation determined by the image signal Vid.
In contrast, the scanning line driving circuit 20 according to the first modification makes the duration of the fifth switching period T5 sufficiently long, equal to the duration of the sixth switching period T6, and makes the waveform of the control signal Gel(i) when it changes from H level to L level gentle, thereby preventing the potential fluctuation of the control line 144 from propagating to the gate node g (gate electrode G1). This enables each pixel to accurately display the gradation defined by the image signal Vid, enabling high-quality display.

<Modification 2>
In the above-described embodiment, each pixel circuit 110 is configured such that, when viewed in a planar view, the scanning line 12 and the control line 143 intersect with the gate electrode G1, but in addition to the scanning line 12 and the control line 143, the control line 145 may also intersect with the gate electrode G1.
Fig. 14 is a plan view showing a configuration of a pixel circuit 110 according to Modification 2. The pixel circuit 110 according to Modification 2 is configured similarly to the pixel circuit 110 according to the embodiment shown in Fig. 5, except that the control line 145 and the gate electrode G1 intersect when viewed in plan, and the control line 145 has a branch portion 145a branched in the Y direction for each pixel circuit 110.
According to this configuration, the multiple control lines (scanning line 12, control lines 143, 144, 145) extending in the X direction can be wired at a higher density and the pitch of the control lines can be narrowed, compared to a case where the control line 145 is provided so as not to intersect with the gate of the transistor 121. This enables the electro-optical device (display unit) to be made smaller and the display to have a higher resolution.
In addition, when the control line 145 and the gate electrode G1 intersect, the scanning line driving circuit 20 may switch the potential supplied to the control line 145 so that the waveform of the control signal Gorst(i) when it changes from an L level to an H level becomes gentler than the waveform when it changes from an H level to an L level, as shown in FIG. 15 .
FIG. 15 is a timing chart for explaining the operation of the electro-optical device according to the second modification.
15, the scanning line driving circuit 20 according to the second modification changes the potential supplied to the control line 145 so that the time length of an eighth switching period T8 during which the potential supplied to the control line 145 is switched from the first potential V1 to the second potential V2 is sufficiently longer than the time length of a seventh switching period T7 during which the potential is switched from the second potential V2 to the first potential V1. In this case, after the potential of the gate node g (gate electrode G1) of the transistor 121 is determined to be the potential Vgate that determines the luminance of the OLED 130, potential fluctuations in the control line 145 are prevented from propagating to the gate electrode G1, and each pixel can accurately display the gradation determined by the image signal Vid.

<Modification 3>
In the above-described embodiment and modification, each pixel circuit 110 includes transistors 121 to 125, an OLED 130, and a storage capacitor 132. However, the pixel circuit 110 may include at least a transistor 121, a transistor 122, and an OLED 130. In this case, the display unit 100 may include only control lines corresponding to the transistors included in the pixel circuit 110 of modification 3 among the multiple control lines (scanning line 12, control lines 143, 144, 145) extending in the X direction provided in the display unit 100 in the above-described embodiment and modification. That is, the display unit 100 according to modification 3 may include one or more control lines including the scanning line 12 in each row. For example, when each pixel circuit 110 includes a transistor 121, a transistor 122, an OLED 130, and a storage capacitor 132, only the scanning line 12 is provided as a control line corresponding to each row. Furthermore, each pixel circuit 110 may include transistors other than the transistors 121 to 125, and in this case, the display unit 100 may be provided with control lines corresponding to those transistors.
When one or more control lines including the scanning line 12 are provided in each row, at least one of the one or more control lines extending in the X direction provided in each row is provided so as to intersect, in a plan view, with the gate node g (gate electrode G1) of the transistor 121. This allows the control lines extending in the X direction to be wired at a high density, making it possible to miniaturize the electro-optical device (display unit) and achieve high-definition display.
Furthermore, when the scanning line driving circuit 20 changes the potential of at least one control line that intersects with the gate electrode G1 in a plan view among the one or more control lines provided in each row between the end of the compensation period and the start of the next scanning period, it is preferable to make the waveform of the potential change gentle. For example, when the gate electrode G1 intersects with the scanning line 12, the scanning line driving circuit 20 may change the potential supplied to the scanning line 12 so that the time length of the second switching period T2 in which the potential supplied to the scanning line 12 is switched from the first potential V1 to the second potential V2 is sufficiently longer than the time length of the first switching period T1 in which the potential is switched from the second potential V2 to the first potential V1. This makes it possible to prevent the potential change of the control line that intersects with the gate electrode G1 from being propagated to the gate electrode G1, and each pixel can accurately display the gray scale defined by the image signal Vid.

The scanning line driving circuit 20 may also make the waveform of the potential change gentle when changing the potential of a control line that does not intersect with the gate electrode G1 in a planar view between the end of a compensation period and the start of the next scanning period. Even if the control line does not intersect with the gate electrode G1, parasitic capacitance may exist between the control line and the gate electrode G1. Therefore, by making the waveform of the potential change of the control line gentle, it is possible to prevent the potential change of the control line from propagating to the gate electrode G1.

<Modification 4>
In the above-described embodiment and modified example, each level shift circuit LS includes the holding capacitance 41, the holding capacitance 44, the transistor 45, the transistor 43, and the transmission gate 42, but the level shift circuit LS may include at least the holding capacitance 44, the transistor 43, and the transistor 45. In this case, the data signal supply circuit 70 and the demultiplexer DM may supply the data signal Vd(j) to the other electrode of the holding capacitance 44 during the writing period.
Even if the level shift circuit LS does not include the storage capacitor 41, the data signal Vd(j) supplied to the other electrode of the storage capacitor 44 is compressed by the capacitance ratio k1 and then supplied to the gate node g. This makes it possible to set the potential of the gate node of the drive transistor with high precision without having to chop the data signal with high precision, so that a current can be supplied to the light-emitting element with high precision, enabling a high-quality display.

<Modification 5>
In the above-described embodiment and modified example, the data line driving circuit 10 includes the level shift circuit LS, the demultiplexer DM, and the data signal supply circuit 70, but the data line driving circuit 10 may include at least the data signal supply circuit 70. In this case, the data line driving circuit 10 directly supplies the data signal Vd(j) to the gate node g.
Furthermore, in the above-described embodiment and modified example, the display panel 2 includes the storage capacitor 50 for each column, but the display panel 2 may be configured without including this.

<Modification 6>
In the above-described embodiment and modified example, the control circuit 3 and the display panel 2 are separate entities, but the control circuit 3 and the display panel 2 may be formed on the same substrate. For example, the control circuit 3 may be integrated on a silicon substrate together with the display unit 100, the data line driving circuit 10, the scanning line driving circuit 20, etc.

<Modification 7>
In the above-described embodiment and modified example, the electro-optical device 1 is configured to be integrated on a silicon substrate, but it may be configured to be integrated on another semiconductor substrate. For example, it may be an SOI substrate. Also, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the present invention is effective for a configuration in which the pixel circuit 110 is miniaturized and the drain current of the transistor 121 changes exponentially and largely with respect to a change in the gate voltage Vgs.
Furthermore, the present invention may be applied to cases where miniaturization of pixel circuits is not required.

<Modification 8>
In the above-described embodiment and modified example, the data lines 14 are grouped in groups of three columns, and the data lines 14 in each group are selected in order to supply data signals, but the number of data lines constituting a group may be a predetermined number between "2" and "3n." For example, the number of data lines constituting a group may be "2," or may be "4" or more.
Also, a configuration may be used in which data signals are simultaneously supplied line-sequentially to the data lines 14 of each column without grouping, that is, without using a demultiplexer DM.

<Modification 9>
In the above-described embodiment and modified examples, the transistors 121 to 125 in the pixel circuit 110 are all P-channel type, but they may all be N-channel type. Also, the P-channel type and the N-channel type may be appropriately combined.
For example, when the transistors 121 to 125 are all N-channel type, a potential whose positive and negative polarities are reversed from that of the data signal Vd(j) in the above-described embodiment and modified example may be supplied to each pixel circuit 110. In this case, the source and drain of the transistors 121 to 125 have a reversed relationship from that in the above-described embodiment and modified example.
In the above-described embodiment and modified examples, the transistor 45 is a P-channel type and the transistor 43 is an N-channel type, but they may be unified as either a P-channel type or an N-channel type. The transistor 45 may be an N-channel type and the transistor 43 may be a P-channel type.
In the above-described embodiment and modified examples, each transistor is a MOS type transistor, but it may be a thin film transistor.

<Modification 10>
In the above-described embodiment and modified example, an OLED, which is a light-emitting element, has been exemplified as an electro-optical element. However, any element that emits light with a luminance according to a current, such as an inorganic light-emitting diode or an LED (Light Emitting Diode), may be used.

<Application Examples>
Next, an electronic device to which the electro-optical device 1 according to the embodiment or application example is applied will be described. The electro-optical device 1 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

FIG. 16 is a diagram showing the appearance of a head mounted display, and FIG. 17 is a diagram showing its optical configuration.
First, as shown in Fig. 16, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. In addition, as shown in Fig. 17, the head mounted display 300 has an electro-optical device 1L for the left eye and an electro-optical device 1R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure).
The image display surface of the electro-optical device 1L is disposed on the left side in Fig. 17. As a result, the image displayed by the electro-optical device 1L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 1L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is disposed on the opposite right side of the electro-optical device 1L. As a result, the image displayed by the electro-optical device 1R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 1R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 1L and 1R in a see-through state in which the images are superimposed on the outside world.
Furthermore, in this head-mounted display 300, when an image for the left eye, among the binocular images with parallax, is displayed on the electro-optical device 1L and an image for the right eye is displayed on the electro-optical device 1R, the wearer can perceive the displayed image as if it has depth and a three-dimensional effect (3D display).

The electro-optical device 1 can be used not only in the head-mounted display 300 but also in electronic viewfinders in video cameras and digital cameras with interchangeable lenses.

1...electro-optical device, 2...display panel, 3...control circuit, 10...data line driving circuit, 12...scanning line, 14...data line, 16...power supply line, 20...scanning line driving circuit, 41, 44, 50...storage capacitance, 100...display section, 110...pixel circuit, 121-125...transistor, 130...OLED, 132...storage capacitance, 143, 144, 145...control line, 150...silicon substrate, LS...level shift circuit, DM...demultiplexer.

Claims (4)

A power supply line;
a light-emitting element that emits light in response to a current supplied from the power supply line;
A data line extending along a first direction;
a scanning line extending along a second direction intersecting the first direction;
A control line extending along the second direction ;
A holding capacity;
a first transistor including a first gate electrode electrically connected to the storage capacitor, the first transistor controlling the current supplied to the light emitting element in response to a voltage stored in the storage capacitor;
a second transistor including a second gate electrode electrically connected to the control line, the second transistor cutting off the current supplied to the light emitting element in response to a control signal supplied from the control line;
a third transistor including a third gate electrode electrically connected to the scanning line, the third transistor electrically connecting the data line and the first gate electrode;
an insulating layer having a first contact hole for electrically connecting the second gate electrode and the control line;
Equipped with
the control line and the first contact hole overlap with the second gate electrode in a plan view. The first transistor includes a drain and a source disposed along the first direction,
the second transistor includes a drain and a source disposed along the first direction;
The electro-optical device according to claim 1 , wherein the third transistor has a drain and a source arranged along the first direction. The electro-optical device according to claim 1 , wherein the power supply line extends along the second direction. An electronic device comprising the electro-optical device according to claim 1 .

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