JP7501726B2 - Electronic clock, method, and program - Google Patents

Description

The present invention relates to an electronic watch, a method , and a program .

In recent years, various electronic devices have been put into practical use that allow users to update the programs of electronic devices in order to correct defects or improve functions and performance after the electronic devices are released. Such electronic devices can be connected to the Internet, for example, and programs can be updated via the network.

Patent document 1 discloses a method for updating control software. The abstract of patent document 1 states that "The wireless terminal device notifies a software supply device connected to the network side of version information of the current control software related to the operation of the device itself, and the software supply device compares the notified version information with the latest version information stored and managed by itself to determine whether an update is necessary, and if an update is necessary, downloads new control software that is compatible with the notified version revision to the wireless terminal device."

JP 2001-078258 A

In an electronic watch, by having two firmware storage areas, even if the rewriting of the firmware in one storage area is interrupted, it is possible to normally start from the firmware in the other storage area. However, in order to realize such a function, the processor of the electronic watch needs to know which storage area is the area in use. For example, if the clock LSI (Large-Scale Integration) is reset due to a voltage drop or the like after the header part of the firmware is rewritten, it is not possible to determine whether the rewriting was successful or not just by reading the version information in the header part, and it is not possible to know which storage area is the area in use, and ultimately it is not possible to erase the storage area appropriately .

SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide an electronic watch, method, and program that properly erases a memory area .

In order to achieve the above object, the present invention provides
A pointer that rotates by a predetermined angle at a predetermined time interval;
A storage unit having two storage areas into which objects to be written are written;
A control unit;
An electronic watch comprising:
The control unit is
determining that one of the two storage areas is a format area or a write area into which the write target will be written next time;
executing an unused area erasure process for erasing the determined formatted area or the write area when the electronic watch is in a normal mode during a time period when it is highly likely that the user is not checking the time;
The electronic watch is characterized by the above.

1 is a diagram showing an outline of the configuration of an electronic timepiece according to an embodiment of the present invention; 13 is a flowchart showing a GPS process after all-clear; 11 is a timing chart showing the movement of the second hand and the GPS flash unused area determination process. FIG. 2 is a diagram illustrating the configuration of memory areas 0 and 1 in the first embodiment. 11 is a flowchart (part 1) showing a process of determining whether an area is used or unused. 13 is a flowchart (part 2) showing a process for determining whether an area is used or unused. 13 is a flowchart showing an erasing process of an unused area. 13 is a flowchart showing a process of rewriting an erased area. FIG. 13 is a diagram illustrating the configuration of memory areas 0 and 1 in the second embodiment. 11 is a flowchart (part 1) showing a process of determining whether an area is used or unused. 13 is a flowchart (part 2) showing a process for determining whether an area is used or unused. 13 is a flowchart showing an erasing process of an unused area. 13 is a flowchart showing a process of rewriting an erased area. FIG. 13 is a diagram illustrating the configuration of memory areas 0 and 1 in the third embodiment. 13 is a flowchart showing a process of rewriting an erased area.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The electronic timepiece of this embodiment copies version information that identifies the firmware or data to the footer section of the storage area to which the firmware or data is written. If the version information of the firmware or data is copied to the footer section, it is possible to detect if the rewriting has failed.

Furthermore, if firmware or data block size information is written to the footer, the block size to be erased becomes clear, making it possible to reduce the erasure time and power consumption associated with the erasure.

FIG. 1 is a schematic diagram showing the configuration of an electronic timepiece 1 according to this embodiment.
The electronic watch 1 is not particularly limited, but may be, for example, a wristwatch-type electronic watch equipped with a band for wearing on the arm. This electronic watch 1 comprises a microcomputer 2, which is a watch LSI, an operation unit 31, a display unit 32, a power supply unit 33, and a battery 34. The electronic watch 1 further comprises a communication unit 4 and an antenna 41, a GPS (Global Positioning System) unit 5 and an antenna 51, a flash memory 6, and a vibrator 7. In the drawings, the antennas 41 and 51 are written as "ANT".

The operation unit 31 is, for example, a crown or a button, and transmits user operation information to the microcomputer 2. The display unit 32 is, for example, a dial and hands, and displays various information including the current time according to instructions from the microcomputer 2. The battery 34 and power supply unit 33 supply power to the electronic watch 1.

The power supply unit 33 is, for example, a voltage conversion circuit. The power supply unit 33 supplies power at the operating voltage of each part in the electronic watch 1. For example, a primary battery such as a button-type dry cell is used as the battery 34. Alternatively, a combination of a solar panel and a secondary battery may be used as the battery 34.

The communication unit 4 communicates with the outside world via the antenna 41, for example, by wireless communication compliant with Bluetooth (registered trademark) Low Energy. This allows the electronic watch 1 to receive new firmware from the outside world.

The GPS section 5 is made up of a GPS receiving IC, and receives ultra-high frequency satellite signals transmitted from GPS satellites by means of an antenna 51, and measures the current position and the current time. This GPS receiving IC comprises a CPU (Central Processing Unit) 52 and a RAM (Random Access Memory) 53. The CPU 52 is a first processor that reads memory area 0 (61) and memory area 1 (62) of the flash memory 6 (described below) into the RAM 53 and executes them.

Flash memory 6 is a non-volatile semiconductor memory that stores information in a readable and writable manner. This flash memory 6 includes memory area 0 (61) and memory area 1 (62). Memory area 0 (61) and memory area 1 (62) store data that is read and referenced by the CPU 52 through the RAM 53.

The unit of data that can be erased from the flash memory 6 at one time is 4Kbytes, which is called a block. When erasing a larger size, erasing 4Kbyte blocks is repeated. When a specified block of the flash memory 6 is erased, all of the data in that block becomes 0xFF.

Data can be written to the erased address space of the flash memory 6. The flash memory 6 writes data in units of 256 bytes at a time, so when writing data larger than this size, it is a good idea to repeatedly write, read, and verify in units of 256 bytes.

CPU 21 is a second processor that controls electronic watch 1. The processing power of CPU 21 is lower than that of CPU 52. The lower limit of the guaranteed operating voltage of CPU 21 is also lower than the lower limit of the guaranteed operating voltage of CPU 52. CPU 21 can continue to operate even after CPU 52 stops operating due to a drop in the power supply voltage.

The oscillator 7 is, for example, a quartz oscillator, and generates a signal with a specific frequency in combination with an oscillation circuit 25 described later.
The microcomputer 2 includes a CPU 21 and a RAM 22. The microcomputer 2 further includes an oscillator circuit 25, a frequency divider circuit 26, and a timer circuit 27, and is connected to an external Read Only Memory (ROM) 23.

The CPU 21 uses the RAM 22 as a work area to carry out various calculation processes using programs stored in the ROM 23 and flash memory 6, and generally controls the overall operation of the electronic watch 1. The RAM 22 has a power backup, so it can conveniently store information to be referenced at the next startup. The information to be referenced by the CPU 21 at the next startup is stored in the RAM 22. The CPU 21 writes a program or data and specific information identifying this program or this data in a specific address space in memory areas 0 and 1, and writes the specific information in an address space different from the specific address space in this memory area.

The oscillator circuit 25 is combined with the vibrator 7 to generate a specific frequency signal and output it to the frequency divider circuit 26. As the oscillator circuit 25, for example, a crystal oscillator circuit is used.
The frequency divider circuit 26 divides the signal input from the oscillator circuit 25 into signals of various frequencies used by the CPU 21 and the timer circuit 27 and outputs the divided signals.

The timer circuit 27 is a counter circuit that counts the number of times a predetermined frequency signal is input from the divider circuit 26 and counts the current time by adding it to the initial time. The current time counted by the timer circuit 27 is read by the CPU 21 and used to display the time. This time counting may be controlled by software. Also, the vibrator 7, the oscillator circuit 25, the divider circuit 26, and the timer circuit 27 may form a timer unit that counts the time.

FIG. 2 is a flowchart showing the GPS processing after all-clear.
When the user performs an all-clear (AC) on the electronic watch 1, the CPU 21 of the electronic watch 1 executes the GPS flash unused area determination process (see FIGS. 5 and 6) (step S10). An all-clear is performed when the battery 34 runs out or the program goes out of control.

The CPU 21 determines whether or not the unused area determination process was successful (step S11). If it is determined that the process was successful (Yes), the CPU 21 proceeds to the process of step S14. If it is determined that the process was unsuccessful (No), the CPU 21 proceeds to the process of step S12.

In step S12, the CPU 21 determines whether the current mode is the normal mode (step S12). Here, normal mode refers to a mode in which the electronic watch 1 keeps time. If the CPU 21 determines that the current mode is not the normal mode (No), it repeats this determination process. If the CPU 21 determines that the current mode is the normal mode (Yes), it proceeds to the process of step S13.

In step S13, the CPU 21 determines whether the seconds of the home time (HT) are 55 seconds. If the seconds of the home time are not 55 seconds (No), the CPU 21 returns to the process of step S12, and if the seconds of the home time are 55 seconds (Yes), the CPU 21 returns to the process of step S10.

In other words, if the current mode is not the normal mode or the home time seconds are not 55 seconds (No), the CPU 21 returns to the process of step S12 and repeats the judgments of steps S12 and S13. If the current mode is the normal mode and the home time seconds are 55 seconds (Yes), the CPU 21 returns to the process of step S10 and executes the unused area determination process again.

In this embodiment, the timing for executing the unused area determination process again is limited to when the second hand indicates 55 seconds, as determined by the judgment processes in steps S12 and S13. In other words, the timing of the unused area determination process is shifted from the timing of the second hand movement, and the unused area is erased when it is considered that the second hand is not moving. This allows the electronic watch 1 to display the correct time to the user.

In step S14, the CPU 21 determines whether the current mode is the normal mode. If the CPU 21 determines that the current mode is not the normal mode (No), the CPU 21 proceeds to the process of step S17. If the CPU 21 determines that the current mode is the normal mode (Yes), the CPU 21 proceeds to the process of step S15.

In step S15, the CPU 21 determines whether the time of the home time (HT) is between 2:00 and 5:00 a.m. The reason for determining this time is that it is highly likely that the user will not check the time during this time period. If the time of the home time (HT) is between 2:00 and 5:00 a.m. (Yes), the CPU 21 further determines whether the minutes and seconds are 30 minutes and 50 seconds (step S16). If the minutes and seconds of the home time (HT) are 30 minutes and 50 seconds, the CPU 21 proceeds to step S19 and executes the process of erasing unused areas of the GPS flash. The reason for determining step S16 is to avoid overlapping with the process of standard radio wave reception and the like that is automatically performed during the same time period. In step S16, if the minutes and seconds of the home time (HT) are not 30 minutes and 50 seconds, the CPU 21 returns to the process of step S14.

That is, if the home time (HT) is not between 2:00 and 5:00 a.m., or if the minutes and seconds are not 30 minutes and 50 seconds, the CPU 21 returns to the process of step S14. If the home time (HT) is between 2:00 and 5:00 a.m., and the minutes and seconds are 30 minutes and 50 seconds, the CPU 21 executes the process of erasing the unused area of the GPS flash (step S19).

The CPU 21 also determines in step S17 whether the current mode is the stopwatch mode. If the CPU 21 determines that the current mode is not the stopwatch mode (No), it returns to the processing of step S14.

If the CPU 21 determines that the current mode is the stopwatch mode (Yes), it further determines whether one minute has passed since the second hand stopped (step S18). If this determination condition is met, the CPU 21 proceeds to step S19 and executes the process of erasing unused areas of the GPS flash (see FIG. 7). The reason for determining step S18 is that if the process is performed while the second hand is stopped, the stoppage of the hand movement during erasure is not noticeable, and if one minute has passed, it is assumed that no user operation has been performed.

Then, in step S20, the CPU 21 determines whether the erasure of the memory area was successful. If the erasure of the memory area was successful (Yes), the CPU 21 ends the process of FIG. 2, and if the erasure of the memory area was unsuccessful (No), the CPU 21 returns to the process of step S14.

In the electronic watch 1, it is extremely difficult to perform erasing and rewriting consecutively due to the current consumption. During erasing, there is a possibility that the timing for moving the hands may occur during communication between the watch LSI (microcomputer 2) and the GPS microcomputer (CPU 52), so the hands are stopped until erasing is complete, and the time cannot be displayed to the user.

By using the GPS processing in Figure 2, the electronic watch 1 erases unused areas when it is believed that the second hand is not moving, such as late at night or when a certain amount of time has passed since the second hand stopped moving. Therefore, the electronic watch 1 erases unused areas while avoiding the timing of the second hand moving, and can display the correct time to the user.

Figure 3 is a timing chart showing the movement of the second hand and the process of determining unused areas of the GPS flash.

The upper part of Figure 3 shows the timing of the second hand movement, which moves when the second value is a multiple of 12. The GPS flash unused area determination process starts at 55 seconds, and the average processing time is 3 seconds. Therefore, the execution of the unused area determination process and the movement of the second hand do not overlap.

First Embodiment
FIG. 4 is a diagram showing the configuration of storage areas 0 and 1 in the first embodiment.
In the memory area 0, a reference data table and map data are stored.

The reference data table is stored in the upper address space 0x100000-(0x100002+X1) of the address space 0x100000-0x10FFFF. The reference data table is made up of 2 bytes of version information in the header and X1 bytes of the main body that follows. Here, the version information is 0x01, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the reference data table from the value of this version information.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x100003+X1) to 0x10FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x110000-(0x110002+Y1) of the address space 0x110000-0x1FFFFB. Map data consists of 2 bytes of version information in the header, followed by Y1 bytes of the main body. Here, the version information is 0x03, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the map data from the value of this version information.

The area following the map data body is a reserved area, stored in the address space from (0x110003+Y1) to 0x1FFFFB. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x100000 to 0x1FFFFB.

In the address space 0x1FFFFC to 0x1FFFFD of memory area 0, version information for reference data tables is stored. In the address space 0x1FFFFE to 0x1FFFFF of memory area 0, version information for map data is stored. This address space 0x1FFFFC to 0x1FFFFF is the footer of memory area 0, and is a different address space from the specific address spaces that store reference data tables and map data.

In the memory area 1, similar to the memory area 0, a reference data table and map data are stored, and the version information of the reference data table and the version information of the map data are copied to the footer.
The reference data table is stored in the upper address space 0x200000-(0x200002+X2) of the address space 0x200000-0x20FFFF. The reference data table is composed of 2 bytes of version information in the header and X2 bytes of the main body following that. Here, the version information is 0x02, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the reference data table from the value of this version information.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x200003+X1) to 0x20FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x210000-(0x210002+Y2) of the address space 0x210000-0x2FFFFB. Map data consists of 2 bytes of version information in the header, followed by Y2 bytes of the main body. Here, the version information is 0x04, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the map data from the value of this version information.

The area following the map data body is a reserved area, stored in the address space from (0x210003+Y2) to 0x2FFFFB. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x200000 to 0x2FFFFB.

In the address space 0x2FFFFC to 0x2FFFFD of memory area 0, version information for reference data tables is stored. In the address space 0x2FFFFE to 0x2FFFFF of memory area 0, version information for map data is stored. This address space 0x2FFFFC to 0x2FFFFF is the footer of memory area 0, and is a different address space from the specific address spaces that store reference data tables and map data.

The electronic watch 1 of the first embodiment has common version information in the header section, which is the first to be rewritten, and the footer section, which is the last to be rewritten, in memory areas 0 and 1. These header and footer sections are separated by 256 bytes or more and are in different write blocks, so the write timing is different.

If a rewrite fails midway and the microcomputer 2 is reset, the version information in the header and footer parts will differ, making it possible to determine that the rewrite failed. Similarly, if an erase fails midway and the microcomputer 2 is reset, the version information in the header and footer parts will differ, making it possible to determine that the erase failed.

5 and 6 are flow charts showing a process for determining whether a storage area is in use or unused.
The CPU 21 reads the version information of the reference data table in the memory area 0 (step S30), and judges whether the version information is 0xFF, 0xFF (step S31). If the version information is not 0xFF, 0xFF (No), the CPU 21 proceeds to the process of step S32, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to the process of step S36.

In step S32, the CPU 21 reads the version information of the map data in memory area 0, and determines whether the read version information is 0xFF, 0xFF (step S33). If the version information is not 0xFF, 0xFF (No), the CPU 21 proceeds to processing of step S34, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing of step S36. The reason for proceeding to processing of step S36 here is that it can be determined that rewriting of memory area 0 has failed. By not determining whether memory area 1 is valid, power consumption can be reduced.

In other words, if either the version information of the reference data table or the version information of the map data is 0xFF, 0xFF (Yes), the CPU 21 determines that memory area 0 is unused and proceeds to processing in step S36. If neither of the version information is 0xFF, 0xFF (No), the CPU 21 proceeds to processing in step S34.

In step S34, the CPU 21 reads both pieces of version information stored in the footer portion of memory area 0. The CPU 21 compares both pieces of version information that have been read with both pieces of version information stored in the header portion of the reference data table and the map data (step S35). If the two pieces of version information do not match (No), the CPU 21 proceeds to processing of step S36. If the two pieces of version information match (Yes), the CPU 21 proceeds to processing of step S40 in FIG. 6.

If the rewrite fails somewhere in memory area 0, the version information in the header and the version information in the footer will no longer match. Therefore, by comparing the version information in the header and the version information in the footer, it is possible to determine whether the rewrite has failed or not.

In step S36, the CPU 21 reads the version information in the footer of the memory area 1 to determine the version of the map data to be used, and determines that the map data in the memory area 1 will be used (step S37). As a result, the CPU 21 determines that the map data has been correctly written in the memory area 1.
For example, the identifier of memory area 1 may be substituted for a variable indicating the destination of use on the RAM 22, and the version of the map data to be used may be substituted for a version variable on the RAM 22. In this way, the CPU 52 reads out the map data written in either memory area 0 or 1, based on the identifier of the variable indicating the destination of use.

The CPU 21 then sets the erase flag for memory area 0 (step S38), turns off the GPS power (step S39), and returns to the process in FIG. 2. The erase flag is placed in, for example, the RAM 22. This causes the CPU 21 to erase the memory area that has not been written to correctly.

In step S40 of FIG. 6, the CPU 21 reads the version information of the reference data table in memory area 1 and determines whether the version information is 0xFF, 0xFF (step S41). If the version information is not 0xFF, 0xFF (No), the CPU 21 proceeds to processing of step S42, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing of step S47.

In step S42, the CPU 21 reads the version information of the map data in the memory area 1, and determines whether the read version information is 0xFF, 0xFF (step S43). If the version information is not 0xFF, 0xFF, the CPU 21 proceeds to processing in step S44, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing in step S47.

In other words, if either the version information of the reference data table or the version information of the map data is 0xFF, 0xFF (Yes), the CPU 21 determines that memory area 1 is unused and proceeds to processing in step S47. If neither version information is 0xFF, 0xFF (No), the CPU 21 proceeds to processing in step S44.

In step S44, the CPU 21 reads out both pieces of version information stored in the footer portion of memory area 1. The CPU 21 compares both pieces of version information that have been read out with both pieces of version information stored in the header portion of the reference data table and the map data (step S45). If the two pieces of version information do not match (No), the CPU 21 proceeds to processing of step S47. If the two pieces of version information match (Yes), the CPU 21 proceeds to processing of step S46. At this time, data is correctly stored in both memory area 0 and memory area 1. Therefore, the versions in the two memory areas are compared, and the one with the newer version stored is used.

In step S46, the CPU 21 compares the version information of memory area 0 with the version information of memory area 1 to determine whether the version information of memory area 1 is the latest. If the version information of memory area 1 is the latest (Yes), the CPU 21 proceeds to the processing of step S36 in FIG. 5, and if the version information of memory area 1 is not the latest (No), the CPU 21 proceeds to the processing of step S47.

In step S47, the CPU 21 determines the version of the map data to be used, and determines to use the map data in the memory area 0. In this way, the CPU 21 determines that the map data has been written correctly in the memory area 0.
For example, the CPU 21 may assign the identifier of the memory area 0 to a variable on the RAM 22 indicating the use destination, and assign the version of the map data to be used to a version variable on the RAM 22 .

The CPU 21 then sets the erase flag in memory area 1 (step S48), turns off the GPS power (step S49), and returns to the process in FIG. 2.

FIG. 7 is a flowchart showing the process of erasing unused areas.
The unused area erasing process of the GPS flash is called in step S19 of FIG.

If the erase flag for memory area 0 is set (step S50→Yes), the CPU 21 erases memory area 0 (step S51) and clears the erase flag (step S52). If the erase flag for memory area 0 is not set (step S50→No), the CPU 21 proceeds to the process of step S53.

If the erase flag for memory area 1 is set (step S53 → Yes), the CPU 21 erases memory area 1 (step S54) and clears the erase flag (step S55). This causes the CPU 21 to end the process of FIG. 7.

If the erase flag for the memory area 1 is not set (step S53: No), the CPU 21 ends the process of FIG.
When the CPU 21 executes the unused area erasure process of the GPS flash, either memory area 0 or 1 is erased, and becomes available for rewriting with new data or firmware.

FIG. 8 is a flowchart showing the process of rewriting an erased area.
This rewriting process is executed, for example, by a user's operation to issue a rewriting instruction.

The CPU 21 determines whether or not the memory area 1 is being used (step S60), and further determines whether or not the erase flag for the memory area 0 is cleared (step S61).
If memory area 1 is being used (step S60→Yes) and the erase flag for memory area 0 is cleared (step S61→Yes), the CPU 21 writes the reference data table and map data to memory area 0 (step S62). By executing step S62, the CPU 21 functions as a first writing unit that writes data to a specific address space in memory area 0.
The CPU 21 further writes version information to the footer of the memory area 0 (step S63), and proceeds to the process of step S64. Here, by executing step S63, the CPU 21 functions as a second writing unit that writes the same specific information as the specific information that identifies the data to an address space different from the specific address space of the memory area 0.

If memory area 1 is not in use (step S60 → No) or the erase flag for memory area 0 has not been cleared (step S61 → No), the CPU 21 proceeds to processing of step S64.

The CPU 21 determines whether or not the memory area 0 is being used (step S64), and further determines whether or not the erase flag for the memory area 1 is cleared (step S65).
If memory area 0 is being used (step S64→Yes) and the erase flag for memory area 1 is cleared (step S65→Yes), the CPU 21 writes the reference data table and map data to memory area 1 (step S66). By executing step S66, the CPU 21 functions as a first writing unit that writes data to a specific address space in memory area 1.
The CPU 21 further writes the version information in the footer of the storage area 1 (step S67), and ends the process in Fig. 8. By executing step S67, the CPU 21 functions as a second writing unit that writes the same specific information as the specific information that identifies the data in an address space different from the specific address space of the storage area 0.

If memory area 0 is not in use (step S64 → No) or the erase flag for memory area 1 has not been cleared (step S65 → No), the CPU 21 ends the process of FIG. 8.

The CPU 21 of the electronic watch 1 of the first embodiment writes common version information to the header section, which is the first section to be rewritten, and the footer section, which is the last section to be rewritten. If a voltage drop or the like occurs during the rewrite and the microcomputer 2 is reset, causing the rewrite to fail, the version information in the header section will differ from the version information in the footer section. Therefore, the CPU 21 can determine that the rewrite has failed.

<<Variation 1>>
4, in this embodiment, version information is stored in the address space 0x100000-0x100001 and the address space 0x110000-0x110001 in the memory area 0. Furthermore, both pieces of version information are copied to the address space 0x1FFFFC-0x1FFFFD and the address space 0x1FFFFE-0x1FFFFF.

However, only the version information stored in the address space 0x100000-0x100001 may be copied to the corresponding address space 0x1FFFFE-0x1FFFFF. In this way, when the storage areas on two sides are made up of multiple pieces of data, the version information of the representative data may be copied to the footer.
The same applies to memory area 1.

<<Variation 2>>
When version information of the reference data table is stored in the address space 0x100000-0x100001 of memory area 0, this version information may be copied to the address space 0x10FFFE-0x10FFFF, which corresponds to the footer of the reference data table area.

Similarly, when map data version information is stored in the address space 0x110000-0x110001 of memory area 0, this version information may be copied to the address space 0x1FFFFE-0x1FFFFF, which corresponds to the footer of the map data area.

In this way, the version information may be copied to the footer of each area in which each data is stored.
The same applies to memory area 1.

Effects of the First Embodiment
A copy of the version information is stored in the footer of the storage area, and by comparing the version information in the header and footer, it is possible to determine whether the rewriting has been successful.

Second Embodiment
The electronic watch 1 of the first embodiment writes the version information and main body of the data in the header section of each storage area, and then copies the version information to the footer section of each storage area.

In contrast, the electronic watch 1 of the second embodiment stores data capacity information in the footer of each storage area. This allows the CPU 21 to determine the range in which data has been written, and by erasing only the range in which data has been written, it is possible to shorten the erasure time and reduce power consumption. This makes it possible to extend the life of the button battery installed in the watch.

FIG. 9 is a diagram showing the configuration of memory areas 0 and 1 in the second embodiment.
In the memory area 0, a reference data table and map data are stored.

The reference data table is stored in the upper address space 0x100000-(0x100002+X1) of the address space 0x100000-0x10FFFF. The reference data table is made up of 2 bytes of version information in the header, followed by X1 bytes of main body data. Here, the version information is given values of 0x01 and 0x00. A value other than 0xFF and 0xFF is given to the version information to determine whether it has been erased or not.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x100003+X1) to 0x10FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x110000-(0x110002+Y1) of the address space 0x110000-0x1FFFFB. Map data consists of 2 bytes of version information in the header, followed by Y1 bytes of the main body. Here, the version information is assigned values of 0x03 and 0x00. A value other than 0xFF and 0xFF is assigned to the version information to determine whether it has been erased or not.

The area following the map data body is a reserved area, stored in the address space from (0x110003+Y1) to 0x1FFFFB. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x100000 to 0x1FFFFB.
Map data capacity information (0x010002+Y1) is stored in the address space 0x1FFFFC to 0x1FFFFF, which is the footer of memory area 0. The address space 0x1FFFFC to 0x1FFFFF is the footer of memory area 0, and is an address space different from the specific address space that stores the reference data table and map data.

In the memory area 1, similar to the memory area 0, a reference data table and map data are stored, and capacity information of the map data is stored in the footer.
The reference data table is stored in the upper address space 0x200000-(0x200002+X2) of the address space 0x200000-0x20FFFF. The reference data table is composed of 2 bytes of version information in the header and X2 bytes of the main body following that. Here, the version information is 0x02, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the reference data table from the value of this version information.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x200003+X1) to 0x20FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x210000-(0x210002+Y2) of the address space 0x210000-0x2FFFFB. Map data consists of 2 bytes of version information in the header, followed by Y2 bytes of the main body. Here, the version information is 0x04, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the map data from the value of this version information.

The area following the map data body is a reserved area, stored in the address space from (0x210003+Y2) to 0x2FFFFB. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x200000 to 0x2FFFFB.

The address space 0x2FFFFC to 0x2FFFFF, which is the footer of memory area 1, stores the map data capacity information (0x010002+Y2). The address space 0x1FFFFC to 0x1FFFFF is the footer of memory area 1, and is an address space that is different from the specific address space that stores the reference data table and map data.

In memory areas 0 and 1, the footer is written last, so if a rewrite fails midway and the microcomputer 2 is reset, the capacity information in the footer will be 0xFF, 0xFF, 0xFF, 0xFF, so it is possible to determine that the rewrite has failed. If an erase fails midway and the microcomputer 2 is reset, the version information in the header will be 0xFF, 0xFF, so it is possible to determine that the erase has failed.

10 and 11 are flow charts showing a process for determining whether a storage area is used or unused.
The CPU 21 reads the version information of the reference data table in the memory area 0 (step S70), and judges whether the version information is 0xFF, 0xFF (step S71). If the version information is not 0xFF, 0xFF (No), the CPU 21 proceeds to the process of step S72, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to the process of step S76.

In step S72, the CPU 21 reads the version information of the map data in memory area 0, and determines whether the read version information is 0xFF, 0xFF (step S73). If the version information is not 0xFF, 0xFF, the CPU 21 proceeds to processing of step S74, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing of step S76. The reason for proceeding to processing of step S76 here is that it can be determined that rewriting of memory area 0 has failed. By not determining whether memory area 1 is valid, power consumption can be reduced.

In other words, if either the version information of the reference data table or the version information of the map data is 0xFF, 0xFF (Yes), the CPU 21 determines that memory area 0 is unused and proceeds to processing in step S76. If neither of the version information is 0xFF, 0xFF (No), the CPU 21 proceeds to processing in step S74.

In step S76, the CPU 21 reads the map capacity information in the footer of memory area 0 and proceeds to processing in step S77.

In step S74, the CPU 21 reads the map capacity information stored in the footer portion of memory area 0 and compares it with 0xFF, 0xFF, 0xFF, 0xFF (step S75). If the map capacity information does not match 0xFF, 0xFF, 0xFF, 0xFF (No), the CPU 21 proceeds to processing of step S77. If the map capacity information matches 0xFF, 0xFF, 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing of step S82 in FIG. 11.

If the rewrite fails anywhere in memory area 0, the map capacity information will not be written and will be in the state it was in immediately after erasure: 0xFF, 0xFF, 0xFF, 0xFF. Therefore, by comparing the map capacity information with 0xFF, 0xFF, 0xFF, 0xFF, it is possible to determine whether the rewrite has failed or not.

In step S77, the CPU 21 reads the version information of the reference data table and map data in the memory area 1. The CPU 21 reads the map capacity information in the footer of the memory area 1 (step S78). The CPU 21 determines that the map data in the memory area 1 will be used, and determines the version of the map data to be used (step S79). This enables the CPU 21 to determine that the map data has been correctly written in the memory area 1.
The CPU 21 may, for example, assign the identifier of the storage area 1 to a variable on the RAM 22 indicating the use destination, and assign the version of the map data to be used to a version variable on the RAM 22 .

The CPU 21 then sets the deletion flag in memory area 0 (step S80), turns off the GPS power (step S81), and returns to the process in FIG. 2. The deletion flag is stored in, for example, the RAM 22.

In step S82 of FIG. 11, the CPU 21 reads the version information of the reference data table in memory area 1, and determines whether the version information is 0xFF, 0xFF (step S83). If the version information is not 0xFF, 0xFF (No), the CPU 21 proceeds to processing of step S84, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing of step S89.

In step S84, the CPU 21 reads the version information of the map data in the memory area 1, and determines whether the read version information is 0xFF, 0xFF (step S85). If the version information is not 0xFF, 0xFF, the CPU 21 proceeds to processing in step S86, and if the version information is 0xFF, 0xFF (Yes), the CPU 21 proceeds to processing in step S89.

In other words, if either the version information of the reference data table or the version information of the map data is 0xFF, 0xFF (Yes), the CPU 21 determines that memory area 1 is unused and proceeds to processing in step S89. If neither version information is 0xFF, 0xFF (No), the CPU 21 proceeds to processing in step S86.

In step S89, the CPU 21 reads the map capacity information stored in the footer portion of memory area 1 and proceeds to processing in step S90.

In step S86, the CPU 21 reads the map capacity information stored in the footer portion of memory area 1 and compares it with 0xFF, 0xFF, 0xFF, 0xFF (step S87). If the map capacity information does not match 0xFF, 0xFF, 0xFF, 0xFF (No), the CPU 21 proceeds to the process of step S90. If the map capacity information matches 0xFF, 0xFF, 0xFF, 0xFF (Yes), the CPU 21 proceeds to the process of step S88. At this time, data is correctly stored in both memory area 0 and memory area 1. Therefore, the versions of the two memory areas are compared and the one with the newer version stored is used.

In step S88, the CPU 21 compares the version information of memory area 0 with the version information of memory area 1, and determines whether the version information of memory area 1 is the latest. If the version information of memory area 1 is the latest (Yes), the CPU 21 proceeds to the processing of step S77 in FIG. 10, and if the version information of memory area 1 is not the latest (No), the CPU 21 proceeds to the processing of step S90.

In step S90, the CPU 21 determines that the map data in the memory area 0 will be used, and determines the version of the map data to be used. In this way, the CPU 21 determines that the map data has been correctly written in the memory area 0.
For example, the CPU 21 may assign the identifier of the memory area 0 to a variable on the RAM 22 indicating the use destination, and assign the version of the map data to be used to a version variable on the RAM 22 .

The CPU 21 then sets the erase flag in memory area 1 (step S91), turns off the GPS power (step S92), and returns to the process in FIG. 2.

FIG. 12 is a flowchart showing the process of erasing an unused area.
The unused area erasing process of the GPS flash is called in step S19 of FIG.

If the erase flag for memory area 0 is set (step S100→Yes), the CPU 21 reads the map capacity stored in the footer of memory area 0 (step S101) and calculates the block size to be erased. The block size to be erased here is the sum of the block size of the reference data table and the map capacity divided by the capacity of one block. The CPU 21 erases a predetermined block from the beginning of memory area 0 (step S102), erases the block in the footer of memory area 0 (step S103), and clears the erase flag (step S104). If the erase flag for memory area 0 is not set (step S100→No), the CPU 21 proceeds to the process of step S105.

If the erase flag for memory area 1 is set (step S105 → Yes), the CPU 21 reads the map capacity stored in the footer of memory area 1 (step S106) and calculates the block size to be erased. The block size to be erased here is the sum of the block size of the reference data table and the map capacity divided by the capacity of one block (4 Kbytes). The CPU 21 erases a predetermined block from the beginning of memory area 1 (step S107), erases the block in the footer of memory area 1 (step S108), and clears the erase flag (step S109). This causes the CPU 21 to end the processing of FIG. 12.

If the erase flag for the memory area 1 is not set (step S105: No), the CPU 21 ends the process of FIG.
When the CPU 21 executes the unused area erasure process of the GPS flash, either memory area 0 or 1 is erased, and becomes available for rewriting with new data or firmware.

FIG. 13 is a flowchart showing the process of rewriting an erased area.
This rewriting process is executed, for example, by a user's operation to issue a rewriting instruction.

The CPU 21 determines whether or not the memory area 1 is being used (step S120), and further determines whether or not the erase flag for the memory area 0 is cleared (step S121).
If memory area 1 is being used (step S120→Yes) and the erase flag for memory area 0 is cleared (step S121→Yes), the CPU 21 writes the reference data table and map data to memory area 0 (step S122). By executing step S122, the CPU 21 functions as a first writing unit that writes data to a specific address space in memory area 0.
The CPU 21 further writes map capacity information to the footer of the memory area 0 (step S123), and proceeds to the process of step S124. Here, by executing step S123, the CPU 21 functions as a second writing unit that writes capacity information indicating the capacity of data to an address space different from the specific address space of the memory area 0.

If memory area 1 is not in use (step S120 → No) or the erase flag for memory area 0 has not been cleared (step S121 → No), the CPU 21 proceeds to processing of step S124.

In step S124, the CPU 21 determines whether or not the memory area 0 is being used, and further determines whether or not the erase flag for the memory area 1 is cleared (step S125).
If memory area 0 is being used (step S124→Yes) and the erase flag for memory area 1 is cleared (step S125→Yes), the CPU 21 writes the reference data table and map data to memory area 1 (step S126). By executing step S126, the CPU 21 functions as a first writing unit that writes data to a specific address space in memory area 1.
The CPU 21 further writes the map capacity information in the footer of the memory area 1 (step S127), and ends the processing in Fig. 13. Here, by executing step S127, the CPU 21 functions as a second writing unit that writes capacity information indicating the capacity of data in an address space different from the specific address space of the memory area 1.

If memory area 0 is not in use (step S124 → No) or the erase flag for memory area 1 has not been cleared (step S125 → No), the CPU 21 ends the processing of FIG. 13.

Effects of the Second Embodiment
By storing data other than 0xFF, 0xFF, ... in the footer of the storage area and checking whether data other than 0xFF, 0xFF, ... is stored in the footer portion, it is possible to determine whether the rewrite was successful or not.

Third Embodiment
The electronic watch 1 of the third embodiment stores power supply voltage information in the footer portion of each storage area.
The main reason why the CPU 21 fails to rewrite the flash memory is that the power supply voltage drops with a decrease in the capacity of the battery 34, making it impossible for the CPU 21 to operate. Therefore, by storing information about the power supply voltage when rewriting the flash memory, it is possible to analyze the cause of the failure to rewrite the flash memory.

FIG. 14 is a diagram showing the configuration of memory areas 0 and 1 in the third embodiment.
In the memory area 0, a reference data table and map data are stored.

The reference data table is stored in the upper address space 0x100000-(0x100002+X1) of the address space 0x100000-0x10FFFF. The reference data table is made up of 2 bytes of version information in the header, followed by X1 bytes of the main body. Here, the version information is given values of 0x01 and 0x00. A value other than 0xFF and 0xFF is given to the version information to determine whether it has been erased or not.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x100003+X1) to 0x10FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x110000-(0x110002+Y1) of the address space 0x110000-0x1FFFF9. Map data consists of 2 bytes of version information in the header, followed by Y1 bytes of the main body. Here, the version information is assigned values of 0x03 and 0x00. A value other than 0xFF and 0xFF is assigned to the version information to determine whether it has been erased or not.

The area following the map data body is a reserved area, stored in the address space from (0x110003+Y1) to 0x1FFFF9. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x100000 to 0x1FFFF9.
The address space 0x1FFFFA to 0x1FFFFB of memory area 0 stores power supply voltage information before writing. The address space 0x1FFFFC to 0x1FFFFD stores version information of the reference data table. The address space 0x1FFFFE to 0x1FFFFF of memory area 0 stores version information of the map data. This address space 0x1FFFFA to 0x1FFFFF is the footer of memory area 0, and is a different address space from the specific address space that stores the reference data table and map data.

In the memory area 1, similar to the memory area 0, a reference data table and map data are stored.
The reference data table is stored in the upper address space 0x200000-(0x200002+X2) of the address space 0x200000-0x20FFFF. The reference data table is composed of 2 bytes of version information in the header and X2 bytes of the main body following that. Here, the version information is 0x02, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the reference data table from the value of this version information.

The area following the main body of the reference data table is a reserved area, which is stored in the address space from (0x200003+X1) to 0x20FFFF. The entire reserved area is 0xFF. This reserved area makes it possible to absorb size differences between versions.

Map data is stored in the upper address space 0x210000-(0x210002+Y2) of the address space 0x210000-0x2FFFF9. Map data consists of 2 bytes of version information in the header, followed by Y2 bytes of the main body. Here, the version information is 0x04, 0x00. A value other than 0xFF, 0xFF is assigned to the version information to determine whether it has been erased or not. The CPU 21 identifies the version of the map data from the value of this version information.

The area following the map data body is a reserved area, stored in the address space from (0x210003+Y2) to 0x2FFFF9. The reserved area is all 0xFF. The reserved area makes it possible to absorb size differences between versions.
That is, the specific address space in which the reference data table and map data are stored is the address space 0x200000 to 0x2FFFF9.

The address space 0x2FFFFA to 0x2FFFFB of memory area 1 stores the power supply voltage information before writing. The address space 0x2FFFFC to 0x2FFFFD stores version information of the reference data table. The address space 0x2FFFFE to 0x2FFFFF of memory area 1 stores version information of the map data. This address space 0x2FFFFA to 0x2FFFFF is the footer of memory area 1, and is a different address space from the specific address spaces that store the reference data table and map data.

FIG. 15 is a flowchart showing the process of rewriting an erased area.
This rewriting process is executed, for example, by a user's operation to issue a rewriting instruction.

The CPU 21 determines whether or not the memory area 1 is being used (step S130), and further determines whether or not the erase flag for the memory area 0 is cleared (step S131).
If memory area 1 is being used (step S130→Yes) and the erase flag for memory area 0 has been cleared (step S131→Yes), the CPU 21 writes power supply voltage information detected by the voltage sensor 211 to the footer of memory area 0 (step S132). The CPU 21 further writes a reference data table and map data to memory area 0 (step S133), adds version information to the footer (step S134), and proceeds to the process of step S135.

If memory area 1 is not in use (step S130 → No) or the erase flag for memory area 0 has not been cleared (step S131 → No), the CPU 21 proceeds to processing of step S135.

In step S135, the CPU 21 determines whether or not the memory area 0 is being used, and further determines whether or not the erasure flag for the memory area 1 is cleared (step S136).
If memory area 0 is being used (step S135→Yes) and the deletion flag of memory area 1 has been cleared (step S136→Yes), the CPU 21 writes the power supply voltage information detected by the voltage sensor 211 to the footer of memory area 1 (step S137). The CPU 21 further writes the reference data table and map data to memory area 1 (step S138), adds version information to the footer (step S139), and ends the processing of FIG.

If memory area 0 is not in use (step S135 → No) or the erase flag for memory area 1 has not been cleared (step S136 → No), the CPU 21 ends the processing of FIG. 15.

(Modification)
The present invention is not limited to the above-described embodiment, and modifications can be made without departing from the spirit of the present invention. For example, the following modifications are possible:

(a) The information written to the memory area is not limited to reference data tables and map data, but may be data to be read and referenced by the CPU 52 of the GPS unit 5, or firmware (programs) to be read and executed by the CPU 52 of the GPS unit 5.

(b) The information stored in the footer of the storage area is not limited to a copy of the version information. For example, other information capable of identifying the data body, such as a checksum value or a CRC (Cyclic Redundancy Check) value of the data body, may be stored.
(c) The version information does not necessarily have to be stored at the beginning of the storage area, but may be stored in a memory space to which the version information is written in the first write operation. For example, the version information may be stored in an address space indicated by a predetermined offset (e.g., 0x000080) in the storage area.

(d) After writing data or software programs to the storage area, information related to the update, such as the writing date and time and the source of the data or software programs, may be written to the footer of the storage area. This makes it possible to identify the information related to the update in the event of a malfunction.
(e) The size of the footer of the storage area is not limited as long as it is equal to or smaller than the erase unit of the flash memory.
(f) Information written to the flash memory is not limited to data referenced by the CPU 52 or firmware (programs) executed by the CPU 52. It may be data referenced by the CPU 21 or firmware (programs) executed by the CPU 21.
(g) The entity that executes the process of determining whether a storage area is in use or unused is not limited to the CPU 21, and may be the CPU 52.
(h) Programs that the CPU 21 reads and executes, or data that the CPU 21 reads and references, may be written into the flash memory by the CPU 21 itself.

The inventions described in the claims originally attached to this application are set forth below. The claim numbers in the appended claims are the same as those in the claims originally attached to this application.
[Additional Notes]

<<Claim 1>>
A memory having a storage area for storing a program or data;
a processor that writes the program or the data and specific information that identifies the program or the data in a specific address space of the storage area, and writes the specific information in an address space different from the specific address space of the storage area;
A data management device comprising:
<<Claim 2>>
the memory includes a plurality of storage areas for storing the programs or the data;
the processor compares specific information included in the program or data in a specific address space of each of the storage areas with specific information included in the different address space of each of the storage areas to determine whether the data or the program has been written correctly, and erases the storage area where the data or the program has not been written correctly;
2. The data management device according to claim 1.
<<Claim 3>>
the memory includes a plurality of storage areas for storing the programs or the data;
the processor compares specific information included in the program or data in the specific address space of each of the storage areas with specific information in the different address space of each of the storage areas to determine whether the data or the program has been correctly written, and uses the program or data stored in the storage area in which the data or the program has been correctly written;
3. The data management device according to claim 1 or 2.
<<Claim 4>>
A memory having a storage area for storing a program or data;
a processor that writes new programs or data into a specific address space of the storage area, and writes capacity information indicating a capacity of the programs or data into an address space different from the specific address space of the storage area;
A data management device comprising:
<Claim 5>
The processor erases the storage area based on the capacity information stored in the different address space of the storage area.
5. The data management device according to claim 4.
<Claim 6>
A first processor;
a memory having a storage area for storing a program to be read and executed by the first processor or data to be read and referenced by the first processor;
a second processor that writes the program or the data into a specific address space of the storage area, and writes specific information that identifies the program or the data into an address space different from the specific address space of the storage area;
A data management device comprising:
<<Claim 7>>
the memory includes a plurality of storage areas for storing the programs or the data;
the second processor compares specific information included in the program or the data in the specific address space of each of the storage areas with specific information in the different address space of each of the storage areas to determine whether the data or the program has been correctly written, and causes the first processor to use the program or data stored in the storage area that has been correctly written;
7. The data management device according to claim 6.
<Claim 8>
the memory includes a plurality of storage areas for storing the programs or the data;
the first processor compares specific information included in the program or the data in the specific address space of each of the storage areas with specific information in the different address space of each of the storage areas to determine whether the data or the program has been correctly written, and reads the program or data stored in the storage area in which the data or the program has been correctly written;
7. The data management device according to claim 6.
<Claim 9>
A battery for supplying power;
a voltage sensor that detects a voltage of the power supply;
the second processor writes, together with identification information for identifying the program or the data, information on the power supply voltage detected by the voltage sensor into the different address space of the storage area;
9. The data management device according to claim 6, wherein the data management device is a data management device.
<Claim 10>
A first processor;
a memory having a storage area for storing a program to be read and executed by the first processor or data to be read and referenced by the first processor;
a second processor that writes a new program or data into a specific address space of the storage area, and writes capacity information indicating a capacity of the program or data into an address space different from the specific address space of the storage area;
A data management device comprising:
<<Claim 11>>
the second processor erases the storage area based on the capacity information stored in the different address space of the storage area;
11. The data management device according to claim 10.
<Claim 12>
A data management device according to any one of claims 1 to 11;
A timekeeping unit that counts time;
a display unit that displays the time counted by the timer unit;
An electronic watch comprising:
<Claim 13>
specific information for identifying data or a program is stored in a specific address space of a storage area, and specific information identical to the specific information is stored in an address space different from the specific address space of the storage area,
comparing the specific information of the specific address space of the storage area with the specific information of the different address space of the storage area to determine whether the data or the program has been correctly written;
A data management method comprising:
<Claim 14>
data or a program is stored in a specific address space of a storage area, and capacity information indicating a capacity of the data or the program is stored in an address space different from the specific address space of the storage area,
erasing the storage area based on the capacity information stored in the different address space of the storage area;
A data management method comprising:
<Claim 15>
a first writing means for writing data or a program into a specific address space of the storage area;
a second writing means for writing, into an address space different from the specific address space of the storage area, specific information identical to the specific information for identifying the data or the program;
a determination means for determining whether or not the data or the program has been correctly written by comparing specific information of the specific address space of the storage area with specific information of the different address space of the storage area;
A data management program that allows a computer to function as a
<Claim 16>
a first writing means for writing data or a program into a specific address space of the storage area;
a second writing means for writing capacity information indicating a capacity of the data or the program to an address space different from the specific address space of the storage area;
an erasing means for erasing the storage area based on the capacity information stored in the different address space of the storage area;
A data management program that allows a computer to function as a

1. Electronic clock (data management device)
2 Microcomputer 21 CPU (second processor)
22 RAM
23 ROM
25 Oscillator circuit 26 Divider circuit 27 Timer circuit 31 Operation unit 32 Display unit 33 Power supply unit 34 Battery 4 Communication unit 41 Antenna 5 GPS unit 51 Antenna 52 CPU (first processor)
53 RAM
6 Flash memory 61 Area 0
62 Area 1
7. Transducer

Claims (7)

A pointer that rotates by a predetermined angle at a predetermined time interval;
A storage unit having two storage areas into which objects to be written are written;
A control unit;
An electronic watch comprising:
The control unit is
determining that one of the two storage areas is a format area or a write area into which the write target will be written next time;
executing an unused area erasure process for erasing the determined formatted area or the write area when the electronic watch is in a normal mode during a time period when it is highly likely that the user is not checking the time;
An electronic watch characterized by: The control unit is
and executing the unused area erasure process during a time period other than the time period during which standard time radio wave reception is being performed.
2. The electronic watch according to claim 1, The control unit is
executes the unused area erasure process when the electronic timepiece is in a stopwatch mode and a predetermined time has elapsed since the hands stopped.
2. The electronic watch according to claim 1, The object to be written is map data.
2. The electronic watch according to claim 1, The control unit is
formatting the storage area determined to be the formatted area and setting it as an area into which the write target will be written next time;
2. The electronic watch according to claim 1, A pointer that rotates by a predetermined angle at a predetermined time interval;
A storage unit having two storage areas into which objects to be written are written;
A method executed by an electronic watch comprising:
determining that one of the two storage areas is a format area or a write area into which the write target will be written next time;
executing an unused area erasure process for erasing the determined formatted area or the write area when the electronic watch is in a normal mode during a time period when it is highly likely that the user is not checking the time;
A method comprising: A pointer that rotates by a predetermined angle at a predetermined time interval;
A storage unit having two storage areas into which objects to be written are written;
By the electronic clock computer having
determining that one of the two storage areas is a format area or a write area into which the object to be written will be written next time;
executing an unused area erasure process for erasing the determined formatted area or the write area when the electronic watch is in a normal mode during a time period when it is highly likely that the user is not checking the time;
A program characterized by: