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JP7499114B2 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP7499114B2
JP7499114B2 JP2020140090A JP2020140090A JP7499114B2 JP 7499114 B2 JP7499114 B2 JP 7499114B2 JP 2020140090 A JP2020140090 A JP 2020140090A JP 2020140090 A JP2020140090 A JP 2020140090A JP 7499114 B2 JP7499114 B2 JP 7499114B2
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Japan
Prior art keywords
semiconductor chip
main surface
semiconductor device
die pad
lead frame
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JP2020140090A
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Japanese (ja)
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JP2022035627A (en
Inventor
敏幸 岡部
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2020140090A priority Critical patent/JP7499114B2/en
Priority to US17/444,779 priority patent/US11810840B2/en
Priority to CN202110916242.5A priority patent/CN114078802A/en
Publication of JP2022035627A publication Critical patent/JP2022035627A/en
Application granted granted Critical
Publication of JP7499114B2 publication Critical patent/JP7499114B2/en
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    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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  • Lead Frames For Integrated Circuits (AREA)

Description

本開示は、半導体装置及びその製造方法に関する。 This disclosure relates to a semiconductor device and a method for manufacturing the same.

ダイパッドの上に半導体素子搭載基板が設けられ、半導体素子搭載基板の上に半導体素子が搭載されるリードフレームが提案されている（特許文献１）。 A lead frame has been proposed in which a semiconductor element mounting substrate is provided on a die pad, and a semiconductor element is mounted on the semiconductor element mounting substrate (Patent Document 1).

特開平５－２１４８０号公報Japanese Patent Application Laid-Open No. 5-21480

従来のリードフレームを用いて製造した半導体装置では、内部で短絡が生じることがある。 Semiconductor devices manufactured using conventional lead frames can sometimes experience internal short circuits.

本開示は、短絡を抑制することができる半導体装置及びその製造方法を提供することを目的とする。 The present disclosure aims to provide a semiconductor device that can suppress short circuits and a method for manufacturing the same.

本開示の一形態によれば、第１主面と、前記第１主面とは反対側の第２主面とを備え、前記第１主面に凹部を含むリードフレームと、第３主面と、前記第３主面とは反対側の第４主面とを備え、前記第４主面を前記凹部の底面に対向させて前記凹部内に配置された中継基板と、前記第３主面の上に設けられた第１半導体チップと、前記リードフレームと前記中継基板とを接続する第１導電材と、前記中継基板と前記第１半導体チップとを接続する第２導電材と、前記中継基板、前記第１半導体チップ、前記第１導電材及び前記第２導電材を封止する樹脂部と、を有し、前記リードフレームは、ダイパッドと、前記ダイパッドの周囲に配置されたリードと、を有し、前記リードは、前記第１主面に含まれる第１上面と、前記第２主面に含まれる第１下面と、前記第１上面及び前記第１下面に繋がる第１側面と、を有し、前記ダイパッドは、前記第１主面に含まれ、前記第１上面と面一の第２上面と、前記第２主面に含まれ、前記第１下面と面一の第２下面と、前記第２上面及び前記第２下面に繋がる第２側面と、を有し、前記ダイパッドの最大厚さは、前記第１上面と前記第１下面との間の距離と等しく、前記樹脂部は、前記第１下面及び前記第２下面と面一の第３下面を有し、前記樹脂部により、前記第１上面と、前記第１側面の一部と、前記第２上面と、前記第２側面とが被覆され、前記第３下面から、前記第１下面と、前記第２下面とが露出し、前記第２主面と前記第３主面との間の第２距離は、前記第２主面と前記第１主面との間の第１距離以下である半導体装置が提供される。 According to one aspect of the present disclosure, there is provided a lead frame including a first main surface and a second main surface opposite to the first main surface, the lead frame including a recess in the first main surface, an intermediate substrate including a third main surface and a fourth main surface opposite to the third main surface, the intermediate substrate being disposed in the recess with the fourth main surface facing a bottom surface of the recess, a first semiconductor chip provided on the third main surface, a first conductive material connecting the lead frame and the intermediate substrate, a second conductive material connecting the intermediate substrate and the first semiconductor chip, and a resin portion sealing the intermediate substrate, the first semiconductor chip, the first conductive material, and the second conductive material, wherein the lead frame has a die pad and leads arranged around the die pad, the leads having a first upper surface included in the first main surface and a second upper surface included in the second main surface. a first bottom surface, and a first side surface connected to the first top surface and the first bottom surface, the die pad having a second top surface included in the first main surface and flush with the first top surface, a second bottom surface included in the second main surface and flush with the first bottom surface, and a second side surface connected to the second top surface and the second bottom surface, a maximum thickness of the die pad is equal to a distance between the first top surface and the first bottom surface, the resin part has a third bottom surface flush with the first bottom surface and the second bottom surface, the first top surface, a portion of the first side surface, the second top surface, and the second side surface are covered by the resin part, the first bottom surface and the second bottom surface are exposed from the third bottom surface, and a second distance between the second main surface and the third main surface is equal to or less than a first distance between the second main surface and the first main surface.

開示の技術によれば、短絡を抑制することができる。 The disclosed technology makes it possible to suppress short circuits.

第１実施形態に係る半導体装置を示す模式図である。1 is a schematic diagram showing a semiconductor device according to a first embodiment; 第１実施形態に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment. 中継基板の例を示す断面図である。FIG. 4 is a cross-sectional view showing an example of an intermediate substrate. リードフレーム集合体のレイアウトを示す図である。FIG. 1 is a diagram showing the layout of a lead frame assembly. 第１実施形態に係る半導体装置の製造方法を示す断面図（その１）である。1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment. 第１実施形態に係る半導体装置の製造方法を示す断面図（その２）である。5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 第１実施形態に係る半導体装置の製造方法を示す断面図（その３）である。5A to 5C are cross-sectional views (part 3) showing the method for manufacturing the semiconductor device according to the first embodiment. 第１実施形態に係る半導体装置の製造方法を示す断面図（その４）である。4 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the first embodiment; 第１実施形態に係る半導体装置の製造方法を示す断面図（その５）である。5A to 5C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 第１実施形態に係る半導体装置の製造方法を示す断面図（その６）である。6 is a cross-sectional view (part 6) showing the method for manufacturing the semiconductor device according to the first embodiment; 第２例に係る中継基板の形成方法を示す断面図である。10A to 10C are cross-sectional views showing a method for forming an intermediate substrate according to a second example. 第２実施形態に係る半導体装置を示す模式図である。FIG. 11 is a schematic diagram showing a semiconductor device according to a second embodiment. 第２実施形態に係る半導体装置を示す断面図である。FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. 第３実施形態に係る半導体装置を示す断面図である。FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment.

本願発明者は、従来の半導体装置において内部で短絡が生じる原因を究明すべく鋭意検討を行った。この結果、リードフレームと半導体素子とを接続する一部のボンディングワイヤが樹脂封止の際に封止樹脂の圧力によって移動し、他のボンディングワイヤに接触していることが判明した。また、このようなボンディングワイヤの移動はボンディングワイヤを短くすることで生じにくくなることも判明した。 The inventors of the present application conducted extensive research to determine the cause of internal short circuits in conventional semiconductor devices. As a result, they discovered that some of the bonding wires connecting the lead frame and the semiconductor element move due to the pressure of the encapsulation resin during resin encapsulation, and come into contact with other bonding wires. They also discovered that such movement of the bonding wires is less likely to occur if the bonding wires are shortened.

以下、実施形態について添付の図面を参照しながら具体的に説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複した説明を省くことがある。また、本開示においては、Ｘ１－Ｘ２方向、Ｙ１－Ｙ２方向、Ｚ１－Ｚ２方向を相互に直交する方向とする。Ｘ１－Ｘ２方向及びＹ１－Ｙ２方向を含む面をＸＹ面と記載し、Ｙ１－Ｙ２方向及びＺ１－Ｚ２方向を含む面をＹＺ面と記載し、Ｚ１－Ｚ２方向及びＸ１－Ｘ２方向を含む面をＺＸ面と記載する。なお、便宜上、Ｚ１－Ｚ２方向を上下方向とする。また、平面視とは、Ｚ１側から対象物を見ることをいう。但し、半導体装置及びリードフレームは天地逆の状態で用いることができ、又は任意の角度で配置することができる。 The following describes the embodiments in detail with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid repetitive description. In this disclosure, the X1-X2, Y1-Y2, and Z1-Z2 directions are defined as mutually orthogonal directions. A plane including the X1-X2 and Y1-Y2 directions is referred to as the XY plane, a plane including the Y1-Y2 and Z1-Z2 directions is referred to as the YZ plane, and a plane including the Z1-Z2 and X1-X2 directions is referred to as the ZX plane. For convenience, the Z1-Z2 direction is referred to as the up-down direction. Planar view refers to viewing an object from the Z1 side. However, the semiconductor device and the lead frame can be used upside down or can be arranged at any angle.

（第１実施形態）
まず、第１実施形態について説明する。第１実施形態は半導体装置に関する。 First Embodiment
First, a first embodiment will be described. The first embodiment relates to a semiconductor device.

［半導体装置の構造］
まず、半導体装置の構造について説明する。図１は、第１実施形態に係る半導体装置を示す模式図である。図２は、第１実施形態に係る半導体装置を示す断面図である。図２は、図１中のII-II線に沿った断面図である。 [Structure of Semiconductor Device]
First, the structure of the semiconductor device will be described. Fig. 1 is a schematic diagram showing the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1.

図１及び図２に示すように、第１実施形態に係る半導体装置１は、リードフレーム１０と、中継基板２０と、第１半導体チップ３０と、第２半導体チップ４０とを有する。なお、図１では、樹脂部７０を透過してリードフレーム１０、中継基板２０、第１半導体チップ３０及び第２半導体チップ４０等を図示している。 As shown in Figures 1 and 2, the semiconductor device 1 according to the first embodiment has a lead frame 10, an intermediate substrate 20, a first semiconductor chip 30, and a second semiconductor chip 40. Note that in Figure 1, the lead frame 10, intermediate substrate 20, first semiconductor chip 30, and second semiconductor chip 40 are shown through a resin portion 70.

リードフレーム１０は、上面１０Ａと、上面１０Ａとは反対側の下面１０Ｂとを備える。平面視で、リードフレーム１０は、平面形状が矩形のダイパッド１６と、ダイパッド１６の周囲に配置された複数のリード１７とを有する。例えば、リード１７の平面形状は矩形状であり、リード１７は立方体状である。ダイパッド１６の下面と、リード１７の下面とが面一になっている。ダイパッド１６の下面及びリード１７の下面は、リードフレーム１０の下面１０Ｂを構成する。また、ダイパッド１６の上面には凹部１１が形成されている。ダイパッド１６の上面のうち凹部が形成されていない部分の上面と、リード１７の上面とが面一になっており、ダイパッド１６の上面のうち凹部が形成されていない部分の上面及びリード１７の上面は、リードフレーム１０の上面１０Ａを構成する。リード１７の上面に金属膜１３が形成され、ダイパッド１６の上面で凹部１１の周囲に金属膜１４が形成されている。ダイパッド１６及びリード１７の下面には金属膜１５が形成されている。図１では、金属膜１３及び１４の図示を省略している。 The lead frame 10 has an upper surface 10A and a lower surface 10B opposite to the upper surface 10A. In a plan view, the lead frame 10 has a die pad 16 having a rectangular planar shape and a plurality of leads 17 arranged around the die pad 16. For example, the planar shape of the leads 17 is rectangular, and the leads 17 are cubic. The lower surface of the die pad 16 and the lower surface of the leads 17 are flush with each other. The lower surface of the die pad 16 and the lower surfaces of the leads 17 constitute the lower surface 10B of the lead frame 10. In addition, a recess 11 is formed on the upper surface of the die pad 16. The upper surface of the part of the upper surface of the die pad 16 where the recess is not formed is flush with the upper surface of the leads 17, and the upper surface of the part of the upper surface of the die pad 16 where the recess is not formed and the upper surface of the leads 17 constitute the upper surface 10A of the lead frame 10. A metal film 13 is formed on the upper surface of the leads 17, and a metal film 14 is formed around the recess 11 on the upper surface of the die pad 16. A metal film 15 is formed on the underside of the die pad 16 and the leads 17. Metal films 13 and 14 are omitted from FIG. 1.

リードフレーム１０の材料としては、例えば、銅（Ｃｕ）、Ｃｕをベースにした合金、鉄－ニッケル（Ｆｅ－Ｎｉ）、Ｆｅ－Ｎｉをベースにした合金、又はステンレス等を用いることができる。金属膜１３、１４及び１５としては、例えば、Ａｇ膜、Ａｕ膜、Ｎｉ／Ａｕ膜（リードフレーム１０側からＮｉ膜とＡｕ膜をこの順番で積膜した金属膜）、Ｎｉ／Ｐｄ／Ａｕ膜（リードフレーム１０側からＮｉ膜とＰｄ膜とＡｕ膜をこの順番で積膜した金属膜）等を用いることができる。例えば、リードフレーム１０の凹部１１が形成されていない部分の厚さは、１５０μｍ～３００μｍであり、凹部１１の深さは、１００μｍ～２５０μｍである。 The lead frame 10 may be made of, for example, copper (Cu), a Cu-based alloy, iron-nickel (Fe-Ni), an Fe-Ni-based alloy, or stainless steel. The metal films 13, 14, and 15 may be, for example, an Ag film, an Au film, a Ni/Au film (a metal film in which a Ni film and an Au film are laminated in this order from the lead frame 10 side), or a Ni/Pd/Au film (a metal film in which a Ni film, a Pd film, and an Au film are laminated in this order from the lead frame 10 side). For example, the thickness of the portion of the lead frame 10 where the recess 11 is not formed is 150 μm to 300 μm, and the depth of the recess 11 is 100 μm to 250 μm.

中継基板２０は、上面２０Ａと、上面２０Ａとは反対側の下面２０Ｂとを備える。中継基板２０の厚さは、リード１７の厚さよりも小さく、ダイパッド１６の凹部１１が形成されていない部分の厚さよりも小さい。中継基板２０は凹部１１内に配置されている。中継基板２０は上面２０Ａに配線２１を有する。中継基板２０は下面２０Ｂが凹部１１の底面１１Ａに対向するように配置されている。底面１１Ａと下面２０Ｂとが接着剤６１により接合されている。接着剤６１としては、例えばダイアタッチフィルム、Ａｇペースト等が用いられる。図１では、配線２１の図示を省略している。 The relay board 20 has an upper surface 20A and a lower surface 20B opposite to the upper surface 20A. The thickness of the relay board 20 is smaller than the thickness of the leads 17 and smaller than the thickness of the portion of the die pad 16 where the recess 11 is not formed. The relay board 20 is disposed within the recess 11. The relay board 20 has wiring 21 on the upper surface 20A. The relay board 20 is disposed so that the lower surface 20B faces the bottom surface 11A of the recess 11. The bottom surface 11A and the lower surface 20B are bonded with an adhesive 61. For example, a die attach film, Ag paste, or the like is used as the adhesive 61. The wiring 21 is not shown in FIG. 1.

中継基板２０の上面２０Ａの上に第１半導体チップ３０が設けられている。第１半導体チップ３０は上面に電極３１を有する。中継基板２０の上面２０Ａと第１半導体チップ３０の下面とが接着剤６２により接合されている。接着剤６２としては、ダイアタッチフィルム、Ａｇペースト等が用いられる。図１では、電極３１の図示を省略している。 The first semiconductor chip 30 is provided on the upper surface 20A of the relay substrate 20. The first semiconductor chip 30 has an electrode 31 on its upper surface. The upper surface 20A of the relay substrate 20 and the lower surface of the first semiconductor chip 30 are joined with an adhesive 62. The adhesive 62 may be a die attach film, Ag paste, or the like. The electrodes 31 are not shown in FIG. 1.

第１半導体チップ３０の上に第２半導体チップ４０が設けられている。第２半導体チップ４０は上面に電極４１を有する。第１半導体チップ３０の上面と第２半導体チップの下面とが接着剤６３により接合されている。接着剤６３としては、ダイアタッチフィルム、Ａｇペースト等が用いられる。図１では、電極４１の図示を省略している。 A second semiconductor chip 40 is provided on the first semiconductor chip 30. The second semiconductor chip 40 has an electrode 41 on its upper surface. The upper surface of the first semiconductor chip 30 and the lower surface of the second semiconductor chip are joined with an adhesive 63. As the adhesive 63, a die attach film, Ag paste, or the like is used. The electrode 41 is not shown in FIG. 1.

半導体装置１は、第１ボンディングワイヤ５１と、第２ボンディングワイヤ５２と、第３ボンディングワイヤ５３と、第４ボンディングワイヤ５４とを有する。第１ボンディングワイヤ５１は、リードフレーム１０の金属膜１３又は１４と中継基板２０の配線２１とを接続する。第２ボンディングワイヤ５２は、中継基板２０の配線２１と第１半導体チップ３０の電極３１とを接続する。第３ボンディングワイヤ５３は、中継基板２０の配線２１と第２半導体チップ４０の電極４１とを接続する。第４ボンディングワイヤ５４は、第１半導体チップ３０の電極３１と第２半導体チップ４０の電極４１とを接続する。１本又は複数本の第１ボンディングワイヤ５１は、リード１７の金属膜１３と中継基板２０の配線２１とを接続し、他の１本又は複数本の第１ボンディングワイヤ５１は、ダイパッド１６の金属膜１４と中継基板２０の配線２１とを接続する。半導体装置１は、リードフレーム１０の金属膜１３又は１４と第１半導体チップ３０の電極３１とを接続するボンディングワイヤを含んでもよい。第１ボンディングワイヤ５１は第１導電材の一例であり、第２ボンディングワイヤ５２は第２導電材の一例であり、第３ボンディングワイヤ５３は第３導電材の一例であり、第４ボンディングワイヤ５４は第４導電材の一例である。ボンディングワイヤとしては、例えば、銅、金等の金属のワイヤが用いられる。 The semiconductor device 1 has a first bonding wire 51, a second bonding wire 52, a third bonding wire 53, and a fourth bonding wire 54. The first bonding wire 51 connects the metal film 13 or 14 of the lead frame 10 and the wiring 21 of the relay substrate 20. The second bonding wire 52 connects the wiring 21 of the relay substrate 20 and the electrode 31 of the first semiconductor chip 30. The third bonding wire 53 connects the wiring 21 of the relay substrate 20 and the electrode 41 of the second semiconductor chip 40. The fourth bonding wire 54 connects the electrode 31 of the first semiconductor chip 30 and the electrode 41 of the second semiconductor chip 40. One or more first bonding wires 51 connect the metal film 13 of the lead 17 and the wiring 21 of the relay substrate 20, and the other one or more first bonding wires 51 connect the metal film 14 of the die pad 16 and the wiring 21 of the relay substrate 20. The semiconductor device 1 may include a bonding wire that connects the metal film 13 or 14 of the lead frame 10 to the electrode 31 of the first semiconductor chip 30. The first bonding wire 51 is an example of a first conductive material, the second bonding wire 52 is an example of a second conductive material, the third bonding wire 53 is an example of a third conductive material, and the fourth bonding wire 54 is an example of a fourth conductive material. As the bonding wire, for example, a wire made of a metal such as copper or gold is used.

第１ボンディングワイヤ５１には、例えば、リード１７の金属膜１３と中継基板２０の配線２１とを接続する第１ボンディングワイヤ５１Ａと、ダイパッド１６の金属膜１４と中継基板２０の配線２１とを接続する第１ボンディングワイヤ５１Ｂとが含まれる。例えば、第１ボンディングワイヤ５１Ａは信号の伝送に用いられ、第１ボンディングワイヤ５１Ｂは接地電位の印加に用いられる。 The first bonding wires 51 include, for example, a first bonding wire 51A that connects the metal film 13 of the lead 17 to the wiring 21 of the relay substrate 20, and a first bonding wire 51B that connects the metal film 14 of the die pad 16 to the wiring 21 of the relay substrate 20. For example, the first bonding wire 51A is used to transmit signals, and the first bonding wire 51B is used to apply a ground potential.

半導体装置１は、中継基板２０、第１半導体チップ３０、第２半導体チップ４０、第１ボンディングワイヤ５１、第２ボンディングワイヤ５２、第３ボンディングワイヤ５３及び第４ボンディングワイヤ５４を封止する樹脂部７０を有する。樹脂部７０としては、例えば、エポキシ樹脂にフィラーを含有させた所謂モールド樹脂等が用いられる。 The semiconductor device 1 has a resin part 70 that seals the relay substrate 20, the first semiconductor chip 30, the second semiconductor chip 40, the first bonding wire 51, the second bonding wire 52, the third bonding wire 53, and the fourth bonding wire 54. For example, a so-called mold resin made of epoxy resin containing a filler is used as the resin part 70.

ダイパッド１６の下面と樹脂部７０の下面とが面一になっており、ダイパッド１６の下面が樹脂部７０の下面から露出している。また、ダイパッド１６の上面及び側面は樹脂部７０により被覆されている。 The bottom surface of the die pad 16 and the bottom surface of the resin part 70 are flush with each other, and the bottom surface of the die pad 16 is exposed from the bottom surface of the resin part 70. In addition, the top surface and side surfaces of the die pad 16 are covered by the resin part 70.

リード１７の下面と樹脂部７０の下面とが面一になっており、リード１７の下面が樹脂部７０の下面から露出している。また、リード１７の上面は樹脂部７０により被覆されている。リード１７の側面のうち、ダイパッド１６に対向する側面は樹脂部７０により被覆され、この側面とは反対側の側面は樹脂部７０の側面から露出している。また、リード１７の側面のうち、ダイパッド１６に対向する側面とこの側面とは反対側の側面との間の側面は樹脂部７０により被覆されている。 The lower surface of the lead 17 and the lower surface of the resin part 70 are flush with each other, and the lower surface of the lead 17 is exposed from the lower surface of the resin part 70. The upper surface of the lead 17 is covered by the resin part 70. Of the side surfaces of the lead 17, the side surface facing the die pad 16 is covered by the resin part 70, and the side surface opposite this side surface is exposed from the side surface of the resin part 70. Of the side surfaces of the lead 17, the side surface between the side surface facing the die pad 16 and the side surface opposite this side surface is covered by the resin part 70.

ここで、中継基板２０の例について説明する。図３は、中継基板２０の例を示す断面図である。 Here, an example of the relay board 20 will be described. Figure 3 is a cross-sectional view showing an example of the relay board 20.

図３（ａ）に示すように、第１例に係る中継基板２０１では、絶縁性の基材２２の上に、銅、銅合金等の金属を用いて配線２１が形成されている。例えば、基材２２の材料はガラスエポキシ樹脂である。すなわち、基材２２と配線２１とから片面配線基板が構成されている。基材２２の材料は、半導体装置１の用途に応じて選択できる。 As shown in FIG. 3(a), in the relay board 201 according to the first example, the wiring 21 is formed on the insulating base material 22 using a metal such as copper or a copper alloy. For example, the material of the base material 22 is glass epoxy resin. In other words, the base material 22 and the wiring 21 constitute a single-sided wiring board. The material of the base material 22 can be selected according to the application of the semiconductor device 1.

図３（ｂ）に示すように、第２例に係る中継基板２０２では、テープ基材８１の上に、銅、銅合金等の金属を用いて配線２１が形成されている。すなわち、テープ基材８１と配線２１とからＴＡＢ（tape automated bonding）テープ等のフレキシブル配線基板が構成されている。テープ基材８１は下面に設けられた接着層８２によりキャリア８３に接合されている。例えば、テープ基材８１の材料はポリイミド等の絶縁樹脂であり、キャリア８３の材料は銅、銅合金、アルミニウム及びアルミニウム合金等の金属である。第２例によれば、第１例よりも中継基板２０を薄く構成しやすい。また、キャリア８３をヒートシンクとして機能させることも可能である。キャリア８３の材料が絶縁体であってもよい。なお、キャリア８３の材料が導電性を有する場合、平面視で、キャリア８３はテープ基材８１の縁の内側にあることが好ましい。これは、詳細は後述するが、製造時におけるキャリア８３と配線２１との間の絶縁信頼性の低下を抑制するためである。 3B, in the relay board 202 according to the second example, the wiring 21 is formed on the tape base material 81 using a metal such as copper or a copper alloy. That is, the tape base material 81 and the wiring 21 constitute a flexible wiring board such as a TAB (tape automated bonding) tape. The tape base material 81 is bonded to the carrier 83 by an adhesive layer 82 provided on the lower surface. For example, the material of the tape base material 81 is an insulating resin such as polyimide, and the material of the carrier 83 is a metal such as copper, a copper alloy, aluminum, or an aluminum alloy. According to the second example, it is easier to configure the relay board 20 thinner than in the first example. It is also possible to make the carrier 83 function as a heat sink. The material of the carrier 83 may be an insulator. In addition, when the material of the carrier 83 is conductive, it is preferable that the carrier 83 is inside the edge of the tape base material 81 in a plan view. This is to suppress a decrease in the insulation reliability between the carrier 83 and the wiring 21 during manufacturing, as will be described in detail later.

中継基板２０として、多層配線構造のコアレス基板等のモジュール基板が用いられてもよい。 A module substrate such as a coreless substrate with a multilayer wiring structure may be used as the relay substrate 20.

リードフレーム１０の下面１０Ｂと中継基板２０の上面２０Ａとの間の距離Ｌ２が、リードフレーム１０の下面１０Ｂと上面１０Ａとの間の距離Ｌ１以下である。距離Ｌ２が距離Ｌ１と等しくてもよい。上面１０Ａは第１主面の一例であり、下面１０Ｂは第２主面の一例であり、上面２０Ａは第３主面の一例であり、下面１０Ｂは第４主面の一例である。 The distance L2 between the lower surface 10B of the lead frame 10 and the upper surface 20A of the relay substrate 20 is equal to or less than the distance L1 between the lower surface 10B of the lead frame 10 and the upper surface 10A. Distance L2 may be equal to distance L1. The upper surface 10A is an example of the first main surface, the lower surface 10B is an example of the second main surface, the upper surface 20A is an example of the third main surface, and the lower surface 10B is an example of the fourth main surface.

このように、第１実施形態に係る半導体装置１では、中継基板２０が凹部１１内に配置され、リードフレーム１０の下面１０Ｂと中継基板２０の上面２０Ａとの間の距離Ｌ２が、リードフレーム１０の下面１０Ｂと上面１０Ａとの間の距離Ｌ１以下である。また、第１半導体チップ３０及び第２半導体チップ４０が中継基板２０の上に設けられている。このため、ボンディングワイヤ５１～５４として短いボンディングワイヤを用いることができる。例えば、距離Ｌ２が距離Ｌ１超であると、リードフレーム１０と中継基板２０とを接続する第１ボンディングワイヤ５１が長くなり、その分だけ第１ボンディングワイヤ５１が移動しやすくなる。本実施形態では、距離Ｌ２が距離Ｌ１以下であるため、第１ボンディングワイヤ５１の移動を抑制できる。また、リードフレーム１０と第２半導体チップ４０とを１本のボンディングワイヤで接続しようとする場合、当該ボンディングワイヤは長くなりやすいが、第１実施形態では、第１ボンディングワイヤ５１、配線２１及び第３ボンディングワイヤ５３を介してリードフレーム１０と第２半導体チップ４０とを互いに接続することができる。このため、長くなりやすいボンディングワイヤを用いる必要がなく、半導体装置１の内部での短絡を抑制しやすい。なお、距離Ｌ１に金属膜１４の厚さが含まれると共に、距離Ｌ２に配線２１の厚さが含まれ、距離Ｌ２が距離Ｌ１以下になっていてもよい。 In this way, in the semiconductor device 1 according to the first embodiment, the relay substrate 20 is disposed in the recess 11, and the distance L2 between the lower surface 10B of the lead frame 10 and the upper surface 20A of the relay substrate 20 is equal to or less than the distance L1 between the lower surface 10B of the lead frame 10 and the upper surface 10A of the relay substrate 20. In addition, the first semiconductor chip 30 and the second semiconductor chip 40 are provided on the relay substrate 20. For this reason, short bonding wires can be used as the bonding wires 51 to 54. For example, if the distance L2 is greater than the distance L1, the first bonding wire 51 connecting the lead frame 10 and the relay substrate 20 becomes longer, and the first bonding wire 51 becomes more likely to move. In this embodiment, the distance L2 is equal to or less than the distance L1, so that the movement of the first bonding wire 51 can be suppressed. In addition, when attempting to connect the lead frame 10 and the second semiconductor chip 40 with one bonding wire, the bonding wire tends to be long, but in the first embodiment, the lead frame 10 and the second semiconductor chip 40 can be connected to each other via the first bonding wire 51, the wiring 21, and the third bonding wire 53. Therefore, there is no need to use a bonding wire that tends to be long, and it is easy to suppress short circuits inside the semiconductor device 1. Note that the distance L1 may include the thickness of the metal film 14, and the distance L2 may include the thickness of the wiring 21, and the distance L2 may be equal to or less than the distance L1.

更に、距離Ｌ２が距離Ｌ１以下であるため、半導体装置１の厚さ（Ｚ１－Ｚ２方向の寸法）を小さくすることができる。 Furthermore, since the distance L2 is equal to or less than the distance L1, the thickness of the semiconductor device 1 (the dimension in the Z1-Z2 direction) can be reduced.

［半導体装置の製造方法］
次に、第１実施形態に係る半導体装置１の製造方法について説明する。この方法では、複数のリードフレーム１０を含むリードフレーム集合体を形成し、その後に中継基板２０をリードフレーム１０の凹部１１に配置し、中継基板２０の上に第１半導体チップ３０及び第２半導体チップ４０を設ける。図４は、リードフレーム集合体のレイアウトを示す図である。図５～図１０は、第１実施形態に係る半導体装置１の製造方法を示す断面図である。 [Method of Manufacturing Semiconductor Device]
Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. In this method, a leadframe assembly including a plurality of leadframes 10 is formed, and then an intermediate substrate 20 is placed in the recess 11 of the leadframe 10, and a first semiconductor chip 30 and a second semiconductor chip 40 are provided on the intermediate substrate 20. Fig. 4 is a diagram showing the layout of the leadframe assembly. Figs. 5 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device 1 according to the first embodiment.

まず、リードフレーム集合体９０の平面構成について説明する。図４に示すように、リードフレーム集合体９０は、平面視略矩形状の基板フレーム９１に、複数のリードフレーム領域群９２が離間して配列された構造を有している。 First, the planar configuration of the lead frame assembly 90 will be described. As shown in FIG. 4, the lead frame assembly 90 has a structure in which a plurality of lead frame region groups 92 are arranged at a distance from each other on a substrate frame 91 that is generally rectangular in plan view.

図４に示す例では、３つのリードフレーム領域群９２を１列に配列しているが、配列するリードフレーム領域群９２の数は任意に決定することができる。また、リードフレーム領域群９２を複数列に配列しても構わない。また、図４に示す例では、互いに隣り合うリードフレーム領域群９２の間にスリット９１Ｘが設けられているが、これは必須ではない。 In the example shown in FIG. 4, three lead frame region groups 92 are arranged in one row, but the number of lead frame region groups 92 to be arranged can be determined arbitrarily. Also, the lead frame region groups 92 may be arranged in multiple rows. Also, in the example shown in FIG. 4, a slit 91X is provided between adjacent lead frame region groups 92, but this is not required.

リードフレーム領域群９２には、複数のリードフレーム領域９３がマトリクス状に配列されている。リードフレーム領域９３は、最終的に第１半導体チップ３０及び第２半導体チップ４０が搭載され、切断位置Ｃ１で切断されて、個々のリードフレーム１０となる領域である。なお、図４に示す例では、リードフレーム領域群９２が８行８列に配列されたリードフレーム領域９３から構成されているが、リードフレーム領域群９２を構成するリードフレーム領域９３の数は任意に決定することができる。 In the leadframe region group 92, a plurality of leadframe regions 93 are arranged in a matrix. The leadframe region 93 is an area where the first semiconductor chip 30 and the second semiconductor chip 40 are ultimately mounted and cut at the cutting position C1 to become individual leadframes 10. Note that in the example shown in FIG. 4, the leadframe region group 92 is composed of leadframe regions 93 arranged in 8 rows and 8 columns, but the number of leadframe regions 93 constituting the leadframe region group 92 can be determined arbitrarily.

リードフレーム集合体９０は、このような平面構成を備える。 The lead frame assembly 90 has such a planar configuration.

リードフレーム集合体９０の形成に際して、まず、図５（ａ）に示すように、金属板１０１を準備する。金属板１０１は、上面１０１Ａと、上面１０１Ａとは反対側の下面１０１Ｂとを備える。金属板１０１は、最終的にリードフレーム１０となる部材であり、上面１０１Ａがリードフレーム１０の上面１０Ａとなり、下面１０１Ｂがリードフレーム１０の下面１０Ｂとなる。金属板１０１の材料としては、例えば、銅（Ｃｕ）、Ｃｕをベースにした合金、鉄－ニッケル（Ｆｅ－Ｎｉ）、Ｆｅ－Ｎｉをベースにした合金、又はステンレス等を用いることができる。 When forming the lead frame assembly 90, first, a metal plate 101 is prepared as shown in FIG. 5(a). The metal plate 101 has an upper surface 101A and a lower surface 101B opposite to the upper surface 101A. The metal plate 101 is a member that will eventually become the lead frame 10, with the upper surface 101A becoming the upper surface 10A of the lead frame 10 and the lower surface 101B becoming the lower surface 10B of the lead frame 10. Examples of materials that can be used for the metal plate 101 include copper (Cu), a Cu-based alloy, iron-nickel (Fe-Ni), an Fe-Ni-based alloy, and stainless steel.

次に、図５（ｂ）に示すように、金属板１０１の上面１０１Ａの全面に感光性のレジスト層１１１を形成し、金属板１０１の下面１０１Ｂの全面に感光性のレジスト層１１２を形成する。レジスト層１１１及び１１２は、例えばレジスト液の塗布及び乾燥により形成してもよく、レジストフィルムの貼り付けにより形成してもよい。レジスト層１１１及び１１２としては、例えば、ドライフィルムレジストや電着レジスト等を用いることができる。 Next, as shown in FIG. 5(b), a photosensitive resist layer 111 is formed on the entire upper surface 101A of the metal plate 101, and a photosensitive resist layer 112 is formed on the entire lower surface 101B of the metal plate 101. The resist layers 111 and 112 may be formed, for example, by applying and drying a resist liquid, or by attaching a resist film. For example, dry film resist or electrodeposition resist can be used as the resist layers 111 and 112.

次に、図５（ｃ）に示すように、レジスト層１１１の露光及び現像により、レジスト層１１１に開口部１１１Ｘ及び１１１Ｙを形成し、レジスト層１１２の露光及び現像により、レジスト層１１２に開口部１１２Ｙを形成する。開口部１１１Ｘは、凹部１１を形成する予定の領域に形成される。開口部１１１Ｙ及び１１２Ｙは、ダイパッド１６とリード１７とを互いから離間させる貫通孔を形成する予定の領域に形成される。 Next, as shown in FIG. 5(c), the resist layer 111 is exposed and developed to form openings 111X and 111Y in the resist layer 111, and the resist layer 112 is exposed and developed to form openings 112Y in the resist layer 112. The openings 111X are formed in the area where the recess 11 is to be formed. The openings 111Y and 112Y are formed in the area where the through holes that separate the die pad 16 and the leads 17 from each other are to be formed.

次に、図６（ａ）に示すように、開口部１１１Ｘ及び１１１Ｙ内に露出する金属板１０１を上面１０１Ａ側からハーフエッチングすると共に、開口部１１２Ｙ内に露出する金属板１０１を下面１０１Ｂ側からハーフエッチングする。これにより、上面１０１Ａに凹部１１が形成され、金属板１０１を貫通する貫通孔１２が形成される。凹部１１は底面１１Ａを有する。金属板１０１が銅である場合には、金属板１０１のハーフエッチングには、例えば、塩化第二鉄又は塩化第二銅の水溶液を用いることができる。 Next, as shown in FIG. 6(a), the metal plate 101 exposed in the openings 111X and 111Y is half-etched from the upper surface 101A side, and the metal plate 101 exposed in the opening 112Y is half-etched from the lower surface 101B side. As a result, a recess 11 is formed in the upper surface 101A, and a through hole 12 penetrating the metal plate 101 is formed. The recess 11 has a bottom surface 11A. When the metal plate 101 is copper, for example, an aqueous solution of ferric chloride or cupric chloride can be used for half-etching the metal plate 101.

次に、図６（ｂ）に示すように、レジスト層１１１及び１１２を剥離液により剥離する。 Next, as shown in FIG. 6(b), the resist layers 111 and 112 are stripped using a stripping solution.

次に、図６（ｃ）に示すように、金属板１０１の上面１０１Ａ及び下面１０１Ｂと、凹部１１の側壁面及び底面と、貫通孔１２の側壁面とに感光性のめっきレジスト層１１３を形成する。 Next, as shown in FIG. 6(c), a photosensitive plating resist layer 113 is formed on the upper surface 101A and the lower surface 101B of the metal plate 101, the side wall surface and bottom surface of the recess 11, and the side wall surface of the through hole 12.

次に、図７（ａ）に示すように、めっきレジスト層１１３の露光及び現像により、めっきレジスト層１１３に開口部１１３Ｘ及び１１３Ｙを形成する。開口部１１３Ｘは上面１０１Ａの金属膜１３を形成する予定の領域に形成される。開口部１１３Ｙは上面１０１Ａの金属膜１４を形成する予定の領域に形成される。 Next, as shown in FIG. 7(a), the plating resist layer 113 is exposed to light and developed to form openings 113X and 113Y in the plating resist layer 113. The openings 113X are formed in the area of the upper surface 101A where the metal film 13 is to be formed. The openings 113Y are formed in the area of the upper surface 101A where the metal film 14 is to be formed.

次に、図７（ｂ）に示すように、開口部１１３Ｘ内に金属膜１３を形成し、開口部１１３Ｙ内に金属膜１４を形成する。金属膜１３及び１４は、例えば、金属板１０１を給電経路とする電解めっき法により形成できる。 Next, as shown in FIG. 7(b), a metal film 13 is formed in the opening 113X, and a metal film 14 is formed in the opening 113Y. The metal films 13 and 14 can be formed, for example, by electrolytic plating using the metal plate 101 as a power supply path.

次に、図７（ｃ）に示すように、レジスト層１１３を剥離液により剥離する。 Next, as shown in FIG. 7(c), the resist layer 113 is stripped using a stripping solution.

このようにして、リードフレーム集合体９０が形成される。 In this manner, the lead frame assembly 90 is formed.

次に、図８（ａ）に示すように、中継基板２０を凹部１１内に配置する。中継基板２０は下面２０Ｂが凹部１１の底面１１Ａに対向するように配置する。このとき、底面１１Ａと下面２０Ｂとを接着剤６１により接合する。接着剤６１としては、ダイアタッチフィルム、Ａｇペースト等が用いられる。 Next, as shown in FIG. 8(a), the relay substrate 20 is placed in the recess 11. The relay substrate 20 is placed so that the lower surface 20B faces the bottom surface 11A of the recess 11. At this time, the bottom surface 11A and the lower surface 20B are joined with an adhesive 61. As the adhesive 61, a die attach film, Ag paste, etc. are used.

次に、図８（ｂ）に示すように、中継基板２０の上に第１半導体チップ３０を設ける。第１半導体チップ３０は上面に電極３１を有する。このとき、中継基板２０の上面２０Ａと第１半導体チップ３０の下面とを接着剤６２により接合する。接着剤６２としては、ダイアタッチフィルム、Ａｇペースト等が用いられる。 Next, as shown in FIG. 8(b), a first semiconductor chip 30 is provided on the relay substrate 20. The first semiconductor chip 30 has an electrode 31 on its upper surface. At this time, the upper surface 20A of the relay substrate 20 and the lower surface of the first semiconductor chip 30 are joined with an adhesive 62. As the adhesive 62, a die attach film, Ag paste, or the like is used.

更に、同じく図８（ｂ）に示すように、第１半導体チップ３０の上に第２半導体チップ４０を設ける。第２半導体チップ４０は上面に電極４１を有する。このとき、第１半導体チップ３０の上面と第２半導体チップの下面とを接着剤６３により接合する。接着剤６３としては、ダイアタッチフィルム、Ａｇペースト等が用いられる。 Furthermore, as also shown in FIG. 8(b), a second semiconductor chip 40 is provided on the first semiconductor chip 30. The second semiconductor chip 40 has an electrode 41 on its upper surface. At this time, the upper surface of the first semiconductor chip 30 and the lower surface of the second semiconductor chip are joined with an adhesive 63. As the adhesive 63, a die attach film, Ag paste, or the like is used.

次に、図９（ａ）に示すように、第１ボンディングワイヤ５１（５１Ａ及び５１Ｂ）と、第２ボンディングワイヤ５２と、第３ボンディングワイヤ５３と、第４ボンディングワイヤ５４とを形成する。第１ボンディングワイヤ５１は、リードフレーム集合体９０の金属膜１３又は１４と中継基板２０の配線２１とを接続する。第２ボンディングワイヤ５２は、中継基板２０の配線２１と第１半導体チップ３０の電極３１とを接続する。第３ボンディングワイヤ５３は、中継基板２０の配線２１と第２半導体チップ４０の電極４１とを接続する。第４ボンディングワイヤ５４は、第１半導体チップ３０の電極３１と第２半導体チップ４０の電極４１とを接続する。更に、リードフレーム１０の金属膜１３又は１４と第１半導体チップ３０の電極３１とを接続するボンディングワイヤを形成してもよい。 9(a), a first bonding wire 51 (51A and 51B), a second bonding wire 52, a third bonding wire 53, and a fourth bonding wire 54 are formed. The first bonding wire 51 connects the metal film 13 or 14 of the lead frame assembly 90 to the wiring 21 of the relay substrate 20. The second bonding wire 52 connects the wiring 21 of the relay substrate 20 to the electrode 31 of the first semiconductor chip 30. The third bonding wire 53 connects the wiring 21 of the relay substrate 20 to the electrode 41 of the second semiconductor chip 40. The fourth bonding wire 54 connects the electrode 31 of the first semiconductor chip 30 to the electrode 41 of the second semiconductor chip 40. Furthermore, a bonding wire may be formed that connects the metal film 13 or 14 of the lead frame 10 to the electrode 31 of the first semiconductor chip 30.

次に、図９（ｂ）に示すように、中継基板２０、第１半導体チップ３０、第２半導体チップ４０、第１ボンディングワイヤ５１、第２ボンディングワイヤ５２、第３ボンディングワイヤ５３及び第４ボンディングワイヤ５４を封止する樹脂部７０を形成する。金属板１０１の下面１０１Ｂが樹脂部７０の下面から露出するようにして、金属板１０１も樹脂部７０により封止される。例えば、金属板１０１は、その下面１０１Ｂと樹脂部７０の下面とが面一になるように、樹脂部７０により封止される。樹脂部７０としては、例えば、エポキシ樹脂にフィラーを含有させた所謂モールド樹脂等を用いることができる。樹脂部７０は、例えば、トランスファーモールド法やコンプレッションモールド法等により形成できる。 9(b), a resin portion 70 is formed to seal the relay substrate 20, the first semiconductor chip 30, the second semiconductor chip 40, the first bonding wire 51, the second bonding wire 52, the third bonding wire 53, and the fourth bonding wire 54. The metal plate 101 is also sealed by the resin portion 70 so that the lower surface 101B of the metal plate 101 is exposed from the lower surface of the resin portion 70. For example, the metal plate 101 is sealed by the resin portion 70 so that the lower surface 101B of the metal plate 101 is flush with the lower surface of the resin portion 70. For example, the resin portion 70 can be a so-called mold resin in which a filler is contained in an epoxy resin. The resin portion 70 can be formed by, for example, a transfer molding method or a compression molding method.

次に、図１０（ａ）に示すように、金属板１０１の下面１０１Ｂに金属膜１５を形成する。金属膜１５は、例えば、金属板１０１を給電経路とする電解めっき法により形成できる。 Next, as shown in FIG. 10(a), a metal film 15 is formed on the lower surface 101B of the metal plate 101. The metal film 15 can be formed, for example, by electrolytic plating using the metal plate 101 as a power supply path.

次に、図１０（ｂ）に示すように、図１０（ａ）に示す構造体を切断位置Ｃ１で切断して個片化することにより、複数の半導体装置１が完成する。金属板１０１からリードフレーム１０が得られる。切断は、例えば、スライサー等により実行できる。 Next, as shown in FIG. 10(b), the structure shown in FIG. 10(a) is cut at cutting positions C1 to separate the structure, thereby completing a number of semiconductor devices 1. A lead frame 10 is obtained from the metal plate 101. The cutting can be performed, for example, by a slicer or the like.

なお、半導体装置１を１つの製品として流通させてもよいし、リードフレーム集合体９０を１つの製品として流通させてもよい。また、図８（ａ）に示すようなリードフレーム集合体９０に中継基板２０が搭載された状態の中継基板搭載リードフレームを１つの製品として流通させてもよい。 The semiconductor device 1 may be distributed as a single product, or the lead frame assembly 90 may be distributed as a single product. Also, a relay board-mounted lead frame in which a relay board 20 is mounted on a lead frame assembly 90 as shown in FIG. 8(a) may be distributed as a single product.

ここで、第２例に係る中継基板２０２の形成方法について説明する。図１１は、第２例に係る中継基板２０２の形成方法を示す断面図である。 Here, we will explain the method of forming the relay substrate 202 according to the second example. Figure 11 is a cross-sectional view showing the method of forming the relay substrate 202 according to the second example.

まず、図１１（ａ）に示すように、複数のテープ基材８１が集合したテープ基材１８１と、テープ基材１８１の上面に形成された配線２１とを備えるＴＡＢテープ等のフレキシブル基板を準備する。テープ基材１８１は、後に切断位置Ｃ２で切断されてテープ基材８１となる。 First, as shown in FIG. 11(a), a flexible substrate such as a TAB tape is prepared, which includes a tape substrate 181 formed of a plurality of tape substrates 81 and wiring 21 formed on the upper surface of the tape substrate 181. The tape substrate 181 is later cut at a cutting position C2 to form the tape substrate 81.

次に、図１１（ｂ）に示すように、テープ基材１８１の下面に接着層１８２を形成する。 Next, as shown in FIG. 11(b), an adhesive layer 182 is formed on the lower surface of the tape substrate 181.

次に、図１１（ｃ）に示すように、テープ基材１８１のテープ基材８１となる領域ごとにキャリア８３を接着層１８２に貼り付ける。 Next, as shown in FIG. 11(c), a carrier 83 is attached to the adhesive layer 182 in each area of the tape substrate 181 that will become the tape substrate 81.

次に、図１１（ｄ）に示すように、図１１（ｃ）に示す構造体を切断位置Ｃ２で切断して個片化することにより、複数の中継基板２０２が完成する。テープ基材１８１からテープ基材８１が得られ、接着層１８２から接着層８２が得られる。 Next, as shown in FIG. 11(d), the structure shown in FIG. 11(c) is cut at cutting position C2 to separate it into individual pieces, thereby completing a plurality of relay substrates 202. Tape substrate 81 is obtained from tape substrate 181, and adhesive layer 82 is obtained from adhesive layer 182.

図１１（ｃ）に示す工程では、テープ基材１８１のテープ基材８１となる領域ごとにキャリア８３を貼り付けているが、キャリア８３が集合して構成された１つのキャリア集合体を貼り付け、図１１（ｄ）に示す工程においてキャリア集合体を含む構造体を切断位置Ｃ２で切断してもよい。ただし、キャリア集合体が金属製である場合、キャリア集合体の切断時に金属バリが生じたり、金属の切断粉がテープ基材８１の側面に付着したりするおそれがある。そして、金属バリや切断粉により、キャリア８３と配線２１とがショートするおそれがある。このため、キャリア８３が金属製である場合は、絶縁信頼性の低下を抑制するために、キャリア８３をテープ基材８１となる領域ごとに準備し、その切断を行わないことが好ましい。そして、この場合には、結果的に、平面視で、キャリア８３がテープ基材８１の縁の内側に位置するようになる。 11(c), the carrier 83 is attached to each region of the tape substrate 181 that will become the tape substrate 81, but a single carrier assembly formed by assembling the carriers 83 may be attached, and the structure including the carrier assembly may be cut at the cutting position C2 in the process shown in FIG. 11(d). However, if the carrier assembly is made of metal, there is a risk that metal burrs may be generated when the carrier assembly is cut, or that metal cutting powder may adhere to the side of the tape substrate 81. The metal burrs or cutting powder may cause a short circuit between the carrier 83 and the wiring 21. For this reason, if the carrier 83 is made of metal, it is preferable to prepare the carrier 83 for each region that will become the tape substrate 81 and not cut it, in order to suppress a decrease in insulation reliability. In this case, the carrier 83 will end up being located inside the edge of the tape substrate 81 in a plan view.

（第２実施形態）
次に、第２実施形態について説明する。第２実施形態は、主として第１半導体チップ及び第２半導体チップの配置の点で第１実施形態と相違する。図１２は、第２実施形態に係る半導体装置を示す模式図である。図１３は、第２実施形態に係る半導体装置を示す断面図である。図１３は、図１２中のXIII-XIII線に沿った断面図である。なお、図１２では、樹脂部７０を透過してリードフレーム１０、中継基板２０、第１半導体チップ３０及び第２半導体チップ４０等を図示している。また、図１２では、配線２１等の図示を省略している。 Second Embodiment
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the arrangement of the first semiconductor chip and the second semiconductor chip. FIG. 12 is a schematic diagram showing a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. Note that FIG. 12 illustrates the lead frame 10, relay substrate 20, first semiconductor chip 30, second semiconductor chip 40, etc. through the resin part 70. Also, FIG. 12 omits the illustration of wiring 21, etc.

図１２及び図１３に示すように、第２実施形態に係る半導体装置２では、第２半導体チップ４０が中継基板２０の上に第１半導体チップ３０と並んで設けられている。中継基板２０の上面２０Ａと第２半導体チップ４０の下面とが接着剤６３により接合されている。 As shown in Figures 12 and 13, in the semiconductor device 2 according to the second embodiment, the second semiconductor chip 40 is provided on the relay substrate 20 alongside the first semiconductor chip 30. The upper surface 20A of the relay substrate 20 and the lower surface of the second semiconductor chip 40 are joined with an adhesive 63.

半導体装置２は、第１ボンディングワイヤ５１と、第２ボンディングワイヤ５２と、第３ボンディングワイヤ５３と、第４ボンディングワイヤ５４とを有する。第１ボンディングワイヤ５１は、リードフレーム１０の金属膜１３又は１４と中継基板２０の配線２１とを接続する。第２ボンディングワイヤ５２は、中継基板２０の配線２１と第１半導体チップ３０の電極３１とを接続する。第３ボンディングワイヤ５３は、中継基板２０の配線２１と第２半導体チップ４０の電極４１とを接続する。第４ボンディングワイヤ５４は、第１半導体チップ３０の電極３１と第２半導体チップ４０の電極４１とを接続する。 The semiconductor device 2 has a first bonding wire 51, a second bonding wire 52, a third bonding wire 53, and a fourth bonding wire 54. The first bonding wire 51 connects the metal film 13 or 14 of the lead frame 10 to the wiring 21 of the relay substrate 20. The second bonding wire 52 connects the wiring 21 of the relay substrate 20 to the electrode 31 of the first semiconductor chip 30. The third bonding wire 53 connects the wiring 21 of the relay substrate 20 to the electrode 41 of the second semiconductor chip 40. The fourth bonding wire 54 connects the electrode 31 of the first semiconductor chip 30 to the electrode 41 of the second semiconductor chip 40.

他の構成は第１実施形態と同様である。 The other configurations are the same as in the first embodiment.

例えば、平面視で、リードフレーム１０は、平面形状が矩形のダイパッド１６と、ダイパッド１６の周囲に配置された複数のリード１７とを有する。例えば、リード１７の平面形状は矩形状であり、リード１７は立方体状である。ダイパッド１６の下面と、リード１７の下面とが面一になっている。ダイパッド１６の下面及びリード１７の下面は、リードフレーム１０の下面１０Ｂを構成する。また、ダイパッド１６の上面には凹部１１が形成されている。ダイパッド１６の上面のうち凹部が形成されていない部分の上面と、リード１７の上面とが面一になっており、ダイパッド１６の上面のうち凹部が形成されていない部分の上面及びリード１７の上面は、リードフレーム１０の上面１０Ａを構成する。 For example, in a plan view, the lead frame 10 has a die pad 16 with a rectangular planar shape and a number of leads 17 arranged around the die pad 16. For example, the planar shape of the leads 17 is rectangular, and the leads 17 are cubic. The lower surface of the die pad 16 and the lower surface of the leads 17 are flush with each other. The lower surface of the die pad 16 and the lower surfaces of the leads 17 constitute the lower surface 10B of the lead frame 10. In addition, a recess 11 is formed on the upper surface of the die pad 16. The upper surface of the portion of the upper surface of the die pad 16 where the recess is not formed is flush with the upper surface of the leads 17, and the upper surface of the portion of the upper surface of the die pad 16 where the recess is not formed and the upper surface of the leads 17 constitute the upper surface 10A of the lead frame 10.

ダイパッド１６の下面と樹脂部７０の下面とが面一になっており、ダイパッド１６の下面が樹脂部７０の下面から露出している。また、ダイパッド１６の上面及び側面は樹脂部７０により被覆されている。 The bottom surface of the die pad 16 and the bottom surface of the resin part 70 are flush with each other, and the bottom surface of the die pad 16 is exposed from the bottom surface of the resin part 70. In addition, the top surface and side surfaces of the die pad 16 are covered by the resin part 70.

リード１７の下面と樹脂部７０の下面とが面一になっており、リード１７の下面が樹脂部７０の下面から露出している。また、リード１７の上面は樹脂部７０により被覆されている。リード１７の側面のうち、ダイパッド１６に対向する側面は樹脂部７０により被覆され、この側面とは反対側の側面は樹脂部７０の側面から露出している。また、リード１７の側面のうち、ダイパッド１６に対向する側面とこの側面とは反対側の側面との間の側面は樹脂部７０により被覆されている。 The lower surface of the lead 17 and the lower surface of the resin part 70 are flush with each other, and the lower surface of the lead 17 is exposed from the lower surface of the resin part 70. The upper surface of the lead 17 is covered by the resin part 70. Of the side surfaces of the lead 17, the side surface facing the die pad 16 is covered by the resin part 70, and the side surface opposite this side surface is exposed from the side surface of the resin part 70. Of the side surfaces of the lead 17, the side surface between the side surface facing the die pad 16 and the side surface opposite this side surface is covered by the resin part 70.

第２実施形態においても、ボンディングワイヤ５１～５４として短いボンディングワイヤを用いることができる。例えば、本実施形態でも、距離Ｌ２が距離Ｌ１以下であるため、第１ボンディングワイヤ５１の移動を抑制できる。また、第２半導体チップ４０の電極４１に電気的に接続されるリード１７と第２半導体チップ４０との間に第１半導体チップ３０が位置する場合でも、第１ボンディングワイヤ５１、配線２１及び第３ボンディングワイヤ５３を介してリードフレーム１０と第２半導体チップ４０とを互いに接続することができる。つまり、第１半導体チップ３０を跨ぎ、長くなりやすいボンディングワイヤを用いる必要がなく、半導体装置２の内部での短絡を抑制しやすい。 In the second embodiment, short bonding wires can be used as the bonding wires 51 to 54. For example, in this embodiment, the distance L2 is equal to or less than the distance L1, so that the movement of the first bonding wire 51 can be suppressed. Even if the first semiconductor chip 30 is located between the second semiconductor chip 40 and the lead 17 electrically connected to the electrode 41 of the second semiconductor chip 40, the lead frame 10 and the second semiconductor chip 40 can be connected to each other via the first bonding wire 51, the wiring 21, and the third bonding wire 53. In other words, there is no need to use a bonding wire that spans the first semiconductor chip 30 and is likely to become long, making it easier to suppress short circuits inside the semiconductor device 2.

（第３実施形態）
次に、第３実施形態について説明する。第３実施形態は、主として第１半導体チップの実装の形態の点で第１実施形態と相違する。図１４は、第３実施形態に係る半導体装置を示す断面図である。 Third Embodiment
Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the manner in which the first semiconductor chip is mounted. Fig. 14 is a cross-sectional view showing a semiconductor device according to the third embodiment.

図１４に示すように、第３実施形態に係る半導体装置３では、第１半導体チップ３０が電極３１に代えて電極３３１を有する。第１半導体チップ３０は、電極３３１が形成された面が中継基板２０の上面２０Ａに対向するようにして中継基板２０に実装されている。すなわち、第１半導体チップ３０は中継基板２０にフリップチップ実装されている。配線２１と電極３３１との間には導電バンプ３５２が設けられており、導電バンプ３５２により、配線２１と電極３３１とが互いに接続されている。導電バンプ３５２は第２導電材の一例である。導電バンプ３５２としては、例えばはんだバンプが用いられる。 As shown in FIG. 14, in the semiconductor device 3 according to the third embodiment, the first semiconductor chip 30 has an electrode 331 instead of the electrode 31. The first semiconductor chip 30 is mounted on the relay substrate 20 such that the surface on which the electrode 331 is formed faces the upper surface 20A of the relay substrate 20. In other words, the first semiconductor chip 30 is flip-chip mounted on the relay substrate 20. A conductive bump 352 is provided between the wiring 21 and the electrode 331, and the wiring 21 and the electrode 331 are connected to each other by the conductive bump 352. The conductive bump 352 is an example of a second conductive material. For example, a solder bump is used as the conductive bump 352.

第２半導体チップ４０は、第１半導体チップ３０の電極３３１が設けられた面とは反対側の面の上に設けられている。第１半導体チップ３０と第２半導体チップ４０とが接着剤６３により接合されている。 The second semiconductor chip 40 is provided on the surface opposite to the surface on which the electrodes 331 of the first semiconductor chip 30 are provided. The first semiconductor chip 30 and the second semiconductor chip 40 are joined by an adhesive 63.

第１実施形態と同様に、半導体装置２は、第１ボンディングワイヤ５１と、第３ボンディングワイヤ５３とを有する。中継基板２０の配線２１と第１半導体チップ３０の電極３１とを接続する第２ボンディングワイヤ５２は必要とされない。第１半導体チップ３０の電極３１と第２半導体チップ４０の電極４１とを接続する第４ボンディングワイヤ５４も必要とされない。 As in the first embodiment, the semiconductor device 2 has a first bonding wire 51 and a third bonding wire 53. The second bonding wire 52 that connects the wiring 21 of the relay substrate 20 and the electrode 31 of the first semiconductor chip 30 is not required. The fourth bonding wire 54 that connects the electrode 31 of the first semiconductor chip 30 and the electrode 41 of the second semiconductor chip 40 is also not required.

他の構成は第１実施形態と同様である。 The other configurations are the same as in the first embodiment.

例えば、平面視で、リードフレーム１０は、平面形状が矩形のダイパッド１６と、ダイパッド１６の周囲に配置された複数のリード１７とを有する。例えば、リード１７の平面形状は矩形状であり、リード１７は立方体状である。ダイパッド１６の下面と、リード１７の下面とが面一になっている。ダイパッド１６の下面及びリード１７の下面は、リードフレーム１０の下面１０Ｂを構成する。また、ダイパッド１６の上面には凹部１１が形成されている。ダイパッド１６の上面のうち凹部が形成されていない部分の上面と、リード１７の上面とが面一になっており、ダイパッド１６の上面のうち凹部が形成されていない部分の上面及びリード１７の上面は、リードフレーム１０の上面１０Ａを構成する。 For example, in a plan view, the lead frame 10 has a die pad 16 with a rectangular planar shape and a number of leads 17 arranged around the die pad 16. For example, the planar shape of the leads 17 is rectangular, and the leads 17 are cubic. The lower surface of the die pad 16 and the lower surface of the leads 17 are flush with each other. The lower surface of the die pad 16 and the lower surfaces of the leads 17 constitute the lower surface 10B of the lead frame 10. In addition, a recess 11 is formed on the upper surface of the die pad 16. The upper surface of the portion of the upper surface of the die pad 16 where the recess is not formed is flush with the upper surface of the leads 17, and the upper surface of the portion of the upper surface of the die pad 16 where the recess is not formed and the upper surface of the leads 17 constitute the upper surface 10A of the lead frame 10.

ダイパッド１６の下面と樹脂部７０の下面とが面一になっており、ダイパッド１６の下面が樹脂部７０の下面から露出している。また、ダイパッド１６の上面及び側面は樹脂部７０により被覆されている。 The bottom surface of the die pad 16 and the bottom surface of the resin part 70 are flush with each other, and the bottom surface of the die pad 16 is exposed from the bottom surface of the resin part 70. In addition, the top surface and side surfaces of the die pad 16 are covered by the resin part 70.

リード１７の下面と樹脂部７０の下面とが面一になっており、リード１７の下面が樹脂部７０の下面から露出している。また、リード１７の上面は樹脂部７０により被覆されている。リード１７の側面のうち、ダイパッド１６に対向する側面は樹脂部７０により被覆され、この側面とは反対側の側面は樹脂部７０の側面から露出している。また、リード１７の側面のうち、ダイパッド１６に対向する側面とこの側面とは反対側の側面との間の側面は樹脂部７０により被覆されている。 The lower surface of the lead 17 and the lower surface of the resin part 70 are flush with each other, and the lower surface of the lead 17 is exposed from the lower surface of the resin part 70. The upper surface of the lead 17 is covered by the resin part 70. Of the side surfaces of the lead 17, the side surface facing the die pad 16 is covered by the resin part 70, and the side surface opposite this side surface is exposed from the side surface of the resin part 70. Of the side surfaces of the lead 17, the side surface between the side surface facing the die pad 16 and the side surface opposite this side surface is covered by the resin part 70.

第３実施形態においても、ボンディングワイヤ５１及び５３として短いボンディングワイヤを用いることができる。例えば、本実施形態でも、距離Ｌ２が距離Ｌ１以下であるため、第１ボンディングワイヤ５１の移動を抑制できる。また、リードフレーム１０と第２半導体チップ４０とを１本のボンディングワイヤで接続しようとする場合、当該ボンディングワイヤは長くなりやすいが、第３実施形態では、第１ボンディングワイヤ５１、配線２１及び第３ボンディングワイヤ５３を介してリードフレーム１０と第２半導体チップ４０とを互いに接続することができる。このため、長くなりやすいボンディングワイヤを用いる必要がなく、半導体装置３の内部での短絡を抑制しやすい。 In the third embodiment, short bonding wires can be used as the bonding wires 51 and 53. For example, in this embodiment, the distance L2 is equal to or less than the distance L1, so that the movement of the first bonding wire 51 can be suppressed. In addition, when attempting to connect the lead frame 10 and the second semiconductor chip 40 with a single bonding wire, the bonding wire tends to be long. However, in the third embodiment, the lead frame 10 and the second semiconductor chip 40 can be connected to each other via the first bonding wire 51, the wiring 21, and the third bonding wire 53. Therefore, there is no need to use a bonding wire that tends to be long, and it is easy to suppress short circuits inside the semiconductor device 3.

以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。 Although the preferred embodiments have been described above in detail, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

１、２、３ 半導体装置
１０ リードフレーム
１０Ａ 上面（第１主面）
１０Ｂ 下面（第２主面）
１１ 凹部
１１Ａ 底面
１６ ダイパッド
１７ リード
２０、２０１、２０２ 中継基板
２０Ａ 上面（第３主面）
２０Ｂ 下面（第４主面）
３０、４０ 半導体チップ
５１、５２、５３、５４ ボンディングワイヤ 1, 2, 3 Semiconductor device 10 Lead frame 10A Top surface (first main surface)
10B Lower surface (second main surface)
11: Recess 11A: Bottom surface 16: Die pad 17: Leads 20, 201, 202: Interconnect substrate 20A: Top surface (third main surface)
20B Lower surface (fourth main surface)
30, 40 Semiconductor chip 51, 52, 53, 54 Bonding wire

Claims (10)

第１主面と、前記第１主面とは反対側の第２主面とを備え、前記第１主面に凹部を含むリードフレームと、
第３主面と、前記第３主面とは反対側の第４主面とを備え、前記第４主面を前記凹部の底面に対向させて前記凹部内に配置された中継基板と、
前記第３主面の上に設けられた第１半導体チップと、
前記リードフレームと前記中継基板とを接続する第１導電材と、
前記中継基板と前記第１半導体チップとを接続する第２導電材と、
前記中継基板、前記第１半導体チップ、前記第１導電材及び前記第２導電材を封止する樹脂部と、
を有し、
前記リードフレームは、
前記凹部を含むダイパッドと、
前記ダイパッドの周囲に配置されたリードと、
を有し、
前記リードは、
前記第１主面に含まれる第１上面と、
前記第２主面に含まれる第１下面と、
前記第１上面及び前記第１下面に繋がる第１側面と、
を有し、
前記ダイパッドは、
前記第１主面に含まれ、前記第１上面と面一の第２上面と、
前記第２主面に含まれ、前記第１下面と面一の第２下面と、
前記第２上面及び前記第２下面に繋がる第２側面と、
を有し、
前記ダイパッドの最大厚さは、前記第１上面と前記第１下面との間の距離と等しく、
前記樹脂部は、前記第１下面及び前記第２下面と面一の第３下面を有し、
前記樹脂部により、前記第１上面と、前記第１側面の一部と、前記第２上面と、前記第２側面とが被覆され、
前記第３下面から、前記第１下面と、前記第２下面とが露出し、
前記第２主面と前記第３主面との間の第２距離は、前記第２主面と前記第１主面との間の第１距離以下であることを特徴とする半導体装置。 a lead frame having a first major surface and a second major surface opposite the first major surface, the first major surface including a recess;
an intermediate substrate including a third main surface and a fourth main surface opposite to the third main surface, the intermediate substrate being disposed in the recess with the fourth main surface facing a bottom surface of the recess;
a first semiconductor chip provided on the third main surface;
a first conductive material connecting the lead frame and the intermediate substrate;
a second conductive material that connects the intermediate substrate and the first semiconductor chip;
a resin portion that seals the relay substrate, the first semiconductor chip, the first conductive material, and the second conductive material;
having
The lead frame is
a die pad including the recess;
leads arranged around the die pad;
having
The lead is
A first upper surface included in the first main surface;
A first lower surface included in the second main surface;
a first side surface connected to the first upper surface and the first lower surface;
having
The die pad is
a second upper surface included in the first main surface and flush with the first upper surface;
a second lower surface included in the second main surface and flush with the first lower surface;
a second side surface connected to the second upper surface and the second lower surface;
having
a maximum thickness of the die pad is equal to a distance between the first upper surface and the first lower surface;
the resin portion has a third lower surface that is flush with the first lower surface and the second lower surface,
the resin portion covers the first upper surface, a portion of the first side surface, the second upper surface, and the second side surface;
the first lower surface and the second lower surface are exposed from the third lower surface,
A semiconductor device, wherein a second distance between the second main surface and the third main surface is equal to or smaller than a first distance between the second main surface and the first main surface. 前記第１導電材は、ボンディングワイヤであり、
前記第２導電材は、ボンディングワイヤ又は導電バンプであることを特徴とする請求項１に記載の半導体装置。 the first conductive material is a bonding wire;
2. The semiconductor device according to claim 1, wherein the second conductive material is a bonding wire or a conductive bump. 前記第３主面の上方に設けられた第２半導体チップと、
前記中継基板と前記第２半導体チップとを接続する第３導電材と、
を有することを特徴とする請求項１又は２に記載の半導体装置。 a second semiconductor chip provided above the third main surface;
a third conductive material that connects the intermediate substrate and the second semiconductor chip;
3. The semiconductor device according to claim 1, further comprising: 前記第３導電材は、ボンディングワイヤであることを特徴とする請求項３に記載の半導体装置。 The semiconductor device according to claim 3, characterized in that the third conductive material is a bonding wire. 前記第１半導体チップと前記第２半導体チップとを接続する第４導電材を有することを特徴とする請求項３又は４に記載の半導体装置。 The semiconductor device according to claim 3 or 4, characterized in that it has a fourth conductive material that connects the first semiconductor chip and the second semiconductor chip. 前記第２半導体チップは、前記第１半導体チップの上に設けられていることを特徴とする請求項３乃至５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 3 to 5, characterized in that the second semiconductor chip is provided on the first semiconductor chip. 前記第２半導体チップは、前記中継基板の上に、前記第１半導体チップと並んで設けられていることを特徴とする請求項３乃至５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 3 to 5, characterized in that the second semiconductor chip is provided on the intermediate substrate alongside the first semiconductor chip. 前記中継基板は、配線基板を含むことを特徴とする請求項１乃至７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, characterized in that the relay substrate includes a wiring substrate. 前記中継基板は、フレキシブル配線基板を含むことを特徴とする請求項１乃至７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, characterized in that the relay substrate includes a flexible wiring substrate. 第１主面と、前記第１主面とは反対側の第２主面とを備え、前記第１主面に凹部を含むリードフレームを作成する工程と、
第３主面と、前記第３主面とは反対側の第４主面とを備える中継基板を、前記第４主面を前記凹部の底面に対向させて前記凹部内に配置する工程と、
前記第３主面の上に第１半導体チップを設ける工程と、
前記リードフレームと前記中継基板とを接続する第１導電材を設ける工程と、
前記中継基板と前記第１半導体チップとを接続する第２導電材を設ける工程と、
前記中継基板、前記第１半導体チップ、前記第１導電材及び前記第２導電材を封止する樹脂部を設ける工程と、
を有し、
前記リードフレームは、
前記凹部を含むダイパッドと、
前記ダイパッドの周囲に配置されたリードと、
を有し、
前記リードは、
前記第１主面に含まれる第１上面と、
前記第２主面に含まれる第１下面と、
前記第１上面及び前記第１下面に繋がる第１側面と、
を有し、
前記ダイパッドは、
前記第１主面に含まれ、前記第１上面と面一の第２上面と、
前記第２主面に含まれ、前記第１下面と面一の第２下面と、
前記第２上面及び前記第２下面に繋がる第２側面と、
を有し、
前記ダイパッドの最大厚さは、前記第１上面と前記第１下面との間の距離と等しく、
前記樹脂部は、前記第１下面及び前記第２下面と面一の第３下面を有し、
前記樹脂部により、前記第１上面と、前記第１側面の一部と、前記第２上面と、前記第２側面とが被覆され、
前記第３下面から、前記第１下面と、前記第２下面とが露出し、
前記第２主面と前記第３主面との間の第２距離は、前記第２主面と前記第１主面との間の第１距離以下であることを特徴とする半導体装置の製造方法。 creating a leadframe having a first major surface and a second major surface opposite the first major surface, the first major surface including a recess;
a step of disposing an intermediate substrate having a third main surface and a fourth main surface opposite to the third main surface in the recess with the fourth main surface facing a bottom surface of the recess;
providing a first semiconductor chip on the third major surface;
providing a first conductive material that connects the lead frame and the relay substrate;
providing a second conductive material that connects the relay substrate and the first semiconductor chip;
providing a resin portion that seals the relay substrate, the first semiconductor chip, the first conductive material, and the second conductive material;
having
The lead frame is
a die pad including the recess;
leads arranged around the die pad;
having
The lead is
A first upper surface included in the first main surface;
A first lower surface included in the second main surface;
a first side surface connected to the first upper surface and the first lower surface;
having
The die pad is
a second upper surface included in the first main surface and flush with the first upper surface;
a second lower surface included in the second main surface and flush with the first lower surface;
a second side surface connected to the second upper surface and the second lower surface;
having
a maximum thickness of the die pad is equal to the distance between the first upper surface and the first lower surface;
the resin portion has a third lower surface that is flush with the first lower surface and the second lower surface,
the resin portion covers the first upper surface, a portion of the first side surface, the second upper surface, and the second side surface;
the first lower surface and the second lower surface are exposed from the third lower surface,
A method for manufacturing a semiconductor device, wherein a second distance between the second main surface and the third main surface is equal to or less than a first distance between the second main surface and the first main surface.
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