JP7499089B2 - Display device - Google Patents

Description

This disclosure relates to a display device.

OLED (Organic Light-Emitting Diode) elements are current-driven self-emitting elements, which eliminate the need for a backlight and have the advantages of low power consumption, a wide viewing angle, and a high contrast ratio. In addition, flexible OLED display devices using organic EL devices do not require a backlight, making it possible to realize ultra-thin and flexible display devices.

The substrate structure of a conventional flexible OLED display device has a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially laminated on a polyimide film having a thickness of 10 um to 15 um, and a TFT (Thin Film Transistor) array is formed on the substrate.

JP 2017-216323 A JP 2018-6671 A

Flexible OLED display devices that use a polyimide film as a substrate have the problem of stronger image retention (reversible afterimage) than OLED display devices that use a glass substrate.

The display device according to one aspect of the present disclosure includes a first polyimide layer, a first silicon oxide layer formed on and in direct contact with the first polyimide layer, an amorphous silicon layer formed on and in direct contact with the first silicon oxide layer, a second polyimide layer formed on and in direct contact with the amorphous silicon layer, a plurality of light-emitting elements formed on the second polyimide layer, a transistor array formed on the second polyimide layer for controlling the light emission of the plurality of light-emitting elements, a transparent conductive layer formed between the transistor array and the second polyimide layer, and a second silicon oxide layer formed between the transparent conductive layer and the second polyimide layer in direct contact with each of the transparent conductive layer and the second polyimide layer.

According to one aspect of the present disclosure, it is possible to prevent the laminated film constituting the display device from peeling off during manufacturing, or to reduce image retention in a display device with improved bending resistance.

1 shows a schematic configuration example of an OLED display device. 2 shows a configuration example of a pixel circuit. 4 shows another example of the configuration of the pixel circuit. The results of a comparative evaluation of the characteristics of a TFT on a conventional flexible substrate and a TFT on a glass substrate are shown. 2A and 2B are schematic diagrams illustrating cross-sectional structures of a flexible substrate, a driving TFT, an OLED element, and a sealing structure of a TFT substrate. 1 shows a process for manufacturing a backplane in an example of a method for manufacturing an OLED display device. 1 shows a process for manufacturing a backplane in an example of a method for manufacturing an OLED display device. 1 shows a schematic cross section of an OLED display device of a comparative example. 1 shows a schematic cross-section of an OLED display device including a transparent conductive layer according to an embodiment.

Below, an embodiment of the present invention will be described with reference to the attached drawings. It should be noted that this embodiment is merely one example for realizing the present invention, and does not limit the technical scope of the present invention. The same reference symbols are used for common configurations in each drawing. For ease of understanding, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

The OLED (Organic Light-Emitting Diode) display device disclosed below includes a transparent conductive layer between a polyimide layer and a TFT (Thin Film Transistor) array. The transparent conductive layer reduces the effect of the electric field caused by the charges in the polyimide layer on the characteristics of the TFT, and can reduce image retention. In addition, the transparent conductive layer can avoid the effect on alignment in later processes without the need for patterning.

The OLED display device disclosed below further includes an adhesion improving layer between the transparent conductive layer and the polyimide layer. The adhesion improving layer can prevent the transparent conductive layer from peeling off from the polyimide layer. The features of this embodiment can be applied to a self-luminous display device different from the OLED display device.
[overall structure]

Figure 1 shows a schematic example of the configuration of an OLED display device 10. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light-emitting elements) are formed, and a sealing structure 200 that seals the OLED elements. A scanning driver 131, an emission driver 132, a protection circuit 133, a driver IC 134, and a demultiplexer 136 are arranged around the cathode electrode formation region 114 outside the display region 125 of the TFT substrate 100.

The driver IC 134 is connected to external devices via a flexible printed circuit (FPC) 135. The scan driver 131 drives the scan lines of the TFT substrate 100. The emission driver 132 drives the emission control lines to control the emission of each pixel. The protection circuit 133 prevents electrostatic damage to elements in the TFT substrate. The driver IC 134 is implemented using, for example, an anisotropic conductive film (ACF).

The driver IC 134 provides power and timing signals (control signals) to the scan driver 131 and the emission driver 132. In addition, the driver IC 134 provides power and data signals to the demultiplexer 136.

The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 136 switches the output data line of the data signal from the driver IC 134 d times within a scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 134.
[Circuit configuration]

On the TFT substrate 100, a number of pixel circuits are formed, which control the current supplied to the anode electrodes of the sub-pixels. FIG. 2A shows an example of the configuration of the pixel circuits. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the emission of the OLED element E1. The transistors are TFTs.

The selection transistor T2 is a switch that selects a subpixel. The selection transistor T2 is a p-channel TFT, and the gate terminal is connected to the scanning line 106. The source terminal is connected to the data line 105. The drain terminal is connected to the gate terminal of the drive transistor T1.

The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the power supply line 108 (Vdd). The drain terminal is connected to the source terminal of the emission transistor T3. A storage capacitor C1 is formed between the gate terminal and source terminal of the driving transistor T1.

The emission transistor T3 is a switch that controls the supply and stop of the drive current to the OLED element E1. The emission transistor T3 is a p-channel TFT, and the gate terminal is connected to the emission control line 107. The source terminal of the emission transistor T3 is connected to the drain terminal of the drive transistor T1. The drain terminal of the emission transistor T3 is connected to the OLED element E1.

Next, the operation of the pixel circuit will be described. The scanning driver 131 outputs a selection pulse to the scanning line 106, turning on the selection transistor T2. The data voltage supplied from the driver IC 134 via the data line 105 is stored in the holding capacitance C1. The holding capacitance C1 holds the stored voltage throughout one frame period. The hold voltage causes the conductance of the driving transistor T1 to change in an analog manner, and the driving transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

The emission transistor T3 is located on the supply path of the drive current. The emission driver 132 outputs a control signal to the emission control line 107 to control the on/off of the emission transistor T3. When the emission transistor T3 is in the on state, the drive current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, this supply is stopped. By controlling the on/off of the emission transistor T3, the lighting period (duty ratio) within one field period can be controlled.

Figure 2B shows another example of the configuration of a pixel circuit. This pixel circuit has a reset transistor T4 instead of the emission transistor T3 in Figure 2A. The reset transistor T4 controls the electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from a reset control line 109 to the gate of the reset transistor T4.

The reset transistor T4 can be used for various purposes. For example, the reset transistor T4 may be used to temporarily reset the anode electrode of the OLED element E1 to a voltage sufficiently low below the black signal level in order to suppress crosstalk due to leakage current between the OLED elements E1.

The reset transistor T4 may also be used to measure the characteristics of the drive transistor T1. For example, by selecting bias conditions so that the drive transistor T1 operates in the saturation region and the reset transistor T4 operates in the linear region, and measuring the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref), the voltage-current conversion characteristics of the drive transistor T1 can be accurately measured. By generating a data signal in an external circuit that compensates for differences in the voltage-current conversion characteristics of the drive transistor T1 between subpixels, a highly uniform display image can be achieved.

On the other hand, if the drive transistor T1 is turned off and the reset transistor T4 is operated in the linear region, and a voltage that causes the OLED element E1 to emit light is applied from the reference voltage supply line 110, the voltage-current characteristics of the OLED element E1 can be accurately measured. For example, even if the OLED element E1 deteriorates due to long-term use, a data signal that compensates for the amount of deterioration can be generated by an external circuit, thereby achieving a longer lifespan.

The pixel circuits of Figures 2A and 2B are examples, and the pixel circuits may have other circuit configurations. Although the pixel circuits of Figures 2A and 2B use p-channel TFTs, the pixel circuits may also use n-channel TFTs.
[Image Retention]

The substrate structure of a conventional flexible OLED display device has a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially laminated on a polyimide film having a thickness of 10 um to 15 um, and a TFT (Thin Film Transistor) array is formed on the substrate.

Flexible OLED display devices that use a polyimide film as a substrate have stronger image retention (reversible afterimage) than OLED display devices that use a glass substrate. Figure 3 shows the results of a comparative evaluation of the characteristics of TFTs on a conventional flexible substrate and TFTs on a glass substrate.

In the graph shown in FIG. 3, line 251 shows the change in drive current over time when a data signal to display white is applied to the TFT on the glass substrate, followed by a data signal to display gray. Line 252 shows the change in drive current over time when a data signal to display black is applied to the TFT on the glass substrate, followed by a data signal to display gray.

The drive current exhibits a transient response characteristic (overshoot) in response to a sudden change in the signal. Specifically, when switching from white to gray, as shown by line 251, the current value is initially slightly lower than the target current value, and then gradually increases over time to approach the target current value. On the other hand, when switching from black to gray, as shown by line 252, the current value is initially slightly higher than the target current value, and then gradually decreases over time to approach the target current value. If the changes in the current values of lines 251 and 252 converge in a short time to the same value, no afterimage would be visible. However, in reality, it takes a considerable amount of time for the drive currents 251 and 252 to converge to the same value, and the difference 253 between them causes the afterimage.

In the graph shown in FIG. 3, line 255 shows the change in drive current over time when a data signal to display white is applied to the TFT on the flexible substrate (polyimide substrate) and then a data signal to display gray is applied. Line 256 shows the change in drive current over time when a data signal to display black is applied to the TFT on the flexible substrate and then a data signal to display gray is applied. The difference 257 between drive currents 255 and 256 causes the afterimage.

According to the results of a comparative evaluation of the characteristics of TFTs on a conventional flexible substrate and TFTs on a glass substrate, the drive currents 251 and 252 flowing through the TFTs on the glass substrate show current transient characteristics that are nearly symmetrical along the time axis. However, the drive currents 255 and 256 flowing through the TFTs on the flexible substrate lack symmetry. In other words, when the TFTs on the flexible substrate are driven, a current drift occurs that is not seen in the TFTs on the glass substrate. It was found that the image retention is further deteriorated as a result of the bias being continuously applied by the TFTs and this current drift being superimposed on the inherently symmetric current transient characteristics of the TFTs.

In this way, the current flowing through the TFTs on a flexible substrate exhibits instability that deteriorates image retention. Since TFTs on a glass substrate do not exhibit this instability, it is reasonable to assume that this instability is caused by electrical bias stress due to the polyimide film when the TFTs are driven. In other words, the electric field from the polyimide film reaches the channel part of the TFT and changes the characteristics of the TFT, which is the main cause of the deterioration of image retention.

Therefore, in order to prevent the TFT drive from affecting the polyimide film when the TFT is driven, it is effective to place an electrostatic shield that electrically separates the TFT and the polyimide film.

The following describes the structure of a flexible OLED display device that uses an electrostatic shield to prevent an electric field from a polyimide film to a channel portion of a TFT, and the manufacturing method (process conditions) of an OLED display device having the structure.
[OLED display device structure]

The structure of the OLED display device is described below. The structure of the pixel circuit and the light-emitting element is generally described. FIG. 4 shows a schematic cross-sectional structure of the flexible substrate of the TFT substrate 100, the driving TFT and the OLED element, and the sealing structure 200. In the following description, the top and bottom refer to the top and bottom in the drawing.

The OLED display device includes a TFT substrate 100 and a sealing structure 200. The TFT substrate 100 includes a flexible substrate, and a pixel circuit (TFT array) and an OLED element configured on the flexible substrate. The pixel circuit and the OLED element are configured between the flexible substrate and the sealing structure 200.

The flexible substrate includes, from the bottom up, a polyimide layer (first polyimide layer) 302, a silicon oxide layer (first silicon oxide layer, SiOx layer) 303, an amorphous silicon layer (a-Si layer) 304, and a polyimide layer (second polyimide layer) 305. The silicon oxide layer 303 is formed on and in direct contact with the polyimide layer 302. The amorphous silicon layer 304 is formed on and in direct contact with the silicon oxide layer 303. The polyimide layer 305 is formed on and in direct contact with the amorphous silicon layer 304.

The TFT substrate 100 includes, from the bottom up, a silicon oxide layer (second silicon oxide layer) 306, a transparent conductive layer 307, a silicon oxide layer ( third silicon oxide layer) 308, a silicon nitride layer (SiNx layer) 309, and a silicon oxide layer ( fourth silicon oxide layer) 310 on a flexible substrate (polyimide layer 305).

A pixel circuit (TFT array) and an OLED element are formed on the silicon oxide layer 310. As described above, the flexible substrate includes multiple polyimide layers 302 and 305, which provides a base layer for forming polysilicon with good properties, as described below.

It is also known that polyimide layers contain moisture, and when this moisture diffuses into the layer in which the TFTs are formed, it deteriorates the TFT characteristics. The lower polyimide layer 302 reduces the moisture contained in the upper polyimide layer 305, and can suppress deterioration of the TFT characteristics. In one example, the lower polyimide layer 302 is thicker than the upper polyimide layer 305. This reduces the moisture contained in the upper polyimide layer 305, and more effectively reduces the effect of moisture on the TFT array.

In a flexible laminated film composed of multiple films as in this embodiment, it is very important to consider the adhesion between the films. If adhesion is not taken into consideration, peeling of the films will occur during manufacturing, and bending resistance will not be ensured.

The silicon oxide layer 303 and the amorphous silicon layer 304 improve the adhesion between the two polyimide layers 302 and 305. The silicon oxide layer 303 has high adhesion to the polyimide layer 302 directly below, and the amorphous silicon layer 304 has high adhesion to the silicon oxide layer 303 directly below and the polyimide layer 305 directly above. The silicon oxide layer 303 and the amorphous silicon layer 304 can prevent the upper polyimide layer 305 from peeling off from the lower polyimide layer 302.

A transparent conductive layer 307 is formed between the polyimide layer 305 and the pixel circuit. From the viewpoint of film adhesion and bending resistance, the film thickness of the transparent conductive layer 307 is, for example, 50 nm or less. The transparent conductive layer 307 reduces the influence of the electric field from the charge present in the polyimide layer 305 or 302 on the TFT in the pixel circuit. Since the transparent conductive layer 307 is transparent, it is possible to avoid the influence on the mask alignment in the manufacturing process described later. The transparent conductive layer 307 is formed so as to cover the entire surface of the polyimide layer 305. This makes it possible to more effectively suppress the electric field from the polyimide layer 305, and as will be described later, patterning in the manufacturing process is not required.

In this embodiment, a transparent conductive layer 307 is used between the polyimide layer 305 and the pixel circuit, but the transparent conductive layer 307 does not need to be completely transparent, and it is sufficient if it is a conductive film that is not affected by reflected light during mask alignment. For example, a thin amorphous silicon film has conductivity that functions as a shielding effect, but reflects weak light so it does not affect mask alignment, and has good adhesion to the insulating film, so it is fully applicable.

The transparent conductive layer 307 is applied with a ground potential or is in an electrically floating state. The ground potential can effectively suppress the influence of the electric field generated between the TFT and the polyimide film by the transparent conductive layer 307. Even in an electrically floating state, the transparent conductive layer 307 has an area that is overwhelmingly larger than the element area of the TFT and has sufficient capacity, so that it is possible to obtain a shielding effect equivalent to that when a ground potential is applied. The transparent conductive layer 307 in this example can simplify the configuration of the OLED display device.

The transparent conductive layer 307 is formed of amorphous oxides such as ITO and IZO. ITO has high conductivity (low resistance) and can effectively suppress the electric field caused by the charge in the polyimide. IZO can improve the bending resistance of the OLED display device.

The silicon oxide layer 306 is formed between the polyimide layer 305 and the transparent conductive layer 307 in direct contact with them. The silicon oxide layer 306 covers the entire surface of the polyimide layer 305. The silicon oxide layer 306 can improve the adhesion of the transparent conductive layer 307 to the polyimide layer 305.

The silicon oxide layer 308 is formed on and in direct contact with the transparent conductive layer 307. The silicon oxide layer 308 improves the adhesion between the transparent conductive layer 307 and the silicon nitride layer 309, and is also a barrier layer against moisture and oxygen for the OLED element. The silicon nitride layer 309 is formed on and in direct contact with the silicon oxide layer 308. The silicon nitride layer 309 also acts as a barrier layer, so that it can effectively prevent moisture from penetrating from the polyimide layer 305 into the layer of the OLED element.

The silicon oxide layer 310 is formed directly on and in contact with the silicon nitride layer 309. The silicon oxide layer 310 enables good properties of the subsequently formed polysilicon. As mentioned above, the lower silicon oxide layer 308 is a barrier layer against moisture and oxygen, and its thickness is greater than that of the upper silicon oxide layer 310.

An OLED element is formed on a flexible substrate including the above-mentioned layers. The OLED element includes a lower electrode (e.g., an anode electrode 408), an upper electrode (e.g., a cathode electrode 402), and an organic light-emitting multilayer film 404. The organic light-emitting multilayer film 404 is disposed between the cathode electrode 402 and the anode electrode 408. The multiple anode electrodes 408 are disposed on the same surface (e.g., on the planarization film 421), and one organic light-emitting multilayer film 404 is disposed on one anode electrode 408. In the example of FIG. 4, the cathode electrode 402 of one subpixel is part of a continuous conductor film.

Figure 4 shows an example of a pixel structure of a top emission type (OLED element). In a top emission type pixel structure, a cathode electrode 402 common to multiple pixels is arranged on the side from which light is emitted (upper side of the drawing). The cathode electrode 402 has a shape that covers the entire display area 125. In a top emission type pixel structure, the anode electrode 408 reflects light, and the cathode electrode 402 is optically transparent. This results in a configuration in which light from the organic light-emitting multilayer film 404 is emitted toward the sealing structure 200.

Compared with the bottom-emission type, in which light is extracted to the polyimide layer side , the top-emission type does not require a transparent region for light extraction within the pixel region, and therefore has a high degree of freedom in the layout of the pixel circuits, in that the light-emitting section can be formed on top of the pixel circuits and wiring.

The bottom-emission pixel structure has a transparent anode electrode and a reflective cathode electrode, and emits light to the outside through the flexible substrate. A transparent display device can also be realized by forming both the anode electrode and the cathode electrode from a light-transmitting material. The flexible substrate structure of the present disclosure can be applied to any of these types of OLED display devices, and can also be applied to display devices that include light-emitting elements other than OLEDs.

In a full-color OLED display device, the subpixels typically display one of three colors: red, green, or blue. The red, green, and blue subpixels make up one main pixel. A pixel circuit containing multiple thin-film transistors controls the emission of the corresponding OLED element. The OLED element is composed of an anode electrode, which is the lower electrode, an organic light-emitting layer, and a cathode electrode, which is the upper electrode.

The OLED display device has a number of pixel circuits (TFT array) each including a number of switches. Each of the pixel circuits is formed between the silicon oxide layer 310 and the anode electrode 408, and controls the current supplied to each of the anode electrodes 408. The drive TFT shown in FIG. 4 has a top-gate structure. The other TFTs also have a top-gate structure.

A polysilicon layer is present on and in direct contact with the silicon oxide layer 310. The polysilicon layer has a channel 415 which provides the transistor characteristics of the TFT at a position where a gate electrode 414 will later be formed, and on either side are source/drain regions 416, 417 which are heavily doped with impurities to provide electrical connection to the upper wiring layer.

Between the channel 415 and the source/drain regions 416, 417, an LDD (Lightly Doped Drain) doped with a low concentration of impurities may be formed. Note that the LDD is not shown in the figure to avoid complication. A gate electrode 414 is formed on the polysilicon layer via a gate insulating film 423. An interlayer insulating film 422 is formed on the layer of the gate electrode 414.

In the display region 125, source/drain electrodes 410, 412 are formed on an interlayer insulating film 422. The source/drain electrodes 410, 412 are formed of, for example, a high melting point metal or its alloy. The source/drain electrodes 410, 412 are connected to source/drain regions 416, 417 of the polysilicon layer via contact holes 411, 413 formed in the interlayer insulating film 422 and the gate insulating film 423.

An insulating organic planarization film 421 is formed on the source/drain electrodes 410, 412. An anode electrode 408 is formed on the planarization film 421. The anode electrode 408 is connected to the source/drain electrode 412 via a contact hole 409 in the planarization film 421. The TFT of the pixel circuit is formed below the anode electrode 408.

The anode electrode 408 is composed of, for example, a central reflective metal layer and transparent conductive layers sandwiching the reflective metal layer. The anode electrode 408 has, for example, an ITO/Ag/ITO structure or an IZO/Ag/IZO structure. IZO has a higher resistance than ITO, but can improve the bending resistance of the OLED display device.

An insulating pixel defining layer (PDL) 407 is formed on the anode electrode 408 to separate the OLED elements. The OLED elements are formed in the openings 406 in the pixel defining layer 407.

An organic light-emitting multilayer film 404 is formed on the anode electrode 408. The organic light-emitting multilayer film 404 is attached to the pixel definition layer 407 at the opening 406 of the pixel definition layer 407 and its periphery. A film of organic light-emitting material is formed for each of the RGB colors, and the organic light-emitting multilayer film 404 is formed on the anode electrode 408.

The organic light-emitting multilayer film 404 is formed by depositing an organic light-emitting material at positions corresponding to the pixels using a metal mask. The organic light-emitting multilayer film 404 is composed of, from the bottom up, for example, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The layered structure of the organic light-emitting multilayer film 404 is determined by design.

A cathode electrode 402 is formed on the organic light-emitting multilayer film 404. The cathode electrode 402 is an electrode having optical transparency. The cathode electrode 402 transmits a portion of the visible light from the organic light-emitting multilayer film 404. The layer of the cathode electrode 402 is formed by, for example, evaporating a metal such as Al or Mg or an alloy containing these metals. If the resistance of the cathode electrode 402 is high and the uniformity of the light emission brightness is impaired, an auxiliary electrode layer is further added using a material for forming a transparent electrode such as ITO, IZO, ZnO or In2O3.

The laminated film of the anode electrode 408, the organic light-emitting multilayer film 404, and the cathode electrode 402 formed in the opening 406 of the pixel definition layer 407 constitutes an OLED element. The sealing structure 200 is formed in direct contact with the cathode electrode 402. The sealing structure (thin film sealing portion) 200 includes, from the bottom, an inorganic insulator (e.g., SiNx, AlOx) layer 401, an organic planarization film 431, and an inorganic insulator (e.g., SiNx, AlOx) layer 432. The inorganic insulators 401 and 432 are lower and upper passivation layers, respectively, for improving reliability.

On the sealing structure 200, from the bottom up, a touch screen film 433, a λ/4 plate 434, a polarizing plate 435, and a resin cover lens 436 are laminated. The λ/4 plate 434 and the polarizing plate 435 suppress reflection of light incident from the outside. Note that the laminated structure of the OLED display device described with reference to Fig. 4 is an example, and some of the layers shown in Fig. 4 may be omitted, and layers not shown in Fig. 4 may be added.
[Production method]

Next, an example of a method for manufacturing an OLED display device will be described. Figures 5A and 5B show the manufacturing process of a backplane in an example of a method for manufacturing an OLED display device. Note that the following description is intended to explain the features of this embodiment, and some of the steps in the actual manufacturing of an OLED display device are omitted.

As shown in FIG. 5A, the OLED display device is manufactured by first forming a polyimide layer 302 (first polyimide layer) on a glass substrate (insulating support substrate) (not shown) by, for example, coating and heat treatment (S11). The polyimide layer 302 has a thickness that can provide the strength required for a flexible substrate.

Next, silicon oxide is deposited on the polyimide layer 302, for example, by a chemical vapor deposition (CVD) method to form a silicon oxide layer 303 (S13). Next, amorphous silicon is deposited on the silicon oxide layer 303, for example, by a CVD method to form an amorphous silicon layer 304 (S15).

As described above, the silicon oxide layer 303 is an adhesion improving layer for the polyimide layer 302, and the amorphous silicon layer 304 is an adhesion improving layer for the polyimide layer 305 (second polyimide layer). These layers prevent the polyimide layer 305 from peeling off from the polyimide layer 302.

Next, a polyimide layer 305 is formed on the amorphous silicon layer 304, for example, by coating and heat treatment (S17). As described above, in order to reduce the effect of the electric field caused by moisture in the polyimide layer 305 on the characteristics of the TFT, the polyimide layer 305 is formed thinner than the underlying polyimide layer 302. Next, a silicon oxide layer 306 is formed on the polyimide layer 305, for example, by a CVD method (S19). As described above, the silicon oxide layer 306 improves the adhesion of the upper transparent conductive layer 307 to the polyimide layer 305.

Next, a transparent conductor is deposited on the silicon oxide layer 306, for example, by sputtering, to form a transparent conductive layer 307 (S21). The transparent conductive layer 307 can be, for example, a metal oxide thin film such as an ITO layer or an IZO layer, or a semiconductor film such as amorphous silicon formed by a CVD method.

Generally, amorphous silicon thin films have high electrical resistance and are therefore not suitable for use as conductive wiring layers, but have a sufficiently low resistance value for use as a shielding layer. According to experiments conducted by the applicants, it was confirmed that a film thickness of 1.0 nm or more is effective in blocking the effects of charges in the polyimide layers 305 and 302 on the TFTs. It was also confirmed that a film thickness of 5.0 nm or less ensures sufficient transmittance, similar to that of a metal thin film.

More preferably, if the thickness of the amorphous silicon layer 304 is 5.0 nm or less, the transparent conductive layer 307 can be used sufficiently for applications using transmitted light such as transparent displays and under-panel cameras. Since the transparent conductive layer 307 is transparent, unlike a reflective metal layer, no patterning is required, and the effect on mask alignment in a later process can be avoided.

In addition, since no patterning is performed, the entire substrate is covered with a conductive layer from below the TFT elements, which has the same effect as an apparent ground electrode against static electricity generated during the TFT manufacturing process, helping to reduce defects caused by static electricity and suppress characteristic variations caused by static electricity.

Furthermore, even after the cathode is formed, the TFT element circuit covers the entire panel module from below with an area larger than the area of the cathode, providing the same effect as electrostatically shielding the entire module. For example, the mounting terminal section of a driver IC that uses an anisotropic conductive film is outside the cathode electrode area and is therefore susceptible to the effects of static electricity, but with this structure the floating conductive film covers the entire terminal area, making it possible to suppress the effects of static electricity during the mounting process.

Next, silicon oxide is deposited on the transparent conductive layer 307, for example by CVD, to form a silicon oxide layer 308 (S23). The silicon oxide layer 308 is a barrier layer against moisture and oxygen, and is formed with a thickness that functions appropriately as a barrier layer with a focus on throughput, and the thickness is thicker than that of the upper silicon oxide layer 310.

Next, the silicon nitride layer 309, the silicon oxide layer 310, and the amorphous silicon layer are successively formed on the silicon oxide layer 308 under film-forming conditions that prioritize film quality, for example, by the CVD method (S25). These three layers are formed at a lower deposition rate than the silicon oxide layer 308 in order to obtain good film quality. Furthermore, the amorphous silicon layer is heated to perform a dehydrogenation process. Usually, this heating process is often performed in air at 400° C. or higher, but in this embodiment, for example, it is performed in an inert gas (e.g., nitrogen gas) atmosphere at 400° C. or lower. This makes it possible to ensure good TFT characteristics while suppressing deterioration of film quality due to crystallization of the transparent conductive layer 307 formed in a process prior to the TFT.

Through these steps, a flexible substrate is formed. Each step described with reference to Figure 5A is completed without patterning each layer.

Next, as shown in FIG. 5B, the OLED display device is manufactured by crystallizing the amorphous silicon by ELA (Excimer Laser Annealing) to form a polysilicon film (S27), and then patterning the polysilicon layer (S29). ELA is performed under conditions that emphasize uniformity of TFT characteristics (energy significantly lower than the maximum mobility conditions).

Next, the source/drain regions 416, 417 for connection to the source/drain electrodes 410, 412 are doped with a high concentration of impurities to reduce their resistance (S31). Similarly, the polysilicon with reduced resistance can also be used for connections between elements within the display area 125.

Next, for example, silicon oxide is deposited on the polysilicon layer including the channel 415 by, for example, CVD to form a gate insulating film 423 (S33). Furthermore, a metal material is deposited by, for example, sputtering, and patterned to form a metal layer including the gate electrode 414 (S35). In addition to the gate electrode 414, the metal layer can include, for example, a storage capacitance electrode, a scanning line 106, an emission control line 107, etc.

The metal layer may be a single layer made of a material selected from the group consisting of Mo, W, Nb, MoW, MoNb, Al, Nd, Ti, Cu, Cu alloy, Al alloy, Ag, and Ag alloy, or a two-layer structure or more multiple structures made of one or more low-resistance materials selected from Mo, Cu, Al, and Ag to reduce the wiring resistance.

Next, silicon nitride is deposited by, for example, CVD to form the interlayer insulating film 422 (S37). Next, annealing is performed to activate and hydrogenate the polysilicon layer (S39). Hydrogenation utilizes hydrogen in the interlayer insulating film 422 formed of silicon nitride. This annealing is performed, for example, at 400° C. or less in an inert gas (for example, nitrogen gas) atmosphere. This makes it possible to ensure good TFT characteristics while suppressing crystallization of the transparent conductive layer 307. The annealing S39 may be performed after the subsequent contact hole formation S41.

Next, anisotropic etching is performed on the interlayer insulating film 422 and the gate insulating film 423 to open contact holes (S41). Contact holes 411, 413 that connect the source/drain electrodes 410, 412 to the source/drain regions 416, 417 are formed in the interlayer insulating film 422 and the gate insulating film 423.

Next, a conductive film such as Ti/Al/Ti is deposited by, for example, a sputtering method, and then patterned to form a metal layer. The metal layer includes the source/drain electrodes 410, 412 and the insides of the contact holes 411, 413. In addition, the data line 105, the power line 108, etc. may also be formed in the same layer.

Next, a photosensitive organic material is deposited to form a planarization film 421 (S45). Contact holes 409 for connecting the source/drain electrodes 412 and the anode electrodes 408 of the TFTs are opened by exposure and development.

Next, the anode electrode 408 is formed on the planarization film 421 in which the contact hole 409 is formed (S47). The anode electrode 408 includes three layers: a transparent conductive layer of ITO, IZO, ZnO, In2O3, etc.; a reflective layer of a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc. or an alloy containing these metals; and the transparent conductive layer described above. The IZO transparent conductive layer can improve the bending resistance of the OLED display device. The three-layer structure of the anode electrode 408 is one example, and it may be two layers. The anode electrode 408 is connected to the source/drain electrode 412 via the contact hole 409.

Next, for example, a photosensitive organic resin film is deposited by, for example, spin coating, and patterned to form a pixel definition layer 407 (S49). By patterning, an opening 406 is formed in the pixel definition layer 407, and the anode electrode 408 of each subpixel is exposed at the bottom of the opening 406. The pixel definition layer 407 separates the light-emitting regions of each subpixel.

By the above steps, a flexible substrate and a pixel circuit (TFT array) on the flexible substrate can be formed. Note that the steps after forming the pixel definition layer 407 can be performed using conventional technology, and therefore a description thereof will be omitted.

In the manufacture of OLED display devices, the temperature is the highest in the dehydrogenation process S25 by heating the amorphous silicon layer or in the hydrogenation and activation process of the polysilicon layer. Therefore, by carrying out these processes at a temperature of, for example, 400°C or less, the entire process of manufacturing the OLED display device can be carried out at a temperature of 400°C or less. In addition, a process of forming a metal layer and an interlayer insulating film can be added to the above process to form a storage capacitor.

As described above, the OLED display device of this embodiment includes a transparent conductive layer between the polyimide layer and the TFT array (pixel circuit). This reduces the effect of the electric field caused by the charges contained in the polyimide layer on the TFT, making the operation of the TFT more stable and suppressing image retention. In addition, since the transparent conductive layer is disposed below the TFT array, it is easy to adjust the neutral plane to coincide with the TFT layer. The neutral plane here refers to a virtual surface in the cross section of the flexible laminate that is not subjected to stress when folded.

Figure 6A shows a schematic cross-section of a comparative OLED display device. The TFT layer 501 is sandwiched between an upper multilayer film 503 and a lower multilayer film 505. In a flexible OLED display device, the multi-functional layers are concentrated in the upper multilayer film 503, so that the neutral plane 507 is located in the upper multilayer film 503 above the TFT layer 501.

Figure 6B shows a schematic cross-section of an OLED display device including the transparent conductive layer 519 of this embodiment. The TFT layer 511 is sandwiched between the upper multilayer film 513 and the lower multilayer film 515. The transparent conductive layer 519 is included in the lower multilayer film 515. In this way, since the transparent conductive layer 519 is present below the TFT layer 511, it is easy to adjust the neutral plane 517 to coincide with the TFT layer 511. Therefore, the bending reliability of the OLED display device can be improved.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily modify, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

10 Display device, 100 TFT substrate, 200 Sealing structure, 302 Polyimide layer, 303 Silicon oxide layer, 304 Amorphous silicon layer, 305 Polyimide layer, 306 Silicon oxide layer, 307 Transparent conductive layer, 308 Silicon oxide layer, 309 Silicon nitride layer, 310 Silicon oxide layer, 401 Inorganic insulating layer, 402 Cathode electrode, 404 Organic light-emitting multilayer film, 406 Opening, 407 Pixel definition layer, 408 Anode electrode, 409 Contact hole, 410, 412 Source/drain electrode, 411, 413 Contact hole, 414 Gate electrode, 415 Channel, 416, 417 Source/drain region, 421 Planarization film, 422 Interlayer insulating film, 423 Gate insulating film, 431 Planarization film, 432 Inorganic insulating layer, 433 Touch screen film, 434 λ/4 plate, 435 polarizing plate, 436 resin cover lens, 501, 511 TFT layer, 503, 513 upper multilayer film, 505, 515 lower multilayer film, 507, 517 neutral plane, 519 transparent conductive layer

Claims (14)

A first polyimide layer;
a first silicon oxide layer formed on and in direct contact with the first polyimide layer;
an amorphous silicon layer formed directly on and in contact with the first silicon oxide layer;
a second polyimide layer formed directly on and in contact with the amorphous silicon layer;
A plurality of light emitting elements formed on the second polyimide layer;
a transistor array formed on the second polyimide layer for controlling light emission of the plurality of light-emitting elements;
a transparent conductive layer formed between the transistor array and the second polyimide layer;
a second silicon oxide layer formed between the transparent conductive layer and the second polyimide layer in direct contact with each of the transparent conductive layer and the second polyimide layer;
a polysilicon layer of the transistor array;
a third silicon oxide layer formed between the polysilicon layer and the transparent conductive layer and in direct contact with the transparent conductive layer;
a silicon nitride layer formed between the polysilicon layer and the third silicon oxide layer;
a fourth silicon oxide layer formed between the polysilicon layer and the silicon nitride layer and in direct contact with the polysilicon layer;
A display device comprising: The display device according to claim 1 ,
the second silicon oxide layer and the transparent conductive layer cover the entire surface of the second polyimide layer;
Display device. The display device according to claim 1 ,
The transparent conductive layer is electrically floating.
Display device. The display device according to claim 1 ,
The transparent conductive layer is an ITO layer or an IZO layer.
Display device. The display device according to claim 1 ,
The transparent conductive layer is formed of amorphous silicon.
Display device. The display device according to claim 5 ,
The thickness of the transparent conductive layer is 1.0 nm or more and 5.0 nm or less.
Display device. The display device according to claim 1 ,
The sum of the thicknesses of the amorphous silicon layer and the transparent conductive layer is 5.0 nm or less.
Display device. The display device according to claim 1 ,
The transistor array is composed of top-gate polysilicon thin-film transistors.
Display device. The display device according to claim 1 ,
the transparent conductive layer is an IZO layer,
The anode electrodes of the light emitting devices include two IZO layers and a reflective metal layer between the two IZO layers;
Display device. The display device according to claim 1 ,
The second polyimide layer is thinner than the first polyimide layer.
Display device. A method for manufacturing a display device, comprising the steps of:
A first step of forming a first silicon oxide layer directly on the first polyimide layer;
a second step of forming an amorphous silicon layer directly on the first silicon oxide layer;
a third step of forming a second polyimide layer directly on the amorphous silicon layer;
a fourth step of forming a second silicon oxide layer directly on the second polyimide layer;
a fifth step of forming a transparent conductive layer directly on the second silicon oxide layer;
a sixth step of forming a transistor array on the second silicon oxide layer for controlling light emission of a plurality of light emitting elements;
Including,
The method for manufacturing the display device further includes, before the sixth step,
a seventh step of forming a third silicon oxide layer directly on the transparent conductive layer;
an eighth step of forming a silicon nitride layer on the third silicon oxide layer;
a ninth step of forming a fourth silicon oxide layer on the silicon nitride layer;
Including,
the sixth step includes forming a polysilicon layer directly on the fourth silicon oxide layer;
A method for manufacturing a display device. A method for manufacturing a display device according to claim 11, comprising the steps of:
The fourth step includes depositing silicon oxide to form the second silicon oxide layer and completing the fourth step without patterning the second silicon oxide layer;
The fifth step is to deposit a transparent conductor to form the transparent conductive layer, and is completed without patterning the transparent conductive layer.
A method for manufacturing a display device. A method for manufacturing the display device according to claim 11, comprising the steps of:
The sixth step includes a heat treatment in an inert gas atmosphere after doping the polysilicon layer with impurities.
A method for manufacturing a display device. A method for manufacturing a display device according to claim 11, comprising the steps of:
the sixth step includes, after forming the second amorphous silicon layer, performing a heat treatment in an inert gas atmosphere before changing the second amorphous silicon layer into a polysilicon layer by laser annealing;
A method for manufacturing a display device.

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