JP7498502B2 - Explicit signaling of extended long-term reference picture retention - Patents.com - Google Patents

Description

This application claims the benefit of priority to U.S. Provisional Patent Application No. 62/797,806, filed January 28, 2019, entitled "EXPLICIT SIGNALING OF EXTENDED LONG TERM REFERENCE PICTURE RETENTION," which is incorporated herein by reference in its entirety.

The present invention relates generally to the field of video compression. In particular, the present invention is directed to explicit signaling of extended long-term reference picture retention.

A video codec may include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video to a compressed format, or vice versa. In the context of video compression, a device that compresses (and/or performs some of the functions of) the video may typically be called an encoder, and a device that decompresses (and/or performs some of the functions of) the video may be called a decoder.

The format of the compressed data can conform to standard video compression specifications. The compression can be lossy, in that the compressed video lacks certain information present in the original video. Consequences of this can include that the decompressed video may have lower quality than the original uncompressed video, because insufficient information exists to exactly reconstruct the original video.

There can be a complex relationship between video quality, the amount of data used to represent the video (e.g., determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end delay (e.g., latency), and the like.

Motion compensation may include an approach for predicting a video frame or a portion thereof given reference frames, such as previous and/or future frames, by considering the motion of the camera and/or objects in the video. It may be employed in encoding and decoding video data for video compression, for example, in encoding and decoding using the Moving Picture Experts Group (MPEG)-2 (also referred to as Advanced Video Coding (AVC) and H.264) standard. Motion compensation may describe a picture in terms of the transformation of a reference picture into the current picture. The reference picture may be earlier in time compared to the current picture, from the future compared to the current picture, or may include a long-term reference (LTR) frame. Compression efficiency may be improved when images can be accurately synthesized from previously transmitted and/or stored images.

Long-term reference (LTR) frames are used in video coding standards such as MPEG-2, H.264 (also referred to as AVC or MPEG-4 Part 10), and H.265 (also referred to as High Efficiency Video Coding (HEVC)). A frame marked as an LTR frame in a video bitstream is available for use as a reference until it is explicitly removed by bitstream signaling. LTR frames improve prediction and compression efficiency in scenes with a static background over a long period of time (e.g., background in a video conference or video of a parking lot surveillance). However, over time, the background of a scene changes gradually (e.g., when a car is parked in an empty spot, the car becomes part of the background scene). Thus, updating the LTR frame improves compression performance by allowing better prediction.

Current standards such as H.264 and H.265 allow updates of LTR frames by signaling a newly decoded frame to be stored and made available as a reference frame. Such updates are signaled by the encoder and the entire frame is updated. However, updating the entire frame can be costly. Also, when an LTR frame is updated, the previous LTR frame is discarded. If the static background associated with the previous discarded LTR frame reoccurs in the video (e.g., in a video that switches from a first scene to a second scene and then back to the first scene), the previous LTR frame must be encoded again in the bitstream, which reduces compression efficiency.

In one aspect, a decoder includes circuitry configured to receive a bitstream, store a plurality of long-term reference frames in a reference list, retain the long-term reference frames in the reference list for a length of time based on a retention time, and decode at least a portion of the video using the long-term reference frames retained in the reference list.

In another aspect, a method includes a decoder receiving a bitstream. The method includes the decoder storing a plurality of long-term reference frames in a reference list. The method includes the decoder retaining the long-term reference frames in the reference list for a length of time based on the retention time. The method includes the decoder decoding at least a portion of the video using the long-term reference frames retained in the reference list.

The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims.
The present invention provides, for example, the following items.
(Item 1)
10. A decoder, the decoder comprising a circuit, the circuit comprising:
Receiving a bitstream;
storing a plurality of long term reference frames in a reference list;
retaining a long term reference frame in the reference list for a length of time based on a retention time;
decoding at least a portion of a video using the long term reference frames maintained in the reference list;
A decoder configured to:
(Item 2)
2. The decoder of claim 1, wherein each long term reference frame in the stored long term reference frames includes an associated retention time.
(Item 3)
2. The decoder of claim 1, further configured to mark the long term reference frame as unavailable after the long term reference frame has resided in the reference list for at least the retention time.
(Item 4)
4. The decoder of claim 3, further configured to mark the long term reference frame as available based on a signal in the bitstream.
(Item 5)
2. The decoder of claim 1, wherein the bitstream includes a signal for removing the long term reference frame from memory.
(Item 6)
6. The decoder of claim 5, further configured to remove the long term reference frame from the reference list based on the signal.
(Item 7)
an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients;
an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing an inverse discrete cosine;
A deblocking filter;
A frame buffer;
Intra prediction processor
2. The decoder of claim 1, further comprising:
(Item 8)
Receiving a coded block;
determining that an inter prediction mode is enabled for the coded block;
determining a decoded block using the long-term reference frame as a reference frame and according to the inter prediction mode;
2. The decoder of claim 1, further configured to:
(Item 9)
9. The decoder of claim 8, wherein the decoded blocks form part of a quad tree plus a binary decision tree.
(Item 10)
9. The decoder of claim 8, wherein the decoded blocks are non-leaf nodes of the quadtree plus binary decision tree.
(Item 11)
1. A method, comprising:
A decoder receives a bitstream;
storing a plurality of long term reference frames in a reference list;
the decoder retaining a long term reference frame in the reference list for a length of time based on a retention time;
the decoder decoding at least a portion of a video using the long-term reference frames maintained in the reference list;
A method comprising:
(Item 12)
12. The method of claim 11, wherein each long term reference frame in the stored long term reference frames includes an associated retention time.
(Item 13)
12. The method of claim 11, further comprising marking the long term reference frame as unavailable after the long term reference frame has resided in the reference list for at least the retention time.
(Item 14)
14. The method of claim 13, further comprising marking the long term reference frame as available based on a signal in the bitstream.
(Item 15)
12. The method of claim 11, wherein the bitstream includes a signal for removing the long term reference frame from memory.
(Item 16)
16. The method of claim 15, further comprising removing the long term reference frame from the reference list based on the signal.
(Item 17)
The decoder further comprises:
an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients;
an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing an inverse discrete cosine;
A deblocking filter;
A frame buffer;
Intra prediction processor
Item 12. The method of item 11, comprising:
(Item 18)
Receiving a coded block;
determining that an inter prediction mode is enabled for the coded block;
determining a decoded block using the long-term reference frame as a reference frame and according to the inter prediction mode;
12. The method of claim 11, further comprising:
(Item 19)
20. The method of claim 18, wherein the decoded blocks form part of a quad tree plus a binary decision tree.
(Item 20)
20. The method of claim 18, wherein the decoded blocks are non-leaf nodes of the quadtree plus binary decision tree.

For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings.
FIG. 1 illustrates an example reference list for long term frame prediction.

FIG. 2 is a process flow diagram illustrating one example process of extended long-term reference (eLTR) frame retention in which eLTR frames are retained in a reference list.

FIG. 3 is a system block diagram illustrating an example decoder capable of decoding a bitstream with eLTR frames held in a reference list.

FIG. 4 is a process flow diagram illustrating an example process for encoding video with eLTR frames held in a reference list in accordance with some aspects of the present subject matter that can enable improved compression efficiency compared to some existing approaches.

FIG. 5 is a system block diagram illustrating an example video encoder capable of signaling for eLTR retention in a reference list.

FIG. 6 is a block diagram of a computing system that can be used to implement any one or more of the methods and any one or more portions thereof disclosed herein.

The drawings are not necessarily to scale and may be illustrated by phantom lines, schematic representations, and partial views. In some instances, details that are not necessary for an understanding of the embodiments or that make other details difficult to perceive may be omitted. Like reference symbols in the various drawings indicate like elements.

Long-term reference pictures (LTRs) may be used for better prediction of video frames in cases where a portion of a frame repeatedly becomes occluded and then uncovered over time. Traditionally, an LTR is used for the duration of a scene or group of pictures, after which it is replaced or discarded. Some implementations of the present subject matter extend the usefulness of LTR use by selecting the best candidate LTR for retention in the reference list. In some implementations, explicitly signaled extended long-term reference (eLTR) frames may be retained in the reference list for an explicitly signaled length of time. Some implementations of the present subject matter may provide significant compression efficiency gains compared to some existing approaches.

Some implementations of the present subject matter may achieve eLTR frame selection and retention in video coding. The eLTR may be retained in a picture reference list that may be used by a current frame or group of frames for prediction. The eLTR may be retained in the reference list while all other frames in the list change over a relatively short period of time. For example, FIG. 1 illustrates an example reference list for frame prediction over a long period of time. As a non-limiting and illustrative example, the video frames shown shaded may be reconstructed using the reference frames. The reference list may contain frames that change over time and the eLTRs that are retained.

In some implementations, with continued reference to FIG. 1, an encoder performs the eLTR selection and retention calculation operations. The selected frame and the time of retention may be signaled to the decoder, for example, using the pair (eLTRn, TRn) indicating an index for the eLTR (eLTRn) and retention time (TRn) for frame n. The decoder may retain frame eLTRn in the reference list for a period of TRn. After the eLTRn frame has resided in the reference list for at least TRn, the eLTRn frame may be marked as unavailable for further use. In some implementations, the eLTRn frame may be maintained in memory but in an unavailable state. In some implementations, the encoder may explicitly signal the decoder to mark the eLTRn frame as available or unavailable. For example, an eLTRn frame previously marked as unavailable after the retention time TRn has elapsed may be marked as available. Such a feature may allow eLTRn to be used again in the future, such as for videos containing back-and-forth scenes. In some implementations, the encoder may include a signal in the bitstream for the decoder to remove the eLTRn frame from memory. The decoder may remove the eLTRn frame from the reference list and memory based on such a signal.

Figure 2 is a process flow diagram illustrating a non-limiting example of a process 200 of eLTR frame retention in which eLTR frames are retained in a reference list. Such eLTR retention may enable compression efficiency improvements compared to some existing approaches to video encoding and decoding.

At step 210, with continued reference to FIG. 2, a bitstream is received by the decoder. The bitstream may include, for example, data found in a stream of bits that is input to the decoder when using data compression. The bitstream may include information necessary to decode the video. Receiving may include extracting and/or parsing blocks and associated signaling information from the bitstream. In some implementations, receiving the bitstream may include parsing eLTR frames, indexes to such frames (eLTRn), and associated retention times (TRn), where the retention times are based on the frames and/or times in the video being decoded.

With continued reference to FIG. 2, at step 220, the eLTR frame may be stored in a reference picture list.

At step 230, and still referring to FIG. 2, the stored eLTR frame may be retained (e.g., maintained) in the reference list for a length of time based on the associated retention time (TRn).

At step 240, with continued reference to FIG. 2, at least a portion of the video may be decoded from the bitstream. The decoding may include decoding a current block. For example, a received current coded block contained in the bitstream may be decoded, for example, by using inter prediction. Decoding via inter prediction may include using previous frames, future frames, and/or eLTR frames as references to calculate a prediction, which may be combined with a residual contained in the bitstream.

With further reference to FIG. 2, for a subsequent current block, the eLTR frame may be utilized as a reference frame for inter prediction. For example, a second coded block may be received. It may be determined whether an inter prediction mode is enabled for the second coded block, and the determination may include receiving an explicit signal from the bitstream indicating whether the inter prediction mode is enabled. A second decoded block may be determined using the eLTR frame as a reference frame and according to the inter prediction mode. For example, decoding via inter prediction may include using the eLTR frame as a reference to calculate a prediction, and the prediction may be combined with a residual contained within the bitstream.

FIG. 3 is a system block diagram illustrating a non-limiting example of a decoder 300 capable of decoding a bitstream 370 with eLTR frames retained in a reference list. The decoder 300 may include an entropy decoder processor 310, an inverse quantization and inverse transform processor 320, a deblocking filter 330, a frame buffer 340, a motion compensation processor 350, and an intra prediction processor 360. In some implementations, the bitstream 370 may include parameters (e.g., fields in a header of the bitstream) signaling an eLTR index (eLTRn) and a retention time (TRn). The motion compensation processor 350 may use the eLTR frames to reconstruct pixel information and retain the eLTR frames according to their associated retention times (TRn). For example, when an eLTR frame (eLTRn) is received and retained in a reference list for at least an associated retention time, the eLTR frame (eLTRn) may be used as a reference for an inter prediction mode for at least the associated reference time.

In operation, and still referring to FIG. 3, a bitstream 370 may be received by the decoder 300 and input to the entropy decoder processor 310, which may entropy decode the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 320, which may perform inverse quantization and inverse transform to create a residual signal, which may be added to the output of the motion compensation processor 350 or the intra prediction processor 360, depending on the processing mode. The output of the motion compensation processor 350 and the intra prediction processor 360 may include block predictions based on previously decoded blocks and/or eLTR frames maintained in the reference list. The prediction and residual sums may be processed by the deblocking filter 630 and stored in the frame buffer 640.

FIG. 4 is a process flow diagram illustrating a non-limiting example of a process 400 for encoding a video with eLTR frames retained in a reference list in accordance with some aspects of the present subject matter, which may enable compression efficiency improvements compared to some existing approaches. At step 410, a sequence of video frames is encoded, which may include determining one or more eLTR frames. At step 420, an eLTR frame retention time (TRn) may be determined, for example, based on the length of time that the eLTR frame is utilized by the encoder/decoder, e.g., the time is based on the frame being decoded in the video.

At step 430, still referring to FIG. 4, additional signaling parameters may be determined. For example, whether and when to mark eLTR frames as unavailable or available may be determined, and whether and when each eLTR frame should be removed from memory may be determined.

At step 440, and still referring to FIG. 4, the eLTR retention time and additional signaling parameters may be included in the bitstream.

5 is a system block diagram illustrating a non-limiting example of a video encoder 500 capable of signaling for eLTR retention in a reference list. The exemplary video encoder 500 receives an input video 505, which may first be segmented or divided according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., a quad tree plus a binary tree). An example of a tree-structured macroblock partitioning scheme may include a partitioning scheme that divides a picture frame into larger block elements, which for purposes of this disclosure may be referred to as coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks, which may be referred to as coding units (CUs). The results of this partitioning may include a group of sub-blocks, which for purposes of this disclosure may be referred to as prediction units (PUs). Transform units (TUs) may also be utilized.

Continuing to refer to FIG. 5, the exemplary video encoder 500 may include an intra-prediction processor 515, a motion estimation/compensation processor 520 (also referred to as an inter-prediction processor) capable of supporting eLTR frame retention, a transform/quantization processor 525, an inverse quantization/inverse transform processor 530, an in-loop filter 535, a decoded picture buffer 540, and an entropy coding processor 545. In some implementations, the motion estimation/compensation processor 520 may determine the eLTR retention time and additional signaling parameters. Bitstream parameters signaling the eLTR frame retention and additional parameters may be input to the entropy coding processor 545 for inclusion in the output bitstream 550.

In operation, and continuing to refer to FIG. 5, for each block of a frame of input video 505, it may be determined whether the block should be processed via intra-picture prediction or using motion estimation/compensation. The block may be provided to intra-prediction processor 510 or motion estimation/compensation processor 520. If the block is to be processed via intra-prediction, intra-prediction processor 510 may perform processing and output a predictor. If the block is to be processed via motion estimation/compensation, motion estimation/compensation processor 520 may perform processing including using an eLTR frame as a reference for inter prediction, if applicable.

Continuing with reference to FIG. 5, a residual may be formed by subtracting a predictor from the input video. The residual may be received by a transform/quantization processor 525, which may perform a transform process (e.g., a discrete cosine transform (DCT)) to generate coefficients, which may be quantized. The quantized coefficients and any associated signaling information may be provided to an entropy coding processor 545 for entropy encoding and inclusion in the output bitstream 550. The entropy encoding processor 545 may assist in encoding signaling information related to eLTR frame retention. Additionally, the quantized coefficients may be provided to an inverse quantization/inverse transform processor 530, which may reconstruct the pixels, which may be combined with the predictor and processed by an in-loop filter 535, the output of which may be stored in a decoded picture buffer 540 for use by the motion estimation/compensation processor 520, which may assist with eLTR frame retention.

With continued reference to FIG. 5, several variations have been described in detail above, but other modifications or additions are possible. For example, in some implementations, the current block may include any symmetric block (8×8, 16×16, 32×32, 64×64, 128×128, etc.) and any asymmetric block (8×4, 16×8, etc.).

In some implementations, and continuing to refer to FIG. 5, a quad-tree plus binary decision tree (QTBT) may be implemented. In QTBT, at the coding tree unit level, the splitting parameters of QTBT may be dynamically derived to fit local characteristics without transmitting any overhead. Then, at the coding unit level, a joint classifier decision tree structure may eliminate unnecessary iterations and control the risk of erroneous prediction.

In some implementations, the decoder may include an eLTR frame preservation processor (not shown) that determines whether and for how long eLTR frames should be marked as unavailable or removed from the reference list.

In some implementations, the subject matter can be applied to broadcast (and similar) scenarios where a decoder tunes in midway through a retention period. To support standard playback, an encoder may mark (e)LTR frames as Instantaneous Decoding Refresh (IDR) type frames. In this case, streaming may resume after the next available LTR (IDR) frame. Such an approach may be similar to some current broadcast standards that specify interframes as IDR frames.

The subject matter described herein provides many technical advantages. For example, some implementations of the subject matter may provide for decoding blocks using eLTR frames that are maintained in a reference list. Such an approach may improve compression efficiency.

It should be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic circuitry, integrated circuits, specially designed application specific integrated circuits (ASICs), field programmable gate array (FPGA) computer hardware, firmware, software, and/or combinations thereof realized and/or implemented in one or more machines (e.g., one or more computing devices utilized as user computing devices for electronic documents, one or more server devices such as document servers, etc.) programmed in accordance with the teachings herein, as would be apparent to one of ordinary skill in the computer arts. These various aspects or features may include implementation in one or more computer programs and/or software executable and/or readable on a programmable system including at least one programmable processor, which may be dedicated or general purpose, coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Appropriate software coding may be readily prepared by skilled programmers based on the teachings of the present disclosure, as would be apparent to one of ordinary skill in the software arts. The aspects and implementations discussed above that employ software and/or software modules may also include suitable hardware to assist in implementing the machine-executable instructions of the software and/or software modules.

Such software may be a computer program product employing a machine-readable storage medium. A machine-readable storage medium may be any medium capable of storing and/or encoding a sequence of instructions for execution by a machine (e.g., a computing device) and causing the machine to perform any one of the methods and/or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random access memory "RAM" devices, magnetic cards, optical cards, solid-state memory devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and/or any combination thereof. Machine-readable media, as used herein, is intended to include a single medium as well as a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with a computer memory. As used herein, machine-readable storage media does not include a transitory form of signal transmission.

Such software may also include information (e.g., data) carried as a data signal on a data carrier, such as a carrier wave. For example, machine-executable information may be included as a data carrying signal embodied in a data carrier, the signal encoding a sequence of instructions or portions thereof for execution by a machine (e.g., a computing device), as well as any associated information (e.g., data structures and data) that causes the machine to perform any one of the methods and/or embodiments described herein.

Examples of computing devices include, but are not limited to, e-book reading devices, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smartphones, etc.), web appliances, network routers, network switches, network bridges, any machine capable of executing a sequence of instructions that define actions to be taken by the machine, and any combination thereof. In one example, a computing device may include and/or be included within a kiosk.

6 illustrates a diagrammatic representation of one embodiment of a computing device as an exemplary form of computer system 600 on which a set of instructions for causing a control system to perform any one or more of the aspects and/or methods of the present disclosure may be executed. It is also contemplated that multiple computing devices may be utilized to implement a set of instructions specifically configured to cause one or more of the devices to perform any one or more of the aspects and/or methods of the present disclosure. Computer system 600 includes a processor 604 and a memory 608, which communicate with each other and with other components via a bus 612. Bus 612 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of a variety of bus architectures.

The memory 608 may include a variety of components (e.g., machine-readable media), including, but not limited to, random access memory components, read-only components, and any combination thereof. In one example, a basic input/output system 616 (BIOS), including basic routines that help to transfer information between elements within the computer system 600, such as during startup, may be stored in the memory 608. The memory 608 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 620 that embody any one or more of the aspects and/or methods of the present disclosure. In another example, the memory 608 may further include any number of program modules, including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combination thereof.

Computer system 600 may also include a storage device 624. Examples of storage devices (e.g., storage device 624) include, but are not limited to, hard disk drives, magnetic disk drives, optical disk drives combined with optical media, solid-state memory devices, and any combination thereof. Storage device 624 may be connected to bus 612 by a suitable interface (not illustrated). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE®), and any combination thereof. In one example, storage device 624 (or one or more of its components) may be removably interfaced with computer system 600 (e.g., via an external port connector (not illustrated)). In particular, storage device 624 and associated machine-readable media 628 may provide non-volatile and/or volatile storage of machine-readable instructions, data structures, program modules, and/or other data for computer system 600. In one example, the software 620 may reside, completely or partially, within the machine-readable medium 628. In another example, the software 620 may reside, completely or partially, within the processor 604.

Computer system 600 may also include input devices 632. In one example, a user of computer system 600 may type commands and/or other information into computer system 600 via input devices 632. Examples of input devices 632 include, but are not limited to, alphanumeric input devices (e.g., keyboards), pointing devices, joysticks, gamepads, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., mice), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touch screens, and any combination thereof. Input devices 632 may be interfaced to bus 612 via any of a variety of interfaces (not illustrated), including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE® interface, a direct interface to bus 612, and any combination thereof. Input devices 632 may include a touch screen interface, which may be part of or separate from display 636, discussed further below. The input device 632 may be utilized as a user selection device for selecting one or more graphical representations in a graphical interface as described above.

A user may also input commands and/or other information to computer system 600 via storage device 624 (e.g., removable disk drive, flash drive, etc.) and/or network interface device 640. A network interface device, such as network interface device 640, may be utilized to connect computer system 600 to one or more of a variety of networks, such as network 644, and one or more remote devices 648 connected thereto. Examples of network interface devices include, but are not limited to, network interface cards (e.g., mobile network interface cards, LAN cards), modems, and any combination thereof. Examples of networks include, but are not limited to, wide area networks (e.g., the Internet, an enterprise network), local area networks (e.g., a network associated with an office, building, campus, or other relatively small geographic space), telephone networks, data networks associated with a telephone/voice provider (e.g., a mobile communications provider's data and/or voice network), a direct connection between two computing devices, and any combination thereof. A network, such as network 644, may employ wired and/or wireless modes of communication. In general, any network topology may be used. Information (e.g., data, software 620, etc.) may be communicated to and/or from computer system 600 via network interface device 640.

The computer system 600 may further include a video display adapter 652 for communicating images displayable on a display device, such as the display device 636. Examples of display devices include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combination thereof. The display adapter 652 and the display device 636 may be utilized in combination with the processor 604 to provide graphical representations of aspects of the present disclosure. In addition to a display device, the computer system 600 may include one or more other peripheral output devices, including, but not limited to, audio speakers, a printer, and any combination thereof. Such peripheral output devices may be connected to the bus 612 via a peripheral interface 656. Examples of peripheral interfaces include, but are not limited to, a serial port, a USB connection, a FIREWIRE® connection, a parallel connection, and any combination thereof.

The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions may be made without departing from the spirit and scope of the present invention. Features of each of the various embodiments described above may be combined with features of other described embodiments, as appropriate, to provide a combination of features in related new embodiments. Moreover, while the foregoing describes several separate embodiments, what has been described herein is merely illustrative of the application of the principles of the present invention. In addition, although certain methods herein may be illustrated and/or described as being performed in a specific order, the order may be varied considerably within ordinary skill in the art to achieve the embodiments as disclosed herein. Thus, this description is intended to be taken only as an example, and is not intended to otherwise limit the scope of the present invention.

In the above description and in the claims, phrases such as "at least one of" or "one or more of" may occur followed by a conjunctive enumeration of elements or features. The term "and/or" may also occur within a enumeration of two or more elements or features. Unless otherwise implied or explicitly contradicted by the context in which such a phrase is used, this is intended to mean any of the elements or features listed individually or any of the elements or features listed in combination with any of the other listed elements or features. For example, the phrases "at least one of A and B," "one or more of A and B," and "A and/or B" are each intended to mean "A only, B only, or both A and B." A similar interpretation is intended with respect to enumerations containing more than two items. For example, the phrases "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, and/or C" are each intended to mean "A only, B only, C only, both A and B, both A and C, both B and C, or both A, B, and C." Additionally, use of the term "based on" above and in the claims is intended to mean "based at least on," such that unrecited features or elements are also allowed.

The subject matter described herein may be embodied as a system, an apparatus, a method, and/or an article, depending on the desired configuration. The implementations described in the foregoing description do not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the subject matter described. Although some variations have been described in detail above, other modifications or additions are possible. In particular, further features and/or variations may be provided in addition to those described herein. For example, the implementations described above may be directed to various combinations and subcombinations of the disclosed features and/or combinations and subcombinations of some further features disclosed above. In addition, the logic flow depicted in the accompanying figures and/or described herein does not necessarily require the particular order or sequential order shown to achieve the desired results. Other implementations may be within the scope of the following claims.

Claims (22)

10. A decoder, the decoder comprising a circuit, the circuit comprising:
Receiving a bitstream;
storing a plurality of long term reference frames in a reference list;
retaining a long term reference frame in the reference list for a length of time based on a retention time;
and decoding at least a portion of a video using the long term reference frames maintained in the reference list, each long term reference frame in the stored long term reference frames including an associated retention time. The decoder of claim 1, further configured to mark the long-term reference frame as unavailable after the long-term reference frame has resided in the reference list for at least the retention time. The decoder of claim 2, further configured to mark the long-term reference frame as available based on a signal in the bitstream. The decoder of claim 1, wherein the bitstream includes a signal for removing the long-term reference frame from memory. The decoder of claim 4, further configured to remove the long-term reference frame from the reference list based on the signal. an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients;
an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing an inverse discrete cosine;
A deblocking filter;
A frame buffer;
The decoder of claim 1 further comprising: an intra-prediction processor; Receiving a coded block;
determining that an inter prediction mode is enabled for the coded block;
The decoder of claim 1 , further configured to: determine a decoded block using the long-term reference frame as a reference frame and according to the inter prediction mode. The decoder of claim 7, wherein the decoded blocks form part of a quad tree plus a binary decision tree. The decoder of claim 8, wherein the decoded block is a non-leaf node of the quad tree plus binary decision tree. 1. A method, comprising:
A decoder receives a bitstream;
storing a plurality of long term reference frames in a reference list;
the decoder retaining a long term reference frame in the reference list for a length of time based on a retention time;
and the decoder decoding at least a portion of a video using the long term reference frames maintained in the reference list, each long term reference frame in the stored long term reference frames including an associated retention time. The method of claim 10, further comprising marking the long-term reference frame as unavailable after the long-term reference frame has resided in the reference list for at least the retention time. The method of claim 11, further comprising marking the long-term reference frame as available based on a signal in the bitstream. The method of claim 10, wherein the bitstream includes a signal for removing the long-term reference frame from memory. The method of claim 13, further comprising removing the long-term reference frame from the reference list based on the signal. The decoder further comprises:
an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients;
an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing an inverse discrete cosine;
A deblocking filter;
A frame buffer;
An intra prediction processor. Receiving a coded block;
determining that an inter prediction mode is enabled for the coded block;
The method of claim 10 , further comprising: determining a decoded block using the long-term reference frame as a reference frame and according to the inter prediction mode. The method of claim 16, wherein the decoded blocks form part of a quad tree plus a binary decision tree. The method of claim 17, wherein the decoded block is a non-leaf node of the quad tree plus binary decision tree. 1. A decoder, comprising:
receiving a bitstream including signaling information and a plurality of coded pictures, the plurality of coded pictures including a picture used as a long-term reference picture, a first coded picture, a second coded picture, and a subsequent coded picture , the picture used as the long-term reference picture being marked as an IDR picture;
decoding the plurality of coded pictures, including a picture used as the long-term reference picture, the first coded picture , the second coded picture, and the subsequent coded picture , and storing the decoded plurality of coded pictures in a decoded picture buffer, wherein the decoding includes:
decoding the first coded picture by forming a first list of reference pictures from the decoded coded pictures in the decoded picture buffer, where one picture in the first list of reference pictures is the long-term reference picture ; and decoding blocks of the first coded picture using the long-term reference picture ;
indicating, in response to at least one parameter in the signaling information, that the long-term reference picture is unavailable as a reference picture while continuing to store the long-term reference picture in the decoded picture buffer;
decoding the second coded picture without using the long-term reference picture indicated as unavailable as a reference picture;
changing an indication of the long-term reference picture in a subsequent list of reference pictures from unavailable to available as a reference picture in response to at least one parameter in the signaling information;
and decoding a block from the subsequent coded picture using the long-term reference picture . 20. The decoder of claim 19, further configured to mark the long-term reference picture as unused for reference purposes and remove the long-term reference picture from the decoded picture buffer. The decoder of claim 19, wherein the parameters are time-related parameters. The decoder of claim 19, wherein the bitstream is a single-view bitstream.