JP7452076B2 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Conventionally, aluminum (Al) and aluminum alloys have been used as materials for electrode pads in power semiconductor devices and electrode wiring layers in integrated circuits. It is common to provide a barrier layer on the substrate. The barrier layer prevents atomic diffusion and mutual reactions between the aluminum electrode layer, the metal layer or metal compound layer below the barrier layer, and the semiconductor substrate, thereby preventing pn junctions and Schottky junctions that constitute semiconductor devices. It has the function of preventing the bond from breaking.

In a semiconductor device equipped with this barrier layer, the barrier properties of the barrier layer are improved by using a titanium nitride (TiN) layer whose crystal orientation is mainly {200} plane as determined by X-ray diffraction. A device has been proposed (for example, see Patent Document 1). Furthermore, in Patent Document 1, the barrier layer is made to have a thickness that is 80% or more of the thickness of the part on the main surface of the semiconductor substrate even on the side wall of a fine contact hole with a high aspect ratio, thereby improving the barrier properties of the barrier layer. Improving. It is disclosed that the preferred thickness of the barrier layer is between 50 nm and 700 nm.

Another semiconductor device with a barrier layer includes a metal nitride layer formed by nitriding and densification through a first heat treatment, and an amorphous metal layer formed above and immediately below the metal nitride layer through a second heat treatment. A device has been proposed in which the barrier properties of the barrier layer are improved by using an oxide layer as the barrier layer (see, for example, Patent Document 2). In Patent Document 2, a barrier layer is formed using titanium or vanadium (V). It is disclosed that the preferred thickness of the barrier layer is between 50 nm and 200 nm.

In addition, as another semiconductor device equipped with a barrier layer, a vanadium layer and an aluminum electrode layer to be an electrode wiring layer were sequentially deposited on a platinum (Pt) silicide layer forming a Schottky junction with a semiconductor substrate. A device has been proposed (for example, see Patent Document 3). Patent Document 3 discloses that a vanadium layer is deposited to a thickness of 0.2 μm while the temperature of a semiconductor substrate (hereinafter referred to as substrate temperature) is 290° C. The vanadium layer is a barrier layer that prevents atoms from diffusing from the aluminum layer to the platinum silicide layer.

Japanese Patent Application Publication No. 10-064852 Japanese Patent Application Publication No. 2000-182993 Japanese Patent Application Publication No. 2010-062518

FIG. 12 is an explanatory diagram schematically showing problems that have arisen in conventional semiconductor devices. FIG. 12 illustrates a front electrode 114 to which the configuration of Patent Document 3 is applied. A vanadium layer was used as an example of the barrier layer. The thickness t101 of the vanadium layer 112 serving as a barrier layer is preferably as thick as possible within the allowable range of material costs, manufacturing time, and the like. The reason for this is that the thicker the thickness t101 of the vanadium layer 112, the more the barrier properties of the vanadium layer 112 can be improved, which increases the effect of providing the vanadium layer 112 (preventing atomic diffusion and mutual reactions). This is because it is possible.

However, the thicker the thickness t101 of the vanadium layer 112, the more likely cracks 121 will occur in the vanadium layer 112, and the barrier properties of the vanadium layer 112 will deteriorate. For example, when the aluminum electrode layer 113 is formed, the cracks 121 of the vanadium layer 112 are filled with aluminum, and the aluminum filled in the cracks 121 reacts with the platinum silicide layer 111 and silicon (Si) of the semiconductor substrate 101, causing a reverse reaction. Directional breakdown voltage characteristics and reverse current characteristics become poor.

Furthermore, there is a possibility that the cracks 121 generated in the vanadium layer 112 penetrate the vanadium layer 112 in the depth direction and reach the platinum silicide layer 111 and the semiconductor substrate 101 below the vanadium layer 112. This causes a problem that the semiconductor device 110 is destroyed and the yield of the semiconductor device 110 is reduced. Further, the above-mentioned Patent Documents 1 to 3 do not describe measures against cracks 121 that occur in the vanadium layer 112 when the thickness t101 of the vanadium layer 112 is increased to an extent exceeding 0.2 μm.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve the barrier properties of a barrier layer in order to solve the problems caused by the prior art described above.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. A first metal layer is provided on a surface of a semiconductor substrate or a surface of a silicide layer on the semiconductor substrate. A second metal layer containing aluminum is provided on the surface of the first metal layer. The second metal layer is electrically connected to the semiconductor substrate via the first metal layer. The thickness of the first metal layer is greater than 0.2 μm. The orientation strength of the specific crystal orientation determined by EBSD measurement with respect to the specific direction of the crystal grains of the first metal layer is 5 or less. The first metal layer is a vanadium layer, the crystal grains are vanadium crystal grains, the specific direction is a crystal growth direction of the vanadium crystal grains, and the specific crystal orientation is <111>.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the orientation strength of the crystal grains of the first metal layer is 4 or less.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the first metal layer is 0.5 μm or more and 1.0 μm or less.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the first metal layer is 0.8 μm or more.

Further, in the semiconductor device according to the present invention, in the above-described invention, the first metal layer is arranged in a direction parallel to the surface of the semiconductor substrate in a portion having a thickness exceeding 0.2 μm from the surface of the semiconductor substrate. It includes a plurality of columnar crystal grains. Some of the first crystal grains among the plurality of crystal grains are oriented in the specific crystal orientation. The remaining second crystal grains among the plurality of crystal grains are oriented in a crystal orientation different from the specific crystal orientation.

Further, in the semiconductor device according to the invention described above, the first metal layer includes a larger number of the first crystal grains than the number of the second crystal grains.

Furthermore, in order to solve the above-mentioned problems and achieve the objects of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. A first step of forming a first metal layer on a surface of a semiconductor substrate or a surface of a silicide layer on the semiconductor substrate is performed. A second step is performed to form a second metal layer containing aluminum on the surface of the first metal layer and electrically connected to the semiconductor substrate via the first metal layer. In the first step, the temperature of the semiconductor substrate is set at 220° C. or more and 290° C. or less so that an index indicating the randomness of crystal orientation of the crystal grains in the first metal layer in a specific direction is maximized. The first metal layer is formed on the surface of the semiconductor substrate in a heated state to a thickness of more than 0.2 μm. In the first step, the peak intensity of a specific crystal plane of the crystal grains of the first metal layer that does not face the specific direction is used as the index. The first metal layer is a vanadium layer, the crystal grains are vanadium crystal grains, the specific direction is a crystal growth direction of the vanadium crystal grains, and the specific crystal plane is a {110} plane.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, the first step is characterized in that the first metal layer is formed by vapor deposition.

According to the above-described invention, it is possible to reduce the probability that vanadium crystal grains are oriented in a direction in which specific crystal planes that are adjacent to each other facing a specific direction of the vanadium crystal grains are separated from each other, thereby reducing the gap between the crystal grains that becomes a crack. is less likely to occur. Thereby, it is possible to suppress the occurrence of cracks in the vanadium layer, and it is possible to suppress the deterioration of the barrier properties of the vanadium layer. Moreover, even if the thickness of the vanadium layer is increased, cracks are less likely to occur in the vanadium layer, so the thickness of the vanadium layer can be increased.

ADVANTAGE OF THE INVENTION According to the semiconductor device and the manufacturing method of a semiconductor device concerning this invention, it is effective in being able to improve the barrier property of a barrier layer.

1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIG. 2 is an enlarged view showing a part of the front electrode of FIG. 1; FIG. 2 is a cross-sectional view showing a part of a front electrode of a conventional semiconductor device. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the embodiment. FIG. 2 is a characteristic diagram showing the relationship between the substrate temperature during vapor deposition of a vanadium layer and the orientation strength of vanadium crystal grains. FIG. 2 is a characteristic diagram showing the relationship between the substrate temperature during vapor deposition of a vanadium layer and the crystal orientation of vanadium crystal grains. FIG. 2 is an explanatory diagram schematically showing a problem occurring in a conventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, a layer or region prefixed with n or p means that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n and p mean that the impurity concentration is higher or lower than that of a layer or region to which n or p is not appended, respectively. Note that in the following description of the embodiment and the accompanying drawings, similar components are denoted by the same reference numerals, and overlapping description will be omitted.

(Embodiment)
The structure of the semiconductor device according to the embodiment will be explained. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIG. 2 is an enlarged view showing a part of the front surface electrode of FIG. 1. FIG. FIG. 3 is a cross-sectional view showing a part of a front electrode of a conventional semiconductor device. In this embodiment, an example is shown in which vanadium (V) is used as the first metal layer. FIG. 3 shows a part of the front electrode 114 shown in FIG. 12 in an enlarged manner. 2 and 3, the 12,112 vanadium crystal grains 12a, 112a of the vanadium (V) layer (first metal layer) are shown as ellipses, and the crystal orientations of the vanadium crystal grains 12a, 112a are indicated by arrows within the ellipses. show.

A semiconductor device 10 according to the embodiment shown in FIG. 1 has a ^bonding surface ( This is a Schottky barrier diode (SBD) that utilizes the rectifying properties of the Schottky barrier formed by the Schottky barrier junction surface (hereinafter referred to as a Schottky barrier junction surface) 6. The semiconductor substrate 1 is, for example, an epitaxial substrate in which an n ^- type semiconductor layer 3, which becomes an n ^- type drift region, is epitaxially grown on the front surface of an n ⁺ type starting substrate 2 made of silicon (Si).

The main surface of the semiconductor substrate 1 on the n ⁻ type semiconductor layer 3 side is the front surface, and the main surface on the n ⁺ type starting substrate 2 side (the back surface of the n ⁺ type starting substrate 2) is the back surface. In the surface region of the front surface of the semiconductor substrate 1, a p-type region serving as a field limiting ring (FLR) as a breakdown voltage structure is provided inside the n ^- type semiconductor layer 3 in the edge termination region. 4 is selectively provided. P-type region 4 is provided in an annular shape surrounding Schottky barrier junction surface 6 .

The edge termination region is a region between the active region and the edge of the semiconductor substrate 1 (chip edge), and surrounds the active region. A breakdown voltage structure such as the above-mentioned FLR is arranged in the edge termination region. Thereby, the edge termination region has a function of alleviating the electric field on the front surface side of the semiconductor substrate 1 and maintaining the withstand voltage (withstanding voltage). Withstand voltage is the limit voltage at which an element will not malfunction or break down. The active region is a region through which current flows when the SBD is in the on state. The active region is arranged, for example, in the center of the semiconductor substrate 1.

The front surface of the semiconductor substrate 1 is covered with an interlayer insulating film 5. One contact hole 5a is provided in the active region, penetrating the interlayer insulating film 5 in the depth direction and reaching the semiconductor substrate 1. The entire front surface of the semiconductor substrate 1 in the active region (the surface of the n ^- type semiconductor layer 3) is exposed in the contact hole 5a. Here, exposed means being in contact with platinum silicide layer 11, which will be described later. The interlayer insulating film 5 is provided in a ring shape surrounding the active region. The inner end (inner peripheral portion) of p-type region 4 may be exposed in contact hole 5a.

A platinum silicide layer 11 is provided on the entire front surface of the semiconductor substrate 1 inside the contact hole 5a. The platinum silicide layer 11 is in contact with the n ⁻ type semiconductor layer 3 inside the contact hole 5 a and forms a Schottky barrier junction surface 6 with the n ⁻ type semiconductor layer 3 . Therefore, the entire front surface of the semiconductor substrate 1 in the active region serves as the Schottky barrier junction surface 6. Platinum silicide layer 11 may be in contact with p-type region 4 at the outer periphery of contact hole 5a.

Inside the contact hole 5a, a vanadium layer 12 is provided over the entire surface of the platinum silicide layer 11. The vanadium layer 12 is an intermediate metal layer provided between the platinum silicide layer 11 and an aluminum electrode layer (second metal layer) 13 (described later) in contact with these layers. The vanadium layer 12 prevents atomic diffusion and interaction between the aluminum electrode layer 13 and the platinum silicide layer 11 and the semiconductor substrate 1 that are lower than the vanadium layer 12, thereby preventing destruction of the Schottky barrier junction surface 6. Functions as a barrier layer to prevent

In a portion of the vanadium layer 12 near the semiconductor substrate 1 (a portion from the surface of the platinum silicide layer 11 to a thickness of about 0.2 μm: hereinafter referred to as an amorphous crystal region), the vanadium crystal does not have a regular shape ( (not shown). Furthermore, the vanadium layer 12 is slightly disposed in a portion away from the semiconductor substrate 1 (a portion having a thickness exceeding about 0.2 μm from the surface of the platinum silicide layer: hereinafter referred to as a columnar crystal region) with respect to the vertical direction of the semiconductor substrate 1. It includes diagonally inclined columnar vanadium crystals (hereinafter referred to as vanadium crystal grains (first and second crystal grains)) 12a and 12b (FIG. 2).

The vanadium crystal grains 12a and 12b have a long cross-sectional shape in the direction of crystal growth of the vanadium crystal grains, and have the same length as the thickness of the columnar crystal region. Vanadium crystal grains 12a and 12b are arranged in an arbitrary order in the horizontal direction of semiconductor substrate 1. In some of the vanadium crystal grains 12b in the columnar crystal region, the crystal orientation in the crystal growth direction of the vanadium crystal grains is not aligned with <111>, which is the crystal orientation in which vanadium crystal grains tend to grow. In this embodiment, the crystal growth direction of the vanadium crystal grains is the longitudinal direction of the vanadium columnar crystals, which is slightly oblique to the direction perpendicular to the front surface of the semiconductor substrate 1.

For example, the vanadium layer 112 deposited (formed) by applying the manufacturing method of the conventional semiconductor device 110 (see FIGS. 3 and 12) (hereinafter referred to as the conventional structure) is a non-conductive layer similar to the vanadium layer 12 of the embodiment. Although it has a regular crystal region, it was confirmed that the <111> orientation strength with respect to the crystal growth direction of the columnar vanadium crystal grains 112a (see FIG. 3) in the columnar crystal region is greater than that of the vanadium layer 12 of the embodiment. Ta.

In the conventional structure, almost all the vanadium crystal grains 112a in the columnar crystal region of the vanadium layer 112 are oriented in <111>, which is the crystal orientation in which the vanadium crystal grains 112a tend to grow. In the columnar crystal region of the vanadium layer 112, vanadium crystal grains (not shown) oriented in <111> are lined up next to each other so as to face each other with a crack 121 (see FIG. 3) in between. It was also confirmed that the vanadium crystal grains oriented in <111> were oriented in a direction in which they opened from each other with the crack 121 in between.

Furthermore, in the conventional structure, it has been confirmed that when the vanadium layer 112 is deposited with the temperature of the semiconductor substrate 101 (substrate temperature) elevated to, for example, about 350° C., cracks 121 occur in the vanadium layer 112. In the columnar crystal region of the vanadium layer 112, the <111> orientation strength of the vanadium crystal grains 112a increases, and the probability that a force acts in the direction of separating adjacent vanadium crystal grains from each other increases, causing It is assumed that a gap that becomes a crack 121 is generated.

Orientation strength refers to the fact that when the intensity distribution of the inverse pole figure (crystal orientation distribution map) of a crystal grain is measured using the EBSD (Electron Backscattered Diffraction) method, all crystal orientations have an equal probability in a specific direction. This is the degree of crystal orientation, with the state that appears (hereinafter referred to as a "completely random state") being 1. The orientation strength increases as the crystallinity in a specific direction increases. For example, when the orientation strength of <111> with respect to the crystal growth direction of a crystal grain is 10, it means that the crystal orientation of the crystal grain appears with a probability of about 10 times that of a completely random state.

The EBSD method is a scanning electron microscope (SEM) or transmission electron microscope (TEM) equipped with a backscattered electron diffraction image detector such as a CCD (Charge Coupled Device) camera. import the diffraction pattern using , is a method of performing crystal orientation analysis. By the EBSD method, a crystal orientation map (not shown) as seen from a specific direction is obtained, in which the orientation of the measurement point on the inverse pole figure of the crystal grain is expressed by a mixture of three primary colors.

In the embodiment, the vanadium layer 12 includes more vanadium crystal grains 12a oriented in the <111> direction in the crystal growth direction of the vanadium crystal grains than vanadium crystal grains 12b oriented in other crystal orientations. There are fewer vanadium crystal grains 12a than in the vanadium layer 112. In addition, the vanadium layer 12 includes vanadium crystal grains 12b oriented, for example, in <001> or <101>.

The orientation strength of <111> (specific crystal orientation) measured by EBSD with respect to the crystal growth direction (specific direction) of the vanadium crystal grains of the vanadium layer 12 is, for example, about 5 or less, preferably about 4 or less. . Specifically, the vanadium crystal grains 12b that are not oriented in the <111> direction in the crystal growth direction of the vanadium crystal grains are included in the columnar crystal region of the vanadium layer 12, so that the crystal growth direction of the vanadium crystal grains in the vanadium layer 12 is The <111> orientation strength relative to the vanadium layer 112 is relatively small compared to the vanadium layer 112 having a conventional structure.

Since the occupancy rate of columnar crystal regions in the vanadium layer 12 is greater than the occupancy rate of amorphous crystal regions, the state of the columnar crystal regions is dominant in the results obtained by EBSD measurement. The amorphous crystal region of the vanadium layer 12 has vanadium crystals that do not have a fixed shape and is oriented <001> in the crystal growth direction of the vanadium crystal grains, which is the same as the vanadium crystal grains 12a in the columnar crystal region. 111>. For this reason, it is presumed that no cracks are formed between adjacent crystal grains.

The peak intensity of the {110} plane of the vanadium layer 12 (peak intensity of a specific crystal plane) is, for example, 3.5 or more, and is larger than the peak intensity of the {110} plane of the vanadium layer 112 of the conventional structure. In this embodiment, the peak intensity of the {110} plane of the vanadium layer 12 formed at a substrate temperature of 350° C. is set to 1. Since the crystal growth direction of the vanadium crystal grains mainly faces the {111} plane, the larger the peak intensity of the {110} plane of the vanadium layer 12, the less the crystal orientation of the vanadium crystal grains is aligned to <111>. Therefore, the peak intensity of a specific crystal plane that does not face the crystal growth direction of the vanadium crystal grains is an index indicating the randomness of the crystal orientation of the vanadium crystal grains. For this reason, when depositing the vanadium layer 12, the peak intensity of a specific crystal plane that does not face the crystal growth direction of the vanadium crystal grains (an index indicating the randomness of the crystal orientation of the vanadium crystal grains) is maximized. All you have to do is set the substrate temperature.

The peak intensity of a specific crystal plane of the vanadium layer 12 can be measured by, for example, an X-ray diffraction (XRD) method. Here, the peak intensity of a specific crystal plane of the vanadium layer 12 measured by the XRD method is used as an index indicating the randomness of the crystal orientation of the vanadium layer 12. can be arbitrarily selected according to, for example, the film forming apparatus for vapor depositing the vanadium layer 12, the film forming conditions of the vanadium layer 12, and the method of measuring the crystal orientation of the vanadium layer 12.

In this way, the orientation strength of <111> with respect to the crystal growth direction of the vanadium crystal grains of the vanadium layer 12 is set to 5 or less, or the peak strength of the {110} plane of the vanadium layer 12 is set to 3.5 or more, or Satisfy both. This reduces the probability that vanadium crystal grains will be oriented in a direction in which specific planes facing specific crystal orientations are separated from each other (vanadium crystal grains will face each other in a direction in which specific crystal planes facing specific crystal orientations will open). , it is assumed that cracks are less likely to occur. Here, the specific crystal orientation with respect to the specific direction of the vanadium crystal grains is <111> with respect to the crystal growth direction of the vanadium crystal grains.

Further, in the embodiment, it is useful when the thickness t1 of the vanadium layer 12 is thicker than about 0.2 μm at which columnar crystal regions are formed in the vanadium layer 12. In particular, the vanadium layer 12 has cracks 121 ( 3 and 12) is likely to occur, for example, when the thickness is about 0.5 μm or more, preferably about 0.8 μm or more. As the thickness t1 of the vanadium layer 12 becomes thicker, the barrier properties of the vanadium layer 12 can be improved, but in consideration of material costs, manufacturing time, etc., it is preferable to set the thickness t1 to about 1.0 μm or less, for example.

By increasing the thickness t1 of the vanadium layer 12 in this way, the thickness t1 of the vanadium layer 12 becomes thicker than the unevenness of the base layer or the height (particle size) of the particles. This eliminates the portion where the vanadium layer 112 is not formed, and it is possible to prevent the aluminum electrode layer 113 from coming into contact with the platinum silicide layer 111 or the semiconductor substrate 101. Particles are fine particles, minute dirt, and dust that cause defects.

As described above, in the conventional structure, when the thickness t101 of the vanadium layer 112 is increased, cracks 121 are likely to occur in the vanadium layer 112. On the other hand, in the embodiment, vanadium can be Cracks are less likely to occur in the layer 12. Therefore, it is possible to prevent the reverse breakdown voltage characteristics and reverse current characteristics of the semiconductor device 10 from becoming poor.

An aluminum electrode layer 13 is provided on the entire surface of the vanadium layer 12. The platinum silicide layer 11, the vanadium layer 12, and the aluminum electrode layer 13 on the front surface of the semiconductor substrate 1 constitute a front surface electrode 14 that functions as an anode electrode. Aluminum electrode layer 13 is electrically connected to n ^- type semiconductor layer 3 via vanadium layer 12 and platinum silicide layer 11 . The aluminum electrode layer 13 also serves as an electrode pad to which a wire made of aluminum or the like is bonded.

The aluminum electrode layer 13 may have a thickness such that a wire bonded to the surface of the aluminum electrode layer 13 does not penetrate through the aluminum electrode layer 13. The thickness of the aluminum electrode layer 13 may be as thin as the thickness t1 of the vanadium layer 12. A back electrode 15 serving as an anode electrode is provided on the back surface of the semiconductor substrate 1. The back electrode 15 is in ohmic contact with the semiconductor substrate 1 and is electrically connected to the n ⁺ type starting substrate 2 which becomes the n ⁺ type cathode region. The back electrode 15 functions as a cathode electrode.

Next, a method for manufacturing the semiconductor device 10 according to the embodiment will be described. 4 to 9 are cross-sectional views showing a state in the middle of manufacturing the semiconductor device according to the embodiment. First, an arsenic (As)-doped silicon substrate, for example, is prepared as an n ⁺ -type starting substrate (semiconductor wafer) 2 that will become an n ⁺ -type cathode region. The impurity concentration and thickness of the n ⁺ type starting substrate 2 may be, for example, about 2×10 ¹⁹ /cm ³ and about 300 μm, respectively.

A semiconductor substrate 1 is fabricated by epitaxially growing, for example, a phosphorus (P)-doped n ^- type semiconductor layer 3 which will become an n ^- type drift region on the front surface of this n ⁺ type starting substrate 2 . The impurity concentration and thickness of the n ^- type semiconductor layer 3 may be, for example, about 2×10 ¹⁴ /cm ³ and about 20 μm, respectively (FIG. 4). Next, an ion implantation mask is formed on the surface of the n ^- type semiconductor layer 3, with an opening corresponding to the region where the p-type region 4 will be formed.

Next, using this ion implantation mask as a mask, ions of a p-type impurity such as boron (B) are implanted into the n ^- type semiconductor layer 3. The acceleration voltage and dose amount for this ion implantation may be, for example, about 45 keV and about 1×10 ¹³ /cm ² , respectively. Next, the ion-implanted impurities are diffused by heat treatment at a temperature of, for example, 1100° C. for about one hour to form a p-type region 4 that becomes an FLR with a depth of, for example, about 1.5 μm (FIG. 5).

Next, an interlayer insulating film 5 is formed on the front surface of the semiconductor substrate 1 (the surface of the n ^- type semiconductor layer 3). Next, the interlayer insulating film 5 is selectively removed by photolithography and etching to form a contact hole 5a that penetrates the interlayer insulating film 5 in the depth direction and reaches the semiconductor substrate 1. In the contact hole 5a of the interlayer insulating film 5, a portion corresponding to the formation region of the Schottky barrier junction surface 6 is exposed (FIG. 6).

Next, for example, the semiconductor substrate 1 is heated in a furnace with a degree of vacuum of 5×10 ⁻⁴ Pa to bring the temperature of the semiconductor substrate 1 (substrate temperature) to about 200° C. A platinum layer 21 having a thickness of, for example, about 0.04 μm is deposited (formed) on the surface. The platinum layer 21 is formed over the entire front surface of the semiconductor substrate 1 from the surface of the portion of the front surface of the semiconductor substrate 1 exposed to the contact hole 5a along the surface of the interlayer insulating film 5 (see FIG. 7).

Due to the thermal history during the deposition of the platinum layer 21, the platinum in the platinum layer 21 reacts with the silicon in the semiconductor substrate 1, and the portion of the platinum layer 21 in contact with the semiconductor substrate 1 is silicided, and the semiconductor is formed in the contact hole 5a. A platinum silicide layer 11 is formed on the front surface of the substrate 1. As a result, a Schottky barrier junction surface 6 between the platinum silicide layer 11 and the n ^- type semiconductor layer 3 is formed in the contact hole 5a.

Next, the unsilicided portions of the platinum layer 21 are removed using hot aqua regia. As a result, the portion of the platinum layer 21 on the interlayer insulating film 5 is completely removed, leaving the platinum silicide layer 11 with a thickness of, for example, about 0.02 μm in the contact hole 5a (FIG. 8). The portion of the platinum layer 21 on the interlayer insulating film 5 may be removed by photolithography and etching instead of using hot aqua regia.

By removing the platinum layer 21 with hot aqua regia, the platinum silicide layer 11 is left in the contact hole 5a and the platinum layer 21 is removed on the interlayer insulating film 5 with fewer steps than when using photolithography and etching. The parts that easily peel off can be removed. When the platinum layer 21 is removed using hot aqua regia, a portion of the platinum layer 21 that is not silicided may remain on the platinum silicide layer 11.

Next, the semiconductor substrate 1 is heated in a furnace so that the substrate temperature is, for example, about 220° C. or more and 290° C. or less, preferably about 240° C. or more and 260° C. or less, and the above-mentioned A vanadium layer 12 having a predetermined thickness t1 is deposited (formed). By depositing the vanadium layer 12 at a substrate temperature equal to or higher than the above lower limit, it is possible to suppress the portion of the vanadium layer 12 that is in contact with the interlayer insulating film 5 from peeling off from the interlayer insulating film 5 .

Furthermore, the higher the substrate temperature is, the more difficult it is for the vanadium layer 12 to peel off from the interlayer insulating film 5, but the vanadium layer 12 tends to be more likely to crack. By depositing the vanadium layer 12 with the substrate temperature below the above upper limit, the orientation intensity of <111> with respect to the crystal growth direction of the vanadium crystal grains of the vanadium layer 12, or the peak intensity of the {110} plane of the vanadium layer 12, or Both of the above conditions can be met.

Next, an aluminum electrode layer 13 having a thickness of, for example, 5 μm is deposited (formed) on the vanadium layer 12 while the substrate temperature is set to, for example, about 150° C. in a furnace. The aluminum electrode layer 13 is, for example, continuously deposited on the vanadium layer 12 . Next, the laminated metal layer consisting of the vanadium layer 12 and the aluminum electrode layer 13 is patterned by photolithography and etching, and the portion of the laminated metal layer on the chip end side is removed (FIG. 9).

Next, on the back surface of the semiconductor substrate 1 (the back surface of the n ⁺ -type starting substrate 2), for example, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film are sequentially laminated to form a back electrode 15. The thicknesses of the titanium film, nickel film, and gold film of the back electrode 15 may be, for example, about 0.2 μm, about 0.7 μm, and about 0.15 μm, respectively. Thereafter, the semiconductor substrate 1 is diced (cut) into individual chips, thereby completing the SBD shown in FIG.

As described above, according to the embodiment, the <111> orientation strength of the vanadium crystal grains of the vanadium layer with respect to the crystal growth direction, the peak strength of the {110} plane of the vanadium layer, or both of the above conditions Make it. Thereby, the crystal orientation of the vanadium layer can be made random so that the vanadium crystal grains of the vanadium layer are not aligned in the <111> direction where the vanadium crystal grains tend to grow. This can reduce the probability that vanadium crystal grains will be oriented in directions away from each other, and gaps that will become cracks are less likely to occur between adjacent vanadium crystals.

Since gaps that become cracks are less likely to occur between adjacent vanadium crystals, it is possible to suppress the generation of cracks in the vanadium layer, and it is possible to suppress a decrease in the barrier properties of the vanadium layer. In addition, since gaps that become cracks are less likely to occur between adjacent vanadium crystals, the vanadium layer can be formed with a uniform thickness. Uniform thickness means that the thickness is the same within a range that includes an allowable error due to process variations. Furthermore, even if the thickness of the vanadium layer is increased, cracks are less likely to occur in the vanadium layer, so the barrier properties of the vanadium layer can be improved by increasing the thickness of the vanadium layer.

(Experiment example)
The substrate temperature during vapor deposition of the vanadium layer 12 was verified. 10 and 11 are characteristic diagrams showing the relationship between the substrate temperature and the orientation strength and crystal orientation of vanadium crystal grains during vapor deposition of a vanadium layer, respectively. A plurality of SBDs were manufactured according to the method for manufacturing the semiconductor device 10 according to the embodiment described above (see FIGS. 4 to 9). These multiple samples each have different substrate temperatures (temperatures of the semiconductor substrate 1) when the vanadium layer 12 functioning as a barrier layer is deposited. The thickness t1 of the vanadium layer 12 was set to 0.8 μm.

FIG. 10 shows the results of measuring the orientation strength of <111> with respect to the crystal growth direction of the vanadium crystal grains of the vanadium layer 12 with respect to the plurality of samples by EBSD measurement. From the results shown in FIG. 10, the orientation intensity distribution of <111> with respect to the crystal growth direction of the vanadium crystal grains of the vanadium layer 12 shows a minimum value at a predetermined temperature (here, 250°C), and below the peak value at the predetermined temperature. It was confirmed that the curve has a convex parabolic shape. Furthermore, among the plurality of samples described above, it was confirmed that the orientation strength could be made 5 or less in a sample (hereinafter referred to as an example) in which the substrate temperature was 220° C. or more and 290° C. or less.

In addition, FIG. 11 shows the results of measuring the peak intensity of the {110} plane of the vanadium layer 12 using the XRD method for the plurality of samples described above. From the results shown in FIG. 11, the peak intensity distribution of the {110} plane of the vanadium layer 12 shows a maximum value at a predetermined temperature (here, 250° C.), and has an upwardly convex parabolic shape with the predetermined temperature as the apex. This was confirmed. Further, in the embodiment, the peak intensity of the {110} plane of the vanadium layer 12 can be increased to 3.5 or more, compared to the above-mentioned conventional structure in which the vanadium layer 112 is deposited with the substrate temperature at 350° C., for example. It was confirmed that the peak intensity of the {110} plane of the vanadium layer 12 could be increased.

In this way, in the embodiment, the <111> orientation strength with respect to the crystal growth direction of the vanadium crystal grains of the vanadium layer 12 is set to 5 or less, or the peak strength of the {110} plane of the vanadium layer 12 is set to 3.5 or more. or both conditions. As a result, even when the thickness t1 of the vanadium layer 12 is made thicker than 0.2 μm, it is possible to suppress the occurrence of cracks in the vanadium layer 12, and the barrier properties according to the thickness t1 of the vanadium layer 12 can be suppressed. It was confirmed that it can be maintained. Furthermore, it was confirmed that the barrier properties of the vanadium layer 12 could be increased by increasing the thickness t1 of the vanadium layer 12.

Furthermore, by increasing the thickness t1 of the vanadium layer 12, even if particles are attached to the surface on which the vanadium layer 12 is formed (the surface of the platinum silicide layer 11 or the front surface of the semiconductor substrate 1), the The particles can be completely covered with the vanadium layer 12. Therefore, deterioration in the barrier properties of the vanadium layer 12 due to particles can be suppressed. Although not shown in the drawings, in the example, the semiconductor device 1 It was confirmed that the yield was improved.

As described above, the present invention is not limited to the embodiments described above, and various changes can be made without departing from the spirit of the present invention. For example, in the embodiments described above, an SBD is used as an example, but the present invention is applicable to various semiconductor devices including a barrier layer between an aluminum electrode layer and a semiconductor substrate. Therefore, instead of the platinum silicide layer that makes Schottky contact with the semiconductor substrate, a metal silicide layer that makes ohmic contact with the semiconductor substrate may be provided between the vanadium layer and the semiconductor substrate. The vanadium layer serving as the barrier layer may be in direct contact with the front surface of the semiconductor substrate.

Furthermore, in the above-described embodiments, the case where the specific crystal orientation with respect to the specific direction of the vanadium crystal grains is <111> with respect to the crystal growth direction of the vanadium crystal grains is explained as an example. The same effect can be obtained even if the direction and specific crystal orientation are used. In addition to vanadium (V), examples of barrier layer materials include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), and chromium. (Cr), zirconium (Zr), or a composite layer thereof may be provided. In this case as well, the same effect as that of the vanadium layer can be obtained by setting the orientation strength of the specific crystal orientation with respect to the specific direction of the crystal grains of the barrier layer, the peak intensity of the specific crystal plane of the barrier layer, or both under the above conditions. has.

As described above, the semiconductor device and the method for manufacturing a semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices of various industrial machines, and the like.

1 Semiconductor substrate 2 N ⁺ type starting substrate 3 N ^- type semiconductor layer 4 P type region 5 Interlayer insulating film 5a Contact hole 6 Schottky barrier junction surface 10 Semiconductor device 11 Platinum silicide layer 12 Vanadium layer 12a, 12b Vanadium crystal grain 13 Aluminum Electrode layer 14 Front electrode 15 Back electrode 21 Platinum layer t1 Thickness of vanadium layer

Claims (8)

a first metal layer provided on a surface of a semiconductor substrate or a surface of a silicide layer on the semiconductor substrate;
a second metal layer containing aluminum, provided on the surface of the first metal layer and electrically connected to the semiconductor substrate via the first metal layer;
Equipped with
The thickness of the first metal layer is thicker than 0.2 μm,
The orientation strength of the specific crystal orientation determined by EBSD measurement with respect to the specific direction of the crystal grains of the first metal layer is 5 or less,
the first metal layer is a vanadium layer,
The crystal grains are vanadium crystal grains,
The specific direction is a crystal growth direction of vanadium crystal grains,
A semiconductor device , wherein the specific crystal orientation is <111> . 2. The semiconductor device according to claim 1, wherein the orientation strength of the crystal grains of the first metal layer is 4 or less. 3. The semiconductor device according to claim 1, wherein the first metal layer has a thickness of 0.5 μm or more and 1.0 μm or less. 4. The semiconductor device according to claim 3, wherein the first metal layer has a thickness of 0.8 μm or more. The first metal layer includes a plurality of columnar crystal grains arranged in a direction parallel to the surface of the semiconductor substrate in a portion having a thickness exceeding 0.2 μm from the surface of the semiconductor substrate,
Some of the first crystal grains of the plurality of crystal grains are oriented in the specific crystal orientation,
5. The semiconductor device according to claim 1, wherein the remaining second crystal grains among the plurality of crystal grains are oriented in a crystal orientation different from the specific crystal orientation. 6. The semiconductor device according to claim 5, wherein the first metal layer includes a greater number of the first crystal grains than the number of the second crystal grains. a first step of forming a first metal layer on a surface of a semiconductor substrate or a surface of a silicide layer on the semiconductor substrate;
a second step of forming a second metal layer containing aluminum on the surface of the first metal layer and electrically connected to the semiconductor substrate via the first metal layer;
including;
In the first step, the temperature of the semiconductor substrate is set at 220° C. or more and 290° C. or less so that an index indicating the randomness of crystal orientation of the crystal grains in the first metal layer in a specific direction is maximized. forming the first metal layer with a thickness of more than 0.2 μm on the surface of the semiconductor substrate in a heated state;
In the first step, the peak intensity of a specific crystal plane not facing the specific direction of the crystal grains of the first metal layer is used as the index,
the first metal layer is a vanadium layer,
The crystal grains are vanadium crystal grains,
The specific direction is a crystal growth direction of vanadium crystal grains,
A method of manufacturing a semiconductor device, wherein the specific crystal plane is a {110} plane. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the first step, the first metal layer is formed by vapor deposition.

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