JP7391694B2 - リードフレーム、半導体装置及びリードフレームの製造方法 - Google Patents
リードフレーム、半導体装置及びリードフレームの製造方法 Download PDFInfo
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- JP7391694B2 JP7391694B2 JP2020019203A JP2020019203A JP7391694B2 JP 7391694 B2 JP7391694 B2 JP 7391694B2 JP 2020019203 A JP2020019203 A JP 2020019203A JP 2020019203 A JP2020019203 A JP 2020019203A JP 7391694 B2 JP7391694 B2 JP 7391694B2
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
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- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- Engineering & Computer Science (AREA)
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- Lead Frames For Integrated Circuits (AREA)
Description
[リードフレームの構成]
図1は、実施例に係るリードフレーム100aの構成の一例を示す平面図である。図1に示すように、リードフレーム100aは、例えば銅又は銅合金等の金属からなる導電性部材であり、枠体101によってマトリクス状に分割される複数の区画それぞれに単体のリードフレーム100が配列された集合体として形成される。単体のリードフレーム100は、半導体素子が搭載されて個々の半導体装置(パッケージ)として分離される要素である。以下の説明では、単体のリードフレーム100を適宜「リードフレーム100」と呼ぶ。
次に、図8及び図9を参照して、実施例に係るリードフレーム100を用いて作成された半導体装置200について説明する。図8は、実施例に係るリードフレーム100を用いて作成された半導体装置200を下面側から見た平面図である。図9は、図8のIX-IX線断面を示す図である。
次に、実施例に係るリードフレーム100の製造方法について説明する。図12は、実施例に係るリードフレーム100の製造方法の一例を示すフローチャートである。
次に、実施例に係る半導体装置200の製造方法について説明する。図21は、実施例に係る半導体装置200の製造方法の一例を示すフローチャートである。半導体装置200は、上述したリードフレーム100を用いて製造される。
101 枠体
102 リード
102a 下面
102b 側面
103 ダイパッド
103a 支持用リード
104 めっき層
110 凹部
111、112 凹部
200 半導体装置
201 半導体素子
202 接続部材
203 封止樹脂
Claims (10)
- 枠体と
前記枠体からそれぞれ突出する複数のリードと、
前記枠体を挟んで互いに隣り合う前記リードの一面に跨って形成される凹部と
を有し、
前記凹部は、
第1凹部と、
底面において前記第1凹部と部分的に重なり且つ前記第1凹部よりも深さが浅い第2凹部と
を有し、
前記リードを前記一面側から見た平面視において、前記第2凹部の領域内に前記第1凹部の領域が含まれおり、且つ前記第2凹部の面積が前記第1凹部の面積よりも大きいことを特徴とするリードフレーム。 - 前記凹部の第1凹部は、
前記リードの一面からの深さが前記リードの厚さに応じて定まる所定値よりも大きく、
前記凹部の第2凹部は、
前記リードの一面からの深さが前記所定値よりも小さい
ことを特徴とする請求項1に記載のリードフレーム。 - 前記凹部は、
一対の前記第1凹部を備え、
一対の前記第1凹部は、
前記リードの一面の少なくとも前記枠体を挟む範囲に互いに分離して配置される
ことを特徴とする請求項1に記載のリードフレーム。 - 前記凹部の第1凹部は、
前記リードの一面において前記枠体を跨いで前記リードの長手方向に連続して設けられる
ことを特徴とする請求項1に記載のリードフレーム。 - 前記枠体は、
前記リードの一面よりも前記リードの厚さ方向に低く形成される面を有し、
前記凹部の第2凹部の底面は、
前記枠体の前記面と同一面上に位置する
ことを特徴とする請求項1に記載のリードフレーム。 - 半導体素子を搭載するためのダイパッドをさらに有することを特徴とする請求項1に記載のリードフレーム。
- リードと、
前記リードに接続部材を介して接続される半導体素子と、
前記リードの一部、前記接続部材及び前記半導体素子を被覆する封止樹脂と
を有し、
前記リードは、
前記接続部材に接続し、前記封止樹脂によって被覆される第1面と、
前記第1面の反対側に位置し、前記封止樹脂から露出する第2面と、
前記第1面及び前記第2面に連続し、少なくとも一部が前記封止樹脂から露出する側面と、
前記第2面の前記側面側の端部に形成される凹部と
を有し、
前記凹部は、
第1凹部と、
底面において前記第1凹部と部分的に重なり且つ前記第1凹部よりも前記第2面からの深さが浅い第2凹部と
を有し、
前記リードを前記第2面側から見た平面視において、前記第2凹部の領域内に前記第1凹部の領域が含まれおり、且つ前記第2凹部の面積が前記第1凹部の面積よりも大きいことを特徴とする半導体装置。 - 前記第1凹部及び前記第2凹部は、
前記封止樹脂から露出する前記リードの前記側面において開放されている
ことを特徴とする請求項7に記載の半導体装置。 - ダイパッドをさらに有し、
前記半導体素子は、前記ダイパッド上に搭載される
ことを特徴とする請求項7に記載の半導体装置。 - 凹部が形成される凹部予定領域を有する金属板にエッチングを施すことにより、前記金属板の前記凹部予定領域に第1凹部を形成する工程と、
前記第1凹部の形成後の前記金属板にさらにエッチングを施すことにより、枠体及び前記枠体からそれぞれ突出する複数のリードを形成するとともに、前記枠体を挟んで互いに隣り合う前記リードの一面に跨って、前記第1凹部と、底面において前記第1凹部と部分的に重なり且つ前記第1凹部よりも前記リードの一面からの深さが浅い第2凹部とを備える前記凹部を形成する工程と
を有することを特徴とするリードフレームの製造方法。
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US17/165,032 US11616005B2 (en) | 2020-02-06 | 2021-02-02 | Plurality of leads having a two stage recess |
TW110104113A TW202201663A (zh) | 2020-02-06 | 2021-02-04 | 引線框架、半導體裝置以及引線框架之製造方法 |
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WO2015145651A1 (ja) | 2014-03-27 | 2015-10-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP2016082222A (ja) | 2014-10-09 | 2016-05-16 | 大日本印刷株式会社 | リードフレームおよびその製造方法 |
US20190252256A1 (en) | 2018-02-14 | 2019-08-15 | Nxp B.V. | Non-leaded device singulation |
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US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
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US8841758B2 (en) | 2012-06-29 | 2014-09-23 | Freescale Semiconductor, Inc. | Semiconductor device package and method of manufacture |
JP6213582B2 (ja) * | 2016-01-22 | 2017-10-18 | 日亜化学工業株式会社 | 発光装置 |
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JP2016082222A (ja) | 2014-10-09 | 2016-05-16 | 大日本印刷株式会社 | リードフレームおよびその製造方法 |
US20190252256A1 (en) | 2018-02-14 | 2019-08-15 | Nxp B.V. | Non-leaded device singulation |
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