JP7390214B2 - Silicon wafer surface condition diagnosis method and surface modification method - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 80
- 229910052710 silicon Inorganic materials 0.000 title claims description 80
- 239000010703 silicon Substances 0.000 title claims description 80
- 238000000034 method Methods 0.000 title claims description 19
- 238000003745 diagnosis Methods 0.000 title claims description 7
- 238000002715 modification method Methods 0.000 title claims description 4
- 238000005259 measurement Methods 0.000 claims description 26
- 238000012986 modification Methods 0.000 claims description 19
- 230000004048 modification Effects 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 19
- 238000010521 absorption reaction Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000004381 surface treatment Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 54
- 238000010586 diagram Methods 0.000 description 6
- 238000000227 grinding Methods 0.000 description 5
- 210000000078 claw Anatomy 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010191 image analysis Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000002003 electron diffraction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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Description
本発明は、シリコンウエハ表面の加工変質層である表面欠陥の修復に係り、特に、レーザ熱処理を用いたシリコンウエハ表面改質に関し、その表面の改質状況を診断するシリコンウエハ表面状態診断方法及び表面改質方法に関する。 The present invention relates to the repair of surface defects that are process-altered layers on the surface of silicon wafers, and in particular to silicon wafer surface modification using laser heat treatment. Relating to a surface modification method.
半導体デバイス等の作製に使用されるシリコンウエハ等の半導体ウェハは、切削・研削・ラッピング・ポッリシングなどの機械加工プロセスによって表面加工が行われている。しかし、その表面及び内部は、加工変質層が形成され、一部の加工変質層には、マイクロクラック（微小亀裂）が含まれる。この内部クラック等の除去は、主にエッチングや化学機械研磨（ＣＭＰ）等の化学的・機械的方法により行われている。 BACKGROUND ART Semiconductor wafers such as silicon wafers used for manufacturing semiconductor devices and the like are subjected to surface processing through machining processes such as cutting, grinding, lapping, and polishing. However, a process-affected layer is formed on the surface and inside thereof, and some of the process-affected layers include microcracks. Removal of internal cracks and the like is mainly performed by chemical/mechanical methods such as etching and chemical mechanical polishing (CMP).
例えば、特許文献１は、単結晶表面にパルスレーザを照射し、パルスレーザ照射部の断面ＴＥＭ（透過型電子顕微鏡）観察像で評価することを記載している。 For example, Patent Document 1 describes that a single crystal surface is irradiated with a pulsed laser and evaluated using a cross-sectional TEM (transmission electron microscope) observation image of the pulsed laser irradiated part.
また、特許文献２は、半導体ウェハの反りを測定し、測定された反りと研削工程で研削された研削深さに基づいて、表面変質層の深さを求めることを記載している。 Further, Patent Document 2 describes that the warpage of a semiconductor wafer is measured, and the depth of the surface altered layer is determined based on the measured warp and the grinding depth obtained in the grinding process.
上記従来技術において、特許文献１に記載のようにＴＥＭ（透過型電子顕微鏡）を用いる方法は、観察試料の厚さを数ｎｍ程度（観察可能な厚さ）にする必要があり、そのため、試料の準備作業には細心の注意が必要で、時間もかかる。また、試料は電子ビームを浴びることで破壊を伴った計測となる。試料に電子を当てて干渉パターンを観察する電子回折や光と物質の相互作用を利用するラマン分光計測等は、同様であり、非常に高価な装置であり、導入は困難である。 In the above-mentioned conventional technology, the method using a TEM (transmission electron microscope) as described in Patent Document 1 requires the thickness of the observation sample to be approximately several nm (thickness that can be observed); The preparation work requires careful attention and is time consuming. Furthermore, the measurement results in destruction of the sample when it is exposed to the electron beam. Electron diffraction, in which an interference pattern is observed by exposing a sample to electrons, and Raman spectroscopy, which utilizes the interaction between light and matter, are similar, and require extremely expensive equipment that is difficult to implement.
また、特許文献２に記載のように反りを計測して加工変質層を評価する方法は、計測時に荷重がかかるため破壊が進行する恐れがある。さらに、ノッチ部のような広域にわたる曲面等のような形状に対する効率的な計測は、現時点で知られていない。 Further, in the method of evaluating the process-affected layer by measuring warpage as described in Patent Document 2, there is a risk that destruction may progress because a load is applied during measurement. Furthermore, efficient measurement of shapes such as curved surfaces over a wide area, such as notches, is currently unknown.
本発明の目的は、上記従来技術の課題を解決し、レーザ表面改質機に搭載することも可能とする。そして、本発明は、リアルタイムな加工中（表面改質中）も含め、表面状態の診断、修復効果確認を行うことで、高品質のシリコンウェハを提供することを目的とする。 An object of the present invention is to solve the problems of the above-mentioned prior art and to enable it to be installed in a laser surface modification machine. An object of the present invention is to provide high-quality silicon wafers by diagnosing the surface condition and confirming the repair effect, including during real-time processing (during surface modification).
上記目的を達成するため、本発明は、レーザ熱処理を用いたシリコンウエハ表面改質におけるシリコンウエハ表面状態診断方法であって、前記シリコンウエハ表面の反射率又は吸収率の測定、及び電気物性を測定する。 In order to achieve the above object, the present invention provides a method for diagnosing a silicon wafer surface condition in silicon wafer surface modification using laser heat treatment, which includes measuring the reflectance or absorptance of the silicon wafer surface and measuring electrical properties. do.
また、前記反射率又は前記吸収率の測定は、波長が５３２、あるいは７８５ｎｍのレーザで行うことが望ましい。 Further, it is preferable that the reflectance or the absorptance be measured using a laser having a wavelength of 532 nm or 785 nm.
さらに、前記電気物性は、前記シリコンウエハの表面処理部に近接して電極を配置し、前記シリコンウエハと前記電極間で形成されるコンデンサの静電容量を測定することが望ましい。 Furthermore, it is preferable that the electrical properties be measured by arranging an electrode close to the surface-treated portion of the silicon wafer and measuring the capacitance of a capacitor formed between the silicon wafer and the electrode.
さらに、前記電気物性は、前記シリコンウエハの表面処理部に近接して電極を配置し、前記シリコンウエハと前記電極間に電圧を印加して極板間引力を測定することが望ましい。 Further, it is preferable to measure the electrical properties by arranging an electrode close to the surface-treated portion of the silicon wafer and applying a voltage between the silicon wafer and the electrode to measure the attractive force between the electrode plates.
さらに、前記極板間引力は、ひずみゲージで測定することが望ましい。 Furthermore, it is desirable that the inter-plate attractive force be measured using a strain gauge.
さらに、前記シリコンウエハを載置するリングポールと、リング形状の極板リングに等分割で配置された薄板と、前記薄板に貼り付けられ、ブリッジ回路が構成される前記ひずみゲージと、を備え、前記極板リングを前記シリコンウエハと間隙を持って配置し、前記リングポールと前記極板リングとの間に電圧を印加して前記極板間引力を測定することが望ましい。 Further, it includes a ring pole on which the silicon wafer is placed, a thin plate arranged in equal parts on a ring-shaped electrode plate ring, and the strain gauge attached to the thin plate to form a bridge circuit, It is preferable that the electrode plate ring is placed with a gap between the electrode plate ring and the silicon wafer, and a voltage is applied between the ring pole and the electrode plate ring to measure the attractive force between the electrode plates.
また、本発明は、レーザ熱処理を用いたシリコンウエハ表面改質方法であって、前記シリコンウエハ表面の反射率測定又は吸収率の測定するステップ１と、前記シリコンウエハの表面処理部に近接して電極を配置し、前記シリコンウエハと前記電極間で形成されるコンデンサの静電容量を測定するステップ２と、前記ステップ１、前記ステップ２に基づいて前記レーザ熱処理の加工条件を決定するステップ３と、を有する。 The present invention also provides a method for modifying the surface of a silicon wafer using laser heat treatment, which includes step 1 of measuring reflectance or absorption of the silicon wafer surface; a step 2 of arranging electrodes and measuring the capacitance of a capacitor formed between the silicon wafer and the electrode; and a step 3 of determining processing conditions for the laser heat treatment based on the steps 1 and 2. , has.
さらに、前記レーザ熱処理の加工中に、前記ステップ１、前記ステップ２を行い、その結果をフィードバック制御して加工を継続することが望ましい。 Furthermore, it is desirable to carry out Step 1 and Step 2 during the laser heat treatment, and continue the processing by controlling the results as feedback.
本発明によれば、シリコンウエハ表面の反射率又は吸収率の測定、及び電気物性を測定してシリコンウエハ表面状態を診断するので、レーザ表面改質機に搭載することも可能である。リアルタイムな加工中（表面改質中）も含め、表面状態の診断、修復効果確認を行うことで、高品質のシリコンウェハを提供することができる。 According to the present invention, since the silicon wafer surface condition is diagnosed by measuring the reflectance or absorptance of the silicon wafer surface and the electrical properties, it can also be installed in a laser surface modification machine. By diagnosing the surface condition and checking the repair effect in real time, including during processing (surface modification), we can provide high quality silicon wafers.
図１は、一実施形態による光の反射率、あるいは吸収率の測定部を示すブロック図、図２は、シリコンウェハと電極間の静電容量や極板間引力の測定部を示すブロック図である。加工変質層は、主にアモルファスシリコン層や多結晶状態となっている。この加工変質層は極めて薄いものであるが、機械的・電気的・光学的性能に大きく影響している。 FIG. 1 is a block diagram showing a measuring section for light reflectance or absorption according to one embodiment, and FIG. 2 is a block diagram showing a measuring section for measuring capacitance between a silicon wafer and an electrode and attraction between electrode plates. be. The process-affected layer is mainly an amorphous silicon layer or a polycrystalline state. Although this processed layer is extremely thin, it greatly affects mechanical, electrical, and optical performance.
本実施形態は、研削やエッチング処理後の加工変質層の表面に関して、反射率（吸収率）の測定や画像解析により表面状態を調べる。また、数μｍ深さ程度の内部の状態に関しては、５３２ｎｍ、近赤外光（７８５ｎｍ）の波長の計測用レーザを照射して反射率（吸収）を調べる。 In the present embodiment, the surface condition of the surface of the process-affected layer after grinding or etching treatment is investigated by measuring reflectance (absorption rate) and image analysis. Regarding the internal state at a depth of several micrometers, reflectance (absorption) is investigated by irradiating a measurement laser with a wavelength of 532 nm and near-infrared light (785 nm).
さらに、外部より電圧を印加（シリコンウェハ表面を帯電させる）することで、アモルファス、多結晶シリコン、単結晶シリコンの電気物性（伝導度、静電容量、極板間引力等）の違いを検知し改質状況を調べる。つまり、シリコンウエハ１表面の反射率又は吸収率の測定、及び電気物性を測定したことになる。 Furthermore, by applying a voltage from the outside (charging the silicon wafer surface), we can detect the differences in electrical properties (conductivity, capacitance, inter-plate attraction, etc.) of amorphous, polycrystalline silicon, and single-crystalline silicon. Check the modification status. In other words, the reflectance or absorption of the surface of the silicon wafer 1 and the electrical properties were measured.
つまり、本実施形態は、シリコンウェハ１表面状態の診断、修復効果確認を行うため、以下の（１）から（４）を組み合わせて総合的に測定及び評価することが好ましい。
（１）測定面の形状も考慮し、偏光させるなどした近赤外光（７８５ｎｍ）を照射して単結晶の反射率、あるいは吸収率を得る。
（２）シリコンウエハ１の測定面１－１の形状も考慮し、偏光させるなどした可視光、あるいは波長５３２ｎｍの光を当てアモルファスの反射率、あるいは吸収率を得る。なお、アモルファスシリコン層は、波長５３２ｎｍの光に強い吸収がある。
（３）画像、接触式等により表面形状（粗さ等も含む）を計測する。
（４）改質前後、及び改質中の加工対象物（シリコンウェハ）の電気物性（電気伝導度、静電容量、極板間引力等）の違いを得る。
That is, in this embodiment, in order to diagnose the surface state of the silicon wafer 1 and confirm the repair effect, it is preferable to perform comprehensive measurement and evaluation by combining the following (1) to (4).
(1) Considering the shape of the measurement surface, polarized near-infrared light (785 nm) is irradiated to obtain the reflectance or absorption of the single crystal.
(2) Considering the shape of the measurement surface 1-1 of the silicon wafer 1, polarized visible light or light with a wavelength of 532 nm is applied to obtain amorphous reflectance or absorption. Note that the amorphous silicon layer has strong absorption of light with a wavelength of 532 nm.
(3) Measure the surface shape (including roughness, etc.) using images, contact methods, etc.
(4) Obtaining differences in electrical properties (electrical conductivity, capacitance, inter-plate attraction, etc.) of the workpiece (silicon wafer) before and during modification, and before and during modification.
図１において、計測用光源２は、シリコンウエハ１の測定面１－１へ計測用レーザ、あるいは可視光を矢印のように表面に照射する。計測用光源（レーザ熱処理）２は、計測用の光源や波長が５３２、あるいは７８５ｎｍのレーザであり、偏光子を介しても良い。そして、その反射光は、フィルターを介してカメラや検出器３で検出、解析し反射率、あるいは吸収率を評価、測定する。 In FIG. 1, a measurement light source 2 irradiates a measurement laser or visible light onto a measurement surface 1-1 of a silicon wafer 1 as shown by an arrow. The measurement light source (laser heat treatment) 2 is a measurement light source or a laser having a wavelength of 532 or 785 nm, and may be provided through a polarizer. Then, the reflected light is detected and analyzed by a camera or a detector 3 through a filter, and the reflectance or absorption rate is evaluated and measured.
光の反射率（吸収）評価、測定において、溶融中のシリコンの反射率は、固体のそれと比較して３０％と高く、表面改質中の反射率測定で表面改質状況を調べることができる。なお、光の反射率（吸収率）の測定は、計測用光源２から測定面１－１へ照射される計測用レーザの入射角の影響を考慮して、偏光子をレーザ出光部の直後に配置することが好ましい。 In light reflectance (absorption) evaluation and measurement, the reflectance of molten silicon is 30% higher than that of solid silicon, and the surface modification status can be investigated by measuring the reflectance during surface modification. . Note that when measuring the light reflectance (absorption rate), the polarizer is placed immediately after the laser emission part, taking into consideration the influence of the incident angle of the measurement laser irradiated from the measurement light source 2 to the measurement surface 1-1. It is preferable to arrange.
図２は、（４）の電気特性として、シリコンウエハ１と電極４間の静電容量７や極板間引力６の測定を示している。図２において、電極４は、シリコンウエハ１の表面処理部に対応するように近接して配置される。そして、静電容量７や極板間引力６は、シリコンウエハ１と電極４間に電圧５を印加して測定され、改質前後で比較する。 FIG. 2 shows the measurement of the capacitance 7 between the silicon wafer 1 and the electrode 4 and the attractive force 6 between the electrode plates as the electrical characteristics (4). In FIG. 2, electrodes 4 are arranged close to and corresponding to the surface-treated portions of silicon wafer 1. In FIG. The capacitance 7 and the inter-plate attractive force 6 are measured by applying a voltage 5 between the silicon wafer 1 and the electrode 4, and compared before and after modification.
溶融状態のシリコンの電気伝導度は、固体に比べ、１００倍以上高いことが知られている。したがって、シリコンウエハ１表面の電気伝導度を測定することで溶融したシリコンの容量を評価することもできる。電気伝導度は、表面処理中に溶融したシリコンの伝導率が変化し、シリコンウエハ１と電極４間で形成されたコンデンサの静電容量７、極板間引力６として変化する。表面改質部の状況は、静電容量７の変化する現象を観察、あるいは測定することで評価することが可能となる。 It is known that the electrical conductivity of molten silicon is more than 100 times higher than that of solid silicon. Therefore, by measuring the electrical conductivity of the surface of the silicon wafer 1, the capacity of the melted silicon can also be evaluated. The electrical conductivity changes as the conductivity of melted silicon changes during surface treatment, and as the capacitance 7 of the capacitor formed between the silicon wafer 1 and the electrode 4 and the attractive force 6 between the electrode plates. The condition of the surface modified portion can be evaluated by observing or measuring the phenomenon in which the capacitance 7 changes.
図３は、レーザ熱処理を用いた表面改質(加工)及び診断のフローチャートである。表面改質(加工)及び診断は、改質処理対象のシリコンウエハ表面状態を測定、あるいは評価し、それに応じた条件でレーザ照射を行うことにより効率良く、効果的な表面改質を行う。まず、でレーザ照射による加工前にシリコンウエハ１表面の反射率又は吸収率の測定及び画像解析を行う（ステップ１）。
次に、図２で示した方法で静電容量７を評価する（ステップ２）。つまり、ステップ１、ステップ２でシリコンウエハ１表面の反射率又は吸収率の測定、及び電気物性としての静電容量７を測定したことになる。そして、加工条件は、ステップ１、ステップ２の測定及び評価に基づいて決定する（ステップ３）。
FIG. 3 is a flowchart of surface modification (processing) and diagnosis using laser heat treatment. Surface modification (processing) and diagnosis involves measuring or evaluating the surface condition of a silicon wafer to be modified, and performing laser irradiation under conditions corresponding to the surface condition to perform efficient and effective surface modification. First, before processing by laser irradiation, the reflectance or absorptance of the surface of the silicon wafer 1 is measured and image analyzed (step 1).
Next, the capacitance 7 is evaluated using the method shown in FIG. 2 (step 2). That is, in steps 1 and 2, the reflectance or absorption of the surface of the silicon wafer 1 was measured, and the capacitance 7 as an electrical property was measured. Processing conditions are then determined based on the measurements and evaluations in steps 1 and 2 (step 3).
加工中は、ステップ１、ステップ２と同様に表面の反射率測定、静電容量の評価(電気伝導度の変化)を行い、その結果をフィードバック制御して加工を継続する（ステップ４）。 During processing, the surface reflectance is measured and the capacitance is evaluated (changes in electrical conductivity) in the same way as in steps 1 and 2, and the results are feedback-controlled to continue processing (step 4).
なお、レーザ照射で加工することで、シリコンウエハ１の酸素排除処理及び結晶性の向上が可能であり、パルスレーザを照射することで、シリコンウエハ１表面の加工変質層である表面欠陥の修復が可能である。 Note that by processing with laser irradiation, it is possible to remove oxygen and improve the crystallinity of the silicon wafer 1, and by irradiating with pulsed laser, it is possible to repair surface defects, which are processing-affected layers on the surface of the silicon wafer 1. It is possible.
特に、シリコンウエハ１の研削後、その表面形状に対応して、少なくとも入射角、ｓ偏光とｐ偏光の成分、エネルギ密度、単位面積当たりの照射回数のいずれか一つを変化させてパルスレーザを照射することで、加工応力の影響をなくし均一な表面に改質することができる。 In particular, after grinding the silicon wafer 1, the pulsed laser is applied by changing at least one of the incident angle, the components of s-polarized light and p-polarized light, the energy density, and the number of irradiations per unit area, depending on the surface shape of the silicon wafer 1. By irradiating it, it is possible to eliminate the influence of processing stress and modify the surface to be uniform.
また、パルスレーザ（ナノ秒）照射による加工は、加工変質層のアモルファス層をナノ秒速で溶融する。そして、パルスレーザ（ナノ秒）照射による溶融は、結晶方位が揃った再結晶化（エピタキシャル成長）を進展させ、機械加工で生じた結晶欠陥を無くすことができる。 Further, processing by pulsed laser (nanosecond) irradiation melts the amorphous layer of the processed damaged layer at a nanosecond speed. Melting by pulsed laser (nanosecond) irradiation promotes recrystallization (epitaxial growth) with uniform crystal orientation, and can eliminate crystal defects caused by machining.
加工後は、ステップ１、ステップ２と同様に表面の反射率測定、画像解析、静電容量の評価（ステップ５、ステップ６）を行い、品質評価をして仕様に対してＯＫかＮＧかを判定する（ステップ７）。
以上により、シリコンウエハ１は、加工中も表面状態の診断、修復効果確認を行うので、高品質にすることができる。
After processing, perform surface reflectance measurement, image analysis, and capacitance evaluation (steps 5 and 6) in the same way as steps 1 and 2 to evaluate quality and decide whether it is OK or NG according to the specifications. Determine (step 7).
As described above, the surface condition of the silicon wafer 1 is diagnosed and the repair effect is confirmed even during processing, so that the quality of the silicon wafer 1 can be made high.
図４は、極板間引力６を測定する構成図である。図５は極板リング１０の平面図、図６は、側面図である。図２で示した極板間引力６は、ひずみゲージ１０－２で測定する。図４において、シリコンウエハ１は、リングポール１１に載置される。極板リング１０は、図２で示した電極４に相当するもので、リング形状のコンプライアンス構造（柔構造）とされている。 FIG. 4 is a configuration diagram for measuring the attractive force 6 between the electrode plates. FIG. 5 is a plan view of the electrode plate ring 10, and FIG. 6 is a side view. The inter-plate attractive force 6 shown in FIG. 2 is measured by a strain gauge 10-2. In FIG. 4 , silicon wafer 1 is placed on ring pole 11 . The electrode plate ring 10 corresponds to the electrode 4 shown in FIG. 2, and has a ring-shaped compliance structure (flexible structure).
薄板１０－１は、極板リング１０の上面に１２０°の等分割でコンプライアンスを持って配置されている。ひずみゲージ１０－２は、薄板１０－１の中心付近にそれぞれ貼り付けられている。また、３個のひずみゲージ１０－２は、ブリッジ回路が構成され、薄板１０－１に掛かる応力を検出する。 The thin plates 10-1 are arranged on the upper surface of the electrode plate ring 10 in equal divisions of 120° with compliance. The strain gauges 10-2 are each attached near the center of the thin plate 10-1. Further, the three strain gauges 10-2 constitute a bridge circuit and detect the stress applied to the thin plate 10-1.
電圧５は、リングポール１１と極板リング１０との間に印加される。シリコンウエハ１は、リングポール１１に載置されるので、電圧５は、シリコンウエハ１と極板リング１０との間に印加されたことになる。なお、リングポール１１は、シリコンウエハ１を載置する通常の回転テーブルに装着しても良い。 A voltage 5 is applied between the ring pole 11 and the plate ring 10. Since the silicon wafer 1 is placed on the ring pole 11, the voltage 5 is applied between the silicon wafer 1 and the plate ring 10. Note that the ring pole 11 may be attached to a normal rotary table on which the silicon wafer 1 is placed.
極板リング１０は、図６に示すように、爪部１０－３が回転可能として設けられている。爪部１０－３は、極板リング１０の内側へ図６（ａ）の矢印のように回転可能とされ、所定位置（図６で９０°）で図６（ｂ）のように固定される。したがって、シリコンウエハ１と極板リング１０は、図６（ｂ）で示すように間隙を持って配置され、図２の静電容量７を形成する。 As shown in FIG. 6, the electrode plate ring 10 is provided with a rotatable claw portion 10-3. The claw portion 10-3 is rotatable toward the inside of the electrode plate ring 10 as shown by the arrow in FIG. 6(a), and is fixed at a predetermined position (90° in FIG. 6) as shown in FIG. 6(b). . Therefore, the silicon wafer 1 and the plate ring 10 are arranged with a gap as shown in FIG. 6(b), forming the capacitance 7 shown in FIG.
つまり、図２で示した電極４は、シリコンウエハ１を挟み込むようにされ、極板間引力６をひずみゲージ１０－２で検出する。シリコンウエハ１と極板リング１０との間隙は、数１００μｍに設定する。極板間引力６は、アモルファスシリコン、多結晶シリコン、単結晶シリコンとで伝導率（移動度、比抵抗）が大きく異なることで表面の改質状況の判別が可能となる。 That is, the electrodes 4 shown in FIG. 2 are arranged to sandwich the silicon wafer 1, and the attractive force 6 between the electrode plates is detected by the strain gauge 10-2. The gap between the silicon wafer 1 and the electrode plate ring 10 is set to several hundred μm. The plate-to-plate attractive force 6 makes it possible to determine the state of surface modification because the conductivity (mobility, specific resistance) differs greatly between amorphous silicon, polycrystalline silicon, and single-crystalline silicon.
測定の手順は、以下のようになる。
（１）シリコンウエハ１は、リングポール１１に載置し、シリコンウエハ１の上に極板リング１０を装着する。
（２）爪部１０－３は、極板リング１０の内側へ回転させ、電圧５をリングポール１１と極板リング１０との間に印加する。
（３）極板間引力６が生じることにより、極板リング１０に応力が掛かり、変形する。
（４）極板リング１０の上面に配置された薄板１０－１に貼りつけられたひずみゲージ１０－２により応力が検出され電気信号として出力される。
The measurement procedure is as follows.
(1) The silicon wafer 1 is placed on the ring pole 11, and the electrode plate ring 10 is mounted on the silicon wafer 1.
(2) The claw portion 10-3 is rotated to the inside of the plate ring 10, and voltage 5 is applied between the ring pole 11 and the plate ring 10.
(3) Due to the generation of the inter-plate attractive force 6, stress is applied to the plate ring 10, causing it to deform.
(4) Stress is detected by the strain gauge 10-2 attached to the thin plate 10-1 placed on the top surface of the electrode plate ring 10 and output as an electrical signal.
以上述べた極板間引力６の測定によれば、改質前後、および改質中の加工対象物（シリコンウエハ）の電気物性（電気伝導度、静電容量、極板間引力等）の違いを高感度に測定が可能となる。 According to the measurement of the plate-to-plate attraction 6 described above, differences in the electrical properties (electrical conductivity, capacitance, plate-to-plate attraction, etc.) of the workpiece (silicon wafer) before, during and after modification. can be measured with high sensitivity.
１…シリコンウエハ
１－１…測定面
２…計測用光源
３…検出器
４…電極
５…電圧
６…極板間引力
７…静電容量
１０…極板リング
１０－１…薄板
１０－２…ゲージ
１０－３…爪部
１１…リングポール
1...Silicon wafer 1-1...Measurement surface 2...Measurement light source 3...Detector 4...Electrode 5...Voltage 6...Attractive force between plates 7...Capacitance 10...Plate ring 10-1...Thin plate 10-2... Gauge 10-3...Claw part 11...Ring pole
Claims (8)
前記シリコンウエハ表面の反射率又は吸収率の測定、及び電気物性を測定することを特徴とするシリコンウエハ表面状態診断方法。 A method for diagnosing a silicon wafer surface condition in silicon wafer surface modification using laser heat treatment, the method comprising:
A method for diagnosing the surface condition of a silicon wafer, comprising measuring reflectance or absorption of the silicon wafer surface and measuring electrical properties.
リング形状の極板リングに等分割で配置された薄板と、
前記薄板に貼り付けられ、ブリッジ回路が構成される前記ひずみゲージと、
を備え、前記極板リングを前記シリコンウエハと間隙を持って配置し、前記リングポールと前記極板リングとの間に電圧を印加して前記極板間引力を測定することを特徴とする請求項５に記載のシリコンウエハ表面状態診断方法。 a ring pole on which the silicon wafer is placed;
Thin plates arranged in equal parts in a ring-shaped polar plate ring,
The strain gauge is attached to the thin plate and forms a bridge circuit;
, wherein the electrode plate ring is arranged with a gap from the silicon wafer, and a voltage is applied between the ring pole and the electrode plate ring to measure the attractive force between the electrode plates. The silicon wafer surface condition diagnosis method according to item 5.
前記シリコンウエハ表面の反射率又は吸収率の測定をするステップ１と、
前記シリコンウエハの表面処理部に近接して電極を配置し、前記シリコンウエハと前記電極間で形成されるコンデンサの静電容量を測定するステップ２と、
前記ステップ１、前記ステップ２に基づいて前記レーザ熱処理の加工条件を決定するステップ３と、
を有するシリコンウエハ表面改質方法。 A silicon wafer surface modification method using laser heat treatment, the method comprising:
Step 1 of measuring reflectance or absorption of the silicon wafer surface;
Step 2 of arranging an electrode close to the surface treatment portion of the silicon wafer and measuring the capacitance of a capacitor formed between the silicon wafer and the electrode;
a step 3 of determining processing conditions for the laser heat treatment based on the steps 1 and 2;
A method for modifying the surface of a silicon wafer.
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