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JP7383554B2 - Substrate processing method and substrate processing apparatus - Google Patents

Substrate processing method and substrate processing apparatus Download PDF

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JP7383554B2
JP7383554B2 JP2020066978A JP2020066978A JP7383554B2 JP 7383554 B2 JP7383554 B2 JP 7383554B2 JP 2020066978 A JP2020066978 A JP 2020066978A JP 2020066978 A JP2020066978 A JP 2020066978A JP 7383554 B2 JP7383554 B2 JP 7383554B2
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substrate processing
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JP2021163928A (en
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穣二 高良
秀彦 佐藤
智之 工藤
宏朗 望月
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Tokyo Electron Ltd
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    • H01L21/67063—Apparatus for fluid treatment for etching
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    • H—ELECTRICITY
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    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
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    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring

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Description

本開示は、基板処理方法及び基板処理装置に関する。 The present disclosure relates to a substrate processing method and a substrate processing apparatus.

基板に所定の処理を施す基板処理装置が知られている。 2. Description of the Related Art Substrate processing apparatuses that perform predetermined processing on a substrate are known.

特許文献１には、基板に所定の処理を施す基板処理装置を制御する制御装置であって、基板に前記所定の処理を施すときの制御値となる所定の目標値を記憶する記憶部と、前記基板処理装置により処理される基板の処理状態を測定器に測定させ、測定させた情報を受信する通信部と、前記通信部により受信された測定情報のうち、今回処理する基板の処理前および処理後の測定情報に基づいて今回処理された基板の処理状態に応じたフィードバック値を算出し、今回より前に算出されたフィードバック値のいずれかに対する今回算出されたフィードバック値の変化値を算出する演算部と、前記演算部により算出されたフィードバック値の変化値と所与の閾値とを比較することにより、前記今回算出されたフィードバック値を破棄するか否かを判定する判定部と、前記判定部により破棄しないと判定された場合、前記今回算出されたフィードバック値を用いて前記記憶部に記憶された目標値を更新する更新部とを備える基板処理装置の制御装置が開示されている。 Patent Document 1 discloses a control device that controls a substrate processing apparatus that performs predetermined processing on a substrate, and includes a storage unit that stores a predetermined target value that is a control value when performing the predetermined processing on the substrate; a communication unit that causes a measuring device to measure the processing state of the substrate processed by the substrate processing apparatus and receives the measured information; and a communication unit that measures the processing state of the substrate to be processed this time and Calculate a feedback value according to the processing state of the substrate processed this time based on the measurement information after processing, and calculate the change value of the feedback value calculated this time with respect to any of the feedback values calculated before this time. a calculation unit; a determination unit that determines whether or not to discard the currently calculated feedback value by comparing a change value of the feedback value calculated by the calculation unit with a given threshold; and the determination unit. A control device for a substrate processing apparatus is disclosed, comprising: an updating section that updates a target value stored in the storage section using the currently calculated feedback value when it is determined by the section that the target value is not to be discarded.

特開２００８－１０３４２４号公報Japanese Patent Application Publication No. 2008-103424

一の側面では、本開示は、複数のチャンバで並列して基板に処理を施す基板処理装置において、処理結果のばらつきを抑制する基板処理方法及び基板処理装置を提供する。 In one aspect, the present disclosure provides a substrate processing method and a substrate processing apparatus that suppress variations in processing results in a substrate processing apparatus that processes substrates in parallel in a plurality of chambers.

上記課題を解決するために、一の態様によれば、前工程と後工程により基板に処理を施し、少なくとも前記後工程は、複数のチャンバにて並行して基板に処理を施す基板処理方法であって、前記前工程で処理された基板を複数の前記チャンバにて並行して前記後工程の処理をする工程と、前記チャンバごとに前記後工程の処理後の基板の特性値を取得する工程と、前記特性値と目標値との差が小さくなるように前記後工程の処理条件を調整した際の特性値の推定値である実力値を算出する工程と、前記チャンバごとに前記実力値と前記目標値との差である補正残差量を取得する工程と、全チャンバの前記補正残差量の平均値を算出する工程と、前記補正残差量の平均値に基づき、前記前工程の処理条件を補正する工程と、前記補正残差量の平均値と前記チャンバごとの前記補正残差量とに基づき、前記チャンバごとの前記後工程の処理条件を補正する工程と、補正された処理条件に基づいて、基板に前記前工程および前記後工程の処理を施す工程と、を有する、基板処理方法が提供される。 In order to solve the above problems, according to one aspect, a substrate processing method is provided, in which a substrate is processed in a pre-process and a post-process, and at least the post-process processes the substrate in parallel in a plurality of chambers. a step of processing the substrate processed in the pre-process in parallel in the post-process in a plurality of the chambers, and a step of obtaining characteristic values of the substrate after the post-process for each of the chambers. and a step of calculating an actual value which is an estimated value of the characteristic value when the processing conditions of the post-process are adjusted so that the difference between the characteristic value and the target value is small, and a step of calculating the actual value and the actual value for each chamber. a step of obtaining a corrected residual amount that is the difference from the target value; a step of calculating an average value of the corrected residual amounts of all chambers; a step of correcting processing conditions; a step of correcting processing conditions of the post-process for each chamber based on the average value of the corrected residual amount and the corrected residual amount for each chamber; and a corrected process. A substrate processing method is provided, comprising the steps of subjecting the substrate to the pre-process and the post-process based on conditions.

一の側面によれば、複数のチャンバで並列して基板に処理を施す基板処理装置において、処理結果のばらつきを抑制する基板処理方法及び基板処理装置を提供することができる。 According to one aspect, it is possible to provide a substrate processing method and a substrate processing apparatus that suppress variations in processing results in a substrate processing apparatus that processes substrates in parallel in a plurality of chambers.

本実施形態に係る基板処理装置の構成図の一例。An example of a configuration diagram of a substrate processing apparatus according to the present embodiment. 本実施形態に係る基板処理装置の動作の一例を示すフローチャート。1 is a flowchart illustrating an example of the operation of the substrate processing apparatus according to the present embodiment. 第１例における基板の断面模式図の一例。An example of a schematic cross-sectional view of a substrate in the first example. 第１例における処理条件の補正を説明する概念図。FIG. 3 is a conceptual diagram illustrating correction of processing conditions in the first example. 第２例における基板の断面模式図の一例。An example of a schematic cross-sectional view of a substrate in a second example.

以下、図面を参照して本開示を実施するための形態について説明する。各図面において、同一構成部分には同一符号を付し、重複した説明を省略する場合がある。 Hereinafter, embodiments for implementing the present disclosure will be described with reference to the drawings. In each drawing, the same components are given the same reference numerals, and redundant explanations may be omitted.

＜基板処理装置Ｓ＞
本実施形態に係る基板処理装置Ｓについて、図１を用いて説明する。図１は、本実施形態に係る基板処理装置Ｓの構成図の一例である。基板処理装置Ｓは、半導体ウェハ等の基板Ｗに前工程の処理及び後工程の処理を施す装置である。 <Substrate processing equipment S>
A substrate processing apparatus S according to this embodiment will be explained using FIG. 1. FIG. 1 is an example of a configuration diagram of a substrate processing apparatus S according to this embodiment. The substrate processing apparatus S is an apparatus that performs pre-processing and post-processing on a substrate W such as a semiconductor wafer.

基板処理装置Ｓは、基板Ｗに前工程の処理を施す前工程処理装置１０と、前工程の処理が施された基板Ｗに後工程の処理を施す後工程処理装置２０と、計測装置３０と、全体制御装置４０と、を備えている。 The substrate processing apparatus S includes a pre-processing apparatus 10 that performs a pre-processing process on a substrate W, a post-processing apparatus 20 that performs a post-processing process on the substrate W that has been subjected to the pre-processing process, and a measuring device 30. , and an overall control device 40.

前工程処理装置１０は、制御部１１により制御され、基板Ｗに前工程の処理を施す。制御部１１は、所定の処理条件に基づいて前工程処理装置１０を制御し、基板Ｗに前工程の処理を施す。前工程処理装置１０で前工程の処理が施された基板Ｗは、例えばＦＯＵＰ（Front Opening Unified Pod）等のキャリアに収容され、後工程処理装置２０に搬送される。 The pre-processing apparatus 10 is controlled by the control unit 11 and performs pre-processing on the substrate W. The control unit 11 controls the pre-processing apparatus 10 based on predetermined processing conditions, and performs the pre-processing on the substrate W. The substrate W that has been subjected to the pre-processing process in the pre-processing apparatus 10 is accommodated in a carrier such as a FOUP (Front Opening Unified Pod), and is transported to the post-processing apparatus 20.

後工程処理装置２０は、前工程の処理が施された基板Ｗに後工程の処理を施す。ここで、後工程処理装置２０は、クラスタ構造（マルチチャンバタイプ）の処理装置である。 The post-processing apparatus 20 performs post-processing on the substrate W that has been subjected to the pre-processing. Here, the post-process processing apparatus 20 is a processing apparatus with a cluster structure (multi-chamber type).

図１に示す例では、後工程処理装置２０は、基板処理室（チャンバ）ＰＭ（Process Module）１～ＰＭ６、搬送室ＶＴＭ（Vacuum Transfer Module）、ロードロック室ＬＬＭ（Load Lock Module）１、ＬＬＭ２、ローダーモジュールＬＭ（Loader Module）及びロードポートＬＰ（Load Port）１～ＬＰ３を有する。 In the example shown in FIG. 1, the post-processing apparatus 20 includes substrate processing chambers (chambers) PM (Process Modules) 1 to PM6, transfer chambers VTM (Vacuum Transfer Module), load lock chambers LLM (Load Lock Module) 1, LLM2. , a loader module LM, and load ports LP1 to LP3.

後工程処理装置２０は、制御部２１により制御され、基板Ｗに後工程の処理を施す。制御部２１は、各基板処理室ＰＭ１～ＰＭ６の処理条件に基づいて後工程処理装置２０を制御し、基板Ｗに後工程の処理を施す。 The post-processing apparatus 20 is controlled by the control unit 21 and performs post-processing on the substrate W. The control unit 21 controls the post-processing apparatus 20 based on the processing conditions of each substrate processing chamber PM1 to PM6, and performs post-processing on the substrate W.

基板処理室ＰＭ１～ＰＭ６は、搬送室ＶＴＭに隣接して配置される。基板処理室ＰＭ１～ＰＭ６を、総称して、基板処理室ＰＭともいう。基板処理室ＰＭ１～ＰＭ６と搬送室ＶＴＭとは、ゲートバルブＧＶの開閉により連通する。基板処理室ＰＭ１～ＰＭ６は、所定の真空雰囲気に減圧され、その内部にて基板Ｗに所望の処理（例えば、エッチング処理、成膜処理、クリーニング処理、アッシング処理等）が施される。 The substrate processing chambers PM1 to PM6 are arranged adjacent to the transfer chamber VTM. The substrate processing chambers PM1 to PM6 are also collectively referred to as the substrate processing chamber PM. The substrate processing chambers PM1 to PM6 and the transfer chamber VTM communicate with each other by opening and closing a gate valve GV. The substrate processing chambers PM1 to PM6 are reduced in pressure to a predetermined vacuum atmosphere, and the substrate W is subjected to desired processing (eg, etching processing, film forming processing, cleaning processing, ashing processing, etc.) therein.

搬送室ＶＴＭの内部には、基板Ｗを搬送する搬送装置ＶＡが配置されている。搬送装置ＶＡは、屈伸及び回転自在な２つのロボットアームＡＣ、ＡＤを有する。各ロボットアームＡＣ、ＡＤの先端部には、それぞれピックＣ、Ｄが取り付けられている。搬送装置ＶＡは、ピックＣ、Ｄのそれぞれに基板Ｗを保持可能であり、ゲートバルブＧＶの開閉に応じて基板処理室ＰＭ１～ＰＭ６と搬送室ＶＴＭとの間で基板Ｗの搬入及び搬出を行う。また、搬送装置ＶＡは、ゲートバルブＧＶの開閉に応じて搬送室ＶＴＭとロードロック室ＬＬＭ１、ＬＬＭ２との間で基板Ｗの搬入及び搬出を行う。 A transport device VA that transports the substrate W is arranged inside the transport chamber VTM. The transport device VA has two robot arms AC and AD that are bendable, extendable and rotatable. Picks C and D are attached to the tips of the robot arms AC and AD, respectively. The transfer device VA is capable of holding a substrate W in each of the picks C and D, and carries in and out the substrate W between the substrate processing chambers PM1 to PM6 and the transfer chamber VTM according to the opening and closing of the gate valve GV. . Further, the transfer device VA carries in and out the substrate W between the transfer chamber VTM and the load lock chambers LLM1 and LLM2 in response to opening and closing of the gate valve GV.

ロードロック室ＬＬＭ１、ＬＬＭ２は、搬送室ＶＴＭとローダーモジュールＬＭとの間に設けられている。ロードロック室ＬＬＭ１、ＬＬＭ２は、大気雰囲気と真空雰囲気とを切り替えて、基板Ｗを大気側のローダーモジュールＬＭから真空側の搬送室ＶＴＭへ搬送したり、真空側の搬送室ＶＴＭから大気側のローダーモジュールＬＭへ搬送したりする。 The load lock chambers LLM1 and LLM2 are provided between the transfer chamber VTM and the loader module LM. The load lock chambers LLM1 and LLM2 switch between an air atmosphere and a vacuum atmosphere to transfer the substrate W from the loader module LM on the atmosphere side to the transfer chamber VTM on the vacuum side, or from the transfer chamber VTM on the vacuum side to the loader on the atmosphere side. It is transported to module LM.

ローダーモジュールＬＭには、ロードポートＬＰ１～ＬＰ３が設けられている。ロードポートＬＰ１～ＬＰ３には、前工程処理装置１０で前工程の処理が施された基板Ｗが収納されたＦＯＵＰまたは空のＦＯＵＰが載置される。ローダーモジュールＬＭは、ロードポートＬＰ１～ＬＰ３内のＦＯＵＰから搬出された基板Ｗをロードロック室ＬＬＭ１、ＬＬＭ２のいずれかに搬入し、ロードロック室ＬＬＭ１、ＬＬＭ２のいずれかから搬出された基板ＷをＦＯＵＰに搬入する。 Loader module LM is provided with load ports LP1 to LP3. On the load ports LP1 to LP3, FOUPs containing substrates W that have been subjected to pre-processing in the pre-processing apparatus 10 or empty FOUPs are placed. The loader module LM loads the substrate W carried out from the FOUP in the load ports LP1 to LP3 into either the load lock chamber LLM1 or LLM2, and loads the substrate W carried out from the load lock chamber LLM1 or LLM2 into the FOUP. to be transported to.

この様な構成により、前工程の処理が施された基板Ｗは、ローダーモジュールＬＭ、ロードロック室ＬＬＭ１、ＬＬＭ２、搬送室ＶＴＭを介して、いずれかの基板処理室ＰＭ１～ＰＭ６に搬送され、後工程の処理が施される。後工程の処理が施された基板Ｗは、搬送室ＶＴＭ、ロードロック室ＬＬＭ１、ＬＬＭ２、ローダーモジュールＬＭを介して、ＦＯＵＰに収納される。 With such a configuration, the substrate W that has been processed in the previous process is transferred to one of the substrate processing chambers PM1 to PM6 via the loader module LM, the load lock chambers LLM1, LLM2, and the transfer chamber VTM, and is subsequently processed. The process is processed. The substrate W subjected to post-processing is stored in the FOUP via the transfer chamber VTM, load lock chambers LLM1, LLM2, and loader module LM.

計測装置３０は、後工程処理装置２０で後工程の処理が施された基板Ｗについて、処理結果を計測する装置である。後工程の処理がエッチング処理の場合、計測装置３０は、例えば、ＣＤ（Critical Dimension）値やエッチング深さを計測する。計測装置３０の計測結果は、全体制御装置４０に送信される。 The measuring device 30 is a device that measures the processing results of the substrate W that has been subjected to post-processing in the post-processing device 20. When the post-processing process is an etching process, the measuring device 30 measures, for example, a CD (Critical Dimension) value or an etching depth. The measurement results of the measuring device 30 are transmitted to the overall control device 40.

全体制御装置４０は、計測装置３０の計測結果に基づいて、前工程処理装置１０の処理条件及び後工程処理装置２０の各基板処理室ＰＭ１～ＰＭ６の処理条件を決定する。決定された前工程処理装置１０の処理条件は、前工程処理装置１０の制御部１１に送信される。また、決定された後工程処理装置２０の各基板処理室ＰＭ１～ＰＭ６の処理条件は、後工程処理装置２０の制御部２１に送信される。 The overall control device 40 determines the processing conditions of the pre-processing device 10 and the processing conditions of each substrate processing chamber PM1 to PM6 of the post-processing device 20 based on the measurement results of the measuring device 30. The determined processing conditions of the pre-processing apparatus 10 are transmitted to the control unit 11 of the pre-processing apparatus 10. Further, the determined processing conditions for each of the substrate processing chambers PM1 to PM6 of the post-processing apparatus 20 are transmitted to the control unit 21 of the post-processing apparatus 20.

＜基板処理装置Ｓの動作＞
次に、基板処理装置Ｓの動作の一例について、図２および図３を用いて説明する。図２は、本実施形態に係る基板処理装置Ｓの動作の一例を示すフローチャートである。図３は、第１例における基板Ｗの断面模式図の一例である。基板Ｗ（図３（ａ）参照）は、基体２００上にエッチング対象膜２１０、ハードマスク膜２２０およびマスクパターン２３０が形成されている。ここでは、基板処理装置Ｓは、基体２００上にエッチング対象膜２１０、ハードマスク膜２２０およびマスクパターン２３０が形成された基板Ｗ（図３（ａ）参照）に対して、前工程としてマスクパターン２３０を通してエッチング処理を施しハードマスク膜２２０に開口２２１を形成する（図３（ｂ）参照）場合を例に説明する。マスクパターン２３０は、例えば、有機膜により形成され、ホールまたはライン状の開口を有する。また、基板処理装置Ｓは、後工程として開口２２１を有するハードマスク膜２２０をマスクとして、エッチング対象膜２１０にエッチング処理を施して開口２１１を形成する（図３（ｃ）参照）場合を例に説明する。また、制御対象の特性値は、エッチング対象膜２１０のＣＤ（Critical Dimension）値である場合を例に説明する。 <Operation of substrate processing apparatus S>
Next, an example of the operation of the substrate processing apparatus S will be described using FIGS. 2 and 3. FIG. 2 is a flowchart showing an example of the operation of the substrate processing apparatus S according to this embodiment. FIG. 3 is an example of a schematic cross-sectional view of the substrate W in the first example. In the substrate W (see FIG. 3A), an etching target film 210, a hard mask film 220, and a mask pattern 230 are formed on a base body 200. Here, the substrate processing apparatus S processes a mask pattern 230 as a pre-process on a substrate W (see FIG. 3A) on which an etching target film 210, a hard mask film 220, and a mask pattern 230 are formed on a base body 200. An example will be described in which an opening 221 is formed in the hard mask film 220 by etching through the hard mask film 220 (see FIG. 3(b)). The mask pattern 230 is formed of, for example, an organic film, and has a hole or a line-shaped opening. Further, the substrate processing apparatus S performs an etching process on the etching target film 210 using the hard mask film 220 having the openings 221 as a mask as a post-process to form the openings 211 (see FIG. 3(c)) as an example. explain. Furthermore, an example will be described in which the characteristic value to be controlled is a CD (Critical Dimension) value of the film 210 to be etched.

ステップＳ１０１において、全体制御装置４０は、前工程処理装置１０を用いて、基板Ｗに前工程の処理を施す。ここでは、前工程処理装置１０の制御部１１は、所定の処理条件で基板Ｗに前工程の処理を施す。ここで、図３（ａ）は、処理前の基板Ｗを示す。基板Ｗは、基体２００上にエッチング対象膜２１０、ハードマスク膜２２０およびマスクパターン２３０が形成されている。図３（ｂ）は、前工程の処理を施した後の基板Ｗを示す。前工程の処理により、基板Ｗのハードマスク膜２２０には、開口２２１が形成されている。 In step S101, the overall control device 40 performs a pre-processing process on the substrate W using the pre-processing apparatus 10. Here, the control unit 11 of the pre-processing apparatus 10 performs the pre-processing on the substrate W under predetermined processing conditions. Here, FIG. 3(a) shows the substrate W before processing. In the substrate W, an etching target film 210, a hard mask film 220, and a mask pattern 230 are formed on a base body 200. FIG. 3(b) shows the substrate W after being subjected to the previous process. An opening 221 is formed in the hard mask film 220 of the substrate W by the previous process.

ステップＳ１０２において、全体制御装置４０は、後工程処理装置２０の複数の基板処理室ＰＭ１～ＰＭ６において、基板Ｗに後工程の処理を施す。即ち、ステップＳ１０１において前工程の処理が施された基板Ｗは、いずれかの基板処理室ＰＭ１～ＰＭ６に搬送され、後工程の処理が施される。後工程処理装置２０の制御部２１は、所定の処理条件で基板Ｗに後工程の処理を施す。ここで、図３（ｃ）は、後工程の処理を施した後の基板Ｗを示す。開口２２１を有するハードマスク膜２２０をマスクとして、エッチング対象膜２１０にエッチング処理を施すことにより、基板Ｗのエッチング対象膜２１０には、開口２１１が形成されている。 In step S102, the overall control device 40 performs post-processing on the substrate W in the plurality of substrate processing chambers PM1 to PM6 of the post-processing apparatus 20. That is, the substrate W that has been subjected to the pre-processing process in step S101 is transported to one of the substrate processing chambers PM1 to PM6, and is subjected to the post-processing process. The control unit 21 of the post-processing apparatus 20 performs post-processing on the substrate W under predetermined processing conditions. Here, FIG. 3(c) shows the substrate W after being subjected to post-processing. The opening 211 is formed in the etching target film 210 of the substrate W by performing an etching process on the etching target film 210 using the hard mask film 220 having the opening 221 as a mask.

ステップＳ１０３において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６で処理された基板Ｗの特性値を取得する。即ち、ステップＳ１０２において後工程の処理が施された基板Ｗは、計測装置３０で特性値（ＣＤ値）を計測する。ここで、特性値とは、基板Ｗに前工程および後工程の処理を施した際に、精度を要求するパラメータをいう。また、基板Ｗに前工程および後工程の処理を施した際に要求される特性値の値を目標値という。特性値（ＣＤ値）は、１枚の基板Ｗの計測値でもよいし、複数枚の基板Ｗの各計測値の平均値であってもよい。 In step S103, the overall control device 40 acquires the characteristic values of the substrates W processed in each of the substrate processing chambers PM1 to PM6. That is, the characteristic value (CD value) of the substrate W that has been subjected to the post-processing process in step S102 is measured by the measuring device 30. Here, the characteristic value refers to a parameter that requires accuracy when the substrate W is subjected to pre-process and post-process processing. Further, the value of the characteristic value required when the substrate W is subjected to the pre-process and post-process is referred to as a target value. The characteristic value (CD value) may be a measured value of one substrate W, or may be an average value of each measured value of a plurality of substrates W.

ステップＳ１０４において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６で処理された基板Ｗの実力値を算出する。ここで、実力値とは、基板処理室ＰＭにおける後工程の処理条件を調整して、特性値を最も目標値に近づけた場合の推定値をいう。なお、全体制御装置４０は、後工程の処理条件を変更した際における特性値の変化量を示すテーブル、シミュレーションモデル等を有していてもよい。全体制御装置４０は、ステップＳ１０３で計測した所定の処理条件での基板処理室ＰＭにおける特性値と、プロセスパラメータ（電力、圧力、ガス流量、温度、処理時間等）に対する特性値の変化量を示すテーブルに基づいて、実力値を算出してもよい。 In step S104, the overall control device 40 calculates the actual performance value of the substrates W processed in each of the substrate processing chambers PM1 to PM6. Here, the actual value refers to an estimated value when the characteristic value is brought closest to the target value by adjusting the processing conditions of the post-process in the substrate processing chamber PM. Note that the overall control device 40 may have a table, a simulation model, etc. that shows the amount of change in characteristic values when the processing conditions of the post-process are changed. The overall control device 40 indicates the characteristic value in the substrate processing chamber PM under the predetermined processing conditions measured in step S103 and the amount of change in the characteristic value with respect to process parameters (power, pressure, gas flow rate, temperature, processing time, etc.) The ability value may be calculated based on a table.

ステップＳ１０５において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６の補正残差量を取得する。全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６の実力値と目標値との差である補正残差量を算出する。即ち、補正残差量は、後工程の処理条件を調整しても、調整しきれない特性値と目標値とのズレ（残差）をいう。ここで、実力値Ａ、目標値Ｘとすると、補正残差量Ｂは「Ｂ＝Ｘ－Ａ」で表すことができる。即ち、実力値Ａが目標値Ｘよりも小さい場合、Ｂは正の値になる。実力値Ａが目標値Ｘよりも大きい場合、Ｂは負の値になる。 In step S105, the overall control device 40 obtains the corrected residual amount of each substrate processing chamber PM1 to PM6. The overall control device 40 calculates a corrected residual amount, which is the difference between the actual performance value and the target value of each substrate processing chamber PM1 to PM6. In other words, the corrected residual amount refers to the difference (residual difference) between the characteristic value and the target value that cannot be fully adjusted even if the processing conditions of the post-process are adjusted. Here, if the actual value A and the target value are X, the corrected residual error amount B can be expressed as "B=X-A". That is, when the actual ability value A is smaller than the target value X, B becomes a positive value. When the actual ability value A is larger than the target value X, B becomes a negative value.

ステップＳ１０６において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６の補正残差量の平均値を算出する。 In step S106, the overall control device 40 calculates the average value of the correction residual amount of each substrate processing chamber PM1 to PM6.

ステップＳ１０７において、全体制御装置４０は、補正残差量の平均値に基づいて、前工程処理装置１０の処理条件を補正する。ここでは、補正残差量の平均値が正の値の場合、エッチング対象膜２１０の開口２１１の特性値（ＣＤ値）が補正残差量の平均値の分だけ大きくなるように、ハードマスク膜２２０の開口２２１の径又は幅や形状（テーパー形状や垂直形状）を決定する（たとえば、ハードマスク膜２２０の開口２２１を大きくする）。補正残差量の平均値が負の値の場合、エッチング対象膜２１０の開口２１１の特性値（ＣＤ値）が補正残差量の平均値の分だけ小さくなるように、ハードマスク膜２２０の開口２２１の径又は幅や形状を決定する（たとえば、ハードマスク膜２２０の開口２２１を小さくする）。決定したハードマスク膜２２０の開口２２１の径又は幅や形状に基づいて、前工程処理装置１０の処理条件を補正（決定）する。 In step S107, the overall control device 40 corrects the processing conditions of the pre-processing device 10 based on the average value of the corrected residual amount. Here, when the average value of the corrected residual amount is a positive value, the hard mask film is The diameter or width or shape (tapered shape or vertical shape) of the opening 221 of the hard mask film 220 is determined (for example, the opening 221 of the hard mask film 220 is made larger). When the average value of the corrected residual amount is a negative value, the opening of the hard mask film 220 is adjusted so that the characteristic value (CD value) of the opening 211 of the etching target film 210 becomes smaller by the average value of the corrected residual amount. The diameter or width or shape of the hard mask film 220 is determined (for example, the opening 221 of the hard mask film 220 is made smaller). Based on the determined diameter, width, and shape of the opening 221 of the hard mask film 220, the processing conditions of the pre-processing apparatus 10 are corrected (determined).

なお、全体制御装置４０は、補正残差量の平均値と前工程処理装置１０の処理条件とを対応付けしたテーブルを予め記憶していてもよい。全体制御装置４０は、補正残差量の平均値およびテーブルに基づいて、前工程処理装置１０の処理条件を補正（決定）する。 Note that the overall control device 40 may store in advance a table that associates the average value of the corrected residual amount with the processing conditions of the pre-processing device 10. The overall control device 40 corrects (determines) the processing conditions of the pre-processing device 10 based on the average value of the corrected residual amount and the table.

ステップＳ１０８において、全体制御装置４０は、補正残差量の平均値と、ステップＳ１０３で取得した各基板処理室ＰＭ１～ＰＭ６の特性と、に基づいて、後工程処理装置２０の各基板処理室ＰＭ１～ＰＭ６の処理条件を補正する。 In step S108, the overall control device 40 controls each substrate processing chamber PM1 of the post-processing apparatus 20 based on the average value of the corrected residual amount and the characteristics of each substrate processing chamber PM1 to PM6 acquired in step S103. ~ Correct the processing conditions for PM6.

ここでは、全体制御装置４０は、前工程の変更に対応して、特性値が目標値に近づくように、各基板処理室ＰＭ１～ＰＭ６の処理条件を補正（決定）する。この際、プロセスパラメータに対する特性値の変化量を示すテーブルを参照して行われてよい。 Here, the overall control device 40 corrects (determines) the processing conditions of each substrate processing chamber PM1 to PM6 so that the characteristic value approaches the target value in response to the change in the previous process. At this time, the determination may be performed with reference to a table showing the amount of change in the characteristic value with respect to the process parameter.

また、全体制御装置４０は、補正残差量の平均値と各基板処理室ＰＭ１～ＰＭ６の補正残差量に基づいて、過補正であるか否かを判定する。過補正（補正残差量の平均値＞補正残差量）の場合、実力値が目標値に近づく（一致する）ように、処理条件を補正する。過補正でない（補正残差量の平均値＜補正残差量）の場合、実力値が目標値にできるだけ近づくように、処理条件を補正する。 Further, the overall control device 40 determines whether over-correction has occurred based on the average value of the corrected residual amount and the corrected residual amount of each substrate processing chamber PM1 to PM6. In the case of over-correction (average value of corrected residual amount>corrected residual amount), the processing conditions are corrected so that the actual value approaches (coincides with) the target value. If it is not overcorrection (average value of corrected residual amount<corrected residual amount), the processing conditions are corrected so that the actual value becomes as close as possible to the target value.

ステップＳ１０９において、全体制御装置４０は、前工程処理装置１０を用いて、補正後の処理条件で基板Ｗに前工程の処理を施す。ここでは、前工程処理装置１０の制御部１１は、ステップＳ１０７で補正された新たな処理条件で基板Ｗに前工程の処理を施す。 In step S109, the overall control device 40 uses the pre-processing device 10 to perform a pre-processing process on the substrate W under the corrected processing conditions. Here, the control unit 11 of the pre-processing apparatus 10 performs the pre-processing on the substrate W under the new processing conditions corrected in step S107.

ステップＳ１１０において、全体制御装置４０は、後工程処理装置２０の複数の基板処理室ＰＭ１～ＰＭ６において、補正後の処理条件で基板Ｗに後工程の処理を施す。ここでは、前工程処理装置１０の制御部１１は、ステップＳ１０８で補正された新たな処理条件で基板Ｗに後工程の処理を施す。 In step S110, the overall control device 40 performs post-processing on the substrate W in the plurality of substrate processing chambers PM1 to PM6 of the post-processing apparatus 20 under the corrected processing conditions. Here, the control unit 11 of the pre-processing apparatus 10 performs post-processing on the substrate W under the new processing conditions corrected in step S108.

図４は、第１例における処理条件の補正を説明する概念図である。図４（ａ）および図４（ｂ）は、ステップＳ１０１からステップＳ１０５の処理後を示す。図４（ａ）に示すように、ある基板処理室ＰＭでは、実力値が目標値Ｘよりも大きくなる。また、図４（ｂ）に示すように、ある基板処理室ＰＭでは、実力値が目標値Ｘよりも小さくなる。 FIG. 4 is a conceptual diagram illustrating correction of processing conditions in the first example. FIGS. 4(a) and 4(b) show the process after steps S101 to S105. As shown in FIG. 4(a), the actual performance value becomes larger than the target value X in a certain substrate processing chamber PM. Moreover, as shown in FIG. 4(b), the actual performance value becomes smaller than the target value X in a certain substrate processing chamber PM.

そして、ステップＳ１０６およびステップＳ１０７において、前工程処理装置１０の処理条件を補正する。即ち、図４（ｃ）に示すように、前工程であるハードマスク膜２２０のエッチング工程における処理条件を変更して、ハードマスク膜２２０の開口２２１の径又は幅や形状を変化させる。 Then, in steps S106 and S107, the processing conditions of the pre-processing device 10 are corrected. That is, as shown in FIG. 4C, the diameter, width, or shape of the opening 221 in the hard mask film 220 is changed by changing the processing conditions in the previous step of etching the hard mask film 220.

そして、ステップＳ１０８において、後工程処理装置２０の処理条件を基板処理室ＰＭごとに補正する。これにより、図４（ｄ）および図４（ｅ）は、補正後の処理条件での後工程の処理結果を示す。これにより、基板処理室ＰＭ間における特性値（ＣＤ値）のばらつきを抑制することができる。 Then, in step S108, the processing conditions of the post-processing apparatus 20 are corrected for each substrate processing chamber PM. As a result, FIGS. 4(d) and 4(e) show the results of post-processing under the corrected processing conditions. Thereby, variations in characteristic values (CD values) between substrate processing chambers PM can be suppressed.

なお、第１例では特性値としてエッチング対象膜２１０の開口２１１のＣＤ値を例に説明したが、特性値はこれに限られるものではない。 Note that in the first example, the CD value of the opening 211 of the etching target film 210 is used as an example of the characteristic value, but the characteristic value is not limited to this.

図５は、第２例における基板Ｗの断面模式図の一例である。第２例では、エッチング対象膜２１０の成膜工程、ハードマスク膜２２０の成膜工程、マスクパターン２３０の形成工程、ハードマスク膜２２０のエッチング工程、エッチング対象膜２１０のエッチング工程を有する。図５（ａ）は、処理前の基板Ｗを示す。基板Ｗは、基体２００を有する。図５（ｂ）は、エッチング対象膜２１０の成膜工程後の基板Ｗを示す。基板Ｗは、基体２００の上に膜厚Ｈのエッチング対象膜２１０が成膜される。図５（ｃ）は、ハードマスク膜２２０の成膜工程後の基板Ｗを示す。基板Ｗは、エッチング対象膜２１０の上にハードマスク膜２２０が成膜される。図５（ｄ）は、マスクパターン２３０の形成工程後の基板Ｗを示す。基板Ｗは、ハードマスク膜２２０の上にマスクパターン２３０が形成される。図５（ｅ）は、ハードマスク膜２２０のエッチング工程後の基板Ｗを示す。基板Ｗのハードマスク膜２２０には、開口２２１が形成されている。図５（ｆ）は、エッチング対象膜２１０のエッチング工程後の基板Ｗを示す。基板Ｗのエッチング対象膜２１０には、エッチング深さＤの開口２１１が形成されている。ここで、開口２１１の底部と基体２００との間には、薄膜部２１２を有する。第２例では、薄膜部２１２の膜厚Ｒが所望の膜厚となるように、制御する。 FIG. 5 is an example of a schematic cross-sectional view of the substrate W in the second example. The second example includes a step of forming the film to be etched 210, a step of forming the hard mask film 220, a step of forming the mask pattern 230, an etching step of the hard mask film 220, and an etching step of the film to be etched 210. FIG. 5(a) shows the substrate W before processing. The substrate W has a base body 200. FIG. 5B shows the substrate W after the process of forming the film 210 to be etched. In the substrate W, an etching target film 210 having a thickness H is formed on a base body 200 . FIG. 5C shows the substrate W after the hard mask film 220 has been formed. On the substrate W, a hard mask film 220 is formed on the etching target film 210 . FIG. 5D shows the substrate W after the process of forming the mask pattern 230. As shown in FIG. On the substrate W, a mask pattern 230 is formed on a hard mask film 220 . FIG. 5E shows the substrate W after the hard mask film 220 has been etched. An opening 221 is formed in the hard mask film 220 of the substrate W. FIG. 5F shows the substrate W after the etching process of the film 210 to be etched. An opening 211 having an etching depth D is formed in the etching target film 210 of the substrate W. Here, a thin film portion 212 is provided between the bottom of the opening 211 and the base 200. In the second example, the thickness R of the thin film portion 212 is controlled to be a desired thickness.

第２例では、エッチング対象膜２１０の成膜工程を前工程とし、エッチング対象膜２１０のエッチング工程を後工程とする。また、制御対象の特性値は、エッチング対象膜２１０の開口２１１のエッチング深さＤとする。 In the second example, the process of forming the film to be etched 210 is a pre-process, and the process of etching the film to be etched 210 is a post-process. Further, the characteristic value to be controlled is the etching depth D of the opening 211 of the film 210 to be etched.

第２例について図２を用いて説明する。 A second example will be explained using FIG. 2.

ステップＳ１０１において、全体制御装置４０は、前工程処理装置１０を用いて、基板Ｗに前工程の処理を施す。ここでは、基体２００に所定の膜厚Ｈのエッチング対象膜２１０を成膜する。 In step S101, the overall control device 40 performs a pre-processing process on the substrate W using the pre-processing apparatus 10. Here, an etching target film 210 having a predetermined thickness H is formed on the base 200.

その後、基板Ｗには、ハードマスク膜２２０の成膜工程、マスクパターン２３０の形成工程、ハードマスク膜２２０のエッチング工程の処理が施される。 Thereafter, the substrate W is subjected to a process of forming a hard mask film 220, a process of forming a mask pattern 230, and an etching process of the hard mask film 220.

ステップＳ１０２において、全体制御装置４０は、後工程処理装置２０の複数の基板処理室ＰＭ１～ＰＭ６において、基板Ｗに後工程の処理を施す。ここでは、開口２２１を有するハードマスク膜２２０をマスクとして、エッチング対象膜２１０をエッチングする。 In step S102, the overall control device 40 performs post-processing on the substrate W in the plurality of substrate processing chambers PM1 to PM6 of the post-processing apparatus 20. Here, the film to be etched 210 is etched using the hard mask film 220 having the opening 221 as a mask.

ステップＳ１０３において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６で処理された基板Ｗの特性値を取得する。即ち、ステップＳ１０２において後工程の処理が施された基板Ｗは、計測装置３０で特性値（エッチング深さＤ）を計測する。ここで、エッチング深さＤの目標値は、ステップＳ１０１で成膜されたエッチング対象膜２１０の膜厚Ｈと、要求される薄膜部２１２の膜厚Ｒとの差から算出される。 In step S103, the overall control device 40 acquires the characteristic values of the substrates W processed in each of the substrate processing chambers PM1 to PM6. That is, the measurement device 30 measures the characteristic value (etching depth D) of the substrate W that has been subjected to the post-processing process in step S102. Here, the target value of the etching depth D is calculated from the difference between the film thickness H of the etching target film 210 formed in step S101 and the required film thickness R of the thin film portion 212.

ステップＳ１０４において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６で処理された基板Ｗの実力値を算出する。 In step S104, the overall control device 40 calculates the actual performance value of the substrates W processed in each of the substrate processing chambers PM1 to PM6.

ステップＳ１０５において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６の補正残差量を取得する。 In step S105, the overall control device 40 obtains the corrected residual amount of each substrate processing chamber PM1 to PM6.

ステップＳ１０６において、全体制御装置４０は、各基板処理室ＰＭ１～ＰＭ６の補正残差量の平均値を算出する。 In step S106, the overall control device 40 calculates the average value of the correction residual amount of each substrate processing chamber PM1 to PM6.

ステップＳ１０７において、全体制御装置４０は、補正残差量の平均値に基づいて、前工程処理装置１０の処理条件を補正する。ここでは、補正残差量の平均値が正の値の場合、エッチング対象膜２１０の膜厚Ｈを補正残差量の平均値の分だけ薄くする。補正残差量の平均値が負の値の場合、エッチング対象膜２１０の膜厚Ｈを補正残差量の平均値の分だけ厚くする。全体制御装置４０は、補正後のエッチング対象膜２１０の膜厚Ｈに基づいて、前工程処理装置１０の処理条件を補正する。 In step S107, the overall control device 40 corrects the processing conditions of the pre-processing device 10 based on the average value of the corrected residual amount. Here, when the average value of the corrected residual amount is a positive value, the film thickness H of the etching target film 210 is reduced by the average value of the corrected residual amount. If the average value of the corrected residual amount is a negative value, the film thickness H of the etching target film 210 is increased by the average value of the corrected residual amount. The overall control device 40 corrects the processing conditions of the pre-processing device 10 based on the corrected film thickness H of the etching target film 210.

なお、全体制御装置４０は、エッチング対象膜２１０の膜厚Ｈと前工程処理装置１０の処理条件とを対応付けしたテーブルを予め記憶していてもよい。全体制御装置４０は、補正残差量の平均値およびテーブルに基づいて、前工程処理装置１０の処理条件を補正する。 Note that the overall control device 40 may store in advance a table that associates the film thickness H of the etching target film 210 with the processing conditions of the pre-processing device 10. The overall control device 40 corrects the processing conditions of the pre-processing device 10 based on the average value of the corrected residual amount and the table.

ステップＳ１０８において、全体制御装置４０は、補正残差量の平均値と、ステップＳ１０３で取得した各基板処理室ＰＭ１～ＰＭ６の特性と、に基づいて、後工程処理装置２０の各基板処理室ＰＭ１～ＰＭ６の処理条件を補正する。 In step S108, the overall control device 40 controls each substrate processing chamber PM1 of the post-processing apparatus 20 based on the average value of the corrected residual amount and the characteristics of each substrate processing chamber PM1 to PM6 acquired in step S103. ~ Correct the processing conditions for PM6.

ここで、エッチング深さＤの補正後の目標値は、補正後の膜厚Ｈと要求される薄膜部２１２の膜厚Ｒとの差から算出される。全体制御装置４０は、特性値が補正後の目標値に近づくように、各基板処理室ＰＭ１～ＰＭ６の処理条件を補正する。この際、プロセスパラメータに対する特性値の変化量を示すテーブルを参照して行われてよい。 Here, the corrected target value of the etching depth D is calculated from the difference between the corrected film thickness H and the required film thickness R of the thin film portion 212. The overall control device 40 corrects the processing conditions of each substrate processing chamber PM1 to PM6 so that the characteristic value approaches the corrected target value. At this time, the determination may be performed with reference to a table showing the amount of change in the characteristic value with respect to the process parameter.

ステップＳ１０９において、全体制御装置４０は、前工程処理装置１０を用いて、補正後の処理条件で基板Ｗに前工程の処理を施す。ここでは、前工程処理装置１０の制御部１１は、ステップＳ１０７で補正された新たな処理条件で基板Ｗに前工程の処理を施す。 In step S109, the overall control device 40 uses the pre-processing device 10 to perform a pre-processing process on the substrate W under the corrected processing conditions. Here, the control unit 11 of the pre-processing apparatus 10 performs the pre-processing on the substrate W under the new processing conditions corrected in step S107.

ステップＳ１１０において、全体制御装置４０は、後工程処理装置２０の複数の基板処理室ＰＭ１～ＰＭ６において、補正後の処理条件で基板Ｗに後工程の処理を施す。ここでは、前工程処理装置１０の制御部１１は、ステップＳ１０８で補正された新たな処理条件で基板Ｗに後工程の処理を施す。 In step S110, the overall control device 40 performs post-processing on the substrate W in the plurality of substrate processing chambers PM1 to PM6 of the post-processing apparatus 20 under the corrected processing conditions. Here, the control unit 11 of the pre-processing apparatus 10 performs post-processing on the substrate W under the new processing conditions corrected in step S108.

これにより、基板処理室ＰＭ間における特性値（エッチング深さＤ）のばらつきを抑制することができる。また、薄膜部２１２の膜厚Ｒのばらつきを抑制することができる。 Thereby, variations in characteristic values (etching depth D) between substrate processing chambers PM can be suppressed. Furthermore, variations in the film thickness R of the thin film portion 212 can be suppressed.

以上、基板処理装置Ｓの実施形態等について説明したが、本開示は上記実施形態等に限定されるものではなく、特許請求の範囲に記載された本開示の要旨の範囲内において、種々の変形、改良が可能である。 Although the embodiments of the substrate processing apparatus S have been described above, the present disclosure is not limited to the above embodiments, etc., and various modifications can be made within the scope of the gist of the present disclosure described in the claims. , improvements are possible.

前工程における処理結果（第１例のハードマスク膜２２０の開口２２１の径又は幅や形状、第２例のエッチング対象膜２１０膜厚Ｈ）は、均一であるものとして説明したが、これに限られるものではない。前工程において各基板の処理結果にばらつきがある場合には、特性値と目標値との差は、前工程の処理結果のばらつきを考慮して算出してもよい。 Although the processing results in the previous step (the diameter, width, and shape of the opening 221 of the hard mask film 220 in the first example, and the thickness H of the etching target film 210 in the second example) are described as being uniform, the present invention is not limited to this. It's not something you can do. If there is variation in the processing results of each substrate in the previous process, the difference between the characteristic value and the target value may be calculated by taking into account the variation in the processing results in the previous process.

Ｓ 基板処理装置
Ｗ 基板
１０ 前工程処理装置
１１ 制御部
２０ 後工程処理装置
２１ 制御部
３０ 計測装置
４０ 全体制御装置
ＰＭ１～ＰＭ６ 基板処理室
２００ 基体
２１０ エッチング対象膜
２２０ ハードマスク膜
２３０ マスクパターン S Substrate processing apparatus W Substrate 10 Pre-process processing apparatus 11 Control section 20 Post-process processing apparatus 21 Control section 30 Measuring device 40 Overall control apparatus PM1 to PM6 Substrate processing chamber 200 Substrate 210 Etching target film 220 Hard mask film 230 Mask pattern

Claims (7)

前工程と後工程により基板に処理を施し、少なくとも前記後工程は、複数のチャンバにて並行して基板に処理を施す基板処理方法であって、
前記前工程で処理された基板を複数の前記チャンバにて並行して前記後工程の処理をする工程と、
前記チャンバごとに前記後工程の処理後の基板の特性値を取得する工程と、
前記特性値と目標値との差が小さくなるように前記後工程の処理条件を調整した際の特性値の推定値である実力値を算出する工程と、
前記チャンバごとに前記実力値と前記目標値との差である補正残差量を取得する工程と、
全チャンバの前記補正残差量の平均値を算出する工程と、
前記補正残差量の平均値に基づき、前記前工程の処理条件を補正する工程と、
前記補正残差量の平均値と前記チャンバごとの前記補正残差量とに基づき、前記チャンバごとの前記後工程の処理条件を補正する工程と、
補正された処理条件に基づいて、基板に前記前工程および前記後工程の処理を施す工程と、を有する、
基板処理方法。 A substrate processing method in which a substrate is processed in a pre-process and a post-process, and at least the post-process processes the substrate in parallel in a plurality of chambers,
processing the substrate processed in the pre-process in parallel in the post-process in a plurality of the chambers;
acquiring characteristic values of the substrate after the post-processing for each chamber;
calculating an actual value that is an estimated value of the characteristic value when the processing conditions of the post-process are adjusted so that the difference between the characteristic value and the target value is reduced;
obtaining a corrected residual amount that is the difference between the actual strength value and the target value for each chamber;
calculating an average value of the corrected residual amounts of all chambers;
correcting the processing conditions of the previous step based on the average value of the corrected residual amount;
correcting the processing conditions of the post-process for each chamber based on the average value of the corrected residual amount and the corrected residual amount for each chamber;
a step of subjecting the substrate to the pre-process and post-process based on the corrected processing conditions;
Substrate processing method. 前記特性値と前記目標値との差は、前記前工程の処理結果のばらつきを考慮して算出する、
請求項１に記載の基板処理方法。 The difference between the characteristic value and the target value is calculated by taking into account variations in the processing results of the previous step.
The substrate processing method according to claim 1. 前記特性値は、複数の基板の前記特性値の平均値である、
請求項１または請求項２に記載の基板処理方法。 The characteristic value is an average value of the characteristic values of a plurality of substrates,
The substrate processing method according to claim 1 or claim 2. 前記実力値を算出する工程は、あらかじめ記憶されたプロセスパラメータに対する前記特性値の変化量を示すテーブルを参照して前記実力値を推定する、
請求項１乃至請求項３のいずれか１項に記載の基板処理方法。 The step of calculating the actual performance value includes estimating the actual performance value with reference to a table showing the amount of change in the characteristic value with respect to a pre-stored process parameter.
The substrate processing method according to any one of claims 1 to 3. 前記前工程の処理条件を補正する工程は、あらかじめ記憶された前記補正残差量の平均値と前記前工程の処理条件とを対応付けしたテーブルを参照して行う、
請求項１乃至請求項４のいずれか１項に記載の基板処理方法。 The step of correcting the processing conditions of the previous step is performed with reference to a table that associates the average value of the corrected residual amount stored in advance with the processing conditions of the previous step.
The substrate processing method according to any one of claims 1 to 4. 前記後工程の処理条件を補正する工程は、あらかじめ記憶されたプロセスパラメータに対する前記特性値の変化量を示すテーブルを参照して行う、
請求項１乃至請求項５のいずれか１項に記載の基板処理方法。 The step of correcting the processing conditions of the post-process is performed with reference to a table showing the amount of change in the characteristic value with respect to the process parameter stored in advance.
The substrate processing method according to any one of claims 1 to 5. 前工程装置、後工程装置、制御部を備える基板処理装置であって、
前記制御部は、請求項１乃至請求項６のいずれか１項に記載の基板処理方法を実行する、
基板処理装置。 A substrate processing apparatus comprising a pre-process device, a post-process device, and a control section,
The control unit executes the substrate processing method according to any one of claims 1 to 6.
Substrate processing equipment.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006506812A (en) 2002-11-12 2006-02-23 アプライド　マテリアルズ　インコーポレイテッド Method and apparatus for improving dielectric etch efficiency using integrated metrology
JP2007035777A (en) 2005-07-25 2007-02-08 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
US20080248412A1 (en) 2007-04-09 2008-10-09 John Douglas Stuber Supervisory etch cd control
JP2009290150A (en) 2008-06-02 2009-12-10 Renesas Technology Corp System and method for manufacturing semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11260683A (en) * 1998-03-10 1999-09-24 Sony Corp Method for determining exposure condition in semiconductor material manufacturing process and semiconductor material manufacturing equipment
US6891627B1 (en) * 2000-09-20 2005-05-10 Kla-Tencor Technologies Corp. Methods and systems for determining a critical dimension and overlay of a specimen
DE10314504B4 (en) * 2003-03-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Process for producing a nitride-containing insulating layer by compensating for nitrogen nonuniformities
JP5242906B2 (en) 2006-10-17 2013-07-24 東京エレクトロン株式会社 Substrate processing apparatus control device, control method, and storage medium storing control program
US20180323060A1 (en) * 2015-10-28 2018-11-08 Tokyo Electron Limited Substrate processing method, substrate processing apparatus, substrate processing system and recording medium
DE102018101173B4 (en) * 2018-01-19 2022-09-01 VON ARDENNE Asset GmbH & Co. KG procedure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006506812A (en) 2002-11-12 2006-02-23 アプライド　マテリアルズ　インコーポレイテッド Method and apparatus for improving dielectric etch efficiency using integrated metrology
JP2007035777A (en) 2005-07-25 2007-02-08 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device and semiconductor manufacturing apparatus
US20080248412A1 (en) 2007-04-09 2008-10-09 John Douglas Stuber Supervisory etch cd control
JP2009290150A (en) 2008-06-02 2009-12-10 Renesas Technology Corp System and method for manufacturing semiconductor device

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